USB eXtensible Host Controller Interface (xHCI) driver. More...

#include <assert.h>
#include <ipxe/pci.h>
#include <ipxe/uaccess.h>
#include <ipxe/usb.h>

Data Structures
struct	xhci_trb_template
	A transfer request block template. More...

struct	xhci_trb_common
	A transfer request block. More...

struct	xhci_trb_normal
	A normal transfer request block. More...

struct	xhci_trb_setup
	A setup stage transfer request block. More...

struct	xhci_trb_data
	A data stage transfer request block. More...

struct	xhci_trb_status
	A status stage transfer request block. More...

struct	xhci_trb_link
	A link transfer request block. More...

struct	xhci_trb_enable_slot
	An enable slot transfer request block. More...

struct	xhci_trb_disable_slot
	A disable slot transfer request block. More...

struct	xhci_trb_context
	A context transfer request block. More...

struct	xhci_trb_reset_endpoint
	A reset endpoint transfer request block. More...

struct	xhci_trb_stop_endpoint
	A stop endpoint transfer request block. More...

struct	xhci_trb_set_tr_dequeue_pointer
	A set transfer ring dequeue pointer transfer request block. More...

struct	xhci_trb_transfer
	A transfer event transfer request block. More...

struct	xhci_trb_complete
	A command completion event transfer request block. More...

struct	xhci_trb_port_status
	A port status change transfer request block. More...

struct	xhci_trb_host_controller
	A port status change transfer request block. More...

union	xhci_trb
	A transfer request block. More...

struct	xhci_control_context
	An input control context. More...

struct	xhci_slot_context
	A slot context. More...

struct	xhci_endpoint_context
	An endpoint context. More...

struct	xhci_event_ring_segment
	An event ring segment. More...

struct	xhci_trb_ring
	A transfer request block command/transfer ring. More...

struct	xhci_event_ring
	An event ring. More...

struct	xhci_pch
	Intel PCH quirk. More...

struct	xhci_dcbaa
	Device context base address array. More...

struct	xhci_scratchpad
	Scratchpad buffer. More...

struct	xhci_device
	An xHCI device. More...

struct	xhci_slot
	An xHCI device slot. More...

struct	xhci_endpoint
	An xHCI endpoint. More...

Macros
#define	XHCI_MIN_ALIGN 64
	Minimum alignment required for data structures. More...

#define	XHCI_MTU 65536
	Maximum transfer size. More...

#define	XHCI_BAR PCI_BASE_ADDRESS_0
	xHCI PCI BAR More...

#define	XHCI_CAP_CAPLENGTH 0x00
	Capability register length. More...

#define	XHCI_CAP_HCIVERSION 0x02
	Host controller interface version number. More...

#define	XHCI_CAP_HCSPARAMS1 0x04
	Structural parameters 1. More...

#define	XHCI_HCSPARAMS1_SLOTS(params) ( ( (params) >> 0 ) & 0xff )
	Number of device slots. More...

#define	XHCI_HCSPARAMS1_INTRS(params) ( ( (params) >> 8 ) & 0x3ff )
	Number of interrupters. More...

#define	XHCI_HCSPARAMS1_PORTS(params) ( ( (params) >> 24 ) & 0xff )
	Number of ports. More...

#define	XHCI_CAP_HCSPARAMS2 0x08
	Structural parameters 2. More...

#define	XHCI_HCSPARAMS2_SCRATCHPADS(params) ( ( ( (params) >> 16 ) & 0x3e0 ) \| ( ( (params) >> 27 ) & 0x1f ) )
	Number of page-sized scratchpad buffers. More...

#define	XHCI_CAP_HCCPARAMS1 0x10
	Capability parameters. More...

#define	XHCI_HCCPARAMS1_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
	64-bit addressing capability More...

#define	XHCI_HCCPARAMS1_CSZ_SHIFT(params) ( 5 + ( ( (params) >> 2 ) & 0x1 ) )
	Context size shift. More...

#define	XHCI_HCCPARAMS1_XECP(params) ( ( ( (params) >> 16 ) & 0xffff ) << 2 )
	xHCI extended capabilities pointer More...

#define	XHCI_CAP_DBOFF 0x14
	Doorbell offset. More...

#define	XHCI_CAP_RTSOFF 0x18
	Runtime register space offset. More...

#define	XHCI_XECP_ID(xecp) ( ( (xecp) >> 0 ) & 0xff )
	xHCI extended capability ID More...

#define	XHCI_XECP_NEXT(xecp) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )
	Next xHCI extended capability pointer. More...

#define	XHCI_XECP_ID_LEGACY 1
	USB legacy support extended capability. More...

#define	XHCI_USBLEGSUP_BIOS 0x02
	USB legacy support BIOS owned semaphore. More...

#define	XHCI_USBLEGSUP_BIOS_OWNED 0x01
	USB legacy support BIOS ownership flag. More...

#define	XHCI_USBLEGSUP_OS 0x03
	USB legacy support OS owned semaphore. More...

#define	XHCI_USBLEGSUP_OS_OWNED 0x01
	USB legacy support OS ownership flag. More...

#define	XHCI_USBLEGSUP_CTLSTS 0x04
	USB legacy support control/status. More...

#define	XHCI_XECP_ID_SUPPORTED 2
	Supported protocol extended capability. More...

#define	XHCI_SUPPORTED_REVISION 0x00
	Supported protocol revision. More...

#define	XHCI_SUPPORTED_REVISION_VER(revision) ( ( (revision) >> 16 ) & 0xffff )
	Supported protocol minor revision. More...

#define	XHCI_SUPPORTED_NAME 0x04
	Supported protocol name. More...

#define	XHCI_SUPPORTED_PORTS 0x08
	Supported protocol ports. More...

#define	XHCI_SUPPORTED_PORTS_OFFSET(ports) ( ( (ports) >> 0 ) & 0xff )
	Supported protocol port offset. More...

#define	XHCI_SUPPORTED_PORTS_COUNT(ports) ( ( (ports) >> 8 ) & 0xff )
	Supported protocol port count. More...

#define	XHCI_SUPPORTED_PORTS_PSIC(ports) ( ( (ports) >> 28 ) & 0x0f )
	Supported protocol PSI count. More...

#define	XHCI_SUPPORTED_SLOT 0x0c
	Supported protocol slot. More...

#define	XHCI_SUPPORTED_SLOT_TYPE(slot) ( ( (slot) >> 0 ) & 0x1f )
	Supported protocol slot type. More...

#define	XHCI_SUPPORTED_PSI(index) ( 0x10 + ( (index) * 4 ) )
	Supported protocol PSI. More...

#define	XHCI_SUPPORTED_PSI_VALUE(psi) ( ( (psi) >> 0 ) & 0x0f )
	Supported protocol PSI value. More...

#define	XHCI_SUPPORTED_PSI_MANTISSA(psi) ( ( (psi) >> 16 ) & 0xffff )
	Supported protocol PSI mantissa. More...

#define	XHCI_SUPPORTED_PSI_EXPONENT(psi) ( ( (psi) >> 4 ) & 0x03 )
	Supported protocol PSI exponent. More...

#define	XHCI_OP_USBCMD 0x00
	USB command register. More...

#define	XHCI_USBCMD_RUN 0x00000001UL
	Run/stop. More...

#define	XHCI_USBCMD_HCRST 0x00000002UL
	Host controller reset. More...

#define	XHCI_OP_USBSTS 0x04
	USB status register. More...

#define	XHCI_USBSTS_HCH 0x00000001UL
	Host controller halted. More...

#define	XHCI_OP_PAGESIZE 0x08
	Page size register. More...

#define	XHCI_PAGESIZE(pagesize) ( (pagesize) << 12 )
	Page size. More...

#define	XHCI_OP_DNCTRL 0x14
	Device notifcation control register. More...

#define	XHCI_OP_CRCR 0x18
	Command ring control register. More...

#define	XHCI_CRCR_RCS 0x00000001UL
	Command ring cycle state. More...

#define	XHCI_CRCR_CA 0x00000004UL
	Command abort. More...

#define	XHCI_CRCR_CRR 0x00000008UL
	Command ring running. More...

#define	XHCI_OP_DCBAAP 0x30
	Device context base address array pointer. More...

#define	XHCI_OP_CONFIG 0x38
	Configure register. More...

#define	XHCI_CONFIG_MAX_SLOTS_EN(slots) ( (slots) << 0 )
	Maximum device slots enabled. More...

#define	XHCI_CONFIG_MAX_SLOTS_EN_MASK XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )
	Maximum device slots enabled mask. More...

#define	XHCI_OP_PORTSC(port) ( 0x400 - 0x10 + ( (port) << 4 ) )
	Port status and control register. More...

#define	XHCI_PORTSC_CCS 0x00000001UL
	Current connect status. More...

#define	XHCI_PORTSC_PED 0x00000002UL
	Port enabled. More...

#define	XHCI_PORTSC_PR 0x00000010UL
	Port reset. More...

#define	XHCI_PORTSC_PLS(pls) ( (pls) << 5 )
	Port link state. More...

#define	XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 )
	Disabled port link state. More...

#define	XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 )
	RxDetect port link state. More...

#define	XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf )
	Port link state mask. More...

#define	XHCI_PORTSC_PP 0x00000200UL
	Port power. More...

#define	XHCI_PORT_POWER_DELAY_MS 20
	Time to delay after enabling power to a port. More...

#define	XHCI_PORTSC_PSIV(portsc) ( ( (portsc) >> 10 ) & 0xf )
	Port speed ID value. More...

#define	XHCI_PORTSC_PIC(indicators) ( (indicators) << 14 )
	Port indicator control. More...

#define	XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 )
	Port indicator control mask. More...

#define	XHCI_PORTSC_LWS 0x00010000UL
	Port link state write strobe. More...

#define	XHCI_LINK_STATE_DELAY_MS 100
	Time to delay after writing the port link state. More...

#define	XHCI_PORTSC_CSC 0x00020000UL
	Connect status change. More...

#define	XHCI_PORTSC_PEC 0x00040000UL
	Port enabled/disabled change. More...

#define	XHCI_PORTSC_WRC 0x00080000UL
	Warm port reset change. More...

#define	XHCI_PORTSC_OCC 0x00100000UL
	Over-current change. More...

#define	XHCI_PORTSC_PRC 0x00200000UL
	Port reset change. More...

#define	XHCI_PORTSC_PLC 0x00400000UL
	Port link state change. More...

#define	XHCI_PORTSC_CEC 0x00800000UL
	Port config error change. More...

#define	XHCI_PORTSC_CHANGE
	Port status change mask. More...

#define	XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP \| XHCI_PORTSC_PIC_MASK )
	Port status and control bits which should be preserved. More...

#define	XHCI_OP_PORTPMSC(port) ( 0x404 - 0x10 + ( (port) << 4 ) )
	Port power management status and control register. More...

#define	XHCI_OP_PORTLI(port) ( 0x408 - 0x10 + ( (port) << 4 ) )
	Port link info register. More...

#define	XHCI_OP_PORTHLPMC(port) ( 0x40c - 0x10 + ( (port) << 4 ) )
	Port hardware link power management control register. More...

#define	XHCI_RUN_ERSTSZ(intr) ( 0x28 + ( (intr) << 5 ) )
	Event ring segment table size register. More...

#define	XHCI_RUN_ERSTBA(intr) ( 0x30 + ( (intr) << 5 ) )
	Event ring segment table base address register. More...

#define	XHCI_RUN_ERDP(intr) ( 0x38 + ( (intr) << 5 ) )
	Event ring dequeue pointer register. More...

#define	XHCI_TRB_C 0x01
	Transfer request block cycle bit flag. More...

#define	XHCI_TRB_TC 0x02
	Transfer request block toggle cycle bit flag. More...

#define	XHCI_TRB_CH 0x10
	Transfer request block chain flag. More...

#define	XHCI_TRB_IOC 0x20
	Transfer request block interrupt on completion flag. More...

#define	XHCI_TRB_IDT 0x40
	Transfer request block immediate data flag. More...

#define	XHCI_TRB_TYPE(type) ( (type) << 2 )
	Transfer request block type. More...

#define	XHCI_TRB_TYPE_MASK XHCI_TRB_TYPE ( 0x3f )
	Transfer request block type mask. More...

#define	XHCI_TRB_NORMAL XHCI_TRB_TYPE ( 1 )
	A normal transfer request block. More...

#define	XHCI_TD_SIZE(remaining) ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )
	Construct TD size field. More...

#define	XHCI_TRB_SETUP XHCI_TRB_TYPE ( 2 )
	A setup stage transfer request block. More...

#define	XHCI_SETUP_IN 3
	Setup stage input data direction. More...

#define	XHCI_SETUP_OUT 2
	Setup stage output data direction. More...

#define	XHCI_TRB_DATA XHCI_TRB_TYPE ( 3 )
	A data stage transfer request block. More...

#define	XHCI_DATA_IN 0x01
	Input data direction. More...

#define	XHCI_DATA_OUT 0x00
	Output data direction. More...

#define	XHCI_TRB_STATUS XHCI_TRB_TYPE ( 4 )
	A status stage transfer request block. More...

#define	XHCI_STATUS_IN 0x01
	Input status direction. More...

#define	XHCI_STATUS_OUT 0x00
	Output status direction. More...

#define	XHCI_TRB_LINK XHCI_TRB_TYPE ( 6 )
	A link transfer request block. More...

#define	XHCI_TRB_NOP XHCI_TRB_TYPE ( 8 )
	A no-op transfer request block. More...

#define	XHCI_TRB_ENABLE_SLOT XHCI_TRB_TYPE ( 9 )
	An enable slot transfer request block. More...

#define	XHCI_TRB_DISABLE_SLOT XHCI_TRB_TYPE ( 10 )
	A disable slot transfer request block. More...

#define	XHCI_TRB_ADDRESS_DEVICE XHCI_TRB_TYPE ( 11 )
	An address device transfer request block. More...

#define	XHCI_TRB_CONFIGURE_ENDPOINT XHCI_TRB_TYPE ( 12 )
	A configure endpoint transfer request block. More...

#define	XHCI_TRB_EVALUATE_CONTEXT XHCI_TRB_TYPE ( 13 )
	An evaluate context transfer request block. More...

#define	XHCI_TRB_RESET_ENDPOINT XHCI_TRB_TYPE ( 14 )
	A reset endpoint transfer request block. More...

#define	XHCI_TRB_STOP_ENDPOINT XHCI_TRB_TYPE ( 15 )
	A stop endpoint transfer request block. More...

#define	XHCI_TRB_SET_TR_DEQUEUE_POINTER XHCI_TRB_TYPE ( 16 )
	A set transfer ring dequeue pointer transfer request block. More...

#define	XHCI_TRB_NOP_CMD XHCI_TRB_TYPE ( 23 )
	A no-op command transfer request block. More...

#define	XHCI_TRB_TRANSFER XHCI_TRB_TYPE ( 32 )
	A transfer event transfer request block. More...

#define	XHCI_TRB_COMPLETE XHCI_TRB_TYPE ( 33 )
	A command completion event transfer request block. More...

#define	XHCI_TRB_PORT_STATUS XHCI_TRB_TYPE ( 34 )
	A port status change transfer request block. More...

#define	XHCI_TRB_HOST_CONTROLLER XHCI_TRB_TYPE ( 37 )
	A port status change transfer request block. More...

#define	XHCI_SLOT_INFO(entries, hub, speed, route) ( ( (entries) << 27 ) \| ( (hub) << 26 ) \| ( (speed) << 20 ) \| (route) )
	Construct slot context device info. More...

#define	XHCI_ENDPOINT_STATE_MASK 0x07
	Endpoint state mask. More...

#define	XHCI_EP_TYPE(type) ( (type) << 3 )
	Endpoint type. More...

#define	XHCI_EP_TYPE_CONTROL XHCI_EP_TYPE ( 4 )
	Control endpoint type. More...

#define	XHCI_EP_TYPE_IN XHCI_EP_TYPE ( 4 )
	Input endpoint type. More...

#define	XHCI_EP_TYPE_PERIODIC XHCI_EP_TYPE ( 1 )
	Periodic endpoint type. More...

#define	XHCI_EP_DCS 0x00000001UL
	Endpoint dequeue cycle state. More...

#define	XHCI_EP0_TRB_LEN 8
	Control endpoint average TRB length. More...

#define	XHCI_DBVAL(target, stream) ( (target) \| ( (stream) << 16 ) )
	Calculate doorbell register value. More...

#define	XHCI_CTX_SLOT 0
	Slot context index. More...

#define	XHCI_CTX(address)
	Calculate context index from USB endpoint address. More...

#define	XHCI_CTX_EP0 XHCI_CTX ( 0x00 )
	Endpoint zero context index. More...

#define	XHCI_CTX_END 32
	End of contexts. More...

#define	XHCI_DCI(ctx) ( (ctx) + 0 )
	Device context index. More...

#define	XHCI_ICI(ctx) ( (ctx) + 1 )
	Input context index. More...

#define	XHCI_CMD_TRBS_LOG2 2
	Number of TRBs (excluding Link TRB) in the command ring. More...

#define	XHCI_EVENT_TRBS_LOG2 6
	Number of TRBs in the event ring. More...

#define	XHCI_TRANSFER_TRBS_LOG2 6
	Number of TRBs in a transfer ring. More...

#define	XHCI_USBLEGSUP_MAX_WAIT_MS 100
	Maximum time to wait for BIOS to release ownership. More...

#define	XHCI_STOP_MAX_WAIT_MS 100
	Maximum time to wait for host controller to stop. More...

#define	XHCI_RESET_MAX_WAIT_MS 500
	Maximum time to wait for reset to complete. More...

#define	XHCI_COMMAND_MAX_WAIT_MS USB_CONTROL_MAX_WAIT_MS
	Maximum time to wait for a command to complete. More...

#define	XHCI_COMMAND_ABORT_DELAY_MS 500
	Time to delay after aborting a command. More...

#define	XHCI_PORT_RESET_MAX_WAIT_MS 500
	Maximum time to wait for a port reset to complete. More...

#define	XHCI_PCH 0x0001
	Intel PCH quirk flag. More...

#define	XHCI_PCH_XUSB2PR 0xd0
	Intel PCH USB2 port routing register. More...

#define	XHCI_PCH_XUSB2PRM 0xd4
	Intel PCH USB2 port routing mask register. More...

#define	XHCI_PCH_USB3PSSEN 0xd8
	Intel PCH SuperSpeed enable register. More...

#define	XHCI_PCH_USB3PRM 0xdc
	Intel PCH USB3 port routing mask register. More...

#define	XHCI_BAD_PSIV 0x0002
	Invalid protocol speed ID values quirk. More...

Enumerations
enum	xhci_default_psi_value { XHCI_SPEED_FULL = 1, XHCI_SPEED_LOW = 2, XHCI_SPEED_HIGH = 3, XHCI_SPEED_SUPER = 4 }
	Default PSI values. More...

enum	xhci_completion_code { XHCI_CMPLT_SUCCESS = 1, XHCI_CMPLT_SHORT = 13, XHCI_CMPLT_CMD_STOPPED = 24 }
	xHCI completion codes More...

enum	xhci_endpoint_state { XHCI_ENDPOINT_DISABLED = 0, XHCI_ENDPOINT_RUNNING = 1, XHCI_ENDPOINT_HALTED = 2, XHCI_ENDPOINT_STOPPED = 3, XHCI_ENDPOINT_ERROR = 4 }
	Endpoint states. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

static unsigned int	xhci_ring_fill (struct xhci_trb_ring *ring)
	Calculate space used in TRB ring. More...

static unsigned int	xhci_ring_remaining (struct xhci_trb_ring *ring)
	Calculate space remaining in TRB ring. More...

static physaddr_t	xhci_ring_consumed (struct xhci_trb_ring *ring)
	Calculate physical address of most recently consumed TRB. More...

Detailed Description

USB eXtensible Host Controller Interface (xHCI) driver.

Definition in file xhci.h.

Macro Definition Documentation

◆ XHCI_MIN_ALIGN

#define XHCI_MIN_ALIGN 64

Minimum alignment required for data structures.

With the exception of the scratchpad buffer pages (which are page-aligned), data structures used by xHCI generally require from 16 to 64 byte alignment and must not cross an (xHCI) page boundary. We simplify this requirement by aligning each structure on its own size, with a minimum of a 64 byte alignment.

Definition at line 25 of file xhci.h.

◆ XHCI_MTU

#define XHCI_MTU 65536

Maximum transfer size.

Definition at line 28 of file xhci.h.

◆ XHCI_BAR

#define XHCI_BAR PCI_BASE_ADDRESS_0

xHCI PCI BAR

Definition at line 31 of file xhci.h.

◆ XHCI_CAP_CAPLENGTH

#define XHCI_CAP_CAPLENGTH 0x00

Capability register length.

Definition at line 34 of file xhci.h.

◆ XHCI_CAP_HCIVERSION

#define XHCI_CAP_HCIVERSION 0x02

Host controller interface version number.

Definition at line 37 of file xhci.h.

◆ XHCI_CAP_HCSPARAMS1

#define XHCI_CAP_HCSPARAMS1 0x04

Structural parameters 1.

Definition at line 40 of file xhci.h.

◆ XHCI_HCSPARAMS1_SLOTS

#define XHCI_HCSPARAMS1_SLOTS ( params ) ( ( (params) >> 0 ) & 0xff )

Number of device slots.

Definition at line 43 of file xhci.h.

◆ XHCI_HCSPARAMS1_INTRS

#define XHCI_HCSPARAMS1_INTRS ( params ) ( ( (params) >> 8 ) & 0x3ff )

Number of interrupters.

Definition at line 46 of file xhci.h.

◆ XHCI_HCSPARAMS1_PORTS

#define XHCI_HCSPARAMS1_PORTS ( params ) ( ( (params) >> 24 ) & 0xff )

Number of ports.

Definition at line 49 of file xhci.h.

◆ XHCI_CAP_HCSPARAMS2

#define XHCI_CAP_HCSPARAMS2 0x08

Structural parameters 2.

Definition at line 52 of file xhci.h.

◆ XHCI_HCSPARAMS2_SCRATCHPADS

#define XHCI_HCSPARAMS2_SCRATCHPADS ( params ) ( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )

Number of page-sized scratchpad buffers.

Definition at line 55 of file xhci.h.

◆ XHCI_CAP_HCCPARAMS1

#define XHCI_CAP_HCCPARAMS1 0x10

Capability parameters.

Definition at line 59 of file xhci.h.

◆ XHCI_HCCPARAMS1_ADDR64

#define XHCI_HCCPARAMS1_ADDR64 ( params ) ( ( (params) >> 0 ) & 0x1 )

64-bit addressing capability

Definition at line 62 of file xhci.h.

◆ XHCI_HCCPARAMS1_CSZ_SHIFT

#define XHCI_HCCPARAMS1_CSZ_SHIFT ( params ) ( 5 + ( ( (params) >> 2 ) & 0x1 ) )

Context size shift.

Definition at line 65 of file xhci.h.

◆ XHCI_HCCPARAMS1_XECP

#define XHCI_HCCPARAMS1_XECP ( params ) ( ( ( (params) >> 16 ) & 0xffff ) << 2 )

xHCI extended capabilities pointer

Definition at line 68 of file xhci.h.

◆ XHCI_CAP_DBOFF

#define XHCI_CAP_DBOFF 0x14

Doorbell offset.

Definition at line 71 of file xhci.h.

◆ XHCI_CAP_RTSOFF

#define XHCI_CAP_RTSOFF 0x18

Runtime register space offset.

Definition at line 74 of file xhci.h.

◆ XHCI_XECP_ID

#define XHCI_XECP_ID ( xecp ) ( ( (xecp) >> 0 ) & 0xff )

xHCI extended capability ID

Definition at line 77 of file xhci.h.

◆ XHCI_XECP_NEXT

#define XHCI_XECP_NEXT ( xecp ) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )

Next xHCI extended capability pointer.

Definition at line 80 of file xhci.h.

◆ XHCI_XECP_ID_LEGACY

#define XHCI_XECP_ID_LEGACY 1

USB legacy support extended capability.

Definition at line 83 of file xhci.h.

◆ XHCI_USBLEGSUP_BIOS

#define XHCI_USBLEGSUP_BIOS 0x02

USB legacy support BIOS owned semaphore.

Definition at line 86 of file xhci.h.

◆ XHCI_USBLEGSUP_BIOS_OWNED

#define XHCI_USBLEGSUP_BIOS_OWNED 0x01

USB legacy support BIOS ownership flag.

Definition at line 89 of file xhci.h.

◆ XHCI_USBLEGSUP_OS

#define XHCI_USBLEGSUP_OS 0x03

USB legacy support OS owned semaphore.

Definition at line 92 of file xhci.h.

◆ XHCI_USBLEGSUP_OS_OWNED

#define XHCI_USBLEGSUP_OS_OWNED 0x01

USB legacy support OS ownership flag.

Definition at line 95 of file xhci.h.

◆ XHCI_USBLEGSUP_CTLSTS

#define XHCI_USBLEGSUP_CTLSTS 0x04

USB legacy support control/status.

Definition at line 98 of file xhci.h.

◆ XHCI_XECP_ID_SUPPORTED

#define XHCI_XECP_ID_SUPPORTED 2

Supported protocol extended capability.

Definition at line 101 of file xhci.h.

◆ XHCI_SUPPORTED_REVISION

#define XHCI_SUPPORTED_REVISION 0x00

Supported protocol revision.

Definition at line 104 of file xhci.h.

◆ XHCI_SUPPORTED_REVISION_VER

#define XHCI_SUPPORTED_REVISION_VER ( revision ) ( ( (revision) >> 16 ) & 0xffff )

Supported protocol minor revision.

Definition at line 107 of file xhci.h.

◆ XHCI_SUPPORTED_NAME

#define XHCI_SUPPORTED_NAME 0x04

Supported protocol name.

Definition at line 110 of file xhci.h.

◆ XHCI_SUPPORTED_PORTS

#define XHCI_SUPPORTED_PORTS 0x08

Supported protocol ports.

Definition at line 113 of file xhci.h.

◆ XHCI_SUPPORTED_PORTS_OFFSET

#define XHCI_SUPPORTED_PORTS_OFFSET ( ports ) ( ( (ports) >> 0 ) & 0xff )

Supported protocol port offset.

Definition at line 116 of file xhci.h.

◆ XHCI_SUPPORTED_PORTS_COUNT

#define XHCI_SUPPORTED_PORTS_COUNT ( ports ) ( ( (ports) >> 8 ) & 0xff )

Supported protocol port count.

Definition at line 119 of file xhci.h.

◆ XHCI_SUPPORTED_PORTS_PSIC

#define XHCI_SUPPORTED_PORTS_PSIC ( ports ) ( ( (ports) >> 28 ) & 0x0f )

Supported protocol PSI count.

Definition at line 122 of file xhci.h.

◆ XHCI_SUPPORTED_SLOT

#define XHCI_SUPPORTED_SLOT 0x0c

Supported protocol slot.

Definition at line 125 of file xhci.h.

◆ XHCI_SUPPORTED_SLOT_TYPE

#define XHCI_SUPPORTED_SLOT_TYPE ( slot ) ( ( (slot) >> 0 ) & 0x1f )

Supported protocol slot type.

Definition at line 128 of file xhci.h.

◆ XHCI_SUPPORTED_PSI

#define XHCI_SUPPORTED_PSI ( index ) ( 0x10 + ( (index) * 4 ) )

Supported protocol PSI.

Definition at line 131 of file xhci.h.

◆ XHCI_SUPPORTED_PSI_VALUE

#define XHCI_SUPPORTED_PSI_VALUE ( psi ) ( ( (psi) >> 0 ) & 0x0f )

Supported protocol PSI value.

Definition at line 134 of file xhci.h.

◆ XHCI_SUPPORTED_PSI_MANTISSA

#define XHCI_SUPPORTED_PSI_MANTISSA ( psi ) ( ( (psi) >> 16 ) & 0xffff )

Supported protocol PSI mantissa.

Definition at line 137 of file xhci.h.

◆ XHCI_SUPPORTED_PSI_EXPONENT

#define XHCI_SUPPORTED_PSI_EXPONENT ( psi ) ( ( (psi) >> 4 ) & 0x03 )

Supported protocol PSI exponent.

Definition at line 140 of file xhci.h.

◆ XHCI_OP_USBCMD

#define XHCI_OP_USBCMD 0x00

USB command register.

Definition at line 155 of file xhci.h.

◆ XHCI_USBCMD_RUN

#define XHCI_USBCMD_RUN 0x00000001UL

Run/stop.

Definition at line 158 of file xhci.h.

◆ XHCI_USBCMD_HCRST

#define XHCI_USBCMD_HCRST 0x00000002UL

Host controller reset.

Definition at line 161 of file xhci.h.

◆ XHCI_OP_USBSTS

#define XHCI_OP_USBSTS 0x04

USB status register.

Definition at line 164 of file xhci.h.

◆ XHCI_USBSTS_HCH

#define XHCI_USBSTS_HCH 0x00000001UL

Host controller halted.

Definition at line 167 of file xhci.h.

◆ XHCI_OP_PAGESIZE

#define XHCI_OP_PAGESIZE 0x08

Page size register.

Definition at line 170 of file xhci.h.

◆ XHCI_PAGESIZE

#define XHCI_PAGESIZE ( pagesize ) ( (pagesize) << 12 )

Page size.

Definition at line 173 of file xhci.h.

◆ XHCI_OP_DNCTRL

#define XHCI_OP_DNCTRL 0x14

Device notifcation control register.

Definition at line 176 of file xhci.h.

◆ XHCI_OP_CRCR

#define XHCI_OP_CRCR 0x18

Command ring control register.

Definition at line 179 of file xhci.h.

◆ XHCI_CRCR_RCS

#define XHCI_CRCR_RCS 0x00000001UL

Command ring cycle state.

Definition at line 182 of file xhci.h.

◆ XHCI_CRCR_CA

#define XHCI_CRCR_CA 0x00000004UL

Command abort.

Definition at line 185 of file xhci.h.

◆ XHCI_CRCR_CRR

#define XHCI_CRCR_CRR 0x00000008UL

Command ring running.

Definition at line 188 of file xhci.h.

◆ XHCI_OP_DCBAAP

#define XHCI_OP_DCBAAP 0x30

Device context base address array pointer.

Definition at line 191 of file xhci.h.

◆ XHCI_OP_CONFIG

#define XHCI_OP_CONFIG 0x38

Configure register.

Definition at line 194 of file xhci.h.

◆ XHCI_CONFIG_MAX_SLOTS_EN

#define XHCI_CONFIG_MAX_SLOTS_EN ( slots ) ( (slots) << 0 )

Maximum device slots enabled.

Definition at line 197 of file xhci.h.

◆ XHCI_CONFIG_MAX_SLOTS_EN_MASK

#define XHCI_CONFIG_MAX_SLOTS_EN_MASK XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )

Maximum device slots enabled mask.

Definition at line 200 of file xhci.h.

◆ XHCI_OP_PORTSC

#define XHCI_OP_PORTSC ( port ) ( 0x400 - 0x10 + ( (port) << 4 ) )

Port status and control register.

Definition at line 204 of file xhci.h.

◆ XHCI_PORTSC_CCS

#define XHCI_PORTSC_CCS 0x00000001UL

Current connect status.

Definition at line 207 of file xhci.h.

◆ XHCI_PORTSC_PED

#define XHCI_PORTSC_PED 0x00000002UL

Port enabled.

Definition at line 210 of file xhci.h.

◆ XHCI_PORTSC_PR

#define XHCI_PORTSC_PR 0x00000010UL

Port reset.

Definition at line 213 of file xhci.h.

◆ XHCI_PORTSC_PLS

#define XHCI_PORTSC_PLS ( pls ) ( (pls) << 5 )

Port link state.

Definition at line 216 of file xhci.h.

◆ XHCI_PORTSC_PLS_DISABLED

#define XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 )

Disabled port link state.

Definition at line 219 of file xhci.h.

◆ XHCI_PORTSC_PLS_RXDETECT

#define XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 )

RxDetect port link state.

Definition at line 222 of file xhci.h.

◆ XHCI_PORTSC_PLS_MASK

#define XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf )

Port link state mask.

Definition at line 225 of file xhci.h.

◆ XHCI_PORTSC_PP

#define XHCI_PORTSC_PP 0x00000200UL

Port power.

Definition at line 228 of file xhci.h.

◆ XHCI_PORT_POWER_DELAY_MS

#define XHCI_PORT_POWER_DELAY_MS 20

Time to delay after enabling power to a port.

Definition at line 231 of file xhci.h.

◆ XHCI_PORTSC_PSIV

#define XHCI_PORTSC_PSIV ( portsc ) ( ( (portsc) >> 10 ) & 0xf )

Port speed ID value.

Definition at line 234 of file xhci.h.

◆ XHCI_PORTSC_PIC

#define XHCI_PORTSC_PIC ( indicators ) ( (indicators) << 14 )

Port indicator control.

Definition at line 237 of file xhci.h.

◆ XHCI_PORTSC_PIC_MASK

#define XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 )

Port indicator control mask.

Definition at line 240 of file xhci.h.

◆ XHCI_PORTSC_LWS

#define XHCI_PORTSC_LWS 0x00010000UL

Port link state write strobe.

Definition at line 243 of file xhci.h.

◆ XHCI_LINK_STATE_DELAY_MS

#define XHCI_LINK_STATE_DELAY_MS 100

Time to delay after writing the port link state.

Definition at line 246 of file xhci.h.

◆ XHCI_PORTSC_CSC

#define XHCI_PORTSC_CSC 0x00020000UL

Connect status change.

Definition at line 249 of file xhci.h.

◆ XHCI_PORTSC_PEC

#define XHCI_PORTSC_PEC 0x00040000UL

Port enabled/disabled change.

Definition at line 252 of file xhci.h.

◆ XHCI_PORTSC_WRC

#define XHCI_PORTSC_WRC 0x00080000UL

Warm port reset change.

Definition at line 255 of file xhci.h.

◆ XHCI_PORTSC_OCC

#define XHCI_PORTSC_OCC 0x00100000UL

Over-current change.

Definition at line 258 of file xhci.h.

◆ XHCI_PORTSC_PRC

#define XHCI_PORTSC_PRC 0x00200000UL

Port reset change.

Definition at line 261 of file xhci.h.

◆ XHCI_PORTSC_PLC

#define XHCI_PORTSC_PLC 0x00400000UL

Port link state change.

Definition at line 264 of file xhci.h.

◆ XHCI_PORTSC_CEC

#define XHCI_PORTSC_CEC 0x00800000UL

Port config error change.

Definition at line 267 of file xhci.h.

◆ XHCI_PORTSC_CHANGE

#define XHCI_PORTSC_CHANGE

Value:

( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \
          XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
          XHCI_PORTSC_CEC )

Port status change mask.

Definition at line 270 of file xhci.h.

◆ XHCI_PORTSC_PRESERVE

#define XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK )

Port status and control bits which should be preserved.

The port status and control register is a horrendous mix of differing semantics. Some bits are written to only when a separate write strobe bit is set. Some bits should be preserved when modifying other bits. Some bits will be cleared if written back as a one. Most excitingly, the "port enabled" bit has the semantics that 1=enabled, 0=disabled, yet writing a 1 will disable the port.

Definition at line 284 of file xhci.h.

◆ XHCI_OP_PORTPMSC

#define XHCI_OP_PORTPMSC ( port ) ( 0x404 - 0x10 + ( (port) << 4 ) )

Port power management status and control register.

Definition at line 287 of file xhci.h.

◆ XHCI_OP_PORTLI

#define XHCI_OP_PORTLI ( port ) ( 0x408 - 0x10 + ( (port) << 4 ) )

Port link info register.

Definition at line 290 of file xhci.h.

◆ XHCI_OP_PORTHLPMC

#define XHCI_OP_PORTHLPMC ( port ) ( 0x40c - 0x10 + ( (port) << 4 ) )

Port hardware link power management control register.

Definition at line 293 of file xhci.h.

◆ XHCI_RUN_ERSTSZ

#define XHCI_RUN_ERSTSZ ( intr ) ( 0x28 + ( (intr) << 5 ) )

Event ring segment table size register.

Definition at line 296 of file xhci.h.

◆ XHCI_RUN_ERSTBA

#define XHCI_RUN_ERSTBA ( intr ) ( 0x30 + ( (intr) << 5 ) )

Event ring segment table base address register.

Definition at line 299 of file xhci.h.

◆ XHCI_RUN_ERDP

#define XHCI_RUN_ERDP ( intr ) ( 0x38 + ( (intr) << 5 ) )

Event ring dequeue pointer register.

Definition at line 302 of file xhci.h.

◆ XHCI_TRB_C

#define XHCI_TRB_C 0x01

Transfer request block cycle bit flag.

Definition at line 329 of file xhci.h.

◆ XHCI_TRB_TC

#define XHCI_TRB_TC 0x02

Transfer request block toggle cycle bit flag.

Definition at line 332 of file xhci.h.

◆ XHCI_TRB_CH

#define XHCI_TRB_CH 0x10

Transfer request block chain flag.

Definition at line 335 of file xhci.h.

◆ XHCI_TRB_IOC

#define XHCI_TRB_IOC 0x20

Transfer request block interrupt on completion flag.

Definition at line 338 of file xhci.h.

◆ XHCI_TRB_IDT

#define XHCI_TRB_IDT 0x40

Transfer request block immediate data flag.

Definition at line 341 of file xhci.h.

◆ XHCI_TRB_TYPE

#define XHCI_TRB_TYPE ( type ) ( (type) << 2 )

Transfer request block type.

Definition at line 344 of file xhci.h.

◆ XHCI_TRB_TYPE_MASK

#define XHCI_TRB_TYPE_MASK XHCI_TRB_TYPE ( 0x3f )

Transfer request block type mask.

Definition at line 347 of file xhci.h.

◆ XHCI_TRB_NORMAL

#define XHCI_TRB_NORMAL XHCI_TRB_TYPE ( 1 )

A normal transfer request block.

Definition at line 364 of file xhci.h.

◆ XHCI_TD_SIZE

#define XHCI_TD_SIZE ( remaining ) ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )

Construct TD size field.

Definition at line 367 of file xhci.h.

◆ XHCI_TRB_SETUP

#define XHCI_TRB_SETUP XHCI_TRB_TYPE ( 2 )

A setup stage transfer request block.

Definition at line 387 of file xhci.h.

◆ XHCI_SETUP_IN

#define XHCI_SETUP_IN 3

Setup stage input data direction.

Definition at line 390 of file xhci.h.

◆ XHCI_SETUP_OUT

#define XHCI_SETUP_OUT 2

Setup stage output data direction.

Definition at line 393 of file xhci.h.

◆ XHCI_TRB_DATA

#define XHCI_TRB_DATA XHCI_TRB_TYPE ( 3 )

A data stage transfer request block.

Definition at line 412 of file xhci.h.

◆ XHCI_DATA_IN

#define XHCI_DATA_IN 0x01

Input data direction.

Definition at line 415 of file xhci.h.

◆ XHCI_DATA_OUT

#define XHCI_DATA_OUT 0x00

Output data direction.

Definition at line 418 of file xhci.h.

◆ XHCI_TRB_STATUS

#define XHCI_TRB_STATUS XHCI_TRB_TYPE ( 4 )

A status stage transfer request block.

Definition at line 437 of file xhci.h.

◆ XHCI_STATUS_IN

#define XHCI_STATUS_IN 0x01

Input status direction.

Definition at line 440 of file xhci.h.

◆ XHCI_STATUS_OUT

#define XHCI_STATUS_OUT 0x00

Output status direction.

Definition at line 443 of file xhci.h.

◆ XHCI_TRB_LINK

#define XHCI_TRB_LINK XHCI_TRB_TYPE ( 6 )

A link transfer request block.

Definition at line 460 of file xhci.h.

◆ XHCI_TRB_NOP

#define XHCI_TRB_NOP XHCI_TRB_TYPE ( 8 )

A no-op transfer request block.

Definition at line 463 of file xhci.h.

◆ XHCI_TRB_ENABLE_SLOT

#define XHCI_TRB_ENABLE_SLOT XHCI_TRB_TYPE ( 9 )

An enable slot transfer request block.

Definition at line 482 of file xhci.h.

◆ XHCI_TRB_DISABLE_SLOT

#define XHCI_TRB_DISABLE_SLOT XHCI_TRB_TYPE ( 10 )

A disable slot transfer request block.

Definition at line 501 of file xhci.h.

◆ XHCI_TRB_ADDRESS_DEVICE

#define XHCI_TRB_ADDRESS_DEVICE XHCI_TRB_TYPE ( 11 )

An address device transfer request block.

Definition at line 520 of file xhci.h.

◆ XHCI_TRB_CONFIGURE_ENDPOINT

#define XHCI_TRB_CONFIGURE_ENDPOINT XHCI_TRB_TYPE ( 12 )

A configure endpoint transfer request block.

Definition at line 523 of file xhci.h.

◆ XHCI_TRB_EVALUATE_CONTEXT

#define XHCI_TRB_EVALUATE_CONTEXT XHCI_TRB_TYPE ( 13 )

An evaluate context transfer request block.

Definition at line 526 of file xhci.h.

◆ XHCI_TRB_RESET_ENDPOINT

#define XHCI_TRB_RESET_ENDPOINT XHCI_TRB_TYPE ( 14 )

A reset endpoint transfer request block.

Definition at line 545 of file xhci.h.

◆ XHCI_TRB_STOP_ENDPOINT

#define XHCI_TRB_STOP_ENDPOINT XHCI_TRB_TYPE ( 15 )

A stop endpoint transfer request block.

Definition at line 564 of file xhci.h.

◆ XHCI_TRB_SET_TR_DEQUEUE_POINTER

#define XHCI_TRB_SET_TR_DEQUEUE_POINTER XHCI_TRB_TYPE ( 16 )

A set transfer ring dequeue pointer transfer request block.

Definition at line 583 of file xhci.h.

◆ XHCI_TRB_NOP_CMD

#define XHCI_TRB_NOP_CMD XHCI_TRB_TYPE ( 23 )

A no-op command transfer request block.

Definition at line 586 of file xhci.h.

◆ XHCI_TRB_TRANSFER

#define XHCI_TRB_TRANSFER XHCI_TRB_TYPE ( 32 )

A transfer event transfer request block.

Definition at line 609 of file xhci.h.

◆ XHCI_TRB_COMPLETE

#define XHCI_TRB_COMPLETE XHCI_TRB_TYPE ( 33 )

A command completion event transfer request block.

Definition at line 630 of file xhci.h.

◆ XHCI_TRB_PORT_STATUS

#define XHCI_TRB_PORT_STATUS XHCI_TRB_TYPE ( 34 )

A port status change transfer request block.

Definition at line 661 of file xhci.h.

◆ XHCI_TRB_HOST_CONTROLLER

#define XHCI_TRB_HOST_CONTROLLER XHCI_TRB_TYPE ( 37 )

A port status change transfer request block.

Definition at line 680 of file xhci.h.

◆ XHCI_SLOT_INFO

#define XHCI_SLOT_INFO	(	entries,
		hub,
		speed,
		route
	)	( ( (entries) << 27 ) \| ( (hub) << 26 ) \| ( (speed) << 20 ) \| (route) )

Construct slot context device info.

Definition at line 765 of file xhci.h.

◆ XHCI_ENDPOINT_STATE_MASK

#define XHCI_ENDPOINT_STATE_MASK 0x07

Endpoint state mask.

Definition at line 809 of file xhci.h.

◆ XHCI_EP_TYPE

#define XHCI_EP_TYPE ( type ) ( (type) << 3 )

Endpoint type.

Definition at line 812 of file xhci.h.

◆ XHCI_EP_TYPE_CONTROL

#define XHCI_EP_TYPE_CONTROL XHCI_EP_TYPE ( 4 )

Control endpoint type.

Definition at line 815 of file xhci.h.

◆ XHCI_EP_TYPE_IN

#define XHCI_EP_TYPE_IN XHCI_EP_TYPE ( 4 )

Input endpoint type.

Definition at line 818 of file xhci.h.

◆ XHCI_EP_TYPE_PERIODIC

#define XHCI_EP_TYPE_PERIODIC XHCI_EP_TYPE ( 1 )

Periodic endpoint type.

Definition at line 821 of file xhci.h.

◆ XHCI_EP_DCS

#define XHCI_EP_DCS 0x00000001UL

Endpoint dequeue cycle state.

Definition at line 824 of file xhci.h.

◆ XHCI_EP0_TRB_LEN

#define XHCI_EP0_TRB_LEN 8

Control endpoint average TRB length.

Definition at line 827 of file xhci.h.

◆ XHCI_DBVAL

#define XHCI_DBVAL	(	target,
		stream
	)	( (target) \| ( (stream) << 16 ) )

Calculate doorbell register value.

Parameters

target	Doorbell target
stream	Doorbell stream ID

Return values

dbval Doorbell register value

Definition at line 889 of file xhci.h.

◆ XHCI_CTX_SLOT

#define XHCI_CTX_SLOT 0

Slot context index.

Definition at line 943 of file xhci.h.

◆ XHCI_CTX

#define XHCI_CTX ( address )

Value:

( (address) ? ( ( ( (address) & 0x0f ) << 1 ) | \

( ( (address) & 0x80 ) >> 7 ) ) : 1 )

address

uint64_t address

Base address.

Definition: ena.h:24

Calculate context index from USB endpoint address.

Definition at line 946 of file xhci.h.

◆ XHCI_CTX_EP0

#define XHCI_CTX_EP0 XHCI_CTX ( 0x00 )

Endpoint zero context index.

Definition at line 951 of file xhci.h.

◆ XHCI_CTX_END

#define XHCI_CTX_END 32

End of contexts.

Definition at line 954 of file xhci.h.

◆ XHCI_DCI

#define XHCI_DCI ( ctx ) ( (ctx) + 0 )

Device context index.

Definition at line 957 of file xhci.h.

◆ XHCI_ICI

#define XHCI_ICI ( ctx ) ( (ctx) + 1 )

Input context index.

Definition at line 960 of file xhci.h.

◆ XHCI_CMD_TRBS_LOG2

#define XHCI_CMD_TRBS_LOG2 2

Number of TRBs (excluding Link TRB) in the command ring.

This is a policy decision.

Definition at line 966 of file xhci.h.

◆ XHCI_EVENT_TRBS_LOG2

#define XHCI_EVENT_TRBS_LOG2 6

Number of TRBs in the event ring.

This is a policy decision.

Definition at line 972 of file xhci.h.

◆ XHCI_TRANSFER_TRBS_LOG2

#define XHCI_TRANSFER_TRBS_LOG2 6

Number of TRBs in a transfer ring.

This is a policy decision.

Definition at line 978 of file xhci.h.

◆ XHCI_USBLEGSUP_MAX_WAIT_MS

#define XHCI_USBLEGSUP_MAX_WAIT_MS 100

Maximum time to wait for BIOS to release ownership.

This is a policy decision.

Definition at line 984 of file xhci.h.

◆ XHCI_STOP_MAX_WAIT_MS

#define XHCI_STOP_MAX_WAIT_MS 100

Maximum time to wait for host controller to stop.

This is a policy decision.

Definition at line 990 of file xhci.h.

◆ XHCI_RESET_MAX_WAIT_MS

#define XHCI_RESET_MAX_WAIT_MS 500

Maximum time to wait for reset to complete.

This is a policy decision.

Definition at line 996 of file xhci.h.

◆ XHCI_COMMAND_MAX_WAIT_MS

#define XHCI_COMMAND_MAX_WAIT_MS USB_CONTROL_MAX_WAIT_MS

Maximum time to wait for a command to complete.

The "address device" command involves waiting for a response to a USB control transaction, and so we must wait for up to the 5000ms that USB allows for devices to respond to control transactions.

Definition at line 1004 of file xhci.h.

◆ XHCI_COMMAND_ABORT_DELAY_MS

#define XHCI_COMMAND_ABORT_DELAY_MS 500

Time to delay after aborting a command.

This is a policy decision

Definition at line 1010 of file xhci.h.

◆ XHCI_PORT_RESET_MAX_WAIT_MS

#define XHCI_PORT_RESET_MAX_WAIT_MS 500

Maximum time to wait for a port reset to complete.

This is a policy decision.

Definition at line 1016 of file xhci.h.

◆ XHCI_PCH

#define XHCI_PCH 0x0001

Intel PCH quirk flag.

Definition at line 1027 of file xhci.h.

◆ XHCI_PCH_XUSB2PR

#define XHCI_PCH_XUSB2PR 0xd0

Intel PCH USB2 port routing register.

Definition at line 1030 of file xhci.h.

◆ XHCI_PCH_XUSB2PRM

#define XHCI_PCH_XUSB2PRM 0xd4

Intel PCH USB2 port routing mask register.

Definition at line 1033 of file xhci.h.

◆ XHCI_PCH_USB3PSSEN

#define XHCI_PCH_USB3PSSEN 0xd8

Intel PCH SuperSpeed enable register.

Definition at line 1036 of file xhci.h.

◆ XHCI_PCH_USB3PRM

#define XHCI_PCH_USB3PRM 0xdc

Intel PCH USB3 port routing mask register.

Definition at line 1039 of file xhci.h.

◆ XHCI_BAD_PSIV

#define XHCI_BAD_PSIV 0x0002

Invalid protocol speed ID values quirk.

Definition at line 1042 of file xhci.h.

Enumeration Type Documentation

◆ xhci_default_psi_value

enum xhci_default_psi_value

Default PSI values.

Enumerator
XHCI_SPEED_FULL	Full speed (12Mbps)
XHCI_SPEED_LOW	Low speed (1.5Mbps)
XHCI_SPEED_HIGH	High speed (480Mbps)
XHCI_SPEED_SUPER	Super speed.

Definition at line 143 of file xhci.h.

                             {
         /** Full speed (12Mbps) */
         XHCI_SPEED_FULL = 1,
         /** Low speed (1.5Mbps) */
         XHCI_SPEED_LOW = 2,
         /** High speed (480Mbps) */
         XHCI_SPEED_HIGH = 3,
         /** Super speed */
         XHCI_SPEED_SUPER = 4,
 };

◆ xhci_completion_code

enum xhci_completion_code

xHCI completion codes

Enumerator
XHCI_CMPLT_SUCCESS	Success.
XHCI_CMPLT_SHORT	Short packet.
XHCI_CMPLT_CMD_STOPPED	Command ring stopped.

Definition at line 633 of file xhci.h.

                           {
         /** Success */
         XHCI_CMPLT_SUCCESS = 1,
         /** Short packet */
         XHCI_CMPLT_SHORT = 13,
         /** Command ring stopped */
         XHCI_CMPLT_CMD_STOPPED = 24,
 };

◆ xhci_endpoint_state

enum xhci_endpoint_state

Endpoint states.

Enumerator
XHCI_ENDPOINT_DISABLED	Endpoint is disabled.
XHCI_ENDPOINT_RUNNING	Endpoint is running.
XHCI_ENDPOINT_HALTED	Endpoint is halted due to a USB Halt condition.
XHCI_ENDPOINT_STOPPED	Endpoint is stopped.
XHCI_ENDPOINT_ERROR	Endpoint is halted due to a TRB error.

Definition at line 795 of file xhci.h.

                          {
         /** Endpoint is disabled */
         XHCI_ENDPOINT_DISABLED = 0,
         /** Endpoint is running */
         XHCI_ENDPOINT_RUNNING = 1,
         /** Endpoint is halted due to a USB Halt condition */
         XHCI_ENDPOINT_HALTED = 2,
         /** Endpoint is stopped */
         XHCI_ENDPOINT_STOPPED = 3,
         /** Endpoint is halted due to a TRB error */
         XHCI_ENDPOINT_ERROR = 4,
 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

◆ xhci_ring_fill()

static unsigned int xhci_ring_fill ( struct xhci_trb_ring * ring )

inlinestatic

Calculate space used in TRB ring.

Parameters

ring TRB ring

Return values

fill	Number of entries used

Definition at line 898 of file xhci.h.

                                               {
 
         return ( ring->prod - ring->cons );
 }

References xhci_trb_ring::cons, and xhci_trb_ring::prod.

Referenced by xhci_dequeue(), xhci_endpoint_close(), and xhci_ring_remaining().

◆ xhci_ring_remaining()

static unsigned int xhci_ring_remaining ( struct xhci_trb_ring * ring )

inlinestatic

Calculate space remaining in TRB ring.

Parameters

ring TRB ring

Return values

remaining Number of entries remaining

xHCI does not allow us to completely fill a ring; there must be at least one free entry (excluding the Link TRB).

Definition at line 913 of file xhci.h.

                                                    {
         unsigned int fill = xhci_ring_fill ( ring );
 
         /* We choose to utilise rings with ( 2^n + 1 ) entries, with
          * the final entry being a Link TRB.  The maximum fill level
          * is therefore
          *
          *   ( ( 2^n + 1 ) - 1 (Link TRB) - 1 (one slot always empty)
          *       == ( 2^n - 1 )
          *
          * which is therefore equal to the ring mask.
          */
         assert ( fill <= ring->mask );
         return ( ring->mask - fill );
 }

References assert(), fill, xhci_trb_ring::mask, and xhci_ring_fill().

Referenced by xhci_enqueue(), and xhci_enqueue_multi().

◆ xhci_ring_consumed()

static physaddr_t xhci_ring_consumed ( struct xhci_trb_ring * ring )

inlinestatic

Calculate physical address of most recently consumed TRB.

Parameters

ring TRB ring

Return values

trb	TRB physical address

Definition at line 936 of file xhci.h.

                                                   {
         unsigned int index = ( ( ring->cons - 1 ) & ring->mask );
 
         return virt_to_phys ( &ring->trb[index] );
 }

References xhci_trb_ring::cons, index, xhci_trb_ring::mask, xhci_trb_ring::trb, and virt_to_phys().

Referenced by xhci_complete(), and xhci_transfer().

Data Structures

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ XHCI_MIN_ALIGN

◆ XHCI_MTU

◆ XHCI_BAR

◆ XHCI_CAP_CAPLENGTH

◆ XHCI_CAP_HCIVERSION

◆ XHCI_CAP_HCSPARAMS1

◆ XHCI_HCSPARAMS1_SLOTS

◆ XHCI_HCSPARAMS1_INTRS

◆ XHCI_HCSPARAMS1_PORTS

◆ XHCI_CAP_HCSPARAMS2

◆ XHCI_HCSPARAMS2_SCRATCHPADS

◆ XHCI_CAP_HCCPARAMS1

◆ XHCI_HCCPARAMS1_ADDR64

◆ XHCI_HCCPARAMS1_CSZ_SHIFT

◆ XHCI_HCCPARAMS1_XECP

◆ XHCI_CAP_DBOFF

◆ XHCI_CAP_RTSOFF

◆ XHCI_XECP_ID

◆ XHCI_XECP_NEXT

◆ XHCI_XECP_ID_LEGACY

◆ XHCI_USBLEGSUP_BIOS

◆ XHCI_USBLEGSUP_BIOS_OWNED

◆ XHCI_USBLEGSUP_OS

◆ XHCI_USBLEGSUP_OS_OWNED

◆ XHCI_USBLEGSUP_CTLSTS

◆ XHCI_XECP_ID_SUPPORTED

◆ XHCI_SUPPORTED_REVISION

◆ XHCI_SUPPORTED_REVISION_VER

◆ XHCI_SUPPORTED_NAME

◆ XHCI_SUPPORTED_PORTS

◆ XHCI_SUPPORTED_PORTS_OFFSET

◆ XHCI_SUPPORTED_PORTS_COUNT

◆ XHCI_SUPPORTED_PORTS_PSIC

◆ XHCI_SUPPORTED_SLOT

◆ XHCI_SUPPORTED_SLOT_TYPE

◆ XHCI_SUPPORTED_PSI

◆ XHCI_SUPPORTED_PSI_VALUE

◆ XHCI_SUPPORTED_PSI_MANTISSA

◆ XHCI_SUPPORTED_PSI_EXPONENT

◆ XHCI_OP_USBCMD

◆ XHCI_USBCMD_RUN

◆ XHCI_USBCMD_HCRST

◆ XHCI_OP_USBSTS

◆ XHCI_USBSTS_HCH

◆ XHCI_OP_PAGESIZE

◆ XHCI_PAGESIZE

◆ XHCI_OP_DNCTRL

◆ XHCI_OP_CRCR

◆ XHCI_CRCR_RCS

◆ XHCI_CRCR_CA

◆ XHCI_CRCR_CRR

◆ XHCI_OP_DCBAAP

◆ XHCI_OP_CONFIG

◆ XHCI_CONFIG_MAX_SLOTS_EN

◆ XHCI_CONFIG_MAX_SLOTS_EN_MASK

◆ XHCI_OP_PORTSC

◆ XHCI_PORTSC_CCS

◆ XHCI_PORTSC_PED

◆ XHCI_PORTSC_PR

◆ XHCI_PORTSC_PLS

◆ XHCI_PORTSC_PLS_DISABLED

◆ XHCI_PORTSC_PLS_RXDETECT

◆ XHCI_PORTSC_PLS_MASK

◆ XHCI_PORTSC_PP

◆ XHCI_PORT_POWER_DELAY_MS

◆ XHCI_PORTSC_PSIV

◆ XHCI_PORTSC_PIC

◆ XHCI_PORTSC_PIC_MASK

◆ XHCI_PORTSC_LWS

◆ XHCI_LINK_STATE_DELAY_MS

◆ XHCI_PORTSC_CSC

◆ XHCI_PORTSC_PEC

◆ XHCI_PORTSC_WRC

◆ XHCI_PORTSC_OCC