iPXE
ar9003_eeprom.h
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00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef AR9003_EEPROM_H
00021 #define AR9003_EEPROM_H
00022 
00023 FILE_LICENCE ( BSD2 );
00024 
00025 #define AR9300_EEP_VER               0xD000
00026 #define AR9300_EEP_VER_MINOR_MASK    0xFFF
00027 #define AR9300_EEP_MINOR_VER_1       0x1
00028 #define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1
00029 
00030 /* 16-bit offset location start of calibration struct */
00031 #define AR9300_EEP_START_LOC         256
00032 #define AR9300_NUM_5G_CAL_PIERS      8
00033 #define AR9300_NUM_2G_CAL_PIERS      3
00034 #define AR9300_NUM_5G_20_TARGET_POWERS  8
00035 #define AR9300_NUM_5G_40_TARGET_POWERS  8
00036 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
00037 #define AR9300_NUM_2G_20_TARGET_POWERS  3
00038 #define AR9300_NUM_2G_40_TARGET_POWERS  3
00039 /* #define AR9300_NUM_CTLS              21 */
00040 #define AR9300_NUM_CTLS_5G           9
00041 #define AR9300_NUM_CTLS_2G           12
00042 #define AR9300_NUM_BAND_EDGES_5G     8
00043 #define AR9300_NUM_BAND_EDGES_2G     4
00044 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
00045 #define AR9300_EEPMISC_WOW           0x02
00046 #define AR9300_CUSTOMER_DATA_SIZE    20
00047 
00048 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
00049 #define AR9300_MAX_CHAINS            3
00050 #define AR9300_ANT_16S               25
00051 #define AR9300_FUTURE_MODAL_SZ       6
00052 
00053 #define AR9300_PAPRD_RATE_MASK          0x01ffffff
00054 #define AR9300_PAPRD_SCALE_1            0x0e000000
00055 #define AR9300_PAPRD_SCALE_1_S          25
00056 #define AR9300_PAPRD_SCALE_2            0x70000000
00057 #define AR9300_PAPRD_SCALE_2_S          28
00058 
00059 /* Delta from which to start power to pdadc table */
00060 /* This offset is used in both open loop and closed loop power control
00061  * schemes. In open loop power control, it is not really needed, but for
00062  * the "sake of consistency" it was kept. For certain AP designs, this
00063  * value is overwritten by the value in the flag "pwrTableOffset" just
00064  * before writing the pdadc vs pwr into the chip registers.
00065  */
00066 #define AR9300_PWR_TABLE_OFFSET  0
00067 
00068 /* byte addressable */
00069 #define AR9300_EEPROM_SIZE (16*1024)
00070 
00071 #define AR9300_BASE_ADDR_4K 0xfff
00072 #define AR9300_BASE_ADDR 0x3ff
00073 #define AR9300_BASE_ADDR_512 0x1ff
00074 
00075 #define AR9300_OTP_BASE                 0x14000
00076 #define AR9300_OTP_STATUS               0x15f18
00077 #define AR9300_OTP_STATUS_TYPE          0x7
00078 #define AR9300_OTP_STATUS_VALID         0x4
00079 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
00080 #define AR9300_OTP_STATUS_SM_BUSY       0x1
00081 #define AR9300_OTP_READ_DATA            0x15f1c
00082 
00083 enum targetPowerHTRates {
00084         HT_TARGET_RATE_0_8_16,
00085         HT_TARGET_RATE_1_3_9_11_17_19,
00086         HT_TARGET_RATE_4,
00087         HT_TARGET_RATE_5,
00088         HT_TARGET_RATE_6,
00089         HT_TARGET_RATE_7,
00090         HT_TARGET_RATE_12,
00091         HT_TARGET_RATE_13,
00092         HT_TARGET_RATE_14,
00093         HT_TARGET_RATE_15,
00094         HT_TARGET_RATE_20,
00095         HT_TARGET_RATE_21,
00096         HT_TARGET_RATE_22,
00097         HT_TARGET_RATE_23
00098 };
00099 
00100 enum targetPowerLegacyRates {
00101         LEGACY_TARGET_RATE_6_24,
00102         LEGACY_TARGET_RATE_36,
00103         LEGACY_TARGET_RATE_48,
00104         LEGACY_TARGET_RATE_54
00105 };
00106 
00107 enum targetPowerCckRates {
00108         LEGACY_TARGET_RATE_1L_5L,
00109         LEGACY_TARGET_RATE_5S,
00110         LEGACY_TARGET_RATE_11L,
00111         LEGACY_TARGET_RATE_11S
00112 };
00113 
00114 enum ar9300_Rates {
00115         ALL_TARGET_LEGACY_6_24,
00116         ALL_TARGET_LEGACY_36,
00117         ALL_TARGET_LEGACY_48,
00118         ALL_TARGET_LEGACY_54,
00119         ALL_TARGET_LEGACY_1L_5L,
00120         ALL_TARGET_LEGACY_5S,
00121         ALL_TARGET_LEGACY_11L,
00122         ALL_TARGET_LEGACY_11S,
00123         ALL_TARGET_HT20_0_8_16,
00124         ALL_TARGET_HT20_1_3_9_11_17_19,
00125         ALL_TARGET_HT20_4,
00126         ALL_TARGET_HT20_5,
00127         ALL_TARGET_HT20_6,
00128         ALL_TARGET_HT20_7,
00129         ALL_TARGET_HT20_12,
00130         ALL_TARGET_HT20_13,
00131         ALL_TARGET_HT20_14,
00132         ALL_TARGET_HT20_15,
00133         ALL_TARGET_HT20_20,
00134         ALL_TARGET_HT20_21,
00135         ALL_TARGET_HT20_22,
00136         ALL_TARGET_HT20_23,
00137         ALL_TARGET_HT40_0_8_16,
00138         ALL_TARGET_HT40_1_3_9_11_17_19,
00139         ALL_TARGET_HT40_4,
00140         ALL_TARGET_HT40_5,
00141         ALL_TARGET_HT40_6,
00142         ALL_TARGET_HT40_7,
00143         ALL_TARGET_HT40_12,
00144         ALL_TARGET_HT40_13,
00145         ALL_TARGET_HT40_14,
00146         ALL_TARGET_HT40_15,
00147         ALL_TARGET_HT40_20,
00148         ALL_TARGET_HT40_21,
00149         ALL_TARGET_HT40_22,
00150         ALL_TARGET_HT40_23,
00151         ar9300RateSize,
00152 };
00153 
00154 
00155 struct eepFlags {
00156         u8 opFlags;
00157         u8 eepMisc;
00158 } __attribute__((packed));
00159 
00160 enum CompressAlgorithm {
00161         _CompressNone = 0,
00162         _CompressLzma,
00163         _CompressPairs,
00164         _CompressBlock,
00165         _Compress4,
00166         _Compress5,
00167         _Compress6,
00168         _Compress7,
00169 };
00170 
00171 struct ar9300_base_eep_hdr {
00172         uint16_t regDmn[2];
00173         /* 4 bits tx and 4 bits rx */
00174         u8 txrxMask;
00175         struct eepFlags opCapFlags;
00176         u8 rfSilent;
00177         u8 blueToothOptions;
00178         u8 deviceCap;
00179         /* takes lower byte in eeprom location */
00180         u8 deviceType;
00181         /* offset in dB to be added to beginning
00182          * of pdadc table in calibration
00183          */
00184         int8_t pwrTableOffset;
00185         u8 params_for_tuning_caps[2];
00186         /*
00187          * bit0 - enable tx temp comp
00188          * bit1 - enable tx volt comp
00189          * bit2 - enable fastClock - default to 1
00190          * bit3 - enable doubling - default to 1
00191          * bit4 - enable internal regulator - default to 1
00192          */
00193         u8 featureEnable;
00194         /* misc flags: bit0 - turn down drivestrength */
00195         u8 miscConfiguration;
00196         u8 eepromWriteEnableGpio;
00197         u8 wlanDisableGpio;
00198         u8 wlanLedGpio;
00199         u8 rxBandSelectGpio;
00200         u8 txrxgain;
00201         /* SW controlled internal regulator fields */
00202         uint32_t swreg;
00203 } __attribute__((packed));
00204 
00205 struct ar9300_modal_eep_header {
00206         /* 4 idle, t1, t2, b (4 bits per setting) */
00207         uint32_t antCtrlCommon;
00208         /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
00209         uint32_t antCtrlCommon2;
00210         /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
00211         uint16_t antCtrlChain[AR9300_MAX_CHAINS];
00212         /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
00213         u8 xatten1DB[AR9300_MAX_CHAINS];
00214         /* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
00215         u8 xatten1Margin[AR9300_MAX_CHAINS];
00216         int8_t tempSlope;
00217         int8_t voltSlope;
00218         /* spur channels in usual fbin coding format */
00219         u8 spurChans[AR_EEPROM_MODAL_SPURS];
00220         /* 3  Check if the register is per chain */
00221         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
00222         u8 ob[AR9300_MAX_CHAINS];
00223         u8 db_stage2[AR9300_MAX_CHAINS];
00224         u8 db_stage3[AR9300_MAX_CHAINS];
00225         u8 db_stage4[AR9300_MAX_CHAINS];
00226         u8 xpaBiasLvl;
00227         u8 txFrameToDataStart;
00228         u8 txFrameToPaOn;
00229         u8 txClip;
00230         int8_t antennaGain;
00231         u8 switchSettling;
00232         int8_t adcDesiredSize;
00233         u8 txEndToXpaOff;
00234         u8 txEndToRxOn;
00235         u8 txFrameToXpaOn;
00236         u8 thresh62;
00237         uint32_t papdRateMaskHt20;
00238         uint32_t papdRateMaskHt40;
00239         u8 futureModal[10];
00240 } __attribute__((packed));
00241 
00242 struct ar9300_cal_data_per_freq_op_loop {
00243         int8_t refPower;
00244         /* pdadc voltage at power measurement */
00245         u8 voltMeas;
00246         /* pcdac used for power measurement   */
00247         u8 tempMeas;
00248         /* range is -60 to -127 create a mapping equation 1db resolution */
00249         int8_t rxNoisefloorCal;
00250         /*range is same as noisefloor */
00251         int8_t rxNoisefloorPower;
00252         /* temp measured when noisefloor cal was performed */
00253         u8 rxTempMeas;
00254 } __attribute__((packed));
00255 
00256 struct cal_tgt_pow_legacy {
00257         u8 tPow2x[4];
00258 } __attribute__((packed));
00259 
00260 struct cal_tgt_pow_ht {
00261         u8 tPow2x[14];
00262 } __attribute__((packed));
00263 
00264 struct cal_ctl_data_2g {
00265         u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
00266 } __attribute__((packed));
00267 
00268 struct cal_ctl_data_5g {
00269         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
00270 } __attribute__((packed));
00271 
00272 struct ar9300_BaseExtension_1 {
00273         u8 ant_div_control;
00274         u8 future[13];
00275 } __attribute__((packed));
00276 
00277 struct ar9300_BaseExtension_2 {
00278         int8_t    tempSlopeLow;
00279         int8_t    tempSlopeHigh;
00280         u8   xatten1DBLow[AR9300_MAX_CHAINS];
00281         u8   xatten1MarginLow[AR9300_MAX_CHAINS];
00282         u8   xatten1DBHigh[AR9300_MAX_CHAINS];
00283         u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
00284 } __attribute__((packed));
00285 
00286 struct ar9300_eeprom {
00287         u8 eepromVersion;
00288         u8 templateVersion;
00289         u8 macAddr[6];
00290         u8 custData[AR9300_CUSTOMER_DATA_SIZE];
00291 
00292         struct ar9300_base_eep_hdr baseEepHeader;
00293 
00294         struct ar9300_modal_eep_header modalHeader2G;
00295         struct ar9300_BaseExtension_1 base_ext1;
00296         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
00297         struct ar9300_cal_data_per_freq_op_loop
00298          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
00299         u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
00300         u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
00301         u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
00302         u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
00303         struct cal_tgt_pow_legacy
00304          calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
00305         struct cal_tgt_pow_legacy
00306          calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
00307         struct cal_tgt_pow_ht
00308          calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
00309         struct cal_tgt_pow_ht
00310          calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
00311         u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
00312         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
00313         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
00314         struct ar9300_modal_eep_header modalHeader5G;
00315         struct ar9300_BaseExtension_2 base_ext2;
00316         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
00317         struct ar9300_cal_data_per_freq_op_loop
00318          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
00319         u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
00320         u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
00321         u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
00322         struct cal_tgt_pow_legacy
00323          calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
00324         struct cal_tgt_pow_ht
00325          calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
00326         struct cal_tgt_pow_ht
00327          calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
00328         u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
00329         u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
00330         struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
00331 } __attribute__((packed));
00332 
00333 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
00334 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
00335 
00336 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz);
00337 
00338 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
00339                                            struct ath9k_channel *chan);
00340 #endif