iPXE
ath9k_ar9003_eeprom.c
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00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #include <ipxe/io.h>
00021 #include <ipxe/malloc.h>
00022 
00023 #include "hw.h"
00024 #include "ar9003_phy.h"
00025 #include "ar9003_eeprom.h"
00026 
00027 #define COMP_HDR_LEN 4
00028 #define COMP_CKSUM_LEN 2
00029 
00030 #define AR_CH0_TOP (0x00016288)
00031 #define AR_CH0_TOP_XPABIASLVL (0x300)
00032 #define AR_CH0_TOP_XPABIASLVL_S (8)
00033 
00034 #define AR_CH0_THERM (0x00016290)
00035 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
00036 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
00037 #define AR_CH0_THERM_XPASHORT2GND 0x4
00038 #define AR_CH0_THERM_XPASHORT2GND_S 2
00039 
00040 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
00041 #define AR_SWITCH_TABLE_COM_ALL_S (0)
00042 
00043 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
00044 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
00045 
00046 #define AR_SWITCH_TABLE_ALL (0xfff)
00047 #define AR_SWITCH_TABLE_ALL_S (0)
00048 
00049 #define LE16(x) (uint16_t)(x)
00050 #define LE32(x) (uint32_t)(x)
00051 
00052 /* Local defines to distinguish between extension and control CTL's */
00053 #define EXT_ADDITIVE (0x8000)
00054 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
00055 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
00056 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
00057 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
00058 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
00059 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
00060 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
00061 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
00062 
00063 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
00064 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
00065 
00066 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
00067 
00068 #define EEPROM_DATA_LEN_9485    1088
00069 
00070 static int ar9003_hw_power_interpolate(int32_t x,
00071                                        int32_t *px, int32_t *py, uint16_t np);
00072 
00073 
00074 static const struct ar9300_eeprom ar9300_default = {
00075         .eepromVersion = 2,
00076         .templateVersion = 2,
00077         .macAddr = {1, 2, 3, 4, 5, 6},
00078         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00079                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
00080         .baseEepHeader = {
00081                 .regDmn = { LE16(0), LE16(0x1f) },
00082                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
00083                 .opCapFlags = {
00084                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
00085                         .eepMisc = 0,
00086                 },
00087                 .rfSilent = 0,
00088                 .blueToothOptions = 0,
00089                 .deviceCap = 0,
00090                 .deviceType = 5, /* takes lower byte in eeprom location */
00091                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
00092                 .params_for_tuning_caps = {0, 0},
00093                 .featureEnable = 0x0c,
00094                  /*
00095                   * bit0 - enable tx temp comp - disabled
00096                   * bit1 - enable tx volt comp - disabled
00097                   * bit2 - enable fastClock - enabled
00098                   * bit3 - enable doubling - enabled
00099                   * bit4 - enable internal regulator - disabled
00100                   * bit5 - enable pa predistortion - disabled
00101                   */
00102                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
00103                 .eepromWriteEnableGpio = 3,
00104                 .wlanDisableGpio = 0,
00105                 .wlanLedGpio = 8,
00106                 .rxBandSelectGpio = 0xff,
00107                 .txrxgain = 0,
00108                 .swreg = 0,
00109          },
00110         .modalHeader2G = {
00111         /* ar9300_modal_eep_header  2g */
00112                 /* 4 idle,t1,t2,b(4 bits per setting) */
00113                 .antCtrlCommon = LE32(0x110),
00114                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
00115                 .antCtrlCommon2 = LE32(0x22222),
00116 
00117                 /*
00118                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
00119                  * rx1, rx12, b (2 bits each)
00120                  */
00121                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
00122 
00123                 /*
00124                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
00125                  * for ar9280 (0xa20c/b20c 5:0)
00126                  */
00127                 .xatten1DB = {0, 0, 0},
00128 
00129                 /*
00130                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
00131                  * for ar9280 (0xa20c/b20c 16:12
00132                  */
00133                 .xatten1Margin = {0, 0, 0},
00134                 .tempSlope = 36,
00135                 .voltSlope = 0,
00136 
00137                 /*
00138                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
00139                  * channels in usual fbin coding format
00140                  */
00141                 .spurChans = {0, 0, 0, 0, 0},
00142 
00143                 /*
00144                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
00145                  * if the register is per chain
00146                  */
00147                 .noiseFloorThreshCh = {-1, 0, 0},
00148                 .ob = {1, 1, 1},/* 3 chain */
00149                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
00150                 .db_stage3 = {0, 0, 0},
00151                 .db_stage4 = {0, 0, 0},
00152                 .xpaBiasLvl = 0,
00153                 .txFrameToDataStart = 0x0e,
00154                 .txFrameToPaOn = 0x0e,
00155                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
00156                 .antennaGain = 0,
00157                 .switchSettling = 0x2c,
00158                 .adcDesiredSize = -30,
00159                 .txEndToXpaOff = 0,
00160                 .txEndToRxOn = 0x2,
00161                 .txFrameToXpaOn = 0xe,
00162                 .thresh62 = 28,
00163                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
00164                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
00165                 .futureModal = {
00166                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00167                 },
00168          },
00169         .base_ext1 = {
00170                 .ant_div_control = 0,
00171                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
00172         },
00173         .calFreqPier2G = {
00174                 FREQ2FBIN(2412, 1),
00175                 FREQ2FBIN(2437, 1),
00176                 FREQ2FBIN(2472, 1),
00177          },
00178         /* ar9300_cal_data_per_freq_op_loop 2g */
00179         .calPierData2G = {
00180                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00181                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00182                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00183          },
00184         .calTarget_freqbin_Cck = {
00185                 FREQ2FBIN(2412, 1),
00186                 FREQ2FBIN(2484, 1),
00187          },
00188         .calTarget_freqbin_2G = {
00189                 FREQ2FBIN(2412, 1),
00190                 FREQ2FBIN(2437, 1),
00191                 FREQ2FBIN(2472, 1)
00192          },
00193         .calTarget_freqbin_2GHT20 = {
00194                 FREQ2FBIN(2412, 1),
00195                 FREQ2FBIN(2437, 1),
00196                 FREQ2FBIN(2472, 1)
00197          },
00198         .calTarget_freqbin_2GHT40 = {
00199                 FREQ2FBIN(2412, 1),
00200                 FREQ2FBIN(2437, 1),
00201                 FREQ2FBIN(2472, 1)
00202          },
00203         .calTargetPowerCck = {
00204                  /* 1L-5L,5S,11L,11S */
00205                  { {36, 36, 36, 36} },
00206                  { {36, 36, 36, 36} },
00207         },
00208         .calTargetPower2G = {
00209                  /* 6-24,36,48,54 */
00210                  { {32, 32, 28, 24} },
00211                  { {32, 32, 28, 24} },
00212                  { {32, 32, 28, 24} },
00213         },
00214         .calTargetPower2GHT20 = {
00215                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00216                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00217                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00218         },
00219         .calTargetPower2GHT40 = {
00220                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00221                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00222                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
00223         },
00224         .ctlIndex_2G =  {
00225                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
00226                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
00227         },
00228         .ctl_freqbin_2G = {
00229                 {
00230                         FREQ2FBIN(2412, 1),
00231                         FREQ2FBIN(2417, 1),
00232                         FREQ2FBIN(2457, 1),
00233                         FREQ2FBIN(2462, 1)
00234                 },
00235                 {
00236                         FREQ2FBIN(2412, 1),
00237                         FREQ2FBIN(2417, 1),
00238                         FREQ2FBIN(2462, 1),
00239                         0xFF,
00240                 },
00241 
00242                 {
00243                         FREQ2FBIN(2412, 1),
00244                         FREQ2FBIN(2417, 1),
00245                         FREQ2FBIN(2462, 1),
00246                         0xFF,
00247                 },
00248                 {
00249                         FREQ2FBIN(2422, 1),
00250                         FREQ2FBIN(2427, 1),
00251                         FREQ2FBIN(2447, 1),
00252                         FREQ2FBIN(2452, 1)
00253                 },
00254 
00255                 {
00256                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00257                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00258                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00259                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
00260                 },
00261 
00262                 {
00263                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00264                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00265                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00266                         0,
00267                 },
00268 
00269                 {
00270                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00271                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00272                         FREQ2FBIN(2472, 1),
00273                         0,
00274                 },
00275 
00276                 {
00277                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
00278                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
00279                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
00280                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
00281                 },
00282 
00283                 {
00284                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00285                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00286                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00287                 },
00288 
00289                 {
00290                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00291                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00292                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00293                         0
00294                 },
00295 
00296                 {
00297                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00298                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00299                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00300                         0
00301                 },
00302 
00303                 {
00304                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
00305                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
00306                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
00307                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
00308                 }
00309          },
00310         .ctlPowerData_2G = {
00311                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00312                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00313                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
00314 
00315                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
00316                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00317                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00318 
00319                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
00320                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00321                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00322 
00323                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00324                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
00325                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
00326          },
00327         .modalHeader5G = {
00328                 /* 4 idle,t1,t2,b (4 bits per setting) */
00329                 .antCtrlCommon = LE32(0x110),
00330                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
00331                 .antCtrlCommon2 = LE32(0x22222),
00332                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
00333                 .antCtrlChain = {
00334                         LE16(0x000), LE16(0x000), LE16(0x000),
00335                 },
00336                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
00337                 .xatten1DB = {0, 0, 0},
00338 
00339                 /*
00340                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
00341                  * for merlin (0xa20c/b20c 16:12
00342                  */
00343                 .xatten1Margin = {0, 0, 0},
00344                 .tempSlope = 68,
00345                 .voltSlope = 0,
00346                 /* spurChans spur channels in usual fbin coding format */
00347                 .spurChans = {0, 0, 0, 0, 0},
00348                 /* noiseFloorThreshCh Check if the register is per chain */
00349                 .noiseFloorThreshCh = {-1, 0, 0},
00350                 .ob = {3, 3, 3}, /* 3 chain */
00351                 .db_stage2 = {3, 3, 3}, /* 3 chain */
00352                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
00353                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
00354                 .xpaBiasLvl = 0,
00355                 .txFrameToDataStart = 0x0e,
00356                 .txFrameToPaOn = 0x0e,
00357                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
00358                 .antennaGain = 0,
00359                 .switchSettling = 0x2d,
00360                 .adcDesiredSize = -30,
00361                 .txEndToXpaOff = 0,
00362                 .txEndToRxOn = 0x2,
00363                 .txFrameToXpaOn = 0xe,
00364                 .thresh62 = 28,
00365                 .papdRateMaskHt20 = LE32(0x0c80c080),
00366                 .papdRateMaskHt40 = LE32(0x0080c080),
00367                 .futureModal = {
00368                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00369                 },
00370          },
00371         .base_ext2 = {
00372                 .tempSlopeLow = 0,
00373                 .tempSlopeHigh = 0,
00374                 .xatten1DBLow = {0, 0, 0},
00375                 .xatten1MarginLow = {0, 0, 0},
00376                 .xatten1DBHigh = {0, 0, 0},
00377                 .xatten1MarginHigh = {0, 0, 0}
00378         },
00379         .calFreqPier5G = {
00380                 FREQ2FBIN(5180, 0),
00381                 FREQ2FBIN(5220, 0),
00382                 FREQ2FBIN(5320, 0),
00383                 FREQ2FBIN(5400, 0),
00384                 FREQ2FBIN(5500, 0),
00385                 FREQ2FBIN(5600, 0),
00386                 FREQ2FBIN(5725, 0),
00387                 FREQ2FBIN(5825, 0)
00388         },
00389         .calPierData5G = {
00390                         {
00391                                 {0, 0, 0, 0, 0, 0},
00392                                 {0, 0, 0, 0, 0, 0},
00393                                 {0, 0, 0, 0, 0, 0},
00394                                 {0, 0, 0, 0, 0, 0},
00395                                 {0, 0, 0, 0, 0, 0},
00396                                 {0, 0, 0, 0, 0, 0},
00397                                 {0, 0, 0, 0, 0, 0},
00398                                 {0, 0, 0, 0, 0, 0},
00399                         },
00400                         {
00401                                 {0, 0, 0, 0, 0, 0},
00402                                 {0, 0, 0, 0, 0, 0},
00403                                 {0, 0, 0, 0, 0, 0},
00404                                 {0, 0, 0, 0, 0, 0},
00405                                 {0, 0, 0, 0, 0, 0},
00406                                 {0, 0, 0, 0, 0, 0},
00407                                 {0, 0, 0, 0, 0, 0},
00408                                 {0, 0, 0, 0, 0, 0},
00409                         },
00410                         {
00411                                 {0, 0, 0, 0, 0, 0},
00412                                 {0, 0, 0, 0, 0, 0},
00413                                 {0, 0, 0, 0, 0, 0},
00414                                 {0, 0, 0, 0, 0, 0},
00415                                 {0, 0, 0, 0, 0, 0},
00416                                 {0, 0, 0, 0, 0, 0},
00417                                 {0, 0, 0, 0, 0, 0},
00418                                 {0, 0, 0, 0, 0, 0},
00419                         },
00420 
00421         },
00422         .calTarget_freqbin_5G = {
00423                 FREQ2FBIN(5180, 0),
00424                 FREQ2FBIN(5220, 0),
00425                 FREQ2FBIN(5320, 0),
00426                 FREQ2FBIN(5400, 0),
00427                 FREQ2FBIN(5500, 0),
00428                 FREQ2FBIN(5600, 0),
00429                 FREQ2FBIN(5725, 0),
00430                 FREQ2FBIN(5825, 0)
00431         },
00432         .calTarget_freqbin_5GHT20 = {
00433                 FREQ2FBIN(5180, 0),
00434                 FREQ2FBIN(5240, 0),
00435                 FREQ2FBIN(5320, 0),
00436                 FREQ2FBIN(5500, 0),
00437                 FREQ2FBIN(5700, 0),
00438                 FREQ2FBIN(5745, 0),
00439                 FREQ2FBIN(5725, 0),
00440                 FREQ2FBIN(5825, 0)
00441         },
00442         .calTarget_freqbin_5GHT40 = {
00443                 FREQ2FBIN(5180, 0),
00444                 FREQ2FBIN(5240, 0),
00445                 FREQ2FBIN(5320, 0),
00446                 FREQ2FBIN(5500, 0),
00447                 FREQ2FBIN(5700, 0),
00448                 FREQ2FBIN(5745, 0),
00449                 FREQ2FBIN(5725, 0),
00450                 FREQ2FBIN(5825, 0)
00451          },
00452         .calTargetPower5G = {
00453                 /* 6-24,36,48,54 */
00454                 { {20, 20, 20, 10} },
00455                 { {20, 20, 20, 10} },
00456                 { {20, 20, 20, 10} },
00457                 { {20, 20, 20, 10} },
00458                 { {20, 20, 20, 10} },
00459                 { {20, 20, 20, 10} },
00460                 { {20, 20, 20, 10} },
00461                 { {20, 20, 20, 10} },
00462          },
00463         .calTargetPower5GHT20 = {
00464                 /*
00465                  * 0_8_16,1-3_9-11_17-19,
00466                  * 4,5,6,7,12,13,14,15,20,21,22,23
00467                  */
00468                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00469                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00470                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00471                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00472                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00473                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00474                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00475                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00476          },
00477         .calTargetPower5GHT40 =  {
00478                 /*
00479                  * 0_8_16,1-3_9-11_17-19,
00480                  * 4,5,6,7,12,13,14,15,20,21,22,23
00481                  */
00482                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00483                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00484                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00485                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00486                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00487                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00488                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00489                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
00490          },
00491         .ctlIndex_5G =  {
00492                 0x10, 0x16, 0x18, 0x40, 0x46,
00493                 0x48, 0x30, 0x36, 0x38
00494         },
00495         .ctl_freqbin_5G =  {
00496                 {
00497                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00498                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
00499                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
00500                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
00501                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
00502                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
00503                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
00504                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
00505                 },
00506                 {
00507                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00508                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
00509                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
00510                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
00511                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
00512                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
00513                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
00514                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
00515                 },
00516 
00517                 {
00518                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
00519                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
00520                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
00521                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
00522                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
00523                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
00524                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
00525                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
00526                 },
00527 
00528                 {
00529                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00530                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
00531                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
00532                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
00533                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
00534                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
00535                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
00536                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
00537                 },
00538 
00539                 {
00540                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00541                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
00542                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
00543                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
00544                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
00545                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
00546                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
00547                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
00548                 },
00549 
00550                 {
00551                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
00552                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
00553                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
00554                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
00555                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
00556                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
00557                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
00558                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
00559                 },
00560 
00561                 {
00562                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00563                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
00564                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
00565                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
00566                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
00567                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
00568                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
00569                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
00570                 },
00571 
00572                 {
00573                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
00574                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
00575                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
00576                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
00577                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
00578                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
00579                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
00580                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
00581                 },
00582 
00583                 {
00584                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
00585                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
00586                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
00587                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
00588                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
00589                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
00590                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
00591                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
00592                 }
00593          },
00594         .ctlPowerData_5G = {
00595                 {
00596                         {
00597                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00598                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
00599                         }
00600                 },
00601                 {
00602                         {
00603                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00604                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
00605                         }
00606                 },
00607                 {
00608                         {
00609                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
00610                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00611                         }
00612                 },
00613                 {
00614                         {
00615                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
00616                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
00617                         }
00618                 },
00619                 {
00620                         {
00621                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
00622                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
00623                         }
00624                 },
00625                 {
00626                         {
00627                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00628                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
00629                         }
00630                 },
00631                 {
00632                         {
00633                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00634                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
00635                         }
00636                 },
00637                 {
00638                         {
00639                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
00640                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
00641                         }
00642                 },
00643                 {
00644                         {
00645                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
00646                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
00647                         }
00648                 },
00649          }
00650 };
00651 
00652 static const struct ar9300_eeprom ar9300_x113 = {
00653         .eepromVersion = 2,
00654         .templateVersion = 6,
00655         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
00656         .custData = {"x113-023-f0000"},
00657         .baseEepHeader = {
00658                 .regDmn = { LE16(0), LE16(0x1f) },
00659                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
00660                 .opCapFlags = {
00661                         .opFlags = AR5416_OPFLAGS_11A,
00662                         .eepMisc = 0,
00663                 },
00664                 .rfSilent = 0,
00665                 .blueToothOptions = 0,
00666                 .deviceCap = 0,
00667                 .deviceType = 5, /* takes lower byte in eeprom location */
00668                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
00669                 .params_for_tuning_caps = {0, 0},
00670                 .featureEnable = 0x0d,
00671                  /*
00672                   * bit0 - enable tx temp comp - disabled
00673                   * bit1 - enable tx volt comp - disabled
00674                   * bit2 - enable fastClock - enabled
00675                   * bit3 - enable doubling - enabled
00676                   * bit4 - enable internal regulator - disabled
00677                   * bit5 - enable pa predistortion - disabled
00678                   */
00679                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
00680                 .eepromWriteEnableGpio = 6,
00681                 .wlanDisableGpio = 0,
00682                 .wlanLedGpio = 8,
00683                 .rxBandSelectGpio = 0xff,
00684                 .txrxgain = 0x21,
00685                 .swreg = 0,
00686          },
00687         .modalHeader2G = {
00688         /* ar9300_modal_eep_header  2g */
00689                 /* 4 idle,t1,t2,b(4 bits per setting) */
00690                 .antCtrlCommon = LE32(0x110),
00691                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
00692                 .antCtrlCommon2 = LE32(0x44444),
00693 
00694                 /*
00695                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
00696                  * rx1, rx12, b (2 bits each)
00697                  */
00698                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
00699 
00700                 /*
00701                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
00702                  * for ar9280 (0xa20c/b20c 5:0)
00703                  */
00704                 .xatten1DB = {0, 0, 0},
00705 
00706                 /*
00707                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
00708                  * for ar9280 (0xa20c/b20c 16:12
00709                  */
00710                 .xatten1Margin = {0, 0, 0},
00711                 .tempSlope = 25,
00712                 .voltSlope = 0,
00713 
00714                 /*
00715                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
00716                  * channels in usual fbin coding format
00717                  */
00718                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
00719 
00720                 /*
00721                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
00722                  * if the register is per chain
00723                  */
00724                 .noiseFloorThreshCh = {-1, 0, 0},
00725                 .ob = {1, 1, 1},/* 3 chain */
00726                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
00727                 .db_stage3 = {0, 0, 0},
00728                 .db_stage4 = {0, 0, 0},
00729                 .xpaBiasLvl = 0,
00730                 .txFrameToDataStart = 0x0e,
00731                 .txFrameToPaOn = 0x0e,
00732                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
00733                 .antennaGain = 0,
00734                 .switchSettling = 0x2c,
00735                 .adcDesiredSize = -30,
00736                 .txEndToXpaOff = 0,
00737                 .txEndToRxOn = 0x2,
00738                 .txFrameToXpaOn = 0xe,
00739                 .thresh62 = 28,
00740                 .papdRateMaskHt20 = LE32(0x0c80c080),
00741                 .papdRateMaskHt40 = LE32(0x0080c080),
00742                 .futureModal = {
00743                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00744                 },
00745          },
00746          .base_ext1 = {
00747                 .ant_div_control = 0,
00748                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
00749          },
00750         .calFreqPier2G = {
00751                 FREQ2FBIN(2412, 1),
00752                 FREQ2FBIN(2437, 1),
00753                 FREQ2FBIN(2472, 1),
00754          },
00755         /* ar9300_cal_data_per_freq_op_loop 2g */
00756         .calPierData2G = {
00757                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00758                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00759                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
00760          },
00761         .calTarget_freqbin_Cck = {
00762                 FREQ2FBIN(2412, 1),
00763                 FREQ2FBIN(2472, 1),
00764          },
00765         .calTarget_freqbin_2G = {
00766                 FREQ2FBIN(2412, 1),
00767                 FREQ2FBIN(2437, 1),
00768                 FREQ2FBIN(2472, 1)
00769          },
00770         .calTarget_freqbin_2GHT20 = {
00771                 FREQ2FBIN(2412, 1),
00772                 FREQ2FBIN(2437, 1),
00773                 FREQ2FBIN(2472, 1)
00774          },
00775         .calTarget_freqbin_2GHT40 = {
00776                 FREQ2FBIN(2412, 1),
00777                 FREQ2FBIN(2437, 1),
00778                 FREQ2FBIN(2472, 1)
00779          },
00780         .calTargetPowerCck = {
00781                  /* 1L-5L,5S,11L,11S */
00782                  { {34, 34, 34, 34} },
00783                  { {34, 34, 34, 34} },
00784         },
00785         .calTargetPower2G = {
00786                  /* 6-24,36,48,54 */
00787                  { {34, 34, 32, 32} },
00788                  { {34, 34, 32, 32} },
00789                  { {34, 34, 32, 32} },
00790         },
00791         .calTargetPower2GHT20 = {
00792                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
00793                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
00794                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
00795         },
00796         .calTargetPower2GHT40 = {
00797                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
00798                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
00799                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
00800         },
00801         .ctlIndex_2G =  {
00802                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
00803                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
00804         },
00805         .ctl_freqbin_2G = {
00806                 {
00807                         FREQ2FBIN(2412, 1),
00808                         FREQ2FBIN(2417, 1),
00809                         FREQ2FBIN(2457, 1),
00810                         FREQ2FBIN(2462, 1)
00811                 },
00812                 {
00813                         FREQ2FBIN(2412, 1),
00814                         FREQ2FBIN(2417, 1),
00815                         FREQ2FBIN(2462, 1),
00816                         0xFF,
00817                 },
00818 
00819                 {
00820                         FREQ2FBIN(2412, 1),
00821                         FREQ2FBIN(2417, 1),
00822                         FREQ2FBIN(2462, 1),
00823                         0xFF,
00824                 },
00825                 {
00826                         FREQ2FBIN(2422, 1),
00827                         FREQ2FBIN(2427, 1),
00828                         FREQ2FBIN(2447, 1),
00829                         FREQ2FBIN(2452, 1)
00830                 },
00831 
00832                 {
00833                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00834                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00835                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00836                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
00837                 },
00838 
00839                 {
00840                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00841                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00842                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00843                         0,
00844                 },
00845 
00846                 {
00847                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00848                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00849                         FREQ2FBIN(2472, 1),
00850                         0,
00851                 },
00852 
00853                 {
00854                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
00855                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
00856                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
00857                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
00858                 },
00859 
00860                 {
00861                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00862                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00863                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00864                 },
00865 
00866                 {
00867                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00868                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00869                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00870                         0
00871                 },
00872 
00873                 {
00874                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
00875                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
00876                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
00877                         0
00878                 },
00879 
00880                 {
00881                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
00882                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
00883                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
00884                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
00885                 }
00886          },
00887         .ctlPowerData_2G = {
00888                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00889                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00890                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
00891 
00892                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
00893                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00894                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00895 
00896                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
00897                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00898                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00899 
00900                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
00901                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
00902                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
00903          },
00904         .modalHeader5G = {
00905                 /* 4 idle,t1,t2,b (4 bits per setting) */
00906                 .antCtrlCommon = LE32(0x220),
00907                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
00908                 .antCtrlCommon2 = LE32(0x11111),
00909                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
00910                 .antCtrlChain = {
00911                         LE16(0x150), LE16(0x150), LE16(0x150),
00912                 },
00913                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
00914                 .xatten1DB = {0, 0, 0},
00915 
00916                 /*
00917                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
00918                  * for merlin (0xa20c/b20c 16:12
00919                  */
00920                 .xatten1Margin = {0, 0, 0},
00921                 .tempSlope = 68,
00922                 .voltSlope = 0,
00923                 /* spurChans spur channels in usual fbin coding format */
00924                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
00925                 /* noiseFloorThreshCh Check if the register is per chain */
00926                 .noiseFloorThreshCh = {-1, 0, 0},
00927                 .ob = {3, 3, 3}, /* 3 chain */
00928                 .db_stage2 = {3, 3, 3}, /* 3 chain */
00929                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
00930                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
00931                 .xpaBiasLvl = 0xf,
00932                 .txFrameToDataStart = 0x0e,
00933                 .txFrameToPaOn = 0x0e,
00934                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
00935                 .antennaGain = 0,
00936                 .switchSettling = 0x2d,
00937                 .adcDesiredSize = -30,
00938                 .txEndToXpaOff = 0,
00939                 .txEndToRxOn = 0x2,
00940                 .txFrameToXpaOn = 0xe,
00941                 .thresh62 = 28,
00942                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
00943                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
00944                 .futureModal = {
00945                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00946                 },
00947          },
00948         .base_ext2 = {
00949                 .tempSlopeLow = 72,
00950                 .tempSlopeHigh = 105,
00951                 .xatten1DBLow = {0, 0, 0},
00952                 .xatten1MarginLow = {0, 0, 0},
00953                 .xatten1DBHigh = {0, 0, 0},
00954                 .xatten1MarginHigh = {0, 0, 0}
00955          },
00956         .calFreqPier5G = {
00957                 FREQ2FBIN(5180, 0),
00958                 FREQ2FBIN(5240, 0),
00959                 FREQ2FBIN(5320, 0),
00960                 FREQ2FBIN(5400, 0),
00961                 FREQ2FBIN(5500, 0),
00962                 FREQ2FBIN(5600, 0),
00963                 FREQ2FBIN(5745, 0),
00964                 FREQ2FBIN(5785, 0)
00965         },
00966         .calPierData5G = {
00967                         {
00968                                 {0, 0, 0, 0, 0, 0},
00969                                 {0, 0, 0, 0, 0, 0},
00970                                 {0, 0, 0, 0, 0, 0},
00971                                 {0, 0, 0, 0, 0, 0},
00972                                 {0, 0, 0, 0, 0, 0},
00973                                 {0, 0, 0, 0, 0, 0},
00974                                 {0, 0, 0, 0, 0, 0},
00975                                 {0, 0, 0, 0, 0, 0},
00976                         },
00977                         {
00978                                 {0, 0, 0, 0, 0, 0},
00979                                 {0, 0, 0, 0, 0, 0},
00980                                 {0, 0, 0, 0, 0, 0},
00981                                 {0, 0, 0, 0, 0, 0},
00982                                 {0, 0, 0, 0, 0, 0},
00983                                 {0, 0, 0, 0, 0, 0},
00984                                 {0, 0, 0, 0, 0, 0},
00985                                 {0, 0, 0, 0, 0, 0},
00986                         },
00987                         {
00988                                 {0, 0, 0, 0, 0, 0},
00989                                 {0, 0, 0, 0, 0, 0},
00990                                 {0, 0, 0, 0, 0, 0},
00991                                 {0, 0, 0, 0, 0, 0},
00992                                 {0, 0, 0, 0, 0, 0},
00993                                 {0, 0, 0, 0, 0, 0},
00994                                 {0, 0, 0, 0, 0, 0},
00995                                 {0, 0, 0, 0, 0, 0},
00996                         },
00997 
00998         },
00999         .calTarget_freqbin_5G = {
01000                 FREQ2FBIN(5180, 0),
01001                 FREQ2FBIN(5220, 0),
01002                 FREQ2FBIN(5320, 0),
01003                 FREQ2FBIN(5400, 0),
01004                 FREQ2FBIN(5500, 0),
01005                 FREQ2FBIN(5600, 0),
01006                 FREQ2FBIN(5745, 0),
01007                 FREQ2FBIN(5785, 0)
01008         },
01009         .calTarget_freqbin_5GHT20 = {
01010                 FREQ2FBIN(5180, 0),
01011                 FREQ2FBIN(5240, 0),
01012                 FREQ2FBIN(5320, 0),
01013                 FREQ2FBIN(5400, 0),
01014                 FREQ2FBIN(5500, 0),
01015                 FREQ2FBIN(5700, 0),
01016                 FREQ2FBIN(5745, 0),
01017                 FREQ2FBIN(5825, 0)
01018         },
01019         .calTarget_freqbin_5GHT40 = {
01020                 FREQ2FBIN(5190, 0),
01021                 FREQ2FBIN(5230, 0),
01022                 FREQ2FBIN(5320, 0),
01023                 FREQ2FBIN(5410, 0),
01024                 FREQ2FBIN(5510, 0),
01025                 FREQ2FBIN(5670, 0),
01026                 FREQ2FBIN(5755, 0),
01027                 FREQ2FBIN(5825, 0)
01028          },
01029         .calTargetPower5G = {
01030                 /* 6-24,36,48,54 */
01031                 { {42, 40, 40, 34} },
01032                 { {42, 40, 40, 34} },
01033                 { {42, 40, 40, 34} },
01034                 { {42, 40, 40, 34} },
01035                 { {42, 40, 40, 34} },
01036                 { {42, 40, 40, 34} },
01037                 { {42, 40, 40, 34} },
01038                 { {42, 40, 40, 34} },
01039          },
01040         .calTargetPower5GHT20 = {
01041                 /*
01042                  * 0_8_16,1-3_9-11_17-19,
01043                  * 4,5,6,7,12,13,14,15,20,21,22,23
01044                  */
01045                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01046                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01047                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01048                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01049                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01050                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
01051                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
01052                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
01053          },
01054         .calTargetPower5GHT40 =  {
01055                 /*
01056                  * 0_8_16,1-3_9-11_17-19,
01057                  * 4,5,6,7,12,13,14,15,20,21,22,23
01058                  */
01059                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01060                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01061                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01062                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01063                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01064                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
01065                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
01066                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
01067          },
01068         .ctlIndex_5G =  {
01069                 0x10, 0x16, 0x18, 0x40, 0x46,
01070                 0x48, 0x30, 0x36, 0x38
01071         },
01072         .ctl_freqbin_5G =  {
01073                 {
01074                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01075                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01076                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
01077                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01078                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
01079                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01080                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01081                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01082                 },
01083                 {
01084                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01085                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01086                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
01087                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01088                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
01089                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01090                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01091                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01092                 },
01093 
01094                 {
01095                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01096                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
01097                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
01098                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
01099                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
01100                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
01101                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
01102                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
01103                 },
01104 
01105                 {
01106                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01107                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
01108                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
01109                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
01110                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
01111                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01112                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
01113                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
01114                 },
01115 
01116                 {
01117                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01118                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01119                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
01120                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
01121                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
01122                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
01123                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
01124                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
01125                 },
01126 
01127                 {
01128                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01129                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
01130                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
01131                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
01132                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
01133                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
01134                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
01135                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
01136                 },
01137 
01138                 {
01139                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01140                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
01141                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
01142                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
01143                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
01144                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
01145                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
01146                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
01147                 },
01148 
01149                 {
01150                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01151                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01152                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
01153                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01154                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
01155                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01156                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01157                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01158                 },
01159 
01160                 {
01161                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01162                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
01163                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
01164                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
01165                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
01166                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
01167                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
01168                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
01169                 }
01170          },
01171         .ctlPowerData_5G = {
01172                 {
01173                         {
01174                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01175                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01176                         }
01177                 },
01178                 {
01179                         {
01180                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01181                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01182                         }
01183                 },
01184                 {
01185                         {
01186                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01187                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01188                         }
01189                 },
01190                 {
01191                         {
01192                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01193                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01194                         }
01195                 },
01196                 {
01197                         {
01198                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01199                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01200                         }
01201                 },
01202                 {
01203                         {
01204                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01205                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01206                         }
01207                 },
01208                 {
01209                         {
01210                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01211                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01212                         }
01213                 },
01214                 {
01215                         {
01216                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01217                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01218                         }
01219                 },
01220                 {
01221                         {
01222                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
01223                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01224                         }
01225                 },
01226          }
01227 };
01228 
01229 
01230 static const struct ar9300_eeprom ar9300_h112 = {
01231         .eepromVersion = 2,
01232         .templateVersion = 3,
01233         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
01234         .custData = {"h112-241-f0000"},
01235         .baseEepHeader = {
01236                 .regDmn = { LE16(0), LE16(0x1f) },
01237                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
01238                 .opCapFlags = {
01239                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
01240                         .eepMisc = 0,
01241                 },
01242                 .rfSilent = 0,
01243                 .blueToothOptions = 0,
01244                 .deviceCap = 0,
01245                 .deviceType = 5, /* takes lower byte in eeprom location */
01246                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
01247                 .params_for_tuning_caps = {0, 0},
01248                 .featureEnable = 0x0d,
01249                 /*
01250                  * bit0 - enable tx temp comp - disabled
01251                  * bit1 - enable tx volt comp - disabled
01252                  * bit2 - enable fastClock - enabled
01253                  * bit3 - enable doubling - enabled
01254                  * bit4 - enable internal regulator - disabled
01255                  * bit5 - enable pa predistortion - disabled
01256                  */
01257                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
01258                 .eepromWriteEnableGpio = 6,
01259                 .wlanDisableGpio = 0,
01260                 .wlanLedGpio = 8,
01261                 .rxBandSelectGpio = 0xff,
01262                 .txrxgain = 0x10,
01263                 .swreg = 0,
01264         },
01265         .modalHeader2G = {
01266                 /* ar9300_modal_eep_header  2g */
01267                 /* 4 idle,t1,t2,b(4 bits per setting) */
01268                 .antCtrlCommon = LE32(0x110),
01269                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
01270                 .antCtrlCommon2 = LE32(0x44444),
01271 
01272                 /*
01273                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
01274                  * rx1, rx12, b (2 bits each)
01275                  */
01276                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
01277 
01278                 /*
01279                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
01280                  * for ar9280 (0xa20c/b20c 5:0)
01281                  */
01282                 .xatten1DB = {0, 0, 0},
01283 
01284                 /*
01285                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
01286                  * for ar9280 (0xa20c/b20c 16:12
01287                  */
01288                 .xatten1Margin = {0, 0, 0},
01289                 .tempSlope = 25,
01290                 .voltSlope = 0,
01291 
01292                 /*
01293                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
01294                  * channels in usual fbin coding format
01295                  */
01296                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
01297 
01298                 /*
01299                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
01300                  * if the register is per chain
01301                  */
01302                 .noiseFloorThreshCh = {-1, 0, 0},
01303                 .ob = {1, 1, 1},/* 3 chain */
01304                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
01305                 .db_stage3 = {0, 0, 0},
01306                 .db_stage4 = {0, 0, 0},
01307                 .xpaBiasLvl = 0,
01308                 .txFrameToDataStart = 0x0e,
01309                 .txFrameToPaOn = 0x0e,
01310                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
01311                 .antennaGain = 0,
01312                 .switchSettling = 0x2c,
01313                 .adcDesiredSize = -30,
01314                 .txEndToXpaOff = 0,
01315                 .txEndToRxOn = 0x2,
01316                 .txFrameToXpaOn = 0xe,
01317                 .thresh62 = 28,
01318                 .papdRateMaskHt20 = LE32(0x80c080),
01319                 .papdRateMaskHt40 = LE32(0x80c080),
01320                 .futureModal = {
01321                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
01322                 },
01323         },
01324         .base_ext1 = {
01325                 .ant_div_control = 0,
01326                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
01327         },
01328         .calFreqPier2G = {
01329                 FREQ2FBIN(2412, 1),
01330                 FREQ2FBIN(2437, 1),
01331                 FREQ2FBIN(2472, 1),
01332         },
01333         /* ar9300_cal_data_per_freq_op_loop 2g */
01334         .calPierData2G = {
01335                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01336                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01337                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01338         },
01339         .calTarget_freqbin_Cck = {
01340                 FREQ2FBIN(2412, 1),
01341                 FREQ2FBIN(2484, 1),
01342         },
01343         .calTarget_freqbin_2G = {
01344                 FREQ2FBIN(2412, 1),
01345                 FREQ2FBIN(2437, 1),
01346                 FREQ2FBIN(2472, 1)
01347         },
01348         .calTarget_freqbin_2GHT20 = {
01349                 FREQ2FBIN(2412, 1),
01350                 FREQ2FBIN(2437, 1),
01351                 FREQ2FBIN(2472, 1)
01352         },
01353         .calTarget_freqbin_2GHT40 = {
01354                 FREQ2FBIN(2412, 1),
01355                 FREQ2FBIN(2437, 1),
01356                 FREQ2FBIN(2472, 1)
01357         },
01358         .calTargetPowerCck = {
01359                 /* 1L-5L,5S,11L,11S */
01360                 { {34, 34, 34, 34} },
01361                 { {34, 34, 34, 34} },
01362         },
01363         .calTargetPower2G = {
01364                 /* 6-24,36,48,54 */
01365                 { {34, 34, 32, 32} },
01366                 { {34, 34, 32, 32} },
01367                 { {34, 34, 32, 32} },
01368         },
01369         .calTargetPower2GHT20 = {
01370                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
01371                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
01372                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
01373         },
01374         .calTargetPower2GHT40 = {
01375                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
01376                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
01377                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
01378         },
01379         .ctlIndex_2G =  {
01380                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
01381                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
01382         },
01383         .ctl_freqbin_2G = {
01384                 {
01385                         FREQ2FBIN(2412, 1),
01386                         FREQ2FBIN(2417, 1),
01387                         FREQ2FBIN(2457, 1),
01388                         FREQ2FBIN(2462, 1)
01389                 },
01390                 {
01391                         FREQ2FBIN(2412, 1),
01392                         FREQ2FBIN(2417, 1),
01393                         FREQ2FBIN(2462, 1),
01394                         0xFF,
01395                 },
01396 
01397                 {
01398                         FREQ2FBIN(2412, 1),
01399                         FREQ2FBIN(2417, 1),
01400                         FREQ2FBIN(2462, 1),
01401                         0xFF,
01402                 },
01403                 {
01404                         FREQ2FBIN(2422, 1),
01405                         FREQ2FBIN(2427, 1),
01406                         FREQ2FBIN(2447, 1),
01407                         FREQ2FBIN(2452, 1)
01408                 },
01409 
01410                 {
01411                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01412                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01413                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
01414                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
01415                 },
01416 
01417                 {
01418                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01419                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01420                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
01421                         0,
01422                 },
01423 
01424                 {
01425                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01426                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01427                         FREQ2FBIN(2472, 1),
01428                         0,
01429                 },
01430 
01431                 {
01432                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
01433                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
01434                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
01435                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
01436                 },
01437 
01438                 {
01439                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01440                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01441                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
01442                 },
01443 
01444                 {
01445                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01446                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01447                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
01448                         0
01449                 },
01450 
01451                 {
01452                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
01453                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
01454                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
01455                         0
01456                 },
01457 
01458                 {
01459                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
01460                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
01461                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
01462                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
01463                 }
01464         },
01465         .ctlPowerData_2G = {
01466                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01467                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01468                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
01469 
01470                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
01471                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01472                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01473 
01474                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
01475                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01476                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01477 
01478                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
01479                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
01480                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
01481         },
01482         .modalHeader5G = {
01483                 /* 4 idle,t1,t2,b (4 bits per setting) */
01484                 .antCtrlCommon = LE32(0x220),
01485                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
01486                 .antCtrlCommon2 = LE32(0x44444),
01487                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
01488                 .antCtrlChain = {
01489                         LE16(0x150), LE16(0x150), LE16(0x150),
01490                 },
01491                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
01492                 .xatten1DB = {0, 0, 0},
01493 
01494                 /*
01495                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
01496                  * for merlin (0xa20c/b20c 16:12
01497                  */
01498                 .xatten1Margin = {0, 0, 0},
01499                 .tempSlope = 45,
01500                 .voltSlope = 0,
01501                 /* spurChans spur channels in usual fbin coding format */
01502                 .spurChans = {0, 0, 0, 0, 0},
01503                 /* noiseFloorThreshCh Check if the register is per chain */
01504                 .noiseFloorThreshCh = {-1, 0, 0},
01505                 .ob = {3, 3, 3}, /* 3 chain */
01506                 .db_stage2 = {3, 3, 3}, /* 3 chain */
01507                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
01508                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
01509                 .xpaBiasLvl = 0,
01510                 .txFrameToDataStart = 0x0e,
01511                 .txFrameToPaOn = 0x0e,
01512                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
01513                 .antennaGain = 0,
01514                 .switchSettling = 0x2d,
01515                 .adcDesiredSize = -30,
01516                 .txEndToXpaOff = 0,
01517                 .txEndToRxOn = 0x2,
01518                 .txFrameToXpaOn = 0xe,
01519                 .thresh62 = 28,
01520                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
01521                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
01522                 .futureModal = {
01523                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
01524                 },
01525         },
01526         .base_ext2 = {
01527                 .tempSlopeLow = 40,
01528                 .tempSlopeHigh = 50,
01529                 .xatten1DBLow = {0, 0, 0},
01530                 .xatten1MarginLow = {0, 0, 0},
01531                 .xatten1DBHigh = {0, 0, 0},
01532                 .xatten1MarginHigh = {0, 0, 0}
01533         },
01534         .calFreqPier5G = {
01535                 FREQ2FBIN(5180, 0),
01536                 FREQ2FBIN(5220, 0),
01537                 FREQ2FBIN(5320, 0),
01538                 FREQ2FBIN(5400, 0),
01539                 FREQ2FBIN(5500, 0),
01540                 FREQ2FBIN(5600, 0),
01541                 FREQ2FBIN(5700, 0),
01542                 FREQ2FBIN(5825, 0)
01543         },
01544         .calPierData5G = {
01545                 {
01546                         {0, 0, 0, 0, 0, 0},
01547                         {0, 0, 0, 0, 0, 0},
01548                         {0, 0, 0, 0, 0, 0},
01549                         {0, 0, 0, 0, 0, 0},
01550                         {0, 0, 0, 0, 0, 0},
01551                         {0, 0, 0, 0, 0, 0},
01552                         {0, 0, 0, 0, 0, 0},
01553                         {0, 0, 0, 0, 0, 0},
01554                 },
01555                 {
01556                         {0, 0, 0, 0, 0, 0},
01557                         {0, 0, 0, 0, 0, 0},
01558                         {0, 0, 0, 0, 0, 0},
01559                         {0, 0, 0, 0, 0, 0},
01560                         {0, 0, 0, 0, 0, 0},
01561                         {0, 0, 0, 0, 0, 0},
01562                         {0, 0, 0, 0, 0, 0},
01563                         {0, 0, 0, 0, 0, 0},
01564                 },
01565                 {
01566                         {0, 0, 0, 0, 0, 0},
01567                         {0, 0, 0, 0, 0, 0},
01568                         {0, 0, 0, 0, 0, 0},
01569                         {0, 0, 0, 0, 0, 0},
01570                         {0, 0, 0, 0, 0, 0},
01571                         {0, 0, 0, 0, 0, 0},
01572                         {0, 0, 0, 0, 0, 0},
01573                         {0, 0, 0, 0, 0, 0},
01574                 },
01575 
01576         },
01577         .calTarget_freqbin_5G = {
01578                 FREQ2FBIN(5180, 0),
01579                 FREQ2FBIN(5240, 0),
01580                 FREQ2FBIN(5320, 0),
01581                 FREQ2FBIN(5400, 0),
01582                 FREQ2FBIN(5500, 0),
01583                 FREQ2FBIN(5600, 0),
01584                 FREQ2FBIN(5700, 0),
01585                 FREQ2FBIN(5825, 0)
01586         },
01587         .calTarget_freqbin_5GHT20 = {
01588                 FREQ2FBIN(5180, 0),
01589                 FREQ2FBIN(5240, 0),
01590                 FREQ2FBIN(5320, 0),
01591                 FREQ2FBIN(5400, 0),
01592                 FREQ2FBIN(5500, 0),
01593                 FREQ2FBIN(5700, 0),
01594                 FREQ2FBIN(5745, 0),
01595                 FREQ2FBIN(5825, 0)
01596         },
01597         .calTarget_freqbin_5GHT40 = {
01598                 FREQ2FBIN(5180, 0),
01599                 FREQ2FBIN(5240, 0),
01600                 FREQ2FBIN(5320, 0),
01601                 FREQ2FBIN(5400, 0),
01602                 FREQ2FBIN(5500, 0),
01603                 FREQ2FBIN(5700, 0),
01604                 FREQ2FBIN(5745, 0),
01605                 FREQ2FBIN(5825, 0)
01606         },
01607         .calTargetPower5G = {
01608                 /* 6-24,36,48,54 */
01609                 { {30, 30, 28, 24} },
01610                 { {30, 30, 28, 24} },
01611                 { {30, 30, 28, 24} },
01612                 { {30, 30, 28, 24} },
01613                 { {30, 30, 28, 24} },
01614                 { {30, 30, 28, 24} },
01615                 { {30, 30, 28, 24} },
01616                 { {30, 30, 28, 24} },
01617         },
01618         .calTargetPower5GHT20 = {
01619                 /*
01620                  * 0_8_16,1-3_9-11_17-19,
01621                  * 4,5,6,7,12,13,14,15,20,21,22,23
01622                  */
01623                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
01624                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
01625                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
01626                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
01627                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
01628                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
01629                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
01630                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
01631         },
01632         .calTargetPower5GHT40 =  {
01633                 /*
01634                  * 0_8_16,1-3_9-11_17-19,
01635                  * 4,5,6,7,12,13,14,15,20,21,22,23
01636                  */
01637                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
01638                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
01639                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
01640                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
01641                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
01642                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
01643                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
01644                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
01645         },
01646         .ctlIndex_5G =  {
01647                 0x10, 0x16, 0x18, 0x40, 0x46,
01648                 0x48, 0x30, 0x36, 0x38
01649         },
01650         .ctl_freqbin_5G =  {
01651                 {
01652                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01653                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01654                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
01655                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01656                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
01657                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01658                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01659                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01660                 },
01661                 {
01662                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01663                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01664                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
01665                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01666                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
01667                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01668                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01669                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01670                 },
01671 
01672                 {
01673                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01674                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
01675                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
01676                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
01677                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
01678                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
01679                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
01680                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
01681                 },
01682 
01683                 {
01684                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01685                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
01686                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
01687                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
01688                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
01689                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01690                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
01691                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
01692                 },
01693 
01694                 {
01695                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01696                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01697                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
01698                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
01699                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
01700                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
01701                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
01702                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
01703                 },
01704 
01705                 {
01706                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01707                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
01708                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
01709                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
01710                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
01711                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
01712                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
01713                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
01714                 },
01715 
01716                 {
01717                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01718                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
01719                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
01720                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
01721                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
01722                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
01723                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
01724                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
01725                 },
01726 
01727                 {
01728                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
01729                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
01730                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
01731                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
01732                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
01733                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
01734                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
01735                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
01736                 },
01737 
01738                 {
01739                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
01740                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
01741                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
01742                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
01743                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
01744                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
01745                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
01746                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
01747                 }
01748         },
01749         .ctlPowerData_5G = {
01750                 {
01751                         {
01752                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01753                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01754                         }
01755                 },
01756                 {
01757                         {
01758                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01759                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01760                         }
01761                 },
01762                 {
01763                         {
01764                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01765                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01766                         }
01767                 },
01768                 {
01769                         {
01770                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01771                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01772                         }
01773                 },
01774                 {
01775                         {
01776                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01777                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01778                         }
01779                 },
01780                 {
01781                         {
01782                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01783                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
01784                         }
01785                 },
01786                 {
01787                         {
01788                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01789                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
01790                         }
01791                 },
01792                 {
01793                         {
01794                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01795                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
01796                         }
01797                 },
01798                 {
01799                         {
01800                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
01801                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
01802                         }
01803                 },
01804         }
01805 };
01806 
01807 
01808 static const struct ar9300_eeprom ar9300_x112 = {
01809         .eepromVersion = 2,
01810         .templateVersion = 5,
01811         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
01812         .custData = {"x112-041-f0000"},
01813         .baseEepHeader = {
01814                 .regDmn = { LE16(0), LE16(0x1f) },
01815                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
01816                 .opCapFlags = {
01817                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
01818                         .eepMisc = 0,
01819                 },
01820                 .rfSilent = 0,
01821                 .blueToothOptions = 0,
01822                 .deviceCap = 0,
01823                 .deviceType = 5, /* takes lower byte in eeprom location */
01824                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
01825                 .params_for_tuning_caps = {0, 0},
01826                 .featureEnable = 0x0d,
01827                 /*
01828                  * bit0 - enable tx temp comp - disabled
01829                  * bit1 - enable tx volt comp - disabled
01830                  * bit2 - enable fastclock - enabled
01831                  * bit3 - enable doubling - enabled
01832                  * bit4 - enable internal regulator - disabled
01833                  * bit5 - enable pa predistortion - disabled
01834                  */
01835                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
01836                 .eepromWriteEnableGpio = 6,
01837                 .wlanDisableGpio = 0,
01838                 .wlanLedGpio = 8,
01839                 .rxBandSelectGpio = 0xff,
01840                 .txrxgain = 0x0,
01841                 .swreg = 0,
01842         },
01843         .modalHeader2G = {
01844                 /* ar9300_modal_eep_header  2g */
01845                 /* 4 idle,t1,t2,b(4 bits per setting) */
01846                 .antCtrlCommon = LE32(0x110),
01847                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
01848                 .antCtrlCommon2 = LE32(0x22222),
01849 
01850                 /*
01851                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
01852                  * rx1, rx12, b (2 bits each)
01853                  */
01854                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
01855 
01856                 /*
01857                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
01858                  * for ar9280 (0xa20c/b20c 5:0)
01859                  */
01860                 .xatten1DB = {0x1b, 0x1b, 0x1b},
01861 
01862                 /*
01863                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
01864                  * for ar9280 (0xa20c/b20c 16:12
01865                  */
01866                 .xatten1Margin = {0x15, 0x15, 0x15},
01867                 .tempSlope = 50,
01868                 .voltSlope = 0,
01869 
01870                 /*
01871                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
01872                  * channels in usual fbin coding format
01873                  */
01874                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
01875 
01876                 /*
01877                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
01878                  * if the register is per chain
01879                  */
01880                 .noiseFloorThreshCh = {-1, 0, 0},
01881                 .ob = {1, 1, 1},/* 3 chain */
01882                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
01883                 .db_stage3 = {0, 0, 0},
01884                 .db_stage4 = {0, 0, 0},
01885                 .xpaBiasLvl = 0,
01886                 .txFrameToDataStart = 0x0e,
01887                 .txFrameToPaOn = 0x0e,
01888                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
01889                 .antennaGain = 0,
01890                 .switchSettling = 0x2c,
01891                 .adcDesiredSize = -30,
01892                 .txEndToXpaOff = 0,
01893                 .txEndToRxOn = 0x2,
01894                 .txFrameToXpaOn = 0xe,
01895                 .thresh62 = 28,
01896                 .papdRateMaskHt20 = LE32(0x0c80c080),
01897                 .papdRateMaskHt40 = LE32(0x0080c080),
01898                 .futureModal = {
01899                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
01900                 },
01901         },
01902         .base_ext1 = {
01903                 .ant_div_control = 0,
01904                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
01905         },
01906         .calFreqPier2G = {
01907                 FREQ2FBIN(2412, 1),
01908                 FREQ2FBIN(2437, 1),
01909                 FREQ2FBIN(2472, 1),
01910         },
01911         /* ar9300_cal_data_per_freq_op_loop 2g */
01912         .calPierData2G = {
01913                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01914                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01915                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
01916         },
01917         .calTarget_freqbin_Cck = {
01918                 FREQ2FBIN(2412, 1),
01919                 FREQ2FBIN(2472, 1),
01920         },
01921         .calTarget_freqbin_2G = {
01922                 FREQ2FBIN(2412, 1),
01923                 FREQ2FBIN(2437, 1),
01924                 FREQ2FBIN(2472, 1)
01925         },
01926         .calTarget_freqbin_2GHT20 = {
01927                 FREQ2FBIN(2412, 1),
01928                 FREQ2FBIN(2437, 1),
01929                 FREQ2FBIN(2472, 1)
01930         },
01931         .calTarget_freqbin_2GHT40 = {
01932                 FREQ2FBIN(2412, 1),
01933                 FREQ2FBIN(2437, 1),
01934                 FREQ2FBIN(2472, 1)
01935         },
01936         .calTargetPowerCck = {
01937                 /* 1L-5L,5S,11L,11s */
01938                 { {38, 38, 38, 38} },
01939                 { {38, 38, 38, 38} },
01940         },
01941         .calTargetPower2G = {
01942                 /* 6-24,36,48,54 */
01943                 { {38, 38, 36, 34} },
01944                 { {38, 38, 36, 34} },
01945                 { {38, 38, 34, 32} },
01946         },
01947         .calTargetPower2GHT20 = {
01948                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
01949                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
01950                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
01951         },
01952         .calTargetPower2GHT40 = {
01953                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
01954                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
01955                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
01956         },
01957         .ctlIndex_2G =  {
01958                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
01959                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
01960         },
01961         .ctl_freqbin_2G = {
01962                 {
01963                         FREQ2FBIN(2412, 1),
01964                         FREQ2FBIN(2417, 1),
01965                         FREQ2FBIN(2457, 1),
01966                         FREQ2FBIN(2462, 1)
01967                 },
01968                 {
01969                         FREQ2FBIN(2412, 1),
01970                         FREQ2FBIN(2417, 1),
01971                         FREQ2FBIN(2462, 1),
01972                         0xFF,
01973                 },
01974 
01975                 {
01976                         FREQ2FBIN(2412, 1),
01977                         FREQ2FBIN(2417, 1),
01978                         FREQ2FBIN(2462, 1),
01979                         0xFF,
01980                 },
01981                 {
01982                         FREQ2FBIN(2422, 1),
01983                         FREQ2FBIN(2427, 1),
01984                         FREQ2FBIN(2447, 1),
01985                         FREQ2FBIN(2452, 1)
01986                 },
01987 
01988                 {
01989                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
01990                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
01991                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
01992                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
01993                 },
01994 
01995                 {
01996                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
01997                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
01998                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
01999                         0,
02000                 },
02001 
02002                 {
02003                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
02004                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
02005                         FREQ2FBIN(2472, 1),
02006                         0,
02007                 },
02008 
02009                 {
02010                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
02011                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
02012                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
02013                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
02014                 },
02015 
02016                 {
02017                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
02018                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
02019                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
02020                 },
02021 
02022                 {
02023                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
02024                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
02025                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
02026                         0
02027                 },
02028 
02029                 {
02030                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
02031                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
02032                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
02033                         0
02034                 },
02035 
02036                 {
02037                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
02038                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
02039                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
02040                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
02041                 }
02042         },
02043         .ctlPowerData_2G = {
02044                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02045                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02046                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
02047 
02048                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
02049                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02050                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02051 
02052                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
02053                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02054                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02055 
02056                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02057                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
02058                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
02059         },
02060         .modalHeader5G = {
02061                 /* 4 idle,t1,t2,b (4 bits per setting) */
02062                 .antCtrlCommon = LE32(0x110),
02063                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
02064                 .antCtrlCommon2 = LE32(0x22222),
02065                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
02066                 .antCtrlChain = {
02067                         LE16(0x0), LE16(0x0), LE16(0x0),
02068                 },
02069                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
02070                 .xatten1DB = {0x13, 0x19, 0x17},
02071 
02072                 /*
02073                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
02074                  * for merlin (0xa20c/b20c 16:12
02075                  */
02076                 .xatten1Margin = {0x19, 0x19, 0x19},
02077                 .tempSlope = 70,
02078                 .voltSlope = 15,
02079                 /* spurChans spur channels in usual fbin coding format */
02080                 .spurChans = {0, 0, 0, 0, 0},
02081                 /* noiseFloorThreshch check if the register is per chain */
02082                 .noiseFloorThreshCh = {-1, 0, 0},
02083                 .ob = {3, 3, 3}, /* 3 chain */
02084                 .db_stage2 = {3, 3, 3}, /* 3 chain */
02085                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
02086                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
02087                 .xpaBiasLvl = 0,
02088                 .txFrameToDataStart = 0x0e,
02089                 .txFrameToPaOn = 0x0e,
02090                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
02091                 .antennaGain = 0,
02092                 .switchSettling = 0x2d,
02093                 .adcDesiredSize = -30,
02094                 .txEndToXpaOff = 0,
02095                 .txEndToRxOn = 0x2,
02096                 .txFrameToXpaOn = 0xe,
02097                 .thresh62 = 28,
02098                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
02099                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
02100                 .futureModal = {
02101                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
02102                 },
02103         },
02104         .base_ext2 = {
02105                 .tempSlopeLow = 72,
02106                 .tempSlopeHigh = 105,
02107                 .xatten1DBLow = {0x10, 0x14, 0x10},
02108                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
02109                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
02110                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
02111         },
02112         .calFreqPier5G = {
02113                 FREQ2FBIN(5180, 0),
02114                 FREQ2FBIN(5220, 0),
02115                 FREQ2FBIN(5320, 0),
02116                 FREQ2FBIN(5400, 0),
02117                 FREQ2FBIN(5500, 0),
02118                 FREQ2FBIN(5600, 0),
02119                 FREQ2FBIN(5700, 0),
02120                 FREQ2FBIN(5785, 0)
02121         },
02122         .calPierData5G = {
02123                 {
02124                         {0, 0, 0, 0, 0, 0},
02125                         {0, 0, 0, 0, 0, 0},
02126                         {0, 0, 0, 0, 0, 0},
02127                         {0, 0, 0, 0, 0, 0},
02128                         {0, 0, 0, 0, 0, 0},
02129                         {0, 0, 0, 0, 0, 0},
02130                         {0, 0, 0, 0, 0, 0},
02131                         {0, 0, 0, 0, 0, 0},
02132                 },
02133                 {
02134                         {0, 0, 0, 0, 0, 0},
02135                         {0, 0, 0, 0, 0, 0},
02136                         {0, 0, 0, 0, 0, 0},
02137                         {0, 0, 0, 0, 0, 0},
02138                         {0, 0, 0, 0, 0, 0},
02139                         {0, 0, 0, 0, 0, 0},
02140                         {0, 0, 0, 0, 0, 0},
02141                         {0, 0, 0, 0, 0, 0},
02142                 },
02143                 {
02144                         {0, 0, 0, 0, 0, 0},
02145                         {0, 0, 0, 0, 0, 0},
02146                         {0, 0, 0, 0, 0, 0},
02147                         {0, 0, 0, 0, 0, 0},
02148                         {0, 0, 0, 0, 0, 0},
02149                         {0, 0, 0, 0, 0, 0},
02150                         {0, 0, 0, 0, 0, 0},
02151                         {0, 0, 0, 0, 0, 0},
02152                 },
02153 
02154         },
02155         .calTarget_freqbin_5G = {
02156                 FREQ2FBIN(5180, 0),
02157                 FREQ2FBIN(5220, 0),
02158                 FREQ2FBIN(5320, 0),
02159                 FREQ2FBIN(5400, 0),
02160                 FREQ2FBIN(5500, 0),
02161                 FREQ2FBIN(5600, 0),
02162                 FREQ2FBIN(5725, 0),
02163                 FREQ2FBIN(5825, 0)
02164         },
02165         .calTarget_freqbin_5GHT20 = {
02166                 FREQ2FBIN(5180, 0),
02167                 FREQ2FBIN(5220, 0),
02168                 FREQ2FBIN(5320, 0),
02169                 FREQ2FBIN(5400, 0),
02170                 FREQ2FBIN(5500, 0),
02171                 FREQ2FBIN(5600, 0),
02172                 FREQ2FBIN(5725, 0),
02173                 FREQ2FBIN(5825, 0)
02174         },
02175         .calTarget_freqbin_5GHT40 = {
02176                 FREQ2FBIN(5180, 0),
02177                 FREQ2FBIN(5220, 0),
02178                 FREQ2FBIN(5320, 0),
02179                 FREQ2FBIN(5400, 0),
02180                 FREQ2FBIN(5500, 0),
02181                 FREQ2FBIN(5600, 0),
02182                 FREQ2FBIN(5725, 0),
02183                 FREQ2FBIN(5825, 0)
02184         },
02185         .calTargetPower5G = {
02186                 /* 6-24,36,48,54 */
02187                 { {32, 32, 28, 26} },
02188                 { {32, 32, 28, 26} },
02189                 { {32, 32, 28, 26} },
02190                 { {32, 32, 26, 24} },
02191                 { {32, 32, 26, 24} },
02192                 { {32, 32, 24, 22} },
02193                 { {30, 30, 24, 22} },
02194                 { {30, 30, 24, 22} },
02195         },
02196         .calTargetPower5GHT20 = {
02197                 /*
02198                  * 0_8_16,1-3_9-11_17-19,
02199                  * 4,5,6,7,12,13,14,15,20,21,22,23
02200                  */
02201                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
02202                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
02203                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
02204                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
02205                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
02206                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
02207                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
02208                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
02209         },
02210         .calTargetPower5GHT40 =  {
02211                 /*
02212                  * 0_8_16,1-3_9-11_17-19,
02213                  * 4,5,6,7,12,13,14,15,20,21,22,23
02214                  */
02215                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
02216                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
02217                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
02218                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
02219                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
02220                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
02221                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
02222                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
02223         },
02224         .ctlIndex_5G =  {
02225                 0x10, 0x16, 0x18, 0x40, 0x46,
02226                 0x48, 0x30, 0x36, 0x38
02227         },
02228         .ctl_freqbin_5G =  {
02229                 {
02230                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02231                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
02232                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
02233                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
02234                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
02235                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
02236                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
02237                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
02238                 },
02239                 {
02240                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02241                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
02242                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
02243                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
02244                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
02245                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
02246                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
02247                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
02248                 },
02249 
02250                 {
02251                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
02252                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
02253                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
02254                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
02255                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
02256                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
02257                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
02258                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
02259                 },
02260 
02261                 {
02262                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02263                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
02264                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
02265                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
02266                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
02267                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
02268                         /* Data[3].ctledges[6].bchannel */ 0xFF,
02269                         /* Data[3].ctledges[7].bchannel */ 0xFF,
02270                 },
02271 
02272                 {
02273                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02274                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
02275                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
02276                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
02277                         /* Data[4].ctledges[4].bchannel */ 0xFF,
02278                         /* Data[4].ctledges[5].bchannel */ 0xFF,
02279                         /* Data[4].ctledges[6].bchannel */ 0xFF,
02280                         /* Data[4].ctledges[7].bchannel */ 0xFF,
02281                 },
02282 
02283                 {
02284                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
02285                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
02286                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
02287                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
02288                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
02289                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
02290                         /* Data[5].ctledges[6].bchannel */ 0xFF,
02291                         /* Data[5].ctledges[7].bchannel */ 0xFF
02292                 },
02293 
02294                 {
02295                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02296                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
02297                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
02298                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
02299                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
02300                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
02301                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
02302                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
02303                 },
02304 
02305                 {
02306                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
02307                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
02308                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
02309                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
02310                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
02311                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
02312                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
02313                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
02314                 },
02315 
02316                 {
02317                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
02318                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
02319                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
02320                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
02321                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
02322                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
02323                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
02324                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
02325                 }
02326         },
02327         .ctlPowerData_5G = {
02328                 {
02329                         {
02330                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02331                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02332                         }
02333                 },
02334                 {
02335                         {
02336                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02337                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02338                         }
02339                 },
02340                 {
02341                         {
02342                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02343                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02344                         }
02345                 },
02346                 {
02347                         {
02348                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02349                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02350                         }
02351                 },
02352                 {
02353                         {
02354                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02355                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02356                         }
02357                 },
02358                 {
02359                         {
02360                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02361                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02362                         }
02363                 },
02364                 {
02365                         {
02366                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02367                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02368                         }
02369                 },
02370                 {
02371                         {
02372                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02373                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02374                         }
02375                 },
02376                 {
02377                         {
02378                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
02379                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02380                         }
02381                 },
02382         }
02383 };
02384 
02385 static const struct ar9300_eeprom ar9300_h116 = {
02386         .eepromVersion = 2,
02387         .templateVersion = 4,
02388         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
02389         .custData = {"h116-041-f0000"},
02390         .baseEepHeader = {
02391                 .regDmn = { LE16(0), LE16(0x1f) },
02392                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
02393                 .opCapFlags = {
02394                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
02395                         .eepMisc = 0,
02396                 },
02397                 .rfSilent = 0,
02398                 .blueToothOptions = 0,
02399                 .deviceCap = 0,
02400                 .deviceType = 5, /* takes lower byte in eeprom location */
02401                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
02402                 .params_for_tuning_caps = {0, 0},
02403                 .featureEnable = 0x0d,
02404                  /*
02405                   * bit0 - enable tx temp comp - disabled
02406                   * bit1 - enable tx volt comp - disabled
02407                   * bit2 - enable fastClock - enabled
02408                   * bit3 - enable doubling - enabled
02409                   * bit4 - enable internal regulator - disabled
02410                   * bit5 - enable pa predistortion - disabled
02411                   */
02412                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
02413                 .eepromWriteEnableGpio = 6,
02414                 .wlanDisableGpio = 0,
02415                 .wlanLedGpio = 8,
02416                 .rxBandSelectGpio = 0xff,
02417                 .txrxgain = 0x10,
02418                 .swreg = 0,
02419          },
02420         .modalHeader2G = {
02421         /* ar9300_modal_eep_header  2g */
02422                 /* 4 idle,t1,t2,b(4 bits per setting) */
02423                 .antCtrlCommon = LE32(0x110),
02424                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
02425                 .antCtrlCommon2 = LE32(0x44444),
02426 
02427                 /*
02428                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
02429                  * rx1, rx12, b (2 bits each)
02430                  */
02431                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
02432 
02433                 /*
02434                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
02435                  * for ar9280 (0xa20c/b20c 5:0)
02436                  */
02437                 .xatten1DB = {0x1f, 0x1f, 0x1f},
02438 
02439                 /*
02440                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
02441                  * for ar9280 (0xa20c/b20c 16:12
02442                  */
02443                 .xatten1Margin = {0x12, 0x12, 0x12},
02444                 .tempSlope = 25,
02445                 .voltSlope = 0,
02446 
02447                 /*
02448                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
02449                  * channels in usual fbin coding format
02450                  */
02451                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
02452 
02453                 /*
02454                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
02455                  * if the register is per chain
02456                  */
02457                 .noiseFloorThreshCh = {-1, 0, 0},
02458                 .ob = {1, 1, 1},/* 3 chain */
02459                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
02460                 .db_stage3 = {0, 0, 0},
02461                 .db_stage4 = {0, 0, 0},
02462                 .xpaBiasLvl = 0,
02463                 .txFrameToDataStart = 0x0e,
02464                 .txFrameToPaOn = 0x0e,
02465                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
02466                 .antennaGain = 0,
02467                 .switchSettling = 0x2c,
02468                 .adcDesiredSize = -30,
02469                 .txEndToXpaOff = 0,
02470                 .txEndToRxOn = 0x2,
02471                 .txFrameToXpaOn = 0xe,
02472                 .thresh62 = 28,
02473                 .papdRateMaskHt20 = LE32(0x0c80C080),
02474                 .papdRateMaskHt40 = LE32(0x0080C080),
02475                 .futureModal = {
02476                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
02477                 },
02478          },
02479          .base_ext1 = {
02480                 .ant_div_control = 0,
02481                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
02482          },
02483         .calFreqPier2G = {
02484                 FREQ2FBIN(2412, 1),
02485                 FREQ2FBIN(2437, 1),
02486                 FREQ2FBIN(2472, 1),
02487          },
02488         /* ar9300_cal_data_per_freq_op_loop 2g */
02489         .calPierData2G = {
02490                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
02491                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
02492                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
02493          },
02494         .calTarget_freqbin_Cck = {
02495                 FREQ2FBIN(2412, 1),
02496                 FREQ2FBIN(2472, 1),
02497          },
02498         .calTarget_freqbin_2G = {
02499                 FREQ2FBIN(2412, 1),
02500                 FREQ2FBIN(2437, 1),
02501                 FREQ2FBIN(2472, 1)
02502          },
02503         .calTarget_freqbin_2GHT20 = {
02504                 FREQ2FBIN(2412, 1),
02505                 FREQ2FBIN(2437, 1),
02506                 FREQ2FBIN(2472, 1)
02507          },
02508         .calTarget_freqbin_2GHT40 = {
02509                 FREQ2FBIN(2412, 1),
02510                 FREQ2FBIN(2437, 1),
02511                 FREQ2FBIN(2472, 1)
02512          },
02513         .calTargetPowerCck = {
02514                  /* 1L-5L,5S,11L,11S */
02515                  { {34, 34, 34, 34} },
02516                  { {34, 34, 34, 34} },
02517         },
02518         .calTargetPower2G = {
02519                  /* 6-24,36,48,54 */
02520                  { {34, 34, 32, 32} },
02521                  { {34, 34, 32, 32} },
02522                  { {34, 34, 32, 32} },
02523         },
02524         .calTargetPower2GHT20 = {
02525                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
02526                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
02527                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
02528         },
02529         .calTargetPower2GHT40 = {
02530                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
02531                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
02532                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
02533         },
02534         .ctlIndex_2G =  {
02535                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
02536                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
02537         },
02538         .ctl_freqbin_2G = {
02539                 {
02540                         FREQ2FBIN(2412, 1),
02541                         FREQ2FBIN(2417, 1),
02542                         FREQ2FBIN(2457, 1),
02543                         FREQ2FBIN(2462, 1)
02544                 },
02545                 {
02546                         FREQ2FBIN(2412, 1),
02547                         FREQ2FBIN(2417, 1),
02548                         FREQ2FBIN(2462, 1),
02549                         0xFF,
02550                 },
02551 
02552                 {
02553                         FREQ2FBIN(2412, 1),
02554                         FREQ2FBIN(2417, 1),
02555                         FREQ2FBIN(2462, 1),
02556                         0xFF,
02557                 },
02558                 {
02559                         FREQ2FBIN(2422, 1),
02560                         FREQ2FBIN(2427, 1),
02561                         FREQ2FBIN(2447, 1),
02562                         FREQ2FBIN(2452, 1)
02563                 },
02564 
02565                 {
02566                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02567                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02568                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
02569                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
02570                 },
02571 
02572                 {
02573                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02574                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02575                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
02576                         0,
02577                 },
02578 
02579                 {
02580                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02581                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02582                         FREQ2FBIN(2472, 1),
02583                         0,
02584                 },
02585 
02586                 {
02587                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
02588                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
02589                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
02590                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
02591                 },
02592 
02593                 {
02594                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02595                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02596                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
02597                 },
02598 
02599                 {
02600                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02601                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02602                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
02603                         0
02604                 },
02605 
02606                 {
02607                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
02608                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
02609                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
02610                         0
02611                 },
02612 
02613                 {
02614                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
02615                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
02616                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
02617                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
02618                 }
02619          },
02620         .ctlPowerData_2G = {
02621                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02622                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02623                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
02624 
02625                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
02626                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02627                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02628 
02629                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
02630                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02631                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02632 
02633                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
02634                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
02635                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
02636          },
02637         .modalHeader5G = {
02638                 /* 4 idle,t1,t2,b (4 bits per setting) */
02639                 .antCtrlCommon = LE32(0x220),
02640                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
02641                 .antCtrlCommon2 = LE32(0x44444),
02642                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
02643                 .antCtrlChain = {
02644                         LE16(0x150), LE16(0x150), LE16(0x150),
02645                 },
02646                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
02647                 .xatten1DB = {0x19, 0x19, 0x19},
02648 
02649                 /*
02650                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
02651                  * for merlin (0xa20c/b20c 16:12
02652                  */
02653                 .xatten1Margin = {0x14, 0x14, 0x14},
02654                 .tempSlope = 70,
02655                 .voltSlope = 0,
02656                 /* spurChans spur channels in usual fbin coding format */
02657                 .spurChans = {0, 0, 0, 0, 0},
02658                 /* noiseFloorThreshCh Check if the register is per chain */
02659                 .noiseFloorThreshCh = {-1, 0, 0},
02660                 .ob = {3, 3, 3}, /* 3 chain */
02661                 .db_stage2 = {3, 3, 3}, /* 3 chain */
02662                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
02663                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
02664                 .xpaBiasLvl = 0,
02665                 .txFrameToDataStart = 0x0e,
02666                 .txFrameToPaOn = 0x0e,
02667                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
02668                 .antennaGain = 0,
02669                 .switchSettling = 0x2d,
02670                 .adcDesiredSize = -30,
02671                 .txEndToXpaOff = 0,
02672                 .txEndToRxOn = 0x2,
02673                 .txFrameToXpaOn = 0xe,
02674                 .thresh62 = 28,
02675                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
02676                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
02677                 .futureModal = {
02678                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
02679                 },
02680          },
02681         .base_ext2 = {
02682                 .tempSlopeLow = 35,
02683                 .tempSlopeHigh = 50,
02684                 .xatten1DBLow = {0, 0, 0},
02685                 .xatten1MarginLow = {0, 0, 0},
02686                 .xatten1DBHigh = {0, 0, 0},
02687                 .xatten1MarginHigh = {0, 0, 0}
02688          },
02689         .calFreqPier5G = {
02690                 FREQ2FBIN(5180, 0),
02691                 FREQ2FBIN(5220, 0),
02692                 FREQ2FBIN(5320, 0),
02693                 FREQ2FBIN(5400, 0),
02694                 FREQ2FBIN(5500, 0),
02695                 FREQ2FBIN(5600, 0),
02696                 FREQ2FBIN(5700, 0),
02697                 FREQ2FBIN(5785, 0)
02698         },
02699         .calPierData5G = {
02700                         {
02701                                 {0, 0, 0, 0, 0, 0},
02702                                 {0, 0, 0, 0, 0, 0},
02703                                 {0, 0, 0, 0, 0, 0},
02704                                 {0, 0, 0, 0, 0, 0},
02705                                 {0, 0, 0, 0, 0, 0},
02706                                 {0, 0, 0, 0, 0, 0},
02707                                 {0, 0, 0, 0, 0, 0},
02708                                 {0, 0, 0, 0, 0, 0},
02709                         },
02710                         {
02711                                 {0, 0, 0, 0, 0, 0},
02712                                 {0, 0, 0, 0, 0, 0},
02713                                 {0, 0, 0, 0, 0, 0},
02714                                 {0, 0, 0, 0, 0, 0},
02715                                 {0, 0, 0, 0, 0, 0},
02716                                 {0, 0, 0, 0, 0, 0},
02717                                 {0, 0, 0, 0, 0, 0},
02718                                 {0, 0, 0, 0, 0, 0},
02719                         },
02720                         {
02721                                 {0, 0, 0, 0, 0, 0},
02722                                 {0, 0, 0, 0, 0, 0},
02723                                 {0, 0, 0, 0, 0, 0},
02724                                 {0, 0, 0, 0, 0, 0},
02725                                 {0, 0, 0, 0, 0, 0},
02726                                 {0, 0, 0, 0, 0, 0},
02727                                 {0, 0, 0, 0, 0, 0},
02728                                 {0, 0, 0, 0, 0, 0},
02729                         },
02730 
02731         },
02732         .calTarget_freqbin_5G = {
02733                 FREQ2FBIN(5180, 0),
02734                 FREQ2FBIN(5240, 0),
02735                 FREQ2FBIN(5320, 0),
02736                 FREQ2FBIN(5400, 0),
02737                 FREQ2FBIN(5500, 0),
02738                 FREQ2FBIN(5600, 0),
02739                 FREQ2FBIN(5700, 0),
02740                 FREQ2FBIN(5825, 0)
02741         },
02742         .calTarget_freqbin_5GHT20 = {
02743                 FREQ2FBIN(5180, 0),
02744                 FREQ2FBIN(5240, 0),
02745                 FREQ2FBIN(5320, 0),
02746                 FREQ2FBIN(5400, 0),
02747                 FREQ2FBIN(5500, 0),
02748                 FREQ2FBIN(5700, 0),
02749                 FREQ2FBIN(5745, 0),
02750                 FREQ2FBIN(5825, 0)
02751         },
02752         .calTarget_freqbin_5GHT40 = {
02753                 FREQ2FBIN(5180, 0),
02754                 FREQ2FBIN(5240, 0),
02755                 FREQ2FBIN(5320, 0),
02756                 FREQ2FBIN(5400, 0),
02757                 FREQ2FBIN(5500, 0),
02758                 FREQ2FBIN(5700, 0),
02759                 FREQ2FBIN(5745, 0),
02760                 FREQ2FBIN(5825, 0)
02761          },
02762         .calTargetPower5G = {
02763                 /* 6-24,36,48,54 */
02764                 { {30, 30, 28, 24} },
02765                 { {30, 30, 28, 24} },
02766                 { {30, 30, 28, 24} },
02767                 { {30, 30, 28, 24} },
02768                 { {30, 30, 28, 24} },
02769                 { {30, 30, 28, 24} },
02770                 { {30, 30, 28, 24} },
02771                 { {30, 30, 28, 24} },
02772          },
02773         .calTargetPower5GHT20 = {
02774                 /*
02775                  * 0_8_16,1-3_9-11_17-19,
02776                  * 4,5,6,7,12,13,14,15,20,21,22,23
02777                  */
02778                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
02779                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
02780                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
02781                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
02782                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
02783                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
02784                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
02785                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
02786          },
02787         .calTargetPower5GHT40 =  {
02788                 /*
02789                  * 0_8_16,1-3_9-11_17-19,
02790                  * 4,5,6,7,12,13,14,15,20,21,22,23
02791                  */
02792                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
02793                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
02794                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
02795                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
02796                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
02797                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
02798                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
02799                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
02800          },
02801         .ctlIndex_5G =  {
02802                 0x10, 0x16, 0x18, 0x40, 0x46,
02803                 0x48, 0x30, 0x36, 0x38
02804         },
02805         .ctl_freqbin_5G =  {
02806                 {
02807                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02808                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
02809                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
02810                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
02811                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
02812                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
02813                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
02814                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
02815                 },
02816                 {
02817                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02818                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
02819                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
02820                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
02821                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
02822                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
02823                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
02824                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
02825                 },
02826 
02827                 {
02828                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
02829                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
02830                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
02831                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
02832                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
02833                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
02834                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
02835                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
02836                 },
02837 
02838                 {
02839                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02840                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
02841                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
02842                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
02843                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
02844                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
02845                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
02846                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
02847                 },
02848 
02849                 {
02850                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02851                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
02852                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
02853                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
02854                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
02855                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
02856                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
02857                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
02858                 },
02859 
02860                 {
02861                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
02862                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
02863                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
02864                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
02865                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
02866                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
02867                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
02868                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
02869                 },
02870 
02871                 {
02872                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02873                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
02874                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
02875                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
02876                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
02877                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
02878                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
02879                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
02880                 },
02881 
02882                 {
02883                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
02884                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
02885                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
02886                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
02887                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
02888                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
02889                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
02890                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
02891                 },
02892 
02893                 {
02894                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
02895                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
02896                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
02897                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
02898                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
02899                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
02900                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
02901                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
02902                 }
02903          },
02904         .ctlPowerData_5G = {
02905                 {
02906                         {
02907                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02908                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02909                         }
02910                 },
02911                 {
02912                         {
02913                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02914                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02915                         }
02916                 },
02917                 {
02918                         {
02919                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02920                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02921                         }
02922                 },
02923                 {
02924                         {
02925                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02926                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02927                         }
02928                 },
02929                 {
02930                         {
02931                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02932                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02933                         }
02934                 },
02935                 {
02936                         {
02937                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02938                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
02939                         }
02940                 },
02941                 {
02942                         {
02943                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02944                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
02945                         }
02946                 },
02947                 {
02948                         {
02949                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02950                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
02951                         }
02952                 },
02953                 {
02954                         {
02955                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
02956                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
02957                         }
02958                 },
02959          }
02960 };
02961 
02962 
02963 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
02964         &ar9300_default,
02965         &ar9300_x112,
02966         &ar9300_h116,
02967         &ar9300_h112,
02968         &ar9300_x113,
02969 };
02970 
02971 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
02972 {
02973 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
02974         unsigned int it;
02975 
02976         for (it = 0; it < N_LOOP; it++)
02977                 if (ar9300_eep_templates[it]->templateVersion == id)
02978                         return ar9300_eep_templates[it];
02979         return NULL;
02980 #undef N_LOOP
02981 }
02982 
02983 
02984 static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
02985 {
02986         if (fbin == AR5416_BCHAN_UNUSED)
02987                 return fbin;
02988 
02989         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
02990 }
02991 
02992 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
02993 {
02994         return 0;
02995 }
02996 
02997 static int interpolate(int x, int xa, int xb, int ya, int yb)
02998 {
02999         int bf, factor, plus;
03000 
03001         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
03002         factor = bf / 2;
03003         plus = bf % 2;
03004         return ya + factor + plus;
03005 }
03006 
03007 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
03008                                       enum eeprom_param param)
03009 {
03010         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03011         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
03012 
03013         switch (param) {
03014         case EEP_MAC_LSW:
03015                 return eep->macAddr[0] << 8 | eep->macAddr[1];
03016         case EEP_MAC_MID:
03017                 return eep->macAddr[2] << 8 | eep->macAddr[3];
03018         case EEP_MAC_MSW:
03019                 return eep->macAddr[4] << 8 | eep->macAddr[5];
03020         case EEP_REG_0:
03021                 return (uint16_t)(pBase->regDmn[0]);
03022         case EEP_REG_1:
03023                 return (uint16_t)(pBase->regDmn[1]);
03024         case EEP_OP_CAP:
03025                 return pBase->deviceCap;
03026         case EEP_OP_MODE:
03027                 return pBase->opCapFlags.opFlags;
03028         case EEP_RF_SILENT:
03029                 return pBase->rfSilent;
03030         case EEP_TX_MASK:
03031                 return (pBase->txrxMask >> 4) & 0xf;
03032         case EEP_RX_MASK:
03033                 return pBase->txrxMask & 0xf;
03034         case EEP_DRIVE_STRENGTH:
03035 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
03036                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
03037         case EEP_INTERNAL_REGULATOR:
03038                 /* Bit 4 is internal regulator flag */
03039                 return (pBase->featureEnable & 0x10) >> 4;
03040         case EEP_SWREG:
03041                 return (uint32_t)(pBase->swreg);
03042         case EEP_PAPRD:
03043                 return !!(pBase->featureEnable & BIT(5));
03044         case EEP_CHAIN_MASK_REDUCE:
03045                 return (pBase->miscConfiguration >> 0x3) & 0x1;
03046         case EEP_ANT_DIV_CTL1:
03047                 return (uint32_t)(eep->base_ext1.ant_div_control);
03048         default:
03049                 return 0;
03050         }
03051 }
03052 
03053 static int ar9300_eeprom_read_byte(struct ath_common *common, int address,
03054                                     u8 *buffer)
03055 {
03056         u16 val;
03057 
03058         if (!ath9k_hw_nvram_read(common, address / 2, &val))
03059                 return 0;
03060 
03061         *buffer = (val >> (8 * (address % 2))) & 0xff;
03062         return 1;
03063 }
03064 
03065 static int ar9300_eeprom_read_word(struct ath_common *common, int address,
03066                                     u8 *buffer)
03067 {
03068         u16 val;
03069 
03070         if (!ath9k_hw_nvram_read(common, address / 2, &val))
03071                 return 0;
03072 
03073         buffer[0] = val >> 8;
03074         buffer[1] = val & 0xff;
03075 
03076         return 1;
03077 }
03078 
03079 static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
03080                                int count)
03081 {
03082         struct ath_common *common = ath9k_hw_common(ah);
03083         int i;
03084 
03085         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
03086                 DBG("ath9k: "
03087                         "eeprom address not in range\n");
03088                 return 0;
03089         }
03090 
03091         /*
03092          * Since we're reading the bytes in reverse order from a little-endian
03093          * word stream, an even address means we only use the lower half of
03094          * the 16-bit word at that address
03095          */
03096         if (address % 2 == 0) {
03097                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
03098                         goto error;
03099 
03100                 count--;
03101         }
03102 
03103         for (i = 0; i < count / 2; i++) {
03104                 if (!ar9300_eeprom_read_word(common, address, buffer))
03105                         goto error;
03106 
03107                 address -= 2;
03108                 buffer += 2;
03109         }
03110 
03111         if (count % 2)
03112                 if (!ar9300_eeprom_read_byte(common, address, buffer))
03113                         goto error;
03114 
03115         return 1;
03116 
03117 error:
03118         DBG("ath9k: "
03119                 "unable to read eeprom region at offset %d\n", address);
03120         return 0;
03121 }
03122 
03123 static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
03124 {
03125         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
03126 
03127         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
03128                            AR9300_OTP_STATUS_VALID, 1000))
03129                 return 0;
03130 
03131         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
03132         return 1;
03133 }
03134 
03135 static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
03136                             int count)
03137 {
03138         u32 data;
03139         int i;
03140 
03141         for (i = 0; i < count; i++) {
03142                 int offset = 8 * ((address - i) % 4);
03143                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
03144                         return 0;
03145 
03146                 buffer[i] = (data >> offset) & 0xff;
03147         }
03148 
03149         return 1;
03150 }
03151 
03152 
03153 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
03154                                    int *length, int *major, int *minor)
03155 {
03156         unsigned long value[4];
03157 
03158         value[0] = best[0];
03159         value[1] = best[1];
03160         value[2] = best[2];
03161         value[3] = best[3];
03162         *code = ((value[0] >> 5) & 0x0007);
03163         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
03164         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
03165         *major = (value[2] & 0x000f);
03166         *minor = (value[3] & 0x00ff);
03167 }
03168 
03169 static u16 ar9300_comp_cksum(u8 *data, int dsize)
03170 {
03171         int it, checksum = 0;
03172 
03173         for (it = 0; it < dsize; it++) {
03174                 checksum += data[it];
03175                 checksum &= 0xffff;
03176         }
03177 
03178         return checksum;
03179 }
03180 
03181 static int ar9300_uncompress_block(struct ath_hw *ah __unused,
03182                                     u8 *mptr,
03183                                     int mdataSize,
03184                                     u8 *block,
03185                                     int size)
03186 {
03187         int it;
03188         int spot;
03189         int offset;
03190         int length;
03191 
03192         spot = 0;
03193 
03194         for (it = 0; it < size; it += (length+2)) {
03195                 offset = block[it];
03196                 offset &= 0xff;
03197                 spot += offset;
03198                 length = block[it+1];
03199                 length &= 0xff;
03200 
03201                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
03202                         DBG2("ath9k: "
03203                                 "Restore at %d: spot=%d offset=%d length=%d\n",
03204                                 it, spot, offset, length);
03205                         memcpy(&mptr[spot], &block[it+2], length);
03206                         spot += length;
03207                 } else if (length > 0) {
03208                         DBG("ath9k: "
03209                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
03210                                 it, spot, offset, length);
03211                         return 0;
03212                 }
03213         }
03214         return 1;
03215 }
03216 
03217 static int ar9300_compress_decision(struct ath_hw *ah,
03218                                     int it,
03219                                     int code,
03220                                     int reference,
03221                                     u8 *mptr,
03222                                     u8 *word, int length, int mdata_size)
03223 {
03224         const struct ar9300_eeprom *eep = NULL;
03225 
03226         switch (code) {
03227         case _CompressNone:
03228                 if (length != mdata_size) {
03229                         DBG("ath9k: "
03230                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
03231                                 mdata_size, length);
03232                         return -1;
03233                 }
03234                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
03235                 DBG2("ath9k: "
03236                         "restored eeprom %d: uncompressed, length %d\n",
03237                         it, length);
03238                 break;
03239         case _CompressBlock:
03240                 if (reference == 0) {
03241                 } else {
03242                         eep = ar9003_eeprom_struct_find_by_id(reference);
03243                         if (eep == NULL) {
03244                                 DBG("ath9k: "
03245                                         "can't find reference eeprom struct %d\n",
03246                                         reference);
03247                                 return -1;
03248                         }
03249                         memcpy(mptr, eep, mdata_size);
03250                 }
03251                 DBG2("ath9k: "
03252                         "restore eeprom %d: block, reference %d, length %d\n",
03253                         it, reference, length);
03254                 ar9300_uncompress_block(ah, mptr, mdata_size,
03255                                         (u8 *) (word + COMP_HDR_LEN), length);
03256                 break;
03257         default:
03258                 DBG("ath9k: "
03259                         "unknown compression code %d\n", code);
03260                 return -1;
03261         }
03262         return 0;
03263 }
03264 
03265 typedef int (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
03266                                int count);
03267 
03268 static int ar9300_check_header(void *data)
03269 {
03270         u32 *word = data;
03271         return !(*word == 0 || *word == (unsigned int)~0);
03272 }
03273 
03274 static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
03275                                        int base_addr)
03276 {
03277         u8 header[4];
03278 
03279         if (!read(ah, base_addr, header, 4))
03280                 return 0;
03281 
03282         return ar9300_check_header(header);
03283 }
03284 
03285 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
03286                                        int mdata_size)
03287 {
03288         struct ath_common *common = ath9k_hw_common(ah);
03289         u16 *data = (u16 *) mptr;
03290         int i;
03291 
03292         for (i = 0; i < mdata_size / 2; i++, data++)
03293                 ath9k_hw_nvram_read(common, i, data);
03294 
03295         return 0;
03296 }
03297 /*
03298  * Read the configuration data from the eeprom.
03299  * The data can be put in any specified memory buffer.
03300  *
03301  * Returns -1 on error.
03302  * Returns address of next memory location on success.
03303  */
03304 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
03305                                           u8 *mptr, int mdata_size)
03306 {
03307 #define MDEFAULT 15
03308 #define MSTATE 100
03309         int cptr;
03310         u8 *word;
03311         int code;
03312         int reference, length, major, minor;
03313         int osize;
03314         int it;
03315         u16 checksum, mchecksum;
03316         eeprom_read_op read;
03317 
03318         if (ath9k_hw_use_flash(ah))
03319                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
03320 
03321         word = zalloc(2048);
03322         if (!word)
03323                 return -1;
03324 
03325         memcpy(mptr, &ar9300_default, mdata_size);
03326 
03327         read = ar9300_read_eeprom;
03328         if (AR_SREV_9485(ah))
03329                 cptr = AR9300_BASE_ADDR_4K;
03330         else
03331                 cptr = AR9300_BASE_ADDR;
03332         DBG2("ath9k: "
03333                 "Trying EEPROM access at Address 0x%04x\n", cptr);
03334         if (ar9300_check_eeprom_header(ah, read, cptr))
03335                 goto found;
03336 
03337         cptr = AR9300_BASE_ADDR_512;
03338         DBG2("ath9k: "
03339                 "Trying EEPROM access at Address 0x%04x\n", cptr);
03340         if (ar9300_check_eeprom_header(ah, read, cptr))
03341                 goto found;
03342 
03343         read = ar9300_read_otp;
03344         cptr = AR9300_BASE_ADDR;
03345         DBG2("ath9k: "
03346                 "Trying OTP access at Address 0x%04x\n", cptr);
03347         if (ar9300_check_eeprom_header(ah, read, cptr))
03348                 goto found;
03349 
03350         cptr = AR9300_BASE_ADDR_512;
03351         DBG2("ath9k: "
03352                 "Trying OTP access at Address 0x%04x\n", cptr);
03353         if (ar9300_check_eeprom_header(ah, read, cptr))
03354                 goto found;
03355 
03356         goto fail;
03357 
03358 found:
03359         DBG2("ath9k: Found valid EEPROM data\n");
03360 
03361         for (it = 0; it < MSTATE; it++) {
03362                 if (!read(ah, cptr, word, COMP_HDR_LEN))
03363                         goto fail;
03364 
03365                 if (!ar9300_check_header(word))
03366                         break;
03367 
03368                 ar9300_comp_hdr_unpack(word, &code, &reference,
03369                                        &length, &major, &minor);
03370                 DBG2("ath9k: "
03371                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
03372                         cptr, code, reference, length, major, minor);
03373                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
03374                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
03375                         DBG2("ath9k: "
03376                                 "Skipping bad header\n");
03377                         cptr -= COMP_HDR_LEN;
03378                         continue;
03379                 }
03380 
03381                 osize = length;
03382                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
03383                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
03384                 mchecksum = word[COMP_HDR_LEN + osize] |
03385                     (word[COMP_HDR_LEN + osize + 1] << 8);
03386                 DBG2("ath9k: "
03387                         "checksum %x %x\n", checksum, mchecksum);
03388                 if (checksum == mchecksum) {
03389                         ar9300_compress_decision(ah, it, code, reference, mptr,
03390                                                  word, length, mdata_size);
03391                 } else {
03392                         DBG2("ath9k: "
03393                                 "skipping block with bad checksum\n");
03394                 }
03395                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
03396         }
03397 
03398         free(word);
03399         return cptr;
03400 
03401 fail:
03402         free(word);
03403         return -1;
03404 }
03405 
03406 /*
03407  * Restore the configuration structure by reading the eeprom.
03408  * This function destroys any existing in-memory structure
03409  * content.
03410  */
03411 static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
03412 {
03413         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
03414 
03415         if (ar9300_eeprom_restore_internal(ah, mptr,
03416                         sizeof(struct ar9300_eeprom)) < 0)
03417                 return 0;
03418 
03419         return 1;
03420 }
03421 
03422 /* XXX: review hardware docs */
03423 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
03424 {
03425         return ah->eeprom.ar9300_eep.eepromVersion;
03426 }
03427 
03428 /* XXX: could be read from the eepromVersion, not sure yet */
03429 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
03430 {
03431         return 0;
03432 }
03433 
03434 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
03435 {
03436         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03437 
03438         if (is2ghz)
03439                 return eep->modalHeader2G.xpaBiasLvl;
03440         else
03441                 return eep->modalHeader5G.xpaBiasLvl;
03442 }
03443 
03444 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
03445 {
03446         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
03447 
03448         if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
03449                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
03450         else {
03451                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
03452                 REG_RMW_FIELD(ah, AR_CH0_THERM,
03453                                 AR_CH0_THERM_XPABIASLVL_MSB,
03454                                 bias >> 2);
03455                 REG_RMW_FIELD(ah, AR_CH0_THERM,
03456                                 AR_CH0_THERM_XPASHORT2GND, 1);
03457         }
03458 }
03459 
03460 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
03461 {
03462         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03463         uint32_t val;
03464 
03465         if (is2ghz)
03466                 val = eep->modalHeader2G.antCtrlCommon;
03467         else
03468                 val = eep->modalHeader5G.antCtrlCommon;
03469         return (uint32_t)(val);
03470 }
03471 
03472 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
03473 {
03474         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03475         uint32_t val;
03476 
03477         if (is2ghz)
03478                 val = eep->modalHeader2G.antCtrlCommon2;
03479         else
03480                 val = eep->modalHeader5G.antCtrlCommon2;
03481         return (uint32_t)(val);
03482 }
03483 
03484 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
03485                                         int chain,
03486                                         int is2ghz)
03487 {
03488         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03489         uint16_t val = 0;
03490 
03491         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
03492                 if (is2ghz)
03493                         val = eep->modalHeader2G.antCtrlChain[chain];
03494                 else
03495                         val = eep->modalHeader5G.antCtrlChain[chain];
03496         }
03497 
03498         return (uint16_t)(val);
03499 }
03500 
03501 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
03502 {
03503         int chain;
03504         u32 regval;
03505         u32 ant_div_ctl1;
03506         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
03507                         AR_PHY_SWITCH_CHAIN_0,
03508                         AR_PHY_SWITCH_CHAIN_1,
03509                         AR_PHY_SWITCH_CHAIN_2,
03510         };
03511 
03512         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
03513 
03514         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
03515 
03516         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
03517         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
03518 
03519         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
03520                 if ((ah->rxchainmask & BIT(chain)) ||
03521                     (ah->txchainmask & BIT(chain))) {
03522                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
03523                                                              is2ghz);
03524                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
03525                                       AR_SWITCH_TABLE_ALL, value);
03526                 }
03527         }
03528 
03529         if (AR_SREV_9485(ah)) {
03530                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
03531                 /*
03532                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
03533                  * are the fields present
03534                  */
03535                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
03536                 regval &= (~AR_ANT_DIV_CTRL_ALL);
03537                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
03538                 /* enable_lnadiv */
03539                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
03540                 regval |= ((value >> 6) & 0x1) <<
03541                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
03542                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
03543 
03544                 /*enable fast_div */
03545                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
03546                 regval &= (~AR_FAST_DIV_ENABLE);
03547                 regval |= ((value >> 7) & 0x1) <<
03548                                 AR_FAST_DIV_ENABLE_S;
03549                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
03550                 ant_div_ctl1 =
03551                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
03552                 /* check whether antenna diversity is enabled */
03553                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
03554                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
03555                         /*
03556                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
03557                          * main_tb, alt_tb
03558                          */
03559                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
03560                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
03561                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
03562                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
03563                         /* by default use LNA1 for the main antenna */
03564                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
03565                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
03566                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
03567                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
03568                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
03569                 }
03570 
03571 
03572         }
03573 
03574 }
03575 
03576 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
03577 {
03578         int drive_strength;
03579         unsigned long reg;
03580 
03581         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
03582 
03583         if (!drive_strength)
03584                 return;
03585 
03586         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
03587         reg &= ~0x00ffffc0;
03588         reg |= 0x5 << 21;
03589         reg |= 0x5 << 18;
03590         reg |= 0x5 << 15;
03591         reg |= 0x5 << 12;
03592         reg |= 0x5 << 9;
03593         reg |= 0x5 << 6;
03594         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
03595 
03596         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
03597         reg &= ~0xffffffe0;
03598         reg |= 0x5 << 29;
03599         reg |= 0x5 << 26;
03600         reg |= 0x5 << 23;
03601         reg |= 0x5 << 20;
03602         reg |= 0x5 << 17;
03603         reg |= 0x5 << 14;
03604         reg |= 0x5 << 11;
03605         reg |= 0x5 << 8;
03606         reg |= 0x5 << 5;
03607         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
03608 
03609         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
03610         reg &= ~0xff800000;
03611         reg |= 0x5 << 29;
03612         reg |= 0x5 << 26;
03613         reg |= 0x5 << 23;
03614         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
03615 }
03616 
03617 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
03618                                      struct ath9k_channel *chan)
03619 {
03620         int f[3], t[3];
03621         u16 value;
03622         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03623 
03624         if (chain >= 0 && chain < 3) {
03625                 if (IS_CHAN_2GHZ(chan))
03626                         return eep->modalHeader2G.xatten1DB[chain];
03627                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
03628                         t[0] = eep->base_ext2.xatten1DBLow[chain];
03629                         f[0] = 5180;
03630                         t[1] = eep->modalHeader5G.xatten1DB[chain];
03631                         f[1] = 5500;
03632                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
03633                         f[2] = 5785;
03634                         value = ar9003_hw_power_interpolate((s32) chan->channel,
03635                                                             f, t, 3);
03636                         return value;
03637                 } else
03638                         return eep->modalHeader5G.xatten1DB[chain];
03639         }
03640 
03641         return 0;
03642 }
03643 
03644 
03645 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
03646                                             struct ath9k_channel *chan)
03647 {
03648         int f[3], t[3];
03649         u16 value;
03650         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03651 
03652         if (chain >= 0 && chain < 3) {
03653                 if (IS_CHAN_2GHZ(chan))
03654                         return eep->modalHeader2G.xatten1Margin[chain];
03655                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
03656                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
03657                         f[0] = 5180;
03658                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
03659                         f[1] = 5500;
03660                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
03661                         f[2] = 5785;
03662                         value = ar9003_hw_power_interpolate((s32) chan->channel,
03663                                                             f, t, 3);
03664                         return value;
03665                 } else
03666                         return eep->modalHeader5G.xatten1Margin[chain];
03667         }
03668 
03669         return 0;
03670 }
03671 
03672 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
03673 {
03674         int i;
03675         u16 value;
03676         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
03677                                           AR_PHY_EXT_ATTEN_CTL_1,
03678                                           AR_PHY_EXT_ATTEN_CTL_2,
03679                                          };
03680 
03681         /* Test value. if 0 then attenuation is unused. Don't load anything. */
03682         for (i = 0; i < 3; i++) {
03683                 if (ah->txchainmask & BIT(i)) {
03684                         value = ar9003_hw_atten_chain_get(ah, i, chan);
03685                         REG_RMW_FIELD(ah, ext_atten_reg[i],
03686                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
03687 
03688                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
03689                         REG_RMW_FIELD(ah, ext_atten_reg[i],
03690                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
03691                                       value);
03692                 }
03693         }
03694 }
03695 
03696 static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
03697 {
03698         int timeout = 100;
03699 
03700         while ((unsigned int)pmu_set != REG_READ(ah, pmu_reg)) {
03701                 if (timeout-- == 0)
03702                         return 0;
03703                 REG_WRITE(ah, pmu_reg, pmu_set);
03704                 udelay(10);
03705         }
03706 
03707         return 1;
03708 }
03709 
03710 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
03711 {
03712         int internal_regulator =
03713                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
03714 
03715         if (internal_regulator) {
03716                 if (AR_SREV_9485(ah)) {
03717                         int reg_pmu_set;
03718 
03719                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
03720                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
03721                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
03722                                 return;
03723 
03724                         reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
03725                                       (2 << 14) | (6 << 17) | (1 << 20) |
03726                                       (3 << 24) | (1 << 28);
03727 
03728                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
03729                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
03730                                 return;
03731 
03732                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
03733                                         | (4 << 26);
03734                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
03735                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
03736                                 return;
03737 
03738                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
03739                                         | (1 << 21);
03740                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
03741                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
03742                                 return;
03743                 } else {
03744                         /* Internal regulator is ON. Write swreg register. */
03745                         int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
03746                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
03747                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
03748                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
03749                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
03750                         /* Set REG_CONTROL1.SWREG_PROGRAM */
03751                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
03752                                   REG_READ(ah,
03753                                            AR_RTC_REG_CONTROL1) |
03754                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
03755                 }
03756         } else {
03757                 if (AR_SREV_9485(ah)) {
03758                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
03759                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
03760                                               AR_PHY_PMU2_PGM))
03761                                 udelay(10);
03762 
03763                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
03764                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
03765                                                AR_PHY_PMU1_PWD))
03766                                 udelay(10);
03767                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
03768                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
03769                                               AR_PHY_PMU2_PGM))
03770                                 udelay(10);
03771                 } else
03772                         REG_WRITE(ah, AR_RTC_SLEEP_CLK,
03773                                   (REG_READ(ah,
03774                                    AR_RTC_SLEEP_CLK) |
03775                                    AR_RTC_FORCE_SWREG_PRD));
03776         }
03777 
03778 }
03779 
03780 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
03781 {
03782         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03783         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
03784 
03785         if (eep->baseEepHeader.featureEnable & 0x40) {
03786                 tuning_caps_param &= 0x7f;
03787                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
03788                               tuning_caps_param);
03789                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
03790                               tuning_caps_param);
03791         }
03792 }
03793 
03794 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
03795                                              struct ath9k_channel *chan)
03796 {
03797         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
03798         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
03799         ar9003_hw_drive_strength_apply(ah);
03800         ar9003_hw_atten_apply(ah, chan);
03801         if (!AR_SREV_9340(ah))
03802                 ar9003_hw_internal_regulator_apply(ah);
03803         if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
03804                 ar9003_hw_apply_tuning_caps(ah);
03805 }
03806 
03807 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused,
03808                                       struct ath9k_channel *chan __unused)
03809 {
03810 }
03811 
03812 /*
03813  * Returns the interpolated y value corresponding to the specified x value
03814  * from the np ordered pairs of data (px,py).
03815  * The pairs do not have to be in any order.
03816  * If the specified x value is less than any of the px,
03817  * the returned y value is equal to the py for the lowest px.
03818  * If the specified x value is greater than any of the px,
03819  * the returned y value is equal to the py for the highest px.
03820  */
03821 static int ar9003_hw_power_interpolate(int32_t x,
03822                                        int32_t *px, int32_t *py, uint16_t np)
03823 {
03824         int ip = 0;
03825         int lx = 0, ly = 0, lhave = 0;
03826         int hx = 0, hy = 0, hhave = 0;
03827         int dx = 0;
03828         int y = 0;
03829 
03830         lhave = 0;
03831         hhave = 0;
03832 
03833         /* identify best lower and higher x calibration measurement */
03834         for (ip = 0; ip < np; ip++) {
03835                 dx = x - px[ip];
03836 
03837                 /* this measurement is higher than our desired x */
03838                 if (dx <= 0) {
03839                         if (!hhave || dx > (x - hx)) {
03840                                 /* new best higher x measurement */
03841                                 hx = px[ip];
03842                                 hy = py[ip];
03843                                 hhave = 1;
03844                         }
03845                 }
03846                 /* this measurement is lower than our desired x */
03847                 if (dx >= 0) {
03848                         if (!lhave || dx < (x - lx)) {
03849                                 /* new best lower x measurement */
03850                                 lx = px[ip];
03851                                 ly = py[ip];
03852                                 lhave = 1;
03853                         }
03854                 }
03855         }
03856 
03857         /* the low x is good */
03858         if (lhave) {
03859                 /* so is the high x */
03860                 if (hhave) {
03861                         /* they're the same, so just pick one */
03862                         if (hx == lx)
03863                                 y = ly;
03864                         else    /* interpolate  */
03865                                 y = interpolate(x, lx, hx, ly, hy);
03866                 } else          /* only low is good, use it */
03867                         y = ly;
03868         } else if (hhave)       /* only high is good, use it */
03869                 y = hy;
03870         else /* nothing is good,this should never happen unless np=0, ???? */
03871                 y = -(1 << 30);
03872         return y;
03873 }
03874 
03875 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
03876                                        u16 rateIndex, u16 freq, int is2GHz)
03877 {
03878         u16 numPiers, i;
03879         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
03880         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
03881         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03882         struct cal_tgt_pow_legacy *pEepromTargetPwr;
03883         u8 *pFreqBin;
03884 
03885         if (is2GHz) {
03886                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
03887                 pEepromTargetPwr = eep->calTargetPower2G;
03888                 pFreqBin = eep->calTarget_freqbin_2G;
03889         } else {
03890                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
03891                 pEepromTargetPwr = eep->calTargetPower5G;
03892                 pFreqBin = eep->calTarget_freqbin_5G;
03893         }
03894 
03895         /*
03896          * create array of channels and targetpower from
03897          * targetpower piers stored on eeprom
03898          */
03899         for (i = 0; i < numPiers; i++) {
03900                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
03901                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
03902         }
03903 
03904         /* interpolate to get target power for given frequency */
03905         return (u8) ar9003_hw_power_interpolate((s32) freq,
03906                                                  freqArray,
03907                                                  targetPowerArray, numPiers);
03908 }
03909 
03910 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
03911                                             u16 rateIndex,
03912                                             u16 freq, int is2GHz)
03913 {
03914         u16 numPiers, i;
03915         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
03916         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
03917         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03918         struct cal_tgt_pow_ht *pEepromTargetPwr;
03919         u8 *pFreqBin;
03920 
03921         if (is2GHz) {
03922                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
03923                 pEepromTargetPwr = eep->calTargetPower2GHT20;
03924                 pFreqBin = eep->calTarget_freqbin_2GHT20;
03925         } else {
03926                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
03927                 pEepromTargetPwr = eep->calTargetPower5GHT20;
03928                 pFreqBin = eep->calTarget_freqbin_5GHT20;
03929         }
03930 
03931         /*
03932          * create array of channels and targetpower
03933          * from targetpower piers stored on eeprom
03934          */
03935         for (i = 0; i < numPiers; i++) {
03936                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
03937                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
03938         }
03939 
03940         /* interpolate to get target power for given frequency */
03941         return (u8) ar9003_hw_power_interpolate((s32) freq,
03942                                                  freqArray,
03943                                                  targetPowerArray, numPiers);
03944 }
03945 
03946 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
03947                                             u16 rateIndex,
03948                                             u16 freq, int is2GHz)
03949 {
03950         u16 numPiers, i;
03951         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
03952         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
03953         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03954         struct cal_tgt_pow_ht *pEepromTargetPwr;
03955         u8 *pFreqBin;
03956 
03957         if (is2GHz) {
03958                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
03959                 pEepromTargetPwr = eep->calTargetPower2GHT40;
03960                 pFreqBin = eep->calTarget_freqbin_2GHT40;
03961         } else {
03962                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
03963                 pEepromTargetPwr = eep->calTargetPower5GHT40;
03964                 pFreqBin = eep->calTarget_freqbin_5GHT40;
03965         }
03966 
03967         /*
03968          * create array of channels and targetpower from
03969          * targetpower piers stored on eeprom
03970          */
03971         for (i = 0; i < numPiers; i++) {
03972                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
03973                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
03974         }
03975 
03976         /* interpolate to get target power for given frequency */
03977         return (u8) ar9003_hw_power_interpolate((s32) freq,
03978                                                  freqArray,
03979                                                  targetPowerArray, numPiers);
03980 }
03981 
03982 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
03983                                            u16 rateIndex, u16 freq)
03984 {
03985         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
03986         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
03987         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
03988         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
03989         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
03990         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
03991 
03992         /*
03993          * create array of channels and targetpower from
03994          * targetpower piers stored on eeprom
03995          */
03996         for (i = 0; i < numPiers; i++) {
03997                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
03998                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
03999         }
04000 
04001         /* interpolate to get target power for given frequency */
04002         return (u8) ar9003_hw_power_interpolate((s32) freq,
04003                                                  freqArray,
04004                                                  targetPowerArray, numPiers);
04005 }
04006 
04007 /* Set tx power registers to array of values passed in */
04008 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
04009 {
04010 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
04011         /* make sure forced gain is not set */
04012         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
04013 
04014         /* Write the OFDM power per rate set */
04015 
04016         /* 6 (LSB), 9, 12, 18 (MSB) */
04017         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
04018                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
04019                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
04020                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
04021                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
04022 
04023         /* 24 (LSB), 36, 48, 54 (MSB) */
04024         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
04025                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
04026                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
04027                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
04028                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
04029 
04030         /* Write the CCK power per rate set */
04031 
04032         /* 1L (LSB), reserved, 2L, 2S (MSB) */
04033         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
04034                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
04035                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
04036                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
04037                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
04038 
04039         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
04040         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
04041                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
04042                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
04043                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
04044                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
04045             );
04046 
04047         /* Write the power for duplicated frames - HT40 */
04048 
04049         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
04050         REG_WRITE(ah, 0xa3e0,
04051                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
04052                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
04053                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
04054                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
04055             );
04056 
04057         /* Write the HT20 power per rate set */
04058 
04059         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
04060         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
04061                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
04062                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
04063                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
04064                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
04065             );
04066 
04067         /* 6 (LSB), 7, 12, 13 (MSB) */
04068         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
04069                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
04070                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
04071                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
04072                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
04073             );
04074 
04075         /* 14 (LSB), 15, 20, 21 */
04076         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
04077                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
04078                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
04079                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
04080                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
04081             );
04082 
04083         /* Mixed HT20 and HT40 rates */
04084 
04085         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
04086         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
04087                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
04088                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
04089                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
04090                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
04091             );
04092 
04093         /*
04094          * Write the HT40 power per rate set
04095          * correct PAR difference between HT40 and HT20/LEGACY
04096          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
04097          */
04098         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
04099                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
04100                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
04101                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
04102                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
04103             );
04104 
04105         /* 6 (LSB), 7, 12, 13 (MSB) */
04106         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
04107                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
04108                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
04109                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
04110                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
04111             );
04112 
04113         /* 14 (LSB), 15, 20, 21 */
04114         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
04115                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
04116                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
04117                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
04118                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
04119             );
04120 
04121         return 0;
04122 #undef POW_SM
04123 }
04124 
04125 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
04126                                               u8 *targetPowerValT2)
04127 {
04128         /* XXX: hard code for now, need to get from eeprom struct */
04129         u8 ht40PowerIncForPdadc = 0;
04130         int is2GHz = 0;
04131         unsigned int i = 0;
04132 
04133         if (freq < 4000)
04134                 is2GHz = 1;
04135 
04136         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
04137             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
04138                                          is2GHz);
04139         targetPowerValT2[ALL_TARGET_LEGACY_36] =
04140             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
04141                                          is2GHz);
04142         targetPowerValT2[ALL_TARGET_LEGACY_48] =
04143             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
04144                                          is2GHz);
04145         targetPowerValT2[ALL_TARGET_LEGACY_54] =
04146             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
04147                                          is2GHz);
04148         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
04149             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
04150                                              freq);
04151         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
04152             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
04153         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
04154             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
04155         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
04156             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
04157         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
04158             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
04159                                               is2GHz);
04160         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
04161             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
04162                                               freq, is2GHz);
04163         targetPowerValT2[ALL_TARGET_HT20_4] =
04164             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
04165                                               is2GHz);
04166         targetPowerValT2[ALL_TARGET_HT20_5] =
04167             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
04168                                               is2GHz);
04169         targetPowerValT2[ALL_TARGET_HT20_6] =
04170             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
04171                                               is2GHz);
04172         targetPowerValT2[ALL_TARGET_HT20_7] =
04173             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
04174                                               is2GHz);
04175         targetPowerValT2[ALL_TARGET_HT20_12] =
04176             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
04177                                               is2GHz);
04178         targetPowerValT2[ALL_TARGET_HT20_13] =
04179             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
04180                                               is2GHz);
04181         targetPowerValT2[ALL_TARGET_HT20_14] =
04182             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
04183                                               is2GHz);
04184         targetPowerValT2[ALL_TARGET_HT20_15] =
04185             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
04186                                               is2GHz);
04187         targetPowerValT2[ALL_TARGET_HT20_20] =
04188             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
04189                                               is2GHz);
04190         targetPowerValT2[ALL_TARGET_HT20_21] =
04191             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
04192                                               is2GHz);
04193         targetPowerValT2[ALL_TARGET_HT20_22] =
04194             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
04195                                               is2GHz);
04196         targetPowerValT2[ALL_TARGET_HT20_23] =
04197             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
04198                                               is2GHz);
04199         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
04200             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
04201                                               is2GHz) + ht40PowerIncForPdadc;
04202         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
04203             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
04204                                               freq,
04205                                               is2GHz) + ht40PowerIncForPdadc;
04206         targetPowerValT2[ALL_TARGET_HT40_4] =
04207             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
04208                                               is2GHz) + ht40PowerIncForPdadc;
04209         targetPowerValT2[ALL_TARGET_HT40_5] =
04210             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
04211                                               is2GHz) + ht40PowerIncForPdadc;
04212         targetPowerValT2[ALL_TARGET_HT40_6] =
04213             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
04214                                               is2GHz) + ht40PowerIncForPdadc;
04215         targetPowerValT2[ALL_TARGET_HT40_7] =
04216             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
04217                                               is2GHz) + ht40PowerIncForPdadc;
04218         targetPowerValT2[ALL_TARGET_HT40_12] =
04219             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
04220                                               is2GHz) + ht40PowerIncForPdadc;
04221         targetPowerValT2[ALL_TARGET_HT40_13] =
04222             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
04223                                               is2GHz) + ht40PowerIncForPdadc;
04224         targetPowerValT2[ALL_TARGET_HT40_14] =
04225             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
04226                                               is2GHz) + ht40PowerIncForPdadc;
04227         targetPowerValT2[ALL_TARGET_HT40_15] =
04228             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
04229                                               is2GHz) + ht40PowerIncForPdadc;
04230         targetPowerValT2[ALL_TARGET_HT40_20] =
04231             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
04232                                               is2GHz) + ht40PowerIncForPdadc;
04233         targetPowerValT2[ALL_TARGET_HT40_21] =
04234             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
04235                                               is2GHz) + ht40PowerIncForPdadc;
04236         targetPowerValT2[ALL_TARGET_HT40_22] =
04237             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
04238                                               is2GHz) + ht40PowerIncForPdadc;
04239         targetPowerValT2[ALL_TARGET_HT40_23] =
04240             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
04241                                               is2GHz) + ht40PowerIncForPdadc;
04242 
04243         for (i = 0; i < ar9300RateSize; i++) {
04244                 DBG2("ath9k: "
04245                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
04246         }
04247 }
04248 
04249 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
04250                                   int mode,
04251                                   int ipier,
04252                                   int ichain,
04253                                   int *pfrequency,
04254                                   int *pcorrection,
04255                                   int *ptemperature, int *pvoltage)
04256 {
04257         u8 *pCalPier;
04258         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
04259         int is2GHz;
04260         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04261 
04262         if (ichain >= AR9300_MAX_CHAINS) {
04263                 DBG("ath9k: "
04264                         "Invalid chain index, must be less than %d\n",
04265                         AR9300_MAX_CHAINS);
04266                 return -1;
04267         }
04268 
04269         if (mode) {             /* 5GHz */
04270                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
04271                         DBG("ath9k: "
04272                                 "Invalid 5GHz cal pier index, must be less than %d\n",
04273                                 AR9300_NUM_5G_CAL_PIERS);
04274                         return -1;
04275                 }
04276                 pCalPier = &(eep->calFreqPier5G[ipier]);
04277                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
04278                 is2GHz = 0;
04279         } else {
04280                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
04281                         DBG("ath9k: "
04282                                 "Invalid 2GHz cal pier index, must be less than %d\n",
04283                                 AR9300_NUM_2G_CAL_PIERS);
04284                         return -1;
04285                 }
04286 
04287                 pCalPier = &(eep->calFreqPier2G[ipier]);
04288                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
04289                 is2GHz = 1;
04290         }
04291 
04292         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
04293         *pcorrection = pCalPierStruct->refPower;
04294         *ptemperature = pCalPierStruct->tempMeas;
04295         *pvoltage = pCalPierStruct->voltMeas;
04296 
04297         return 0;
04298 }
04299 
04300 static int ar9003_hw_power_control_override(struct ath_hw *ah,
04301                                             int frequency,
04302                                             int *correction,
04303                                             int *voltage __unused, int *temperature)
04304 {
04305         int tempSlope = 0;
04306         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04307         int f[3], t[3];
04308 
04309         REG_RMW(ah, AR_PHY_TPC_11_B0,
04310                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
04311                 AR_PHY_TPC_OLPC_GAIN_DELTA);
04312         if (ah->caps.tx_chainmask & BIT(1))
04313                 REG_RMW(ah, AR_PHY_TPC_11_B1,
04314                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
04315                         AR_PHY_TPC_OLPC_GAIN_DELTA);
04316         if (ah->caps.tx_chainmask & BIT(2))
04317                 REG_RMW(ah, AR_PHY_TPC_11_B2,
04318                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
04319                         AR_PHY_TPC_OLPC_GAIN_DELTA);
04320 
04321         /* enable open loop power control on chip */
04322         REG_RMW(ah, AR_PHY_TPC_6_B0,
04323                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
04324                 AR_PHY_TPC_6_ERROR_EST_MODE);
04325         if (ah->caps.tx_chainmask & BIT(1))
04326                 REG_RMW(ah, AR_PHY_TPC_6_B1,
04327                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
04328                         AR_PHY_TPC_6_ERROR_EST_MODE);
04329         if (ah->caps.tx_chainmask & BIT(2))
04330                 REG_RMW(ah, AR_PHY_TPC_6_B2,
04331                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
04332                         AR_PHY_TPC_6_ERROR_EST_MODE);
04333 
04334         /*
04335          * enable temperature compensation
04336          * Need to use register names
04337          */
04338         if (frequency < 4000)
04339                 tempSlope = eep->modalHeader2G.tempSlope;
04340         else if (eep->base_ext2.tempSlopeLow != 0) {
04341                 t[0] = eep->base_ext2.tempSlopeLow;
04342                 f[0] = 5180;
04343                 t[1] = eep->modalHeader5G.tempSlope;
04344                 f[1] = 5500;
04345                 t[2] = eep->base_ext2.tempSlopeHigh;
04346                 f[2] = 5785;
04347                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
04348                                                         f, t, 3);
04349         } else
04350                 tempSlope = eep->modalHeader5G.tempSlope;
04351 
04352         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
04353         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
04354                       temperature[0]);
04355 
04356         return 0;
04357 }
04358 
04359 /* Apply the recorded correction values. */
04360 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
04361 {
04362         int ichain, ipier, npier;
04363         int mode;
04364         int lfrequency[AR9300_MAX_CHAINS],
04365             lcorrection[AR9300_MAX_CHAINS],
04366             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
04367         int hfrequency[AR9300_MAX_CHAINS],
04368             hcorrection[AR9300_MAX_CHAINS],
04369             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
04370         int fdiff;
04371         int correction[AR9300_MAX_CHAINS],
04372             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
04373         int pfrequency, pcorrection, ptemperature, pvoltage;
04374 
04375         mode = (frequency >= 4000);
04376         if (mode)
04377                 npier = AR9300_NUM_5G_CAL_PIERS;
04378         else
04379                 npier = AR9300_NUM_2G_CAL_PIERS;
04380 
04381         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
04382                 lfrequency[ichain] = 0;
04383                 hfrequency[ichain] = 100000;
04384         }
04385         /* identify best lower and higher frequency calibration measurement */
04386         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
04387                 for (ipier = 0; ipier < npier; ipier++) {
04388                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
04389                                                     &pfrequency, &pcorrection,
04390                                                     &ptemperature, &pvoltage)) {
04391                                 fdiff = frequency - pfrequency;
04392 
04393                                 /*
04394                                  * this measurement is higher than
04395                                  * our desired frequency
04396                                  */
04397                                 if (fdiff <= 0) {
04398                                         if (hfrequency[ichain] <= 0 ||
04399                                             hfrequency[ichain] >= 100000 ||
04400                                             fdiff >
04401                                             (frequency - hfrequency[ichain])) {
04402                                                 /*
04403                                                  * new best higher
04404                                                  * frequency measurement
04405                                                  */
04406                                                 hfrequency[ichain] = pfrequency;
04407                                                 hcorrection[ichain] =
04408                                                     pcorrection;
04409                                                 htemperature[ichain] =
04410                                                     ptemperature;
04411                                                 hvoltage[ichain] = pvoltage;
04412                                         }
04413                                 }
04414                                 if (fdiff >= 0) {
04415                                         if (lfrequency[ichain] <= 0
04416                                             || fdiff <
04417                                             (frequency - lfrequency[ichain])) {
04418                                                 /*
04419                                                  * new best lower
04420                                                  * frequency measurement
04421                                                  */
04422                                                 lfrequency[ichain] = pfrequency;
04423                                                 lcorrection[ichain] =
04424                                                     pcorrection;
04425                                                 ltemperature[ichain] =
04426                                                     ptemperature;
04427                                                 lvoltage[ichain] = pvoltage;
04428                                         }
04429                                 }
04430                         }
04431                 }
04432         }
04433 
04434         /* interpolate  */
04435         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
04436                 DBG2("ath9k: "
04437                         "ch=%d f=%d low=%d %d h=%d %d\n",
04438                         ichain, frequency, lfrequency[ichain],
04439                         lcorrection[ichain], hfrequency[ichain],
04440                         hcorrection[ichain]);
04441                 /* they're the same, so just pick one */
04442                 if (hfrequency[ichain] == lfrequency[ichain]) {
04443                         correction[ichain] = lcorrection[ichain];
04444                         voltage[ichain] = lvoltage[ichain];
04445                         temperature[ichain] = ltemperature[ichain];
04446                 }
04447                 /* the low frequency is good */
04448                 else if (frequency - lfrequency[ichain] < 1000) {
04449                         /* so is the high frequency, interpolate */
04450                         if (hfrequency[ichain] - frequency < 1000) {
04451 
04452                                 correction[ichain] = interpolate(frequency,
04453                                                 lfrequency[ichain],
04454                                                 hfrequency[ichain],
04455                                                 lcorrection[ichain],
04456                                                 hcorrection[ichain]);
04457 
04458                                 temperature[ichain] = interpolate(frequency,
04459                                                 lfrequency[ichain],
04460                                                 hfrequency[ichain],
04461                                                 ltemperature[ichain],
04462                                                 htemperature[ichain]);
04463 
04464                                 voltage[ichain] = interpolate(frequency,
04465                                                 lfrequency[ichain],
04466                                                 hfrequency[ichain],
04467                                                 lvoltage[ichain],
04468                                                 hvoltage[ichain]);
04469                         }
04470                         /* only low is good, use it */
04471                         else {
04472                                 correction[ichain] = lcorrection[ichain];
04473                                 temperature[ichain] = ltemperature[ichain];
04474                                 voltage[ichain] = lvoltage[ichain];
04475                         }
04476                 }
04477                 /* only high is good, use it */
04478                 else if (hfrequency[ichain] - frequency < 1000) {
04479                         correction[ichain] = hcorrection[ichain];
04480                         temperature[ichain] = htemperature[ichain];
04481                         voltage[ichain] = hvoltage[ichain];
04482                 } else {        /* nothing is good, presume 0???? */
04483                         correction[ichain] = 0;
04484                         temperature[ichain] = 0;
04485                         voltage[ichain] = 0;
04486                 }
04487         }
04488 
04489         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
04490                                          temperature);
04491 
04492         DBG2("ath9k: "
04493                 "for frequency=%d, calibration correction = %d %d %d\n",
04494                 frequency, correction[0], correction[1], correction[2]);
04495 
04496         return 0;
04497 }
04498 
04499 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
04500                                            int idx,
04501                                            int edge,
04502                                            int is2GHz)
04503 {
04504         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
04505         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
04506 
04507         if (is2GHz)
04508                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
04509         else
04510                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
04511 }
04512 
04513 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
04514                                              int idx,
04515                                              unsigned int edge,
04516                                              u16 freq,
04517                                              int is2GHz)
04518 {
04519         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
04520         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
04521 
04522         u8 *ctl_freqbin = is2GHz ?
04523                 &eep->ctl_freqbin_2G[idx][0] :
04524                 &eep->ctl_freqbin_5G[idx][0];
04525 
04526         if (is2GHz) {
04527                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
04528                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
04529                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
04530         } else {
04531                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
04532                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
04533                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
04534         }
04535 
04536         return MAX_RATE_POWER;
04537 }
04538 
04539 /*
04540  * Find the maximum conformance test limit for the given channel and CTL info
04541  */
04542 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
04543                                         u16 freq, int idx, int is2GHz)
04544 {
04545         u16 twiceMaxEdgePower = MAX_RATE_POWER;
04546         u8 *ctl_freqbin = is2GHz ?
04547                 &eep->ctl_freqbin_2G[idx][0] :
04548                 &eep->ctl_freqbin_5G[idx][0];
04549         u16 num_edges = is2GHz ?
04550                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
04551         unsigned int edge;
04552 
04553         /* Get the edge power */
04554         for (edge = 0;
04555              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
04556              edge++) {
04557                 /*
04558                  * If there's an exact channel match or an inband flag set
04559                  * on the lower channel use the given rdEdgePower
04560                  */
04561                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
04562                         twiceMaxEdgePower =
04563                                 ar9003_hw_get_direct_edge_power(eep, idx,
04564                                                                 edge, is2GHz);
04565                         break;
04566                 } else if ((edge > 0) &&
04567                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
04568                                                       is2GHz))) {
04569                         twiceMaxEdgePower =
04570                                 ar9003_hw_get_indirect_edge_power(eep, idx,
04571                                                                   edge, freq,
04572                                                                   is2GHz);
04573                         /*
04574                          * Leave loop - no more affecting edges possible in
04575                          * this monotonic increasing list
04576                          */
04577                         break;
04578                 }
04579         }
04580         return twiceMaxEdgePower;
04581 }
04582 
04583 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
04584                                                struct ath9k_channel *chan,
04585                                                u8 *pPwrArray, u16 cfgCtl,
04586                                                u8 twiceAntennaReduction,
04587                                                u8 twiceMaxRegulatoryPower,
04588                                                u16 powerLimit)
04589 {
04590         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
04591         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
04592         u16 twiceMaxEdgePower = MAX_RATE_POWER;
04593         static const u16 tpScaleReductionTable[5] = {
04594                 0, 3, 6, 9, MAX_RATE_POWER
04595         };
04596         int i;
04597         int16_t  twiceLargestAntenna;
04598         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
04599         static const u16 ctlModesFor11a[] = {
04600                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
04601         };
04602         static const u16 ctlModesFor11g[] = {
04603                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
04604                 CTL_11G_EXT, CTL_2GHT40
04605         };
04606         u16 numCtlModes;
04607         const u16 *pCtlMode;
04608         u16 ctlMode, freq;
04609         struct chan_centers centers;
04610         u8 *ctlIndex;
04611         u8 ctlNum;
04612         u16 twiceMinEdgePower;
04613         int is2ghz = IS_CHAN_2GHZ(chan);
04614 
04615         ath9k_hw_get_channel_centers(ah, chan, &centers);
04616 
04617         /* Compute TxPower reduction due to Antenna Gain */
04618         if (is2ghz)
04619                 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
04620         else
04621                 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
04622 
04623         twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
04624                                 twiceLargestAntenna, 0);
04625 
04626         /*
04627          * scaledPower is the minimum of the user input power level
04628          * and the regulatory allowed power level
04629          */
04630         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
04631 
04632         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
04633                 maxRegAllowedPower -=
04634                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
04635         }
04636 
04637         scaledPower = min(powerLimit, maxRegAllowedPower);
04638 
04639         /*
04640          * Reduce scaled Power by number of chains active to get
04641          * to per chain tx power level
04642          */
04643         switch (ar5416_get_ntxchains(ah->txchainmask)) {
04644         case 1:
04645                 break;
04646         case 2:
04647                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
04648                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
04649                 else
04650                         scaledPower = 0;
04651                 break;
04652         case 3:
04653                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
04654                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
04655                 else
04656                         scaledPower = 0;
04657                 break;
04658         }
04659 
04660         scaledPower = max((u16)0, scaledPower);
04661 
04662         /*
04663          * Get target powers from EEPROM - our baseline for TX Power
04664          */
04665         if (is2ghz) {
04666                 /* Setup for CTL modes */
04667                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
04668                 numCtlModes =
04669                         ARRAY_SIZE(ctlModesFor11g) -
04670                                    SUB_NUM_CTL_MODES_AT_2G_40;
04671                 pCtlMode = ctlModesFor11g;
04672                 if (IS_CHAN_HT40(chan))
04673                         /* All 2G CTL's */
04674                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
04675         } else {
04676                 /* Setup for CTL modes */
04677                 /* CTL_11A, CTL_5GHT20 */
04678                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
04679                                          SUB_NUM_CTL_MODES_AT_5G_40;
04680                 pCtlMode = ctlModesFor11a;
04681                 if (IS_CHAN_HT40(chan))
04682                         /* All 5G CTL's */
04683                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
04684         }
04685 
04686         /*
04687          * For MIMO, need to apply regulatory caps individually across
04688          * dynamically running modes: CCK, OFDM, HT20, HT40
04689          *
04690          * The outer loop walks through each possible applicable runtime mode.
04691          * The inner loop walks through each ctlIndex entry in EEPROM.
04692          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
04693          */
04694         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
04695                 int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
04696                         (pCtlMode[ctlMode] == CTL_2GHT40);
04697                 if (isHt40CtlMode)
04698                         freq = centers.synth_center;
04699                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
04700                         freq = centers.ext_center;
04701                 else
04702                         freq = centers.ctl_center;
04703 
04704                 DBG2("ath9k: "
04705                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
04706                         ctlMode, numCtlModes, isHt40CtlMode,
04707                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
04708 
04709                 /* walk through each CTL index stored in EEPROM */
04710                 if (is2ghz) {
04711                         ctlIndex = pEepData->ctlIndex_2G;
04712                         ctlNum = AR9300_NUM_CTLS_2G;
04713                 } else {
04714                         ctlIndex = pEepData->ctlIndex_5G;
04715                         ctlNum = AR9300_NUM_CTLS_5G;
04716                 }
04717 
04718                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
04719                         DBG2("ath9k: "
04720                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
04721                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
04722                                 chan->channel);
04723 
04724                                 /*
04725                                  * compare test group from regulatory
04726                                  * channel list with test mode from pCtlMode
04727                                  * list
04728                                  */
04729                                 if ((((cfgCtl & ~CTL_MODE_M) |
04730                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
04731                                         ctlIndex[i]) ||
04732                                     (((cfgCtl & ~CTL_MODE_M) |
04733                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
04734                                      ((ctlIndex[i] & CTL_MODE_M) |
04735                                        SD_NO_CTL))) {
04736                                         twiceMinEdgePower =
04737                                           ar9003_hw_get_max_edge_power(pEepData,
04738                                                                        freq, i,
04739                                                                        is2ghz);
04740 
04741                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
04742                                                 /*
04743                                                  * Find the minimum of all CTL
04744                                                  * edge powers that apply to
04745                                                  * this channel
04746                                                  */
04747                                                 twiceMaxEdgePower =
04748                                                         min(twiceMaxEdgePower,
04749                                                             twiceMinEdgePower);
04750                                                 else {
04751                                                         /* specific */
04752                                                         twiceMaxEdgePower =
04753                                                           twiceMinEdgePower;
04754                                                         break;
04755                                                 }
04756                                 }
04757                         }
04758 
04759                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
04760 
04761                         DBG2("ath9k: "
04762                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
04763                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
04764                                 scaledPower, minCtlPower);
04765 
04766                         /* Apply ctl mode to correct target power set */
04767                         switch (pCtlMode[ctlMode]) {
04768                         case CTL_11B:
04769                                 for (i = ALL_TARGET_LEGACY_1L_5L;
04770                                      i <= ALL_TARGET_LEGACY_11S; i++)
04771                                         pPwrArray[i] =
04772                                           (u8)min((u16)pPwrArray[i],
04773                                                   minCtlPower);
04774                                 break;
04775                         case CTL_11A:
04776                         case CTL_11G:
04777                                 for (i = ALL_TARGET_LEGACY_6_24;
04778                                      i <= ALL_TARGET_LEGACY_54; i++)
04779                                         pPwrArray[i] =
04780                                           (u8)min((u16)pPwrArray[i],
04781                                                   minCtlPower);
04782                                 break;
04783                         case CTL_5GHT20:
04784                         case CTL_2GHT20:
04785                                 for (i = ALL_TARGET_HT20_0_8_16;
04786                                      i <= ALL_TARGET_HT20_21; i++)
04787                                         pPwrArray[i] =
04788                                           (u8)min((u16)pPwrArray[i],
04789                                                   minCtlPower);
04790                                 pPwrArray[ALL_TARGET_HT20_22] =
04791                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
04792                                           minCtlPower);
04793                                 pPwrArray[ALL_TARGET_HT20_23] =
04794                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
04795                                            minCtlPower);
04796                                 break;
04797                         case CTL_5GHT40:
04798                         case CTL_2GHT40:
04799                                 for (i = ALL_TARGET_HT40_0_8_16;
04800                                      i <= ALL_TARGET_HT40_23; i++)
04801                                         pPwrArray[i] =
04802                                           (u8)min((u16)pPwrArray[i],
04803                                                   minCtlPower);
04804                                 break;
04805                         default:
04806                             break;
04807                         }
04808         } /* end ctl mode checking */
04809 }
04810 
04811 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
04812 {
04813         u8 mod_idx = mcs_idx % 8;
04814 
04815         if (mod_idx <= 3)
04816                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
04817         else
04818                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
04819 }
04820 
04821 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
04822                                         struct ath9k_channel *chan, u16 cfgCtl,
04823                                         u8 twiceAntennaReduction,
04824                                         u8 twiceMaxRegulatoryPower,
04825                                         u8 powerLimit, int test)
04826 {
04827         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
04828         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04829         struct ar9300_modal_eep_header *modal_hdr;
04830         u8 targetPowerValT2[ar9300RateSize];
04831         u8 target_power_val_t2_eep[ar9300RateSize];
04832         unsigned int i = 0, paprd_scale_factor = 0;
04833         u8 pwr_idx, min_pwridx = 0;
04834 
04835         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
04836 
04837         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
04838                 if (IS_CHAN_2GHZ(chan))
04839                         modal_hdr = &eep->modalHeader2G;
04840                 else
04841                         modal_hdr = &eep->modalHeader5G;
04842 
04843                 ah->paprd_ratemask =
04844                                 (uint32_t)(modal_hdr->papdRateMaskHt20) &
04845                         AR9300_PAPRD_RATE_MASK;
04846 
04847                 ah->paprd_ratemask_ht40 =
04848                                 (uint32_t)(modal_hdr->papdRateMaskHt40) &
04849                         AR9300_PAPRD_RATE_MASK;
04850 
04851                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
04852                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
04853                                                   ALL_TARGET_HT20_0_8_16;
04854 
04855                 if (!ah->paprd_table_write_done) {
04856                         memcpy(target_power_val_t2_eep, targetPowerValT2,
04857                                sizeof(targetPowerValT2));
04858                         for (i = 0; i < 24; i++) {
04859                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
04860                                 if (ah->paprd_ratemask & (1 << i)) {
04861                                         if (targetPowerValT2[pwr_idx] &&
04862                                             targetPowerValT2[pwr_idx] ==
04863                                             target_power_val_t2_eep[pwr_idx])
04864                                                 targetPowerValT2[pwr_idx] -=
04865                                                         paprd_scale_factor;
04866                                 }
04867                         }
04868                 }
04869                 memcpy(target_power_val_t2_eep, targetPowerValT2,
04870                        sizeof(targetPowerValT2));
04871         }
04872 
04873         ar9003_hw_set_power_per_rate_table(ah, chan,
04874                                            targetPowerValT2, cfgCtl,
04875                                            twiceAntennaReduction,
04876                                            twiceMaxRegulatoryPower,
04877                                            powerLimit);
04878 
04879         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
04880                 for (i = 0; i < ar9300RateSize; i++) {
04881                         if ((ah->paprd_ratemask & (1 << i)) &&
04882                             ((unsigned int)abs(targetPowerValT2[i] -
04883                                 target_power_val_t2_eep[i]) >
04884                             paprd_scale_factor)) {
04885                                 ah->paprd_ratemask &= ~(1 << i);
04886                                 DBG2("ath9k: "
04887                                         "paprd disabled for mcs %d\n", i);
04888                         }
04889                 }
04890         }
04891 
04892         regulatory->max_power_level = 0;
04893         for (i = 0; i < ar9300RateSize; i++) {
04894                 if (targetPowerValT2[i] > regulatory->max_power_level)
04895                         regulatory->max_power_level = targetPowerValT2[i];
04896         }
04897 
04898         if (test)
04899                 return;
04900 
04901         for (i = 0; i < ar9300RateSize; i++) {
04902                 DBG2("ath9k: "
04903                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
04904         }
04905 
04906         /*
04907          * This is the TX power we send back to driver core,
04908          * and it can use to pass to userspace to display our
04909          * currently configured TX power setting.
04910          *
04911          * Since power is rate dependent, use one of the indices
04912          * from the AR9300_Rates enum to select an entry from
04913          * targetPowerValT2[] to report. Currently returns the
04914          * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
04915          * as CCK power is less interesting (?).
04916          */
04917         i = ALL_TARGET_LEGACY_6_24; /* legacy */
04918         if (IS_CHAN_HT40(chan))
04919                 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
04920         else if (IS_CHAN_HT20(chan))
04921                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
04922 
04923         ah->txpower_limit = targetPowerValT2[i];
04924         regulatory->max_power_level = targetPowerValT2[i];
04925 
04926         /* Write target power array to registers */
04927         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
04928         ar9003_hw_calibration_apply(ah, chan->channel);
04929 
04930         if (IS_CHAN_2GHZ(chan)) {
04931                 if (IS_CHAN_HT40(chan))
04932                         i = ALL_TARGET_HT40_0_8_16;
04933                 else
04934                         i = ALL_TARGET_HT20_0_8_16;
04935         } else {
04936                 if (IS_CHAN_HT40(chan))
04937                         i = ALL_TARGET_HT40_7;
04938                 else
04939                         i = ALL_TARGET_HT20_7;
04940         }
04941         ah->paprd_target_power = targetPowerValT2[i];
04942 }
04943 
04944 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused,
04945                                             u16 i __unused, int is2GHz __unused)
04946 {
04947         return AR_NO_SPUR;
04948 }
04949 
04950 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
04951 {
04952         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04953 
04954         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
04955 }
04956 
04957 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
04958 {
04959         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04960 
04961         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
04962 }
04963 
04964 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
04965 {
04966         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04967 
04968         if (is_2ghz)
04969                 return eep->modalHeader2G.spurChans;
04970         else
04971                 return eep->modalHeader5G.spurChans;
04972 }
04973 
04974 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
04975                                            struct ath9k_channel *chan)
04976 {
04977         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
04978 
04979         if (IS_CHAN_2GHZ(chan))
04980                 return MS((uint32_t)(eep->modalHeader2G.papdRateMaskHt20),
04981                           AR9300_PAPRD_SCALE_1);
04982         else {
04983                 if (chan->channel >= 5700)
04984                 return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt20),
04985                           AR9300_PAPRD_SCALE_1);
04986                 else if (chan->channel >= 5400)
04987                         return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
04988                                    AR9300_PAPRD_SCALE_2);
04989                 else
04990                         return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
04991                                   AR9300_PAPRD_SCALE_1);
04992         }
04993 }
04994 
04995 const struct eeprom_ops eep_ar9300_ops = {
04996         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
04997         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
04998         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
04999         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
05000         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
05001         .set_board_values = ath9k_hw_ar9300_set_board_values,
05002         .set_addac = ath9k_hw_ar9300_set_addac,
05003         .set_txpower = ath9k_hw_ar9300_set_txpower,
05004         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
05005 };