iPXE
eeprom.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef EEPROM_H
00021 #define EEPROM_H
00022 
00023 FILE_LICENCE ( BSD2 );
00024 
00025 #define AR_EEPROM_MODAL_SPURS   5
00026 
00027 #include "../ath.h"
00028 #include "ar9003_eeprom.h"
00029 
00030 #if __BYTE_ORDER == __BIG_ENDIAN
00031 #define AR5416_EEPROM_MAGIC 0x5aa5
00032 #else
00033 #define AR5416_EEPROM_MAGIC 0xa55a
00034 #endif
00035 
00036 #define CTRY_DEBUG   0x1ff
00037 #define CTRY_DEFAULT 0
00038 
00039 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
00040 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
00041 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
00042 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
00043 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
00044 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
00045 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
00046 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
00047 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
00048 
00049 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
00050 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
00051 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
00052 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
00053 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
00054 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
00055 
00056 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
00057 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
00058 
00059 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
00060 #define AR5416_EEPROM_S             2
00061 #define AR5416_EEPROM_OFFSET        0x2000
00062 #define AR5416_EEPROM_MAX           0xae0
00063 
00064 #define AR5416_EEPROM_START_ADDR \
00065         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
00066 
00067 #define SD_NO_CTL               0xE0
00068 #define NO_CTL                  0xff
00069 #define CTL_MODE_M              0xf
00070 #define CTL_11A                 0
00071 #define CTL_11B                 1
00072 #define CTL_11G                 2
00073 #define CTL_2GHT20              5
00074 #define CTL_5GHT20              6
00075 #define CTL_2GHT40              7
00076 #define CTL_5GHT40              8
00077 
00078 #define EXT_ADDITIVE (0x8000)
00079 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
00080 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
00081 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
00082 
00083 #define SUB_NUM_CTL_MODES_AT_5G_40 2
00084 #define SUB_NUM_CTL_MODES_AT_2G_40 3
00085 
00086 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
00087 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
00088 
00089 /*
00090  * For AR9285 and later chipsets, the following bits are not being programmed
00091  * in EEPROM and so need to be enabled always.
00092  *
00093  * Bit 0: en_fcc_mid
00094  * Bit 1: en_jap_mid
00095  * Bit 2: en_fcc_dfs_ht40
00096  * Bit 3: en_jap_ht40
00097  * Bit 4: en_jap_dfs_ht40
00098  */
00099 #define AR9285_RDEXT_DEFAULT    0x1F
00100 
00101 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
00102 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
00103 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
00104 
00105 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
00106 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
00107                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
00108 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
00109                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
00110 
00111 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
00112 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
00113 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
00114 #define AR_EEPROM_RFSILENT_POLARITY_S   1
00115 
00116 #define EEP_RFSILENT_ENABLED        0x0001
00117 #define EEP_RFSILENT_ENABLED_S      0
00118 #define EEP_RFSILENT_POLARITY       0x0002
00119 #define EEP_RFSILENT_POLARITY_S     1
00120 #define EEP_RFSILENT_GPIO_SEL       0x001c
00121 #define EEP_RFSILENT_GPIO_SEL_S     2
00122 
00123 #define AR5416_OPFLAGS_11A           0x01
00124 #define AR5416_OPFLAGS_11G           0x02
00125 #define AR5416_OPFLAGS_N_5G_HT40     0x04
00126 #define AR5416_OPFLAGS_N_2G_HT40     0x08
00127 #define AR5416_OPFLAGS_N_5G_HT20     0x10
00128 #define AR5416_OPFLAGS_N_2G_HT20     0x20
00129 
00130 #define AR5416_EEP_NO_BACK_VER       0x1
00131 #define AR5416_EEP_VER               0xE
00132 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
00133 #define AR5416_EEP_MINOR_VER_2       0x2
00134 #define AR5416_EEP_MINOR_VER_3       0x3
00135 #define AR5416_EEP_MINOR_VER_7       0x7
00136 #define AR5416_EEP_MINOR_VER_9       0x9
00137 #define AR5416_EEP_MINOR_VER_16      0x10
00138 #define AR5416_EEP_MINOR_VER_17      0x11
00139 #define AR5416_EEP_MINOR_VER_19      0x13
00140 #define AR5416_EEP_MINOR_VER_20      0x14
00141 #define AR5416_EEP_MINOR_VER_21      0x15
00142 #define AR5416_EEP_MINOR_VER_22      0x16
00143 
00144 #define AR5416_NUM_5G_CAL_PIERS         8
00145 #define AR5416_NUM_2G_CAL_PIERS         4
00146 #define AR5416_NUM_5G_20_TARGET_POWERS  8
00147 #define AR5416_NUM_5G_40_TARGET_POWERS  8
00148 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
00149 #define AR5416_NUM_2G_20_TARGET_POWERS  4
00150 #define AR5416_NUM_2G_40_TARGET_POWERS  4
00151 #define AR5416_NUM_CTLS                 24
00152 #define AR5416_NUM_BAND_EDGES           8
00153 #define AR5416_NUM_PD_GAINS             4
00154 #define AR5416_PD_GAINS_IN_MASK         4
00155 #define AR5416_PD_GAIN_ICEPTS           5
00156 #define AR5416_NUM_PDADC_VALUES         128
00157 #define AR5416_BCHAN_UNUSED             0xFF
00158 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
00159 #define AR5416_MAX_CHAINS               3
00160 #define AR9300_MAX_CHAINS               3
00161 #define AR5416_PWR_TABLE_OFFSET_DB     -5
00162 
00163 /* Rx gain type values */
00164 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
00165 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
00166 #define AR5416_EEP_RXGAIN_ORIG             2
00167 
00168 /* Tx gain type values */
00169 #define AR5416_EEP_TXGAIN_ORIGINAL         0
00170 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
00171 
00172 #define AR5416_EEP4K_START_LOC                64
00173 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
00174 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
00175 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
00176 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
00177 #define AR5416_EEP4K_NUM_CTLS                 12
00178 #define AR5416_EEP4K_NUM_BAND_EDGES           4
00179 #define AR5416_EEP4K_NUM_PD_GAINS             2
00180 #define AR5416_EEP4K_MAX_CHAINS               1
00181 
00182 #define AR9280_TX_GAIN_TABLE_SIZE 22
00183 
00184 #define AR9287_EEP_VER               0xE
00185 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
00186 #define AR9287_EEP_MINOR_VER_1       0x1
00187 #define AR9287_EEP_MINOR_VER_2       0x2
00188 #define AR9287_EEP_MINOR_VER_3       0x3
00189 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
00190 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
00191 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
00192 
00193 #define AR9287_EEP_START_LOC            128
00194 #define AR9287_HTC_EEP_START_LOC        256
00195 #define AR9287_NUM_2G_CAL_PIERS         3
00196 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
00197 #define AR9287_NUM_2G_20_TARGET_POWERS  3
00198 #define AR9287_NUM_2G_40_TARGET_POWERS  3
00199 #define AR9287_NUM_CTLS                 12
00200 #define AR9287_NUM_BAND_EDGES           4
00201 #define AR9287_PD_GAIN_ICEPTS           1
00202 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
00203 #define AR9287_EEPMISC_WOW              0x02
00204 #define AR9287_MAX_CHAINS               2
00205 #define AR9287_ANT_16S                  32
00206 
00207 #define AR9287_DATA_SZ                  32
00208 
00209 #define AR9287_PWR_TABLE_OFFSET_DB  -5
00210 
00211 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
00212 
00213 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
00214 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
00215 
00216 #define LNA_CTL_BUF_MODE        BIT(0)
00217 #define LNA_CTL_ISEL_LO         BIT(1)
00218 #define LNA_CTL_ISEL_HI         BIT(2)
00219 #define LNA_CTL_BUF_IN          BIT(3)
00220 #define LNA_CTL_FEM_BAND        BIT(4)
00221 #define LNA_CTL_LOCAL_BIAS      BIT(5)
00222 #define LNA_CTL_FORCE_XPA       BIT(6)
00223 #define LNA_CTL_USE_ANT1        BIT(7)
00224 
00225 enum eeprom_param {
00226         EEP_NFTHRESH_5,
00227         EEP_NFTHRESH_2,
00228         EEP_MAC_MSW,
00229         EEP_MAC_MID,
00230         EEP_MAC_LSW,
00231         EEP_REG_0,
00232         EEP_REG_1,
00233         EEP_OP_CAP,
00234         EEP_OP_MODE,
00235         EEP_RF_SILENT,
00236         EEP_OB_5,
00237         EEP_DB_5,
00238         EEP_OB_2,
00239         EEP_DB_2,
00240         EEP_MINOR_REV,
00241         EEP_TX_MASK,
00242         EEP_RX_MASK,
00243         EEP_FSTCLK_5G,
00244         EEP_RXGAIN_TYPE,
00245         EEP_OL_PWRCTRL,
00246         EEP_TXGAIN_TYPE,
00247         EEP_RC_CHAIN_MASK,
00248         EEP_DAC_HPWR_5G,
00249         EEP_FRAC_N_5G,
00250         EEP_DEV_TYPE,
00251         EEP_TEMPSENSE_SLOPE,
00252         EEP_TEMPSENSE_SLOPE_PAL_ON,
00253         EEP_PWR_TABLE_OFFSET,
00254         EEP_DRIVE_STRENGTH,
00255         EEP_INTERNAL_REGULATOR,
00256         EEP_SWREG,
00257         EEP_PAPRD,
00258         EEP_MODAL_VER,
00259         EEP_ANT_DIV_CTL1,
00260         EEP_CHAIN_MASK_REDUCE
00261 };
00262 
00263 enum ar5416_rates {
00264         rate6mb, rate9mb, rate12mb, rate18mb,
00265         rate24mb, rate36mb, rate48mb, rate54mb,
00266         rate1l, rate2l, rate2s, rate5_5l,
00267         rate5_5s, rate11l, rate11s, rateXr,
00268         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
00269         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
00270         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
00271         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
00272         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
00273         Ar5416RateSize
00274 };
00275 
00276 enum ath9k_hal_freq_band {
00277         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
00278         ATH9K_HAL_FREQ_BAND_2GHZ = 1
00279 };
00280 
00281 struct base_eep_header {
00282         u16 length;
00283         u16 checksum;
00284         u16 version;
00285         u8 opCapFlags;
00286         u8 eepMisc;
00287         u16 regDmn[2];
00288         u8 macAddr[6];
00289         u8 rxMask;
00290         u8 txMask;
00291         u16 rfSilent;
00292         u16 blueToothOptions;
00293         u16 deviceCap;
00294         u32 binBuildNumber;
00295         u8 deviceType;
00296         u8 pwdclkind;
00297         u8 fastClk5g;
00298         u8 divChain;
00299         u8 rxGainType;
00300         u8 dacHiPwrMode_5G;
00301         u8 openLoopPwrCntl;
00302         u8 dacLpMode;
00303         u8 txGainType;
00304         u8 rcChainMask;
00305         u8 desiredScaleCCK;
00306         u8 pwr_table_offset;
00307         u8 frac_n_5g;
00308         u8 futureBase_3[21];
00309 } __attribute__((packed));
00310 
00311 struct base_eep_header_4k {
00312         u16 length;
00313         u16 checksum;
00314         u16 version;
00315         u8 opCapFlags;
00316         u8 eepMisc;
00317         u16 regDmn[2];
00318         u8 macAddr[6];
00319         u8 rxMask;
00320         u8 txMask;
00321         u16 rfSilent;
00322         u16 blueToothOptions;
00323         u16 deviceCap;
00324         u32 binBuildNumber;
00325         u8 deviceType;
00326         u8 txGainType;
00327 } __attribute__((packed));
00328 
00329 
00330 struct spur_chan {
00331         u16 spurChan;
00332         u8 spurRangeLow;
00333         u8 spurRangeHigh;
00334 } __attribute__((packed));
00335 
00336 struct modal_eep_header {
00337         u32 antCtrlChain[AR5416_MAX_CHAINS];
00338         u32 antCtrlCommon;
00339         u8 antennaGainCh[AR5416_MAX_CHAINS];
00340         u8 switchSettling;
00341         u8 txRxAttenCh[AR5416_MAX_CHAINS];
00342         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
00343         u8 adcDesiredSize;
00344         u8 pgaDesiredSize;
00345         u8 xlnaGainCh[AR5416_MAX_CHAINS];
00346         u8 txEndToXpaOff;
00347         u8 txEndToRxOn;
00348         u8 txFrameToXpaOn;
00349         u8 thresh62;
00350         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
00351         u8 xpdGain;
00352         u8 xpd;
00353         u8 iqCalICh[AR5416_MAX_CHAINS];
00354         u8 iqCalQCh[AR5416_MAX_CHAINS];
00355         u8 pdGainOverlap;
00356         u8 ob;
00357         u8 db;
00358         u8 xpaBiasLvl;
00359         u8 pwrDecreaseFor2Chain;
00360         u8 pwrDecreaseFor3Chain;
00361         u8 txFrameToDataStart;
00362         u8 txFrameToPaOn;
00363         u8 ht40PowerIncForPdadc;
00364         u8 bswAtten[AR5416_MAX_CHAINS];
00365         u8 bswMargin[AR5416_MAX_CHAINS];
00366         u8 swSettleHt40;
00367         u8 xatten2Db[AR5416_MAX_CHAINS];
00368         u8 xatten2Margin[AR5416_MAX_CHAINS];
00369         u8 ob_ch1;
00370         u8 db_ch1;
00371         u8 lna_ctl;
00372         u8 miscBits;
00373         u16 xpaBiasLvlFreq[3];
00374         u8 futureModal[6];
00375 
00376         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
00377 } __attribute__((packed));
00378 
00379 struct calDataPerFreqOpLoop {
00380         u8 pwrPdg[2][5];
00381         u8 vpdPdg[2][5];
00382         u8 pcdac[2][5];
00383         u8 empty[2][5];
00384 } __attribute__((packed));
00385 
00386 struct modal_eep_4k_header {
00387         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
00388         u32 antCtrlCommon;
00389         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
00390         u8 switchSettling;
00391         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
00392         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
00393         u8 adcDesiredSize;
00394         u8 pgaDesiredSize;
00395         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
00396         u8 txEndToXpaOff;
00397         u8 txEndToRxOn;
00398         u8 txFrameToXpaOn;
00399         u8 thresh62;
00400         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
00401         u8 xpdGain;
00402         u8 xpd;
00403         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
00404         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
00405         u8 pdGainOverlap;
00406 #ifdef __BIG_ENDIAN_BITFIELD
00407         u8 ob_1:4, ob_0:4;
00408         u8 db1_1:4, db1_0:4;
00409 #else
00410         u8 ob_0:4, ob_1:4;
00411         u8 db1_0:4, db1_1:4;
00412 #endif
00413         u8 xpaBiasLvl;
00414         u8 txFrameToDataStart;
00415         u8 txFrameToPaOn;
00416         u8 ht40PowerIncForPdadc;
00417         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
00418         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
00419         u8 swSettleHt40;
00420         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
00421         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
00422 #ifdef __BIG_ENDIAN_BITFIELD
00423         u8 db2_1:4, db2_0:4;
00424 #else
00425         u8 db2_0:4, db2_1:4;
00426 #endif
00427         u8 version;
00428 #ifdef __BIG_ENDIAN_BITFIELD
00429         u8 ob_3:4, ob_2:4;
00430         u8 antdiv_ctl1:4, ob_4:4;
00431         u8 db1_3:4, db1_2:4;
00432         u8 antdiv_ctl2:4, db1_4:4;
00433         u8 db2_2:4, db2_3:4;
00434         u8 reserved:4, db2_4:4;
00435 #else
00436         u8 ob_2:4, ob_3:4;
00437         u8 ob_4:4, antdiv_ctl1:4;
00438         u8 db1_2:4, db1_3:4;
00439         u8 db1_4:4, antdiv_ctl2:4;
00440         u8 db2_2:4, db2_3:4;
00441         u8 db2_4:4, reserved:4;
00442 #endif
00443         u8 tx_diversity;
00444         u8 flc_pwr_thresh;
00445         u8 bb_scale_smrt_antenna;
00446 #define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
00447         u8 futureModal[1];
00448         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
00449 } __attribute__((packed));
00450 
00451 struct base_eep_ar9287_header {
00452         u16 length;
00453         u16 checksum;
00454         u16 version;
00455         u8 opCapFlags;
00456         u8 eepMisc;
00457         u16 regDmn[2];
00458         u8 macAddr[6];
00459         u8 rxMask;
00460         u8 txMask;
00461         u16 rfSilent;
00462         u16 blueToothOptions;
00463         u16 deviceCap;
00464         u32 binBuildNumber;
00465         u8 deviceType;
00466         u8 openLoopPwrCntl;
00467         int8_t pwrTableOffset;
00468         int8_t tempSensSlope;
00469         int8_t tempSensSlopePalOn;
00470         u8 futureBase[29];
00471 } __attribute__((packed));
00472 
00473 struct modal_eep_ar9287_header {
00474         u32 antCtrlChain[AR9287_MAX_CHAINS];
00475         u32 antCtrlCommon;
00476         int8_t antennaGainCh[AR9287_MAX_CHAINS];
00477         u8 switchSettling;
00478         u8 txRxAttenCh[AR9287_MAX_CHAINS];
00479         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
00480         int8_t adcDesiredSize;
00481         u8 txEndToXpaOff;
00482         u8 txEndToRxOn;
00483         u8 txFrameToXpaOn;
00484         u8 thresh62;
00485         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
00486         u8 xpdGain;
00487         u8 xpd;
00488         int8_t iqCalICh[AR9287_MAX_CHAINS];
00489         int8_t iqCalQCh[AR9287_MAX_CHAINS];
00490         u8 pdGainOverlap;
00491         u8 xpaBiasLvl;
00492         u8 txFrameToDataStart;
00493         u8 txFrameToPaOn;
00494         u8 ht40PowerIncForPdadc;
00495         u8 bswAtten[AR9287_MAX_CHAINS];
00496         u8 bswMargin[AR9287_MAX_CHAINS];
00497         u8 swSettleHt40;
00498         u8 version;
00499         u8 db1;
00500         u8 db2;
00501         u8 ob_cck;
00502         u8 ob_psk;
00503         u8 ob_qam;
00504         u8 ob_pal_off;
00505         u8 futureModal[30];
00506         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
00507 } __attribute__((packed));
00508 
00509 struct cal_data_per_freq {
00510         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
00511         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
00512 } __attribute__((packed));
00513 
00514 struct cal_data_per_freq_4k {
00515         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
00516         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
00517 } __attribute__((packed));
00518 
00519 struct cal_target_power_leg {
00520         u8 bChannel;
00521         u8 tPow2x[4];
00522 } __attribute__((packed));
00523 
00524 struct cal_target_power_ht {
00525         u8 bChannel;
00526         u8 tPow2x[8];
00527 } __attribute__((packed));
00528 
00529 struct cal_ctl_edges {
00530         u8 bChannel;
00531         u8 ctl;
00532 } __attribute__((packed));
00533 
00534 struct cal_data_op_loop_ar9287 {
00535         u8 pwrPdg[2][5];
00536         u8 vpdPdg[2][5];
00537         u8 pcdac[2][5];
00538         u8 empty[2][5];
00539 } __attribute__((packed));
00540 
00541 struct cal_data_per_freq_ar9287 {
00542         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
00543         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
00544 } __attribute__((packed));
00545 
00546 union cal_data_per_freq_ar9287_u {
00547         struct cal_data_op_loop_ar9287 calDataOpen;
00548         struct cal_data_per_freq_ar9287 calDataClose;
00549 } __attribute__((packed));
00550 
00551 struct cal_ctl_data_ar9287 {
00552         struct cal_ctl_edges
00553         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
00554 } __attribute__((packed));
00555 
00556 struct cal_ctl_data {
00557         struct cal_ctl_edges
00558         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
00559 } __attribute__((packed));
00560 
00561 struct cal_ctl_data_4k {
00562         struct cal_ctl_edges
00563         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
00564 } __attribute__((packed));
00565 
00566 struct ar5416_eeprom_def {
00567         struct base_eep_header baseEepHeader;
00568         u8 custData[64];
00569         struct modal_eep_header modalHeader[2];
00570         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
00571         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
00572         struct cal_data_per_freq
00573          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
00574         struct cal_data_per_freq
00575          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
00576         struct cal_target_power_leg
00577          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
00578         struct cal_target_power_ht
00579          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
00580         struct cal_target_power_ht
00581          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
00582         struct cal_target_power_leg
00583          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
00584         struct cal_target_power_leg
00585          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
00586         struct cal_target_power_ht
00587          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
00588         struct cal_target_power_ht
00589          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
00590         u8 ctlIndex[AR5416_NUM_CTLS];
00591         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
00592         u8 padding;
00593 } __attribute__((packed));
00594 
00595 struct ar5416_eeprom_4k {
00596         struct base_eep_header_4k baseEepHeader;
00597         u8 custData[20];
00598         struct modal_eep_4k_header modalHeader;
00599         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
00600         struct cal_data_per_freq_4k
00601         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
00602         struct cal_target_power_leg
00603         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
00604         struct cal_target_power_leg
00605         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
00606         struct cal_target_power_ht
00607         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
00608         struct cal_target_power_ht
00609         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
00610         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
00611         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
00612         u8 padding;
00613 } __attribute__((packed));
00614 
00615 struct ar9287_eeprom {
00616         struct base_eep_ar9287_header baseEepHeader;
00617         u8 custData[AR9287_DATA_SZ];
00618         struct modal_eep_ar9287_header modalHeader;
00619         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
00620         union cal_data_per_freq_ar9287_u
00621         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
00622         struct cal_target_power_leg
00623         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
00624         struct cal_target_power_leg
00625         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
00626         struct cal_target_power_ht
00627         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
00628         struct cal_target_power_ht
00629         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
00630         u8 ctlIndex[AR9287_NUM_CTLS];
00631         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
00632         u8 padding;
00633 } __attribute__((packed));
00634 
00635 enum reg_ext_bitmap {
00636         REG_EXT_FCC_MIDBAND = 0,
00637         REG_EXT_JAPAN_MIDBAND = 1,
00638         REG_EXT_FCC_DFS_HT40 = 2,
00639         REG_EXT_JAPAN_NONDFS_HT40 = 3,
00640         REG_EXT_JAPAN_DFS_HT40 = 4
00641 };
00642 
00643 struct ath9k_country_entry {
00644         u16 countryCode;
00645         u16 regDmnEnum;
00646         u16 regDmn5G;
00647         u16 regDmn2G;
00648         u8 isMultidomain;
00649         u8 iso[3];
00650 };
00651 
00652 struct eeprom_ops {
00653         int (*check_eeprom)(struct ath_hw *hw);
00654         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
00655         int (*fill_eeprom)(struct ath_hw *hw);
00656         int (*get_eeprom_ver)(struct ath_hw *hw);
00657         int (*get_eeprom_rev)(struct ath_hw *hw);
00658         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
00659         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
00660         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
00661                            u16 cfgCtl, u8 twiceAntennaReduction,
00662                            u8 twiceMaxRegulatoryPower, u8 powerLimit,
00663                            int test);
00664         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, int is2GHz);
00665 };
00666 
00667 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
00668 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
00669                                u32 shift, u32 val);
00670 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
00671                              int16_t targetLeft,
00672                              int16_t targetRight);
00673 int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
00674                                     u16 *indexL, u16 *indexR);
00675 int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
00676 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
00677                                   int eep_start_loc, int size);
00678 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
00679                              u8 *pVpdList, u16 numIntercepts,
00680                              u8 *pRetVpdList);
00681 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
00682                                        struct ath9k_channel *chan,
00683                                        struct cal_target_power_leg *powInfo,
00684                                        u16 numChannels,
00685                                        struct cal_target_power_leg *pNewPower,
00686                                        u16 numRates, int isExtTarget);
00687 void ath9k_hw_get_target_powers(struct ath_hw *ah,
00688                                 struct ath9k_channel *chan,
00689                                 struct cal_target_power_ht *powInfo,
00690                                 u16 numChannels,
00691                                 struct cal_target_power_ht *pNewPower,
00692                                 u16 numRates, int isHt40Target);
00693 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
00694                                 int is2GHz, int num_band_edges);
00695 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
00696 int ath9k_hw_eeprom_init(struct ath_hw *ah);
00697 
00698 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
00699                                 struct ath9k_channel *chan,
00700                                 void *pRawDataSet,
00701                                 u8 *bChans, u16 availPiers,
00702                                 u16 tPdGainOverlap,
00703                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
00704                                 u16 numXpdGains);
00705 
00706 #define ar5416_get_ntxchains(_txchainmask)                      \
00707         (((_txchainmask >> 2) & 1) +                            \
00708          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
00709 
00710 extern const struct eeprom_ops eep_def_ops;
00711 extern const struct eeprom_ops eep_4k_ops;
00712 extern const struct eeprom_ops eep_ar9287_ops;
00713 extern const struct eeprom_ops eep_ar9287_ops;
00714 extern const struct eeprom_ops eep_ar9300_ops;
00715 
00716 #endif /* EEPROM_H */