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iPXE
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Go to the source code of this file.
| #define AR_EEPROM_MODAL_SPURS 5 |
Definition at line 25 of file eeprom.h.
Referenced by ar5008_hw_spur_mitigate(), ar9002_hw_spur_mitigate(), ar9003_hw_spur_mitigate_ofdm(), ath9k_hw_4k_check_eeprom(), ath9k_hw_ar9287_check_eeprom(), ath9k_hw_def_check_eeprom(), and ath9k_hw_init_config().
| #define AR5416_EEPROM_MAGIC 0xa55a |
Definition at line 33 of file eeprom.h.
Referenced by ath9k_hw_4k_check_eeprom(), ath9k_hw_ar9287_check_eeprom(), and ath9k_hw_def_check_eeprom().
| #define CTRY_DEBUG 0x1ff |
| #define CTRY_DEFAULT 0 |
Definition at line 37 of file eeprom.h.
Referenced by ath9k_hw_init_defaults().
| #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 |
| #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 |
| #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 |
| #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 |
| #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 |
| #define AR_EEPROM_EEPCAP_MAXQCU_S 4 |
| #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 |
| #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 |
| #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 |
| #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 |
| #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 |
| #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 |
| #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 |
| #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 |
| #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 |
| #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 |
| #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 |
| #define AR5416_EEPROM_MAGIC_OFFSET 0x0 |
Definition at line 59 of file eeprom.h.
Referenced by ath9k_hw_4k_check_eeprom(), ath9k_hw_ar9287_check_eeprom(), and ath9k_hw_def_check_eeprom().
| #define AR5416_EEPROM_S 2 |
Definition at line 60 of file eeprom.h.
Referenced by ath9k_hw_usb_gen_fill_eeprom(), and ath_pci_eeprom_read().
| #define AR5416_EEPROM_OFFSET 0x2000 |
Definition at line 61 of file eeprom.h.
Referenced by ath9k_hw_usb_gen_fill_eeprom(), and ath_pci_eeprom_read().
| #define AR5416_EEPROM_MAX 0xae0 |
| #define AR5416_EEPROM_START_ADDR (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 |
| #define SD_NO_CTL 0xE0 |
Definition at line 67 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define NO_CTL 0xff |
Definition at line 68 of file eeprom.h.
Referenced by ath_regd_get_band_ctl().
| #define CTL_MODE_M 0xf |
Definition at line 69 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define CTL_11A 0 |
Definition at line 70 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), ath9k_hw_set_def_power_per_rate_table(), and ath9k_regd_get_ctl().
| #define CTL_11B 1 |
Definition at line 71 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), ath9k_hw_set_def_power_per_rate_table(), and ath9k_regd_get_ctl().
| #define CTL_11G 2 |
Definition at line 72 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), ath9k_hw_set_def_power_per_rate_table(), and ath9k_regd_get_ctl().
| #define CTL_2GHT20 5 |
Definition at line 73 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define CTL_5GHT20 6 |
Definition at line 74 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define CTL_2GHT40 7 |
Definition at line 75 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define CTL_5GHT40 8 |
Definition at line 76 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define EXT_ADDITIVE (0x8000) |
| #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) |
| #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) |
| #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) |
| #define SUB_NUM_CTL_MODES_AT_5G_40 2 |
| #define SUB_NUM_CTL_MODES_AT_2G_40 3 |
| #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ |
Definition at line 86 of file eeprom.h.
Referenced by ath9k_hw_def_set_txpower(), and ath9k_hw_update_regulatory_maxpower().
| #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ |
Definition at line 87 of file eeprom.h.
Referenced by ath9k_hw_def_set_txpower(), and ath9k_hw_update_regulatory_maxpower().
| #define AR9285_RDEXT_DEFAULT 0x1F |
Definition at line 99 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define ATH9K_POW_SM | ( | _r, | |
| _s | |||
| ) | (((_r) & 0x3f) << (_s)) |
Definition at line 101 of file eeprom.h.
Referenced by ath9k_hw_4k_set_txpower(), ath9k_hw_ar9287_set_txpower(), and ath9k_hw_def_set_txpower().
| #define FREQ2FBIN | ( | x, | |
| y | |||
| ) | ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) |
Definition at line 102 of file eeprom.h.
Referenced by ar9287_eeprom_get_tx_gain_index(), ath9k_get_txgain_index(), ath9k_hw_def_set_addac(), and ath9k_hw_get_gain_boundaries_pdadcs().
| #define ath9k_hw_use_flash | ( | _ah | ) | (!(_ah->ah_flags & AH_USE_EEPROM)) |
Definition at line 103 of file eeprom.h.
Referenced by ar9300_eeprom_restore_internal(), ath9k_hw_4k_check_eeprom(), ath9k_hw_4k_fill_eeprom(), ath9k_hw_ar9287_check_eeprom(), ath9k_hw_ar9287_fill_eeprom(), ath9k_hw_def_check_eeprom(), and ath9k_hw_def_fill_eeprom().
| #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) |
Definition at line 105 of file eeprom.h.
Referenced by ath9k_hw_def_get_eeprom(), ath9k_hw_def_set_board_values(), and ath9k_hw_def_set_gain().
| #define OLC_FOR_AR9280_20_LATER |
(AR_SREV_9280_20_OR_LATER(ah) && \ ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
Definition at line 106 of file eeprom.h.
Referenced by ar9002_hw_olc_temp_compensation(), ar9002_olc_init(), ath9k_hw_def_set_txpower(), and ath9k_hw_set_def_power_cal_table().
| #define OLC_FOR_AR9287_10_LATER |
(AR_SREV_9287_11_OR_LATER(ah) && \ ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
Definition at line 108 of file eeprom.h.
Referenced by ar9002_hw_olc_temp_compensation(), and ar9002_olc_init().
| #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c |
| #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 |
| #define AR_EEPROM_RFSILENT_POLARITY 0x0002 |
| #define AR_EEPROM_RFSILENT_POLARITY_S 1 |
| #define EEP_RFSILENT_ENABLED 0x0001 |
Definition at line 116 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define EEP_RFSILENT_ENABLED_S 0 |
| #define EEP_RFSILENT_POLARITY 0x0002 |
Definition at line 118 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define EEP_RFSILENT_POLARITY_S 1 |
| #define EEP_RFSILENT_GPIO_SEL 0x001c |
Definition at line 120 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define EEP_RFSILENT_GPIO_SEL_S 2 |
| #define AR5416_OPFLAGS_11A 0x01 |
Definition at line 123 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define AR5416_OPFLAGS_11G 0x02 |
Definition at line 124 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define AR5416_OPFLAGS_N_5G_HT40 0x04 |
| #define AR5416_OPFLAGS_N_2G_HT40 0x08 |
| #define AR5416_OPFLAGS_N_5G_HT20 0x10 |
| #define AR5416_OPFLAGS_N_2G_HT20 0x20 |
| #define AR5416_EEP_NO_BACK_VER 0x1 |
Definition at line 130 of file eeprom.h.
Referenced by ath9k_hw_4k_check_eeprom(), ath9k_hw_ar9287_check_eeprom(), and ath9k_hw_def_check_eeprom().
| #define AR5416_EEP_VER 0xE |
Definition at line 131 of file eeprom.h.
Referenced by ath9k_hw_4k_check_eeprom(), and ath9k_hw_def_check_eeprom().
| #define AR5416_EEP_VER_MINOR_MASK 0x0FFF |
Definition at line 132 of file eeprom.h.
Referenced by ath9k_hw_4k_get_eeprom(), ath9k_hw_4k_set_board_values(), ath9k_hw_4k_set_gain(), ath9k_hw_4k_set_txpower(), ath9k_hw_def_set_txpower(), ath9k_hw_set_4k_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
| #define AR5416_EEP_MINOR_VER_2 0x2 |
Definition at line 133 of file eeprom.h.
Referenced by ath9k_hw_4k_set_board_values(), ath9k_hw_4k_set_txpower(), ath9k_hw_def_set_board_values(), ath9k_hw_def_set_txpower(), ath9k_hw_set_4k_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
| #define AR5416_EEP_MINOR_VER_3 0x3 |
Definition at line 134 of file eeprom.h.
Referenced by ath9k_hw_4k_set_board_values(), ath9k_hw_4k_set_gain(), ath9k_hw_def_set_board_values(), and ath9k_hw_def_set_gain().
| #define AR5416_EEP_MINOR_VER_7 0x7 |
Definition at line 135 of file eeprom.h.
Referenced by ath9k_hw_4k_set_addac(), and ath9k_hw_def_set_addac().
| #define AR5416_EEP_MINOR_VER_9 0x9 |
| #define AR5416_EEP_MINOR_VER_16 0x10 |
Definition at line 137 of file eeprom.h.
Referenced by ath9k_hw_fill_cap_info().
| #define AR5416_EEP_MINOR_VER_17 0x11 |
Definition at line 138 of file eeprom.h.
Referenced by ar9280_20_hw_init_rxgain_ini().
| #define AR5416_EEP_MINOR_VER_19 0x13 |
Definition at line 139 of file eeprom.h.
Referenced by ar9280_20_hw_init_txgain_ini(), ath9k_hw_4k_get_eeprom(), ath9k_hw_def_get_eeprom(), and ath9k_hw_def_set_board_values().
| #define AR5416_EEP_MINOR_VER_20 0x14 |
Definition at line 140 of file eeprom.h.
Referenced by ath9k_hw_def_get_eeprom(), and ath9k_hw_def_set_board_values().
| #define AR5416_EEP_MINOR_VER_21 0x15 |
Definition at line 141 of file eeprom.h.
Referenced by ath9k_hw_def_get_eeprom().
| #define AR5416_EEP_MINOR_VER_22 0x16 |
Definition at line 142 of file eeprom.h.
Referenced by ath9k_hw_def_get_eeprom().
| #define AR5416_NUM_5G_CAL_PIERS 8 |
Definition at line 144 of file eeprom.h.
Referenced by ath9k_hw_set_def_power_cal_table().
| #define AR5416_NUM_2G_CAL_PIERS 4 |
Definition at line 145 of file eeprom.h.
Referenced by ath9k_hw_set_def_power_cal_table().
| #define AR5416_NUM_5G_20_TARGET_POWERS 8 |
Definition at line 146 of file eeprom.h.
Referenced by ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_5G_40_TARGET_POWERS 8 |
Definition at line 147 of file eeprom.h.
Referenced by ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 |
Definition at line 148 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_2G_20_TARGET_POWERS 4 |
Definition at line 149 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_2G_40_TARGET_POWERS 4 |
Definition at line 150 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_CTLS 24 |
Definition at line 151 of file eeprom.h.
Referenced by ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_BAND_EDGES 8 |
Definition at line 152 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
| #define AR5416_NUM_PD_GAINS 4 |
Definition at line 153 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_set_ar9287_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
| #define AR5416_PD_GAINS_IN_MASK 4 |
Definition at line 154 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
| #define AR5416_PD_GAIN_ICEPTS 5 |
Definition at line 155 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs().
| #define AR5416_NUM_PDADC_VALUES 128 |
Definition at line 156 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), ath9k_hw_set_def_power_cal_table(), and ath9k_olc_get_pdadcs().
| #define AR5416_BCHAN_UNUSED 0xFF |
Definition at line 157 of file eeprom.h.
Referenced by ar9003_hw_get_max_edge_power(), ar9287_eeprom_get_tx_gain_index(), ath9k_get_txgain_index(), ath9k_hw_fbin2freq(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_get_legacy_target_powers(), ath9k_hw_get_max_edge_power(), and ath9k_hw_get_target_powers().
| #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 |
Definition at line 158 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs().
| #define AR5416_MAX_CHAINS 3 |
Definition at line 159 of file eeprom.h.
Referenced by ar9002_hw_adc_dccal_collect(), ar9002_hw_adc_gaincal_collect(), ar9002_hw_iqcal_collect(), ar9002_hw_per_calibration(), ar9003_hw_iqcal_collect(), ath9k_hw_def_check_eeprom(), ath9k_hw_def_set_board_values(), ath9k_hw_loadnf(), ath9k_hw_reset_calibration(), ath9k_hw_set_def_power_cal_table(), and ath9k_hw_update_nfcal_hist_buffer().
| #define AR9300_MAX_CHAINS 3 |
| #define AR5416_PWR_TABLE_OFFSET_DB -5 |
Definition at line 161 of file eeprom.h.
Referenced by ath9k_adjust_pdadc_values(), ath9k_change_gain_boundary_setting(), ath9k_hw_4k_get_eeprom(), ath9k_hw_4k_set_txpower(), and ath9k_hw_def_get_eeprom().
| #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 |
Definition at line 164 of file eeprom.h.
Referenced by ar9280_20_hw_init_rxgain_ini().
| #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 |
Definition at line 165 of file eeprom.h.
Referenced by ar9280_20_hw_init_rxgain_ini().
| #define AR5416_EEP_RXGAIN_ORIG 2 |
| #define AR5416_EEP_TXGAIN_ORIGINAL 0 |
Definition at line 169 of file eeprom.h.
Referenced by ath9k_hw_4k_get_eeprom().
| #define AR5416_EEP_TXGAIN_HIGH_POWER 1 |
Definition at line 170 of file eeprom.h.
Referenced by ar9002_hw_init_mode_gain_regs(), ar9280_20_hw_init_txgain_ini(), and ar9285_hw_pa_cal().
| #define AR5416_EEP4K_START_LOC 64 |
| #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 |
Definition at line 173 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_cal_table().
| #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 |
| #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 |
| #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 |
| #define AR5416_EEP4K_NUM_CTLS 12 |
Definition at line 177 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_per_rate_table().
| #define AR5416_EEP4K_NUM_BAND_EDGES 4 |
Definition at line 178 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_per_rate_table().
| #define AR5416_EEP4K_NUM_PD_GAINS 2 |
Definition at line 179 of file eeprom.h.
Referenced by ath9k_hw_set_4k_power_cal_table().
| #define AR5416_EEP4K_MAX_CHAINS 1 |
Definition at line 180 of file eeprom.h.
Referenced by ath9k_hw_4k_check_eeprom(), and ath9k_hw_set_4k_power_cal_table().
| #define AR9280_TX_GAIN_TABLE_SIZE 22 |
Definition at line 182 of file eeprom.h.
Referenced by ar9002_olc_init(), ar9280_hw_olc_temp_compensation(), and ath9k_get_txgain_index().
| #define AR9287_EEP_VER 0xE |
Definition at line 184 of file eeprom.h.
Referenced by ath9k_hw_ar9287_check_eeprom().
| #define AR9287_EEP_VER_MINOR_MASK 0xFFF |
Definition at line 185 of file eeprom.h.
Referenced by ath9k_hw_ar9287_get_eeprom(), ath9k_hw_ar9287_set_txpower(), and ath9k_hw_set_ar9287_power_cal_table().
| #define AR9287_EEP_MINOR_VER_1 0x1 |
| #define AR9287_EEP_MINOR_VER_2 0x2 |
Definition at line 187 of file eeprom.h.
Referenced by ath9k_hw_ar9287_get_eeprom(), ath9k_hw_ar9287_set_txpower(), and ath9k_hw_set_ar9287_power_cal_table().
| #define AR9287_EEP_MINOR_VER_3 0x3 |
Definition at line 188 of file eeprom.h.
Referenced by ath9k_hw_ar9287_get_eeprom().
| #define AR9287_EEP_START_LOC 128 |
Definition at line 193 of file eeprom.h.
Referenced by __ath9k_hw_ar9287_fill_eeprom().
| #define AR9287_HTC_EEP_START_LOC 256 |
Definition at line 194 of file eeprom.h.
Referenced by __ath9k_hw_usb_ar9287_fill_eeprom().
| #define AR9287_NUM_2G_CAL_PIERS 3 |
Definition at line 195 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_cal_table().
| #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 |
Definition at line 196 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_per_rate_table().
| #define AR9287_NUM_2G_20_TARGET_POWERS 3 |
Definition at line 197 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_per_rate_table().
| #define AR9287_NUM_2G_40_TARGET_POWERS 3 |
Definition at line 198 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_per_rate_table().
| #define AR9287_NUM_CTLS 12 |
Definition at line 199 of file eeprom.h.
Referenced by ath9k_hw_set_ar9287_power_per_rate_table().
| #define AR9287_NUM_BAND_EDGES 4 |
| #define AR9287_PD_GAIN_ICEPTS 1 |
Definition at line 201 of file eeprom.h.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs().
| #define AR9287_EEPMISC_BIG_ENDIAN 0x01 |
| #define AR9287_EEPMISC_WOW 0x02 |
| #define AR9287_MAX_CHAINS 2 |
Definition at line 204 of file eeprom.h.
Referenced by ath9k_hw_ar9287_check_eeprom(), ath9k_hw_ar9287_set_board_values(), and ath9k_hw_set_ar9287_power_cal_table().
| #define AR9287_ANT_16S 32 |
| #define AR9287_DATA_SZ 32 |
| #define AR9287_PWR_TABLE_OFFSET_DB -5 |
Definition at line 209 of file eeprom.h.
Referenced by ath9k_hw_ar9287_set_txpower(), and ath9k_hw_set_ar9287_power_cal_table().
| #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) |
| #define CTL_EDGE_TPOWER | ( | _ctl | ) | ((_ctl) & 0x3f) |
Definition at line 213 of file eeprom.h.
Referenced by ar9003_hw_get_direct_edge_power(), ar9003_hw_get_indirect_edge_power(), and ath9k_hw_get_max_edge_power().
| #define CTL_EDGE_FLAGS | ( | _ctl | ) | (((_ctl) >> 6) & 0x03) |
Definition at line 214 of file eeprom.h.
Referenced by ar9003_hw_get_indirect_edge_power(), and ath9k_hw_get_max_edge_power().
| #define LNA_CTL_BUF_MODE BIT(0) |
| #define LNA_CTL_ISEL_LO BIT(1) |
| #define LNA_CTL_ISEL_HI BIT(2) |
| #define LNA_CTL_BUF_IN BIT(3) |
| #define LNA_CTL_FEM_BAND BIT(4) |
| #define LNA_CTL_LOCAL_BIAS BIT(5) |
Definition at line 221 of file eeprom.h.
Referenced by ath9k_hw_def_set_board_values().
| #define LNA_CTL_FORCE_XPA BIT(6) |
Definition at line 222 of file eeprom.h.
Referenced by ath9k_hw_def_set_board_values().
| #define LNA_CTL_USE_ANT1 BIT(7) |
| #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f |
Definition at line 446 of file eeprom.h.
Referenced by ath9k_hw_4k_set_board_values().
| #define ar5416_get_ntxchains | ( | _txchainmask | ) |
(((_txchainmask >> 2) & 1) + \
((_txchainmask >> 1) & 1) + (_txchainmask & 1))
Definition at line 706 of file eeprom.h.
Referenced by ar9003_hw_set_power_per_rate_table(), ath9k_hw_def_set_txpower(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), ath9k_hw_set_def_power_per_rate_table(), and ath9k_hw_update_regulatory_maxpower().
| enum eeprom_param |
Definition at line 225 of file eeprom.h.
{
EEP_NFTHRESH_5,
EEP_NFTHRESH_2,
EEP_MAC_MSW,
EEP_MAC_MID,
EEP_MAC_LSW,
EEP_REG_0,
EEP_REG_1,
EEP_OP_CAP,
EEP_OP_MODE,
EEP_RF_SILENT,
EEP_OB_5,
EEP_DB_5,
EEP_OB_2,
EEP_DB_2,
EEP_MINOR_REV,
EEP_TX_MASK,
EEP_RX_MASK,
EEP_FSTCLK_5G,
EEP_RXGAIN_TYPE,
EEP_OL_PWRCTRL,
EEP_TXGAIN_TYPE,
EEP_RC_CHAIN_MASK,
EEP_DAC_HPWR_5G,
EEP_FRAC_N_5G,
EEP_DEV_TYPE,
EEP_TEMPSENSE_SLOPE,
EEP_TEMPSENSE_SLOPE_PAL_ON,
EEP_PWR_TABLE_OFFSET,
EEP_DRIVE_STRENGTH,
EEP_INTERNAL_REGULATOR,
EEP_SWREG,
EEP_PAPRD,
EEP_MODAL_VER,
EEP_ANT_DIV_CTL1,
EEP_CHAIN_MASK_REDUCE
};
| enum ar5416_rates |
Definition at line 263 of file eeprom.h.
{
rate6mb, rate9mb, rate12mb, rate18mb,
rate24mb, rate36mb, rate48mb, rate54mb,
rate1l, rate2l, rate2s, rate5_5l,
rate5_5s, rate11l, rate11s, rateXr,
rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
Ar5416RateSize
};
| enum ath9k_hal_freq_band |
Definition at line 276 of file eeprom.h.
{
ATH9K_HAL_FREQ_BAND_5GHZ = 0,
ATH9K_HAL_FREQ_BAND_2GHZ = 1
};
| enum reg_ext_bitmap |
| REG_EXT_FCC_MIDBAND | |
| REG_EXT_JAPAN_MIDBAND | |
| REG_EXT_FCC_DFS_HT40 | |
| REG_EXT_JAPAN_NONDFS_HT40 | |
| REG_EXT_JAPAN_DFS_HT40 |
Definition at line 635 of file eeprom.h.
{
REG_EXT_FCC_MIDBAND = 0,
REG_EXT_JAPAN_MIDBAND = 1,
REG_EXT_FCC_DFS_HT40 = 2,
REG_EXT_JAPAN_NONDFS_HT40 = 3,
REG_EXT_JAPAN_DFS_HT40 = 4
};
| FILE_LICENCE | ( | BSD2 | ) |
| void ath9k_hw_analog_shift_regwrite | ( | struct ath_hw * | ah, |
| u32 | reg, | ||
| u32 | val | ||
| ) |
Definition at line 32 of file ath9k_eeprom.c.
References ath9k_ops_config::analog_shiftreg, ath_hw::config, REG_WRITE, and udelay().
Referenced by ath9k_hw_ar9287_set_board_values().
Definition at line 40 of file ath9k_eeprom.c.
References ath9k_ops_config::analog_shiftreg, ath_hw::config, REG_READ, REG_WRITE, and udelay().
Referenced by ar9002_olc_init(), ath9k_hw_4k_set_board_values(), ath9k_hw_ar9287_set_board_values(), and ath9k_hw_def_set_board_values().
| int16_t ath9k_hw_interpolate | ( | u16 | target, |
| u16 | srcLeft, | ||
| u16 | srcRight, | ||
| int16_t | targetLeft, | ||
| int16_t | targetRight | ||
| ) |
Definition at line 54 of file ath9k_eeprom.c.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_get_legacy_target_powers(), and ath9k_hw_get_target_powers().
| int ath9k_hw_get_lower_upper_index | ( | u8 | target, |
| u8 * | pList, | ||
| u16 | listSize, | ||
| u16 * | indexL, | ||
| u16 * | indexR | ||
| ) |
Definition at line 69 of file ath9k_eeprom.c.
References u16.
Referenced by ar9287_eeprom_get_tx_gain_index(), ath9k_get_txgain_index(), ath9k_hw_fill_vpd_table(), and ath9k_hw_get_gain_boundaries_pdadcs().
{
u16 i;
if (target <= pList[0]) {
*indexL = *indexR = 0;
return 1;
}
if (target >= pList[listSize - 1]) {
*indexL = *indexR = (u16) (listSize - 1);
return 1;
}
for (i = 0; i < listSize - 1; i++) {
if (pList[i] == target) {
*indexL = *indexR = i;
return 1;
}
if (target < pList[i + 1]) {
*indexL = i;
*indexR = (u16) (i + 1);
return 0;
}
}
return 0;
}
| int ath9k_hw_nvram_read | ( | struct ath_common * | common, |
| u32 | off, | ||
| u16 * | data | ||
| ) |
Definition at line 129 of file ath9k_eeprom.c.
References ath_common::bus_ops, and ath_bus_ops::eeprom_read.
Referenced by __ath9k_hw_4k_fill_eeprom(), __ath9k_hw_ar9287_fill_eeprom(), __ath9k_hw_def_fill_eeprom(), ar9300_eeprom_read_byte(), ar9300_eeprom_read_word(), ar9300_eeprom_restore_flash(), ath9k_hw_4k_check_eeprom(), ath9k_hw_ar9287_check_eeprom(), and ath9k_hw_def_check_eeprom().
{
return common->bus_ops->eeprom_read(common, off, data);
}
| void ath9k_hw_usb_gen_fill_eeprom | ( | struct ath_hw * | ah, |
| u16 * | eep_data, | ||
| int | eep_start_loc, | ||
| int | size | ||
| ) |
Definition at line 97 of file ath9k_eeprom.c.
References addr, AR5416_EEPROM_OFFSET, AR5416_EEPROM_S, data, REG_READ_MULTI, and size.
Referenced by __ath9k_hw_usb_4k_fill_eeprom(), __ath9k_hw_usb_ar9287_fill_eeprom(), and __ath9k_hw_usb_def_fill_eeprom().
{
int i = 0, j, addr;
u32 addrdata[8];
u32 data[8];
for (addr = 0; addr < size; addr++) {
addrdata[i] = AR5416_EEPROM_OFFSET +
((addr + eep_start_loc) << AR5416_EEPROM_S);
i++;
if (i == 8) {
REG_READ_MULTI(ah, addrdata, data, i);
for (j = 0; j < i; j++) {
*eep_data = data[j];
eep_data++;
}
i = 0;
}
}
if (i != 0) {
REG_READ_MULTI(ah, addrdata, data, i);
for (j = 0; j < i; j++) {
*eep_data = data[j];
eep_data++;
}
}
}
| void ath9k_hw_fill_vpd_table | ( | u8 | pwrMin, |
| u8 | pwrMax, | ||
| u8 * | pPwrList, | ||
| u8 * | pVpdList, | ||
| u16 | numIntercepts, | ||
| u8 * | pRetVpdList | ||
| ) |
Definition at line 134 of file ath9k_eeprom.c.
References ath9k_hw_get_lower_upper_index(), k, and u16.
Referenced by ath9k_hw_get_gain_boundaries_pdadcs().
{
u16 i, k;
u8 currPwr = pwrMin;
u16 idxL = 0, idxR = 0;
for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
numIntercepts, &(idxL),
&(idxR));
if (idxR < 1)
idxR = 1;
if (idxL == numIntercepts - 1)
idxL = (u16) (numIntercepts - 2);
if (pPwrList[idxL] == pPwrList[idxR])
k = pVpdList[idxL];
else
k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
(pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
(pPwrList[idxR] - pPwrList[idxL]));
pRetVpdList[i] = (u8) k;
currPwr += 2;
}
}
| void ath9k_hw_get_legacy_target_powers | ( | struct ath_hw * | ah, |
| struct ath9k_channel * | chan, | ||
| struct cal_target_power_leg * | powInfo, | ||
| u16 | numChannels, | ||
| struct cal_target_power_leg * | pNewPower, | ||
| u16 | numRates, | ||
| int | isExtTarget | ||
| ) |
Definition at line 161 of file ath9k_eeprom.c.
References AR5416_BCHAN_UNUSED, ath9k_hw_fbin2freq(), ath9k_hw_get_channel_centers(), ath9k_hw_interpolate(), chan_centers::ctl_center, chan_centers::ext_center, IS_CHAN_2GHZ, tPow2x, and cal_target_power_leg::tPow2x.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
{
struct chan_centers centers;
u16 clo, chi;
int i;
int matchIndex = -1, lowIndex = -1;
u16 freq;
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
IS_CHAN_2GHZ(chan))) {
matchIndex = 0;
} else {
for (i = 0; (i < numChannels) &&
(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
IS_CHAN_2GHZ(chan))) {
matchIndex = i;
break;
} else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
IS_CHAN_2GHZ(chan)) && i > 0 &&
freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
IS_CHAN_2GHZ(chan))) {
lowIndex = i - 1;
break;
}
}
if ((matchIndex == -1) && (lowIndex == -1))
matchIndex = i - 1;
}
if (matchIndex != -1) {
*pNewPower = powInfo[matchIndex];
} else {
clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
IS_CHAN_2GHZ(chan));
chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
IS_CHAN_2GHZ(chan));
for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] =
(u8)ath9k_hw_interpolate(freq, clo, chi,
powInfo[lowIndex].tPow2x[i],
powInfo[lowIndex + 1].tPow2x[i]);
}
}
}
| void ath9k_hw_get_target_powers | ( | struct ath_hw * | ah, |
| struct ath9k_channel * | chan, | ||
| struct cal_target_power_ht * | powInfo, | ||
| u16 | numChannels, | ||
| struct cal_target_power_ht * | pNewPower, | ||
| u16 | numRates, | ||
| int | isHt40Target | ||
| ) |
Definition at line 216 of file ath9k_eeprom.c.
References AR5416_BCHAN_UNUSED, ath9k_hw_fbin2freq(), ath9k_hw_get_channel_centers(), ath9k_hw_interpolate(), chan_centers::ctl_center, IS_CHAN_2GHZ, chan_centers::synth_center, tPow2x, and cal_target_power_ht::tPow2x.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
{
struct chan_centers centers;
u16 clo, chi;
int i;
int matchIndex = -1, lowIndex = -1;
u16 freq;
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
freq = isHt40Target ? centers.synth_center : centers.ctl_center;
if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
matchIndex = 0;
} else {
for (i = 0; (i < numChannels) &&
(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
IS_CHAN_2GHZ(chan))) {
matchIndex = i;
break;
} else
if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
IS_CHAN_2GHZ(chan)) && i > 0 &&
freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
IS_CHAN_2GHZ(chan))) {
lowIndex = i - 1;
break;
}
}
if ((matchIndex == -1) && (lowIndex == -1))
matchIndex = i - 1;
}
if (matchIndex != -1) {
*pNewPower = powInfo[matchIndex];
} else {
clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
IS_CHAN_2GHZ(chan));
chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
IS_CHAN_2GHZ(chan));
for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
clo, chi,
powInfo[lowIndex].tPow2x[i],
powInfo[lowIndex + 1].tPow2x[i]);
}
}
}
| u16 ath9k_hw_get_max_edge_power | ( | u16 | freq, |
| struct cal_ctl_edges * | pRdEdgesPower, | ||
| int | is2GHz, | ||
| int | num_band_edges | ||
| ) |
Definition at line 271 of file ath9k_eeprom.c.
References AR5416_BCHAN_UNUSED, ath9k_hw_fbin2freq(), CTL_EDGE_FLAGS, CTL_EDGE_TPOWER, and MAX_RATE_POWER.
Referenced by ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().
{
u16 twiceMaxEdgePower = MAX_RATE_POWER;
int i;
for (i = 0; (i < num_band_edges) &&
(pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
break;
} else if ((i > 0) &&
(freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
is2GHz))) {
if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
is2GHz) < freq &&
CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
twiceMaxEdgePower =
CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
}
break;
}
}
return twiceMaxEdgePower;
}
| void ath9k_hw_update_regulatory_maxpower | ( | struct ath_hw * | ah | ) |
Definition at line 298 of file ath9k_eeprom.c.
References ar5416_get_ntxchains, ath9k_hw_regulatory(), DBG2, INCREASE_MAXPOW_BY_THREE_CHAIN, INCREASE_MAXPOW_BY_TWO_CHAIN, ath_regulatory::max_power_level, and ath_hw::txchainmask.
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
switch (ar5416_get_ntxchains(ah->txchainmask)) {
case 1:
break;
case 2:
regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
break;
case 3:
regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
break;
default:
DBG2("ath9k: "
"Invalid chainmask configuration\n");
break;
}
}
| int ath9k_hw_eeprom_init | ( | struct ath_hw * | ah | ) |
Definition at line 530 of file ath9k_eeprom.c.
References AR_SREV_9271, AR_SREV_9285, AR_SREV_9287, AR_SREV_9300_20_OR_LATER, eeprom_ops::check_eeprom, eep_4k_ops, eep_ar9287_ops, eep_ar9300_ops, eep_def_ops, ath_hw::eep_ops, EIO, eeprom_ops::fill_eeprom, and status.
Referenced by ath9k_hw_post_init().
{
int status;
if (AR_SREV_9300_20_OR_LATER(ah))
ah->eep_ops = &eep_ar9300_ops;
else if (AR_SREV_9287(ah)) {
ah->eep_ops = &eep_ar9287_ops;
} else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
ah->eep_ops = &eep_4k_ops;
} else {
ah->eep_ops = &eep_def_ops;
}
if (!ah->eep_ops->fill_eeprom(ah))
return -EIO;
status = ah->eep_ops->check_eeprom(ah);
return status;
}
| void ath9k_hw_get_gain_boundaries_pdadcs | ( | struct ath_hw * | ah, |
| struct ath9k_channel * | chan, | ||
| void * | pRawDataSet, | ||
| u8 * | bChans, | ||
| u16 | availPiers, | ||
| u16 | tPdGainOverlap, | ||
| u16 * | pPdGainBoundaries, | ||
| u8 * | pPDADCValues, | ||
| u16 | numXpdGains | ||
| ) |
Definition at line 318 of file ath9k_eeprom.c.
References AR5416_BCHAN_UNUSED, AR5416_MAX_PWR_RANGE_IN_HALF_DB, AR5416_NUM_PD_GAINS, AR5416_NUM_PDADC_VALUES, AR5416_PD_GAIN_ICEPTS, AR5416_PD_GAINS_IN_MASK, AR9287_PD_GAIN_ICEPTS, AR_SREV_5416_20_OR_LATER, AR_SREV_9271, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9287, ath9k_hw_fill_vpd_table(), ath9k_hw_get_channel_centers(), ath9k_hw_get_lower_upper_index(), ath9k_hw_interpolate(), FREQ2FBIN, IS_CHAN_2GHZ, k, max, MAX_RATE_POWER, memset(), min, cal_data_per_freq::pwrPdg, cal_data_per_freq_4k::pwrPdg, cal_data_per_freq_ar9287::pwrPdg, ss, chan_centers::synth_center, u16, cal_data_per_freq::vpdPdg, cal_data_per_freq_4k::vpdPdg, and cal_data_per_freq_ar9287::vpdPdg.
Referenced by ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
{
int i, j, k;
int16_t ss;
u16 idxL = 0, idxR = 0, numPiers;
static u8 vpdTableL[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
static u8 vpdTableR[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
static u8 vpdTableI[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
u8 minPwrT4[AR5416_NUM_PD_GAINS];
u8 maxPwrT4[AR5416_NUM_PD_GAINS];
int16_t vpdStep;
int16_t tmpVal;
u16 sizeCurrVpdTable, maxIndex, tgtIndex;
int match;
int16_t minDelta = 0;
struct chan_centers centers;
int pdgain_boundary_default;
struct cal_data_per_freq *data_def = pRawDataSet;
struct cal_data_per_freq_4k *data_4k = pRawDataSet;
struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
int eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
int intercepts;
if (AR_SREV_9287(ah))
intercepts = AR9287_PD_GAIN_ICEPTS;
else
intercepts = AR5416_PD_GAIN_ICEPTS;
memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
for (numPiers = 0; numPiers < availPiers; numPiers++) {
if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
break;
}
match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
IS_CHAN_2GHZ(chan)),
bChans, numPiers, &idxL, &idxR);
if (match) {
if (AR_SREV_9287(ah)) {
for (i = 0; i < numXpdGains; i++) {
minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
maxPwrT4[i] = data_9287[idxL].pwrPdg[i][intercepts - 1];
ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
data_9287[idxL].pwrPdg[i],
data_9287[idxL].vpdPdg[i],
intercepts,
vpdTableI[i]);
}
} else if (eeprom_4k) {
for (i = 0; i < numXpdGains; i++) {
minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
maxPwrT4[i] = data_4k[idxL].pwrPdg[i][intercepts - 1];
ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
data_4k[idxL].pwrPdg[i],
data_4k[idxL].vpdPdg[i],
intercepts,
vpdTableI[i]);
}
} else {
for (i = 0; i < numXpdGains; i++) {
minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
maxPwrT4[i] = data_def[idxL].pwrPdg[i][intercepts - 1];
ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
data_def[idxL].pwrPdg[i],
data_def[idxL].vpdPdg[i],
intercepts,
vpdTableI[i]);
}
}
} else {
for (i = 0; i < numXpdGains; i++) {
if (AR_SREV_9287(ah)) {
pVpdL = data_9287[idxL].vpdPdg[i];
pPwrL = data_9287[idxL].pwrPdg[i];
pVpdR = data_9287[idxR].vpdPdg[i];
pPwrR = data_9287[idxR].pwrPdg[i];
} else if (eeprom_4k) {
pVpdL = data_4k[idxL].vpdPdg[i];
pPwrL = data_4k[idxL].pwrPdg[i];
pVpdR = data_4k[idxR].vpdPdg[i];
pPwrR = data_4k[idxR].pwrPdg[i];
} else {
pVpdL = data_def[idxL].vpdPdg[i];
pPwrL = data_def[idxL].pwrPdg[i];
pVpdR = data_def[idxR].vpdPdg[i];
pPwrR = data_def[idxR].pwrPdg[i];
}
minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
maxPwrT4[i] =
min(pPwrL[intercepts - 1],
pPwrR[intercepts - 1]);
ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
pPwrL, pVpdL,
intercepts,
vpdTableL[i]);
ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
pPwrR, pVpdR,
intercepts,
vpdTableR[i]);
for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
vpdTableI[i][j] =
(u8)(ath9k_hw_interpolate((u16)
FREQ2FBIN(centers.
synth_center,
IS_CHAN_2GHZ
(chan)),
bChans[idxL], bChans[idxR],
vpdTableL[i][j], vpdTableR[i][j]));
}
}
}
k = 0;
for (i = 0; i < numXpdGains; i++) {
if (i == (numXpdGains - 1))
pPdGainBoundaries[i] =
(u16)(maxPwrT4[i] / 2);
else
pPdGainBoundaries[i] =
(u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
pPdGainBoundaries[i] =
min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
minDelta = pPdGainBoundaries[0] - 23;
pPdGainBoundaries[0] = 23;
} else {
minDelta = 0;
}
if (i == 0) {
if (AR_SREV_9280_20_OR_LATER(ah))
ss = (int16_t)(0 - (minPwrT4[i] / 2));
else
ss = 0;
} else {
ss = (int16_t)((pPdGainBoundaries[i - 1] -
(minPwrT4[i] / 2)) -
tPdGainOverlap + 1 + minDelta);
}
vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
ss++;
}
sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
(minPwrT4[i] / 2));
maxIndex = (tgtIndex < sizeCurrVpdTable) ?
tgtIndex : sizeCurrVpdTable;
while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
pPDADCValues[k++] = vpdTableI[i][ss++];
}
vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
vpdTableI[i][sizeCurrVpdTable - 2]);
vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
if (tgtIndex >= maxIndex) {
while ((ss <= tgtIndex) &&
(k < (AR5416_NUM_PDADC_VALUES - 1))) {
tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
(ss - maxIndex + 1) * vpdStep));
pPDADCValues[k++] = (u8)((tmpVal > 255) ?
255 : tmpVal);
ss++;
}
}
}
if (eeprom_4k)
pdgain_boundary_default = 58;
else
pdgain_boundary_default = pPdGainBoundaries[i - 1];
while (i < AR5416_PD_GAINS_IN_MASK) {
pPdGainBoundaries[i] = pdgain_boundary_default;
i++;
}
while (k < AR5416_NUM_PDADC_VALUES) {
pPDADCValues[k] = pPDADCValues[k - 1];
k++;
}
}
| struct eeprom_ops eep_def_ops |
Definition at line 1341 of file ath9k_eeprom_def.c.
Referenced by ath9k_hw_eeprom_init().
| struct eeprom_ops eep_4k_ops |
Definition at line 1068 of file ath9k_eeprom_4k.c.
Referenced by ath9k_hw_eeprom_init().
| struct eeprom_ops eep_ar9287_ops |
Definition at line 713 of file eeprom.h.
Referenced by ath9k_hw_eeprom_init().
| struct eeprom_ops eep_ar9300_ops |
Definition at line 4995 of file ath9k_ar9003_eeprom.c.
Referenced by ath9k_hw_eeprom_init().
1.7.6.1