iPXE
hw.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef HW_H
00021 #define HW_H
00022 
00023 FILE_LICENCE ( BSD2 );
00024 
00025 #include <errno.h>
00026 
00027 #include "mac.h"
00028 #include "ani.h"
00029 #include "eeprom.h"
00030 #include "calib.h"
00031 #include "reg.h"
00032 #include "phy.h"
00033 
00034 #include "../regd.h"
00035 
00036 /* Keep all ath9k files under one errfile ID */
00037 #undef ERRFILE
00038 #define ERRFILE ERRFILE_ath9k
00039 
00040 #define ATHEROS_VENDOR_ID       0x168c
00041 
00042 #define AR5416_DEVID_PCI        0x0023
00043 #define AR5416_DEVID_PCIE       0x0024
00044 #define AR9160_DEVID_PCI        0x0027
00045 #define AR9280_DEVID_PCI        0x0029
00046 #define AR9280_DEVID_PCIE       0x002a
00047 #define AR9285_DEVID_PCIE       0x002b
00048 #define AR2427_DEVID_PCIE       0x002c
00049 #define AR9287_DEVID_PCI        0x002d
00050 #define AR9287_DEVID_PCIE       0x002e
00051 #define AR9300_DEVID_PCIE       0x0030
00052 #define AR9300_DEVID_AR9340     0x0031
00053 #define AR9300_DEVID_AR9485_PCIE 0x0032
00054 
00055 #define AR5416_AR9100_DEVID     0x000b
00056 
00057 #define AR_SUBVENDOR_ID_NOG     0x0e11
00058 #define AR_SUBVENDOR_ID_NEW_A   0x7065
00059 #define AR5416_MAGIC            0x19641014
00060 
00061 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
00062 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
00063 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
00064 
00065 #define AR9300_NUM_BT_WEIGHTS   4
00066 #define AR9300_NUM_WLAN_WEIGHTS 4
00067 
00068 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
00069 
00070 #define ATH_DEFAULT_NOISE_FLOOR -95
00071 
00072 #define ATH9K_RSSI_BAD                  -128
00073 
00074 #define ATH9K_NUM_CHANNELS      38
00075 
00076 /* Register read/write primitives */
00077 #define REG_WRITE(_ah, _reg, _val) \
00078         (_ah)->reg_ops.write((_ah), (_val), (_reg))
00079 
00080 #define REG_READ(_ah, _reg) \
00081         (_ah)->reg_ops.read((_ah), (_reg))
00082 
00083 #define REG_READ_MULTI(_ah, _addr, _val, _cnt)          \
00084         (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
00085 
00086 #define REG_RMW(_ah, _reg, _set, _clr) \
00087         (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
00088 
00089 #define ENABLE_REGWRITE_BUFFER(_ah)                                     \
00090         do {                                                            \
00091                 if ((_ah)->reg_ops.enable_write_buffer) \
00092                         (_ah)->reg_ops.enable_write_buffer((_ah)); \
00093         } while (0)
00094 
00095 #define REGWRITE_BUFFER_FLUSH(_ah)                                      \
00096         do {                                                            \
00097                 if ((_ah)->reg_ops.write_flush)         \
00098                         (_ah)->reg_ops.write_flush((_ah));      \
00099         } while (0)
00100 
00101 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
00102 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
00103 #define REG_RMW_FIELD(_a, _r, _f, _v) \
00104         REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
00105 #define REG_READ_FIELD(_a, _r, _f) \
00106         (((REG_READ(_a, _r) & _f) >> _f##_S))
00107 #define REG_SET_BIT(_a, _r, _f) \
00108         REG_RMW(_a, _r, (_f), 0)
00109 #define REG_CLR_BIT(_a, _r, _f) \
00110         REG_RMW(_a, _r, 0, (_f))
00111 
00112 #define DO_DELAY(x) do {                                        \
00113                 if (((++(x) % 64) == 0) &&                      \
00114                     (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
00115                         != ATH_USB))                            \
00116                         udelay(1);                              \
00117         } while (0)
00118 
00119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
00120         ath9k_hw_write_array(ah, iniarray, column, &(regWr))
00121 
00122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
00123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
00124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
00125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
00126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
00127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
00128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
00129 
00130 #define AR_GPIOD_MASK               0x00001FFF
00131 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
00132 
00133 #define BASE_ACTIVATE_DELAY         100
00134 #define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
00135 #define COEF_SCALE_S                24
00136 #define HT40_CHANNEL_CENTER_SHIFT   10
00137 
00138 #define ATH9K_ANTENNA0_CHAINMASK    0x1
00139 #define ATH9K_ANTENNA1_CHAINMASK    0x2
00140 
00141 #define ATH9K_NUM_DMA_DEBUG_REGS    8
00142 #define ATH9K_NUM_QUEUES            10
00143 
00144 #define MAX_RATE_POWER              63
00145 #define AH_WAIT_TIMEOUT             100000 /* (us) */
00146 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
00147 #define AH_TIME_QUANTUM             10
00148 #define AR_KEYTABLE_SIZE            128
00149 #define POWER_UP_TIME               10000
00150 #define SPUR_RSSI_THRESH            40
00151 
00152 #define CAB_TIMEOUT_VAL             10
00153 #define BEACON_TIMEOUT_VAL          10
00154 #define MIN_BEACON_TIMEOUT_VAL      1
00155 #define SLEEP_SLOP                  3
00156 
00157 #define INIT_CONFIG_STATUS          0x00000000
00158 #define INIT_RSSI_THR               0x00000700
00159 #define INIT_BCON_CNTRL_REG         0x00000000
00160 
00161 #define TU_TO_USEC(_tu)             ((_tu) << 10)
00162 
00163 #define ATH9K_HW_RX_HP_QDEPTH   16
00164 #define ATH9K_HW_RX_LP_QDEPTH   128
00165 
00166 #define PAPRD_GAIN_TABLE_ENTRIES    32
00167 #define PAPRD_TABLE_SZ              24
00168 
00169 enum ath_hw_txq_subtype {
00170         ATH_TXQ_AC_BE = 0,
00171 };
00172 
00173 enum ath_ini_subsys {
00174         ATH_INI_PRE = 0,
00175         ATH_INI_CORE,
00176         ATH_INI_POST,
00177         ATH_INI_NUM_SPLIT,
00178 };
00179 
00180 enum ath9k_hw_caps {
00181         ATH9K_HW_CAP_HT                         = BIT(0),
00182         ATH9K_HW_CAP_RFSILENT                   = BIT(1),
00183         ATH9K_HW_CAP_CST                        = BIT(2),
00184         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
00185         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
00186         ATH9K_HW_CAP_EDMA                       = BIT(6),
00187         ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
00188         ATH9K_HW_CAP_LDPC                       = BIT(8),
00189         ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
00190         ATH9K_HW_CAP_SGI_20                     = BIT(10),
00191         ATH9K_HW_CAP_PAPRD                      = BIT(11),
00192         ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
00193         ATH9K_HW_CAP_2GHZ                       = BIT(13),
00194         ATH9K_HW_CAP_5GHZ                       = BIT(14),
00195         ATH9K_HW_CAP_APM                        = BIT(15),
00196 };
00197 
00198 struct ath9k_hw_capabilities {
00199         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
00200         u16 rts_aggr_limit;
00201         u8 tx_chainmask;
00202         u8 rx_chainmask;
00203         u8 max_txchains;
00204         u8 max_rxchains;
00205         u8 num_gpio_pins;
00206         u8 rx_hp_qdepth;
00207         u8 rx_lp_qdepth;
00208         u8 rx_status_len;
00209         u8 tx_desc_len;
00210         u8 txs_len;
00211         u16 pcie_lcr_offset;
00212         int pcie_lcr_extsync_en;
00213 };
00214 
00215 struct ath9k_ops_config {
00216         int dma_beacon_response_time;
00217         int sw_beacon_response_time;
00218         int additional_swba_backoff;
00219         int ack_6mb;
00220         u32 cwm_ignore_extcca;
00221         u8 pcie_powersave_enable;
00222         int pcieSerDesWrite;
00223         u8 pcie_clock_req;
00224         u32 pcie_waen;
00225         u8 analog_shiftreg;
00226         u8 paprd_disable;
00227         u32 ofdm_trig_low;
00228         u32 ofdm_trig_high;
00229         u32 cck_trig_high;
00230         u32 cck_trig_low;
00231         u32 enable_ani;
00232         int serialize_regmode;
00233         int rx_intr_mitigation;
00234         int tx_intr_mitigation;
00235 #define SPUR_DISABLE            0
00236 #define SPUR_ENABLE_IOCTL       1
00237 #define SPUR_ENABLE_EEPROM      2
00238 #define AR_SPUR_5413_1          1640
00239 #define AR_SPUR_5413_2          1200
00240 #define AR_NO_SPUR              0x8000
00241 #define AR_BASE_FREQ_2GHZ       2300
00242 #define AR_BASE_FREQ_5GHZ       4900
00243 #define AR_SPUR_FEEQ_BOUND_HT40 19
00244 #define AR_SPUR_FEEQ_BOUND_HT20 10
00245         int spurmode;
00246         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
00247         u8 max_txtrig_level;
00248         u16 ani_poll_interval; /* ANI poll interval in ms */
00249 };
00250 
00251 enum ath9k_int {
00252         ATH9K_INT_RX = 0x00000001,
00253         ATH9K_INT_RXDESC = 0x00000002,
00254         ATH9K_INT_RXHP = 0x00000001,
00255         ATH9K_INT_RXLP = 0x00000002,
00256         ATH9K_INT_RXNOFRM = 0x00000008,
00257         ATH9K_INT_RXEOL = 0x00000010,
00258         ATH9K_INT_RXORN = 0x00000020,
00259         ATH9K_INT_TX = 0x00000040,
00260         ATH9K_INT_TXDESC = 0x00000080,
00261         ATH9K_INT_TIM_TIMER = 0x00000100,
00262         ATH9K_INT_BB_WATCHDOG = 0x00000400,
00263         ATH9K_INT_TXURN = 0x00000800,
00264         ATH9K_INT_MIB = 0x00001000,
00265         ATH9K_INT_RXPHY = 0x00004000,
00266         ATH9K_INT_RXKCM = 0x00008000,
00267         ATH9K_INT_SWBA = 0x00010000,
00268         ATH9K_INT_BMISS = 0x00040000,
00269         ATH9K_INT_BNR = 0x00100000,
00270         ATH9K_INT_TIM = 0x00200000,
00271         ATH9K_INT_DTIM = 0x00400000,
00272         ATH9K_INT_DTIMSYNC = 0x00800000,
00273         ATH9K_INT_GPIO = 0x01000000,
00274         ATH9K_INT_CABEND = 0x02000000,
00275         ATH9K_INT_TSFOOR = 0x04000000,
00276         ATH9K_INT_GENTIMER = 0x08000000,
00277         ATH9K_INT_CST = 0x10000000,
00278         ATH9K_INT_GTT = 0x20000000,
00279         ATH9K_INT_FATAL = 0x40000000,
00280         ATH9K_INT_GLOBAL = 0x80000000,
00281         ATH9K_INT_BMISC = ATH9K_INT_TIM |
00282                 ATH9K_INT_DTIM |
00283                 ATH9K_INT_DTIMSYNC |
00284                 ATH9K_INT_TSFOOR |
00285                 ATH9K_INT_CABEND,
00286         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
00287                 ATH9K_INT_RXDESC |
00288                 ATH9K_INT_RXEOL |
00289                 ATH9K_INT_RXORN |
00290                 ATH9K_INT_TXURN |
00291                 ATH9K_INT_TXDESC |
00292                 ATH9K_INT_MIB |
00293                 ATH9K_INT_RXPHY |
00294                 ATH9K_INT_RXKCM |
00295                 ATH9K_INT_SWBA |
00296                 ATH9K_INT_BMISS |
00297                 ATH9K_INT_GPIO,
00298         ATH9K_INT_NOCARD = 0xffffffff
00299 };
00300 
00301 #define CHANNEL_CW_INT    0x00002
00302 #define CHANNEL_CCK       0x00020
00303 #define CHANNEL_OFDM      0x00040
00304 #define CHANNEL_2GHZ      0x00080
00305 #define CHANNEL_5GHZ      0x00100
00306 #define CHANNEL_PASSIVE   0x00200
00307 #define CHANNEL_DYN       0x00400
00308 #define CHANNEL_HALF      0x04000
00309 #define CHANNEL_QUARTER   0x08000
00310 #define CHANNEL_HT20      0x10000
00311 #define CHANNEL_HT40PLUS  0x20000
00312 #define CHANNEL_HT40MINUS 0x40000
00313 
00314 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
00315 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
00316 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
00317 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
00318 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
00319 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
00320 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
00321 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
00322 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
00323 #define CHANNEL_ALL                             \
00324         (CHANNEL_OFDM|                          \
00325          CHANNEL_CCK|                           \
00326          CHANNEL_2GHZ |                         \
00327          CHANNEL_5GHZ |                         \
00328          CHANNEL_HT20 |                         \
00329          CHANNEL_HT40PLUS |                     \
00330          CHANNEL_HT40MINUS)
00331 
00332 struct ath9k_hw_cal_data {
00333         u16 channel;
00334         u32 channelFlags;
00335         int32_t CalValid;
00336         int8_t iCoff;
00337         int8_t qCoff;
00338         int paprd_done;
00339         int nfcal_pending;
00340         int nfcal_interference;
00341         u16 small_signal_gain[AR9300_MAX_CHAINS];
00342         u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
00343         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
00344 };
00345 
00346 struct ath9k_channel {
00347         struct net80211_channel *chan;
00348         struct ar5416AniState ani;
00349         u16 channel;
00350         u32 channelFlags;
00351         u32 chanmode;
00352         s16 noisefloor;
00353 };
00354 
00355 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
00356        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
00357        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
00358        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
00359 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
00360 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
00361 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
00362 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
00363 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
00364 #define IS_CHAN_A_FAST_CLOCK(_ah, _c)                   \
00365         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
00366          ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
00367 
00368 /* These macros check chanmode and not channelFlags */
00369 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
00370 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
00371                           ((_c)->chanmode == CHANNEL_G_HT20))
00372 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
00373                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
00374                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
00375                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
00376 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
00377 
00378 enum ath9k_power_mode {
00379         ATH9K_PM_AWAKE = 0,
00380         ATH9K_PM_FULL_SLEEP,
00381         ATH9K_PM_NETWORK_SLEEP,
00382         ATH9K_PM_UNDEFINED
00383 };
00384 
00385 enum ath9k_tp_scale {
00386         ATH9K_TP_SCALE_MAX = 0,
00387         ATH9K_TP_SCALE_50,
00388         ATH9K_TP_SCALE_25,
00389         ATH9K_TP_SCALE_12,
00390         ATH9K_TP_SCALE_MIN
00391 };
00392 
00393 enum ser_reg_mode {
00394         SER_REG_MODE_OFF = 0,
00395         SER_REG_MODE_ON = 1,
00396         SER_REG_MODE_AUTO = 2,
00397 };
00398 
00399 enum ath9k_rx_qtype {
00400         ATH9K_RX_QUEUE_HP,
00401         ATH9K_RX_QUEUE_LP,
00402         ATH9K_RX_QUEUE_MAX,
00403 };
00404 
00405 struct ath9k_beacon_state {
00406         u32 bs_nexttbtt;
00407         u32 bs_nextdtim;
00408         u32 bs_intval;
00409 #define ATH9K_BEACON_PERIOD       0x0000ffff
00410 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
00411         u32 bs_dtimperiod;
00412         u16 bs_cfpperiod;
00413         u16 bs_cfpmaxduration;
00414         u32 bs_cfpnext;
00415         u16 bs_timoffset;
00416         u16 bs_bmissthreshold;
00417         u32 bs_sleepduration;
00418         u32 bs_tsfoor_threshold;
00419 };
00420 
00421 struct chan_centers {
00422         u16 synth_center;
00423         u16 ctl_center;
00424         u16 ext_center;
00425 };
00426 
00427 enum {
00428         ATH9K_RESET_POWER_ON,
00429         ATH9K_RESET_WARM,
00430         ATH9K_RESET_COLD,
00431 };
00432 
00433 struct ath9k_hw_version {
00434         u32 magic;
00435         u16 devid;
00436         u16 subvendorid;
00437         u32 macVersion;
00438         u16 macRev;
00439         u16 phyRev;
00440         u16 analog5GhzRev;
00441         u16 analog2GhzRev;
00442         u16 subsysid;
00443         enum ath_usb_dev usbdev;
00444 };
00445 
00446 /* Generic TSF timer definitions */
00447 
00448 #define ATH_MAX_GEN_TIMER       16
00449 
00450 #define AR_GENTMR_BIT(_index)   (1 << (_index))
00451 
00452 /*
00453  * Using de Bruijin sequence to look up 1's index in a 32 bit number
00454  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
00455  */
00456 #define debruijn32 0x077CB531U
00457 
00458 struct ath_gen_timer_configuration {
00459         u32 next_addr;
00460         u32 period_addr;
00461         u32 mode_addr;
00462         u32 mode_mask;
00463 };
00464 
00465 struct ath_gen_timer {
00466         void (*trigger)(void *arg);
00467         void (*overflow)(void *arg);
00468         void *arg;
00469         u8 index;
00470 };
00471 
00472 struct ath_gen_timer_table {
00473         u32 gen_timer_index[32];
00474         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
00475         union {
00476                 unsigned long timer_bits;
00477                 u16 val;
00478         } timer_mask;
00479 };
00480 
00481 struct ath_hw_antcomb_conf {
00482         u8 main_lna_conf;
00483         u8 alt_lna_conf;
00484         u8 fast_div_bias;
00485         u8 main_gaintb;
00486         u8 alt_gaintb;
00487         int lna1_lna2_delta;
00488         u8 div_group;
00489 };
00490 
00491 /**
00492  * struct ath_hw_radar_conf - radar detection initialization parameters
00493  *
00494  * @pulse_inband: threshold for checking the ratio of in-band power
00495  *      to total power for short radar pulses (half dB steps)
00496  * @pulse_inband_step: threshold for checking an in-band power to total
00497  *      power ratio increase for short radar pulses (half dB steps)
00498  * @pulse_height: threshold for detecting the beginning of a short
00499  *      radar pulse (dB step)
00500  * @pulse_rssi: threshold for detecting if a short radar pulse is
00501  *      gone (dB step)
00502  * @pulse_maxlen: maximum pulse length (0.8 us steps)
00503  *
00504  * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
00505  * @radar_inband: threshold for checking the ratio of in-band power
00506  *      to total power for long radar pulses (half dB steps)
00507  * @fir_power: threshold for detecting the end of a long radar pulse (dB)
00508  *
00509  * @ext_channel: enable extension channel radar detection
00510  */
00511 struct ath_hw_radar_conf {
00512         unsigned int pulse_inband;
00513         unsigned int pulse_inband_step;
00514         unsigned int pulse_height;
00515         unsigned int pulse_rssi;
00516         unsigned int pulse_maxlen;
00517 
00518         unsigned int radar_rssi;
00519         unsigned int radar_inband;
00520         int fir_power;
00521 
00522         int ext_channel;
00523 };
00524 
00525 /**
00526  * struct ath_hw_private_ops - callbacks used internally by hardware code
00527  *
00528  * This structure contains private callbacks designed to only be used internally
00529  * by the hardware core.
00530  *
00531  * @init_cal_settings: setup types of calibrations supported
00532  * @init_cal: starts actual calibration
00533  *
00534  * @init_mode_regs: Initializes mode registers
00535  * @init_mode_gain_regs: Initialize TX/RX gain registers
00536  *
00537  * @rf_set_freq: change frequency
00538  * @spur_mitigate_freq: spur mitigation
00539  * @rf_alloc_ext_banks:
00540  * @rf_free_ext_banks:
00541  * @set_rf_regs:
00542  * @compute_pll_control: compute the PLL control value to use for
00543  *      AR_RTC_PLL_CONTROL for a given channel
00544  * @setup_calibration: set up calibration
00545  * @iscal_supported: used to query if a type of calibration is supported
00546  *
00547  * @ani_cache_ini_regs: cache the values for ANI from the initial
00548  *      register settings through the register initialization.
00549  */
00550 struct ath_hw_private_ops {
00551         /* Calibration ops */
00552         void (*init_cal_settings)(struct ath_hw *ah);
00553         int (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
00554 
00555         void (*init_mode_regs)(struct ath_hw *ah);
00556         void (*init_mode_gain_regs)(struct ath_hw *ah);
00557         void (*setup_calibration)(struct ath_hw *ah,
00558                                   struct ath9k_cal_list *currCal);
00559 
00560         /* PHY ops */
00561         int (*rf_set_freq)(struct ath_hw *ah,
00562                            struct ath9k_channel *chan);
00563         void (*spur_mitigate_freq)(struct ath_hw *ah,
00564                                    struct ath9k_channel *chan);
00565         int (*rf_alloc_ext_banks)(struct ath_hw *ah);
00566         void (*rf_free_ext_banks)(struct ath_hw *ah);
00567         int (*set_rf_regs)(struct ath_hw *ah,
00568                             struct ath9k_channel *chan,
00569                             u16 modesIndex);
00570         void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
00571         void (*init_bb)(struct ath_hw *ah,
00572                         struct ath9k_channel *chan);
00573         int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
00574         void (*olc_init)(struct ath_hw *ah);
00575         void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
00576         void (*mark_phy_inactive)(struct ath_hw *ah);
00577         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
00578         int (*rfbus_req)(struct ath_hw *ah);
00579         void (*rfbus_done)(struct ath_hw *ah);
00580         void (*restore_chainmask)(struct ath_hw *ah);
00581         void (*set_diversity)(struct ath_hw *ah, int value);
00582         u32 (*compute_pll_control)(struct ath_hw *ah,
00583                                    struct ath9k_channel *chan);
00584         int (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
00585                             int param);
00586         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
00587         void (*set_radar_params)(struct ath_hw *ah,
00588                                  struct ath_hw_radar_conf *conf);
00589 
00590         /* ANI */
00591         void (*ani_cache_ini_regs)(struct ath_hw *ah);
00592 };
00593 
00594 /**
00595  * struct ath_hw_ops - callbacks used by hardware code and driver code
00596  *
00597  * This structure contains callbacks designed to to be used internally by
00598  * hardware code and also by the lower level driver.
00599  *
00600  * @config_pci_powersave:
00601  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
00602  */
00603 struct ath_hw_ops {
00604         void (*config_pci_powersave)(struct ath_hw *ah,
00605                                      int restore,
00606                                      int power_off);
00607         void (*rx_enable)(struct ath_hw *ah);
00608         void (*set_desc_link)(void *ds, u32 link);
00609         void (*get_desc_link)(void *ds, u32 **link);
00610         int (*calibrate)(struct ath_hw *ah,
00611                           struct ath9k_channel *chan,
00612                           u8 rxchainmask,
00613                           int longcal);
00614         int (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
00615         void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
00616                             int is_firstseg, int is_is_lastseg,
00617                             const void *ds0, u32 buf_addr,
00618                             unsigned int qcu);
00619         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
00620                            struct ath_tx_status *ts);
00621         void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
00622                               u32 pktLen, enum ath9k_pkt_type type,
00623                               u32 txPower, u32 keyIx,
00624                               enum ath9k_key_type keyType,
00625                               u32 flags);
00626         void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
00627                                 void *lastds,
00628                                 u32 durUpdateEn, u32 rtsctsRate,
00629                                 u32 rtsctsDuration,
00630                                 struct ath9k_11n_rate_series series[],
00631                                 u32 nseries, u32 flags);
00632         void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
00633                                   u32 aggrLen);
00634         void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
00635                                    u32 numDelims);
00636         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
00637         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
00638         void (*set_clrdmask)(struct ath_hw *ah, void *ds, int val);
00639         void (*antdiv_comb_conf_get)(struct ath_hw *ah,
00640                         struct ath_hw_antcomb_conf *antconf);
00641         void (*antdiv_comb_conf_set)(struct ath_hw *ah,
00642                         struct ath_hw_antcomb_conf *antconf);
00643 
00644 };
00645 
00646 struct ath_nf_limits {
00647         s16 max;
00648         s16 min;
00649         s16 nominal;
00650 };
00651 
00652 /* ah_flags */
00653 #define AH_USE_EEPROM   0x1
00654 #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
00655 
00656 struct ath_hw {
00657         struct ath_ops reg_ops;
00658 
00659         struct net80211_device *dev;
00660         struct ath_common common;
00661         struct ath9k_hw_version hw_version;
00662         struct ath9k_ops_config config;
00663         struct ath9k_hw_capabilities caps;
00664         struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
00665         struct ath9k_channel *curchan;
00666 
00667         union {
00668                 struct ar5416_eeprom_def def;
00669                 struct ar5416_eeprom_4k map4k;
00670                 struct ar9287_eeprom map9287;
00671                 struct ar9300_eeprom ar9300_eep;
00672         } eeprom;
00673         const struct eeprom_ops *eep_ops;
00674 
00675         int sw_mgmt_crypto;
00676         int is_pciexpress;
00677         int is_monitoring;
00678         int need_an_top2_fixup;
00679         u16 tx_trig_level;
00680 
00681         u32 nf_regs[6];
00682         struct ath_nf_limits nf_2g;
00683         struct ath_nf_limits nf_5g;
00684         u16 rfsilent;
00685         u32 rfkill_gpio;
00686         u32 rfkill_polarity;
00687         u32 ah_flags;
00688 
00689         int htc_reset_init;
00690 
00691         enum ath9k_power_mode power_mode;
00692 
00693         struct ath9k_hw_cal_data *caldata;
00694         struct ath9k_pacal_info pacal_info;
00695         struct ar5416Stats stats;
00696         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
00697 
00698         int16_t curchan_rad_index;
00699         int ah_ier;
00700         enum ath9k_int imask;
00701         u32 imrs2_reg;
00702         u32 txok_interrupt_mask;
00703         u32 txerr_interrupt_mask;
00704         u32 txdesc_interrupt_mask;
00705         u32 txeol_interrupt_mask;
00706         u32 txurn_interrupt_mask;
00707         int chip_fullsleep;
00708         u32 atim_window;
00709 
00710         /* Calibration */
00711         u32 supp_cals;
00712         struct ath9k_cal_list iq_caldata;
00713         struct ath9k_cal_list adcgain_caldata;
00714         struct ath9k_cal_list adcdc_caldata;
00715         struct ath9k_cal_list tempCompCalData;
00716         struct ath9k_cal_list *cal_list;
00717         struct ath9k_cal_list *cal_list_last;
00718         struct ath9k_cal_list *cal_list_curr;
00719 #define totalPowerMeasI meas0.unsign
00720 #define totalPowerMeasQ meas1.unsign
00721 #define totalIqCorrMeas meas2.sign
00722 #define totalAdcIOddPhase  meas0.unsign
00723 #define totalAdcIEvenPhase meas1.unsign
00724 #define totalAdcQOddPhase  meas2.unsign
00725 #define totalAdcQEvenPhase meas3.unsign
00726 #define totalAdcDcOffsetIOddPhase  meas0.sign
00727 #define totalAdcDcOffsetIEvenPhase meas1.sign
00728 #define totalAdcDcOffsetQOddPhase  meas2.sign
00729 #define totalAdcDcOffsetQEvenPhase meas3.sign
00730         union {
00731                 u32 unsign[AR5416_MAX_CHAINS];
00732                 int32_t sign[AR5416_MAX_CHAINS];
00733         } meas0;
00734         union {
00735                 u32 unsign[AR5416_MAX_CHAINS];
00736                 int32_t sign[AR5416_MAX_CHAINS];
00737         } meas1;
00738         union {
00739                 u32 unsign[AR5416_MAX_CHAINS];
00740                 int32_t sign[AR5416_MAX_CHAINS];
00741         } meas2;
00742         union {
00743                 u32 unsign[AR5416_MAX_CHAINS];
00744                 int32_t sign[AR5416_MAX_CHAINS];
00745         } meas3;
00746         u16 cal_samples;
00747 
00748         u32 sta_id1_defaults;
00749         u32 misc_mode;
00750         enum {
00751                 AUTO_32KHZ,
00752                 USE_32KHZ,
00753                 DONT_USE_32KHZ,
00754         } enable_32kHz_clock;
00755 
00756         /* Private to hardware code */
00757         struct ath_hw_private_ops private_ops;
00758         /* Accessed by the lower level driver */
00759         struct ath_hw_ops ops;
00760 
00761         /* Used to program the radio on non single-chip devices */
00762         u32 *analogBank0Data;
00763         u32 *analogBank1Data;
00764         u32 *analogBank2Data;
00765         u32 *analogBank3Data;
00766         u32 *analogBank6Data;
00767         u32 *analogBank6TPCData;
00768         u32 *analogBank7Data;
00769         u32 *addac5416_21;
00770         u32 *bank6Temp;
00771 
00772         u8 txpower_limit;
00773         int coverage_class;
00774         u32 slottime;
00775         u32 globaltxtimeout;
00776 
00777         /* ANI */
00778         u32 proc_phyerr;
00779         u32 aniperiod;
00780         int totalSizeDesired[5];
00781         int coarse_high[5];
00782         int coarse_low[5];
00783         int firpwr[5];
00784         enum ath9k_ani_cmd ani_function;
00785 
00786         u32 intr_txqs;
00787         u8 txchainmask;
00788         u8 rxchainmask;
00789 
00790         struct ath_hw_radar_conf radar_conf;
00791 
00792         u32 originalGain[22];
00793         int initPDADC;
00794         int PDADCdelta;
00795         int led_pin;
00796         u32 gpio_mask;
00797         u32 gpio_val;
00798 
00799         struct ar5416IniArray iniModes;
00800         struct ar5416IniArray iniCommon;
00801         struct ar5416IniArray iniBank0;
00802         struct ar5416IniArray iniBB_RfGain;
00803         struct ar5416IniArray iniBank1;
00804         struct ar5416IniArray iniBank2;
00805         struct ar5416IniArray iniBank3;
00806         struct ar5416IniArray iniBank6;
00807         struct ar5416IniArray iniBank6TPC;
00808         struct ar5416IniArray iniBank7;
00809         struct ar5416IniArray iniAddac;
00810         struct ar5416IniArray iniPcieSerdes;
00811         struct ar5416IniArray iniPcieSerdesLowPower;
00812         struct ar5416IniArray iniModesAdditional;
00813         struct ar5416IniArray iniModesAdditional_40M;
00814         struct ar5416IniArray iniModesRxGain;
00815         struct ar5416IniArray iniModesTxGain;
00816         struct ar5416IniArray iniModes_9271_1_0_only;
00817         struct ar5416IniArray iniCckfirNormal;
00818         struct ar5416IniArray iniCckfirJapan2484;
00819         struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
00820         struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
00821         struct ar5416IniArray iniModes_9271_ANI_reg;
00822         struct ar5416IniArray iniModes_high_power_tx_gain_9271;
00823         struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
00824 
00825         struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
00826         struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
00827         struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
00828         struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
00829 
00830         u32 intr_gen_timer_trigger;
00831         u32 intr_gen_timer_thresh;
00832         struct ath_gen_timer_table hw_gen_timers;
00833 
00834         struct ar9003_txs *ts_ring;
00835         void *ts_start;
00836         u32 ts_paddr_start;
00837         u32 ts_paddr_end;
00838         u16 ts_tail;
00839         u8 ts_size;
00840 
00841         unsigned int paprd_target_power;
00842         unsigned int paprd_training_power;
00843         unsigned int paprd_ratemask;
00844         unsigned int paprd_ratemask_ht40;
00845         int paprd_table_write_done;
00846         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
00847         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
00848         /*
00849          * Store the permanent value of Reg 0x4004in WARegVal
00850          * so we dont have to R/M/W. We should not be reading
00851          * this register when in sleep states.
00852          */
00853         u32 WARegVal;
00854 
00855         /* Enterprise mode cap */
00856         u32 ent_mode;
00857 
00858         int is_clk_25mhz;
00859 };
00860 
00861 struct ath_bus_ops {
00862         enum ath_bus_type ath_bus_type;
00863         void (*read_cachesize)(struct ath_common *common, int *csz);
00864         int (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
00865         void (*bt_coex_prep)(struct ath_common *common);
00866         void (*extn_synch_en)(struct ath_common *common);
00867 };
00868 
00869 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
00870 {
00871         return &ah->common;
00872 }
00873 
00874 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
00875 {
00876         return &(ath9k_hw_common(ah)->regulatory);
00877 }
00878 
00879 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
00880 {
00881         return &ah->private_ops;
00882 }
00883 
00884 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
00885 {
00886         return &ah->ops;
00887 }
00888 
00889 static inline u8 get_streams(int mask)
00890 {
00891         return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
00892 }
00893 
00894 /* Initialization, Detach, Reset */
00895 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
00896 void ath9k_hw_deinit(struct ath_hw *ah);
00897 int ath9k_hw_init(struct ath_hw *ah);
00898 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
00899                    struct ath9k_hw_cal_data *caldata, int bChannelChange);
00900 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
00901 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
00902 
00903 /* GPIO / RFKILL / Antennae */
00904 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
00905 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
00906 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
00907                          u32 ah_signal_type);
00908 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
00909 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
00910 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
00911 
00912 /* General Operation */
00913 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
00914 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
00915                           int column, unsigned int *writecnt);
00916 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
00917 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
00918                            u8 phy, int kbps,
00919                            u32 frameLen, u16 rateix, int shortPreamble);
00920 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
00921                                   struct ath9k_channel *chan,
00922                                   struct chan_centers *centers);
00923 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
00924 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
00925 int ath9k_hw_phy_disable(struct ath_hw *ah);
00926 int ath9k_hw_disable(struct ath_hw *ah);
00927 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test);
00928 void ath9k_hw_setopmode(struct ath_hw *ah);
00929 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
00930 void ath9k_hw_setbssidmask(struct ath_hw *ah);
00931 void ath9k_hw_write_associd(struct ath_hw *ah);
00932 void ath9k_hw_init_global_settings(struct ath_hw *ah);
00933 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
00934 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
00935 int ath9k_hw_check_alive(struct ath_hw *ah);
00936 
00937 int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
00938 
00939 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
00940 
00941 /* HTC */
00942 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
00943 
00944 /* PHY */
00945 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
00946                                    u32 *coef_mantissa, u32 *coef_exponent);
00947 
00948 /*
00949  * Code Specific to AR5008, AR9001 or AR9002,
00950  * we stuff these here to avoid callbacks for AR9003.
00951  */
00952 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
00953 int ar9002_hw_rf_claim(struct ath_hw *ah);
00954 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
00955 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
00956 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
00957 
00958 /*
00959  * Code specific to AR9003, we stuff these here to avoid callbacks
00960  * for older families
00961  */
00962 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
00963 
00964 /* Hardware family op attach helpers */
00965 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
00966 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
00967 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
00968 
00969 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
00970 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
00971 
00972 void ar9002_hw_attach_ops(struct ath_hw *ah);
00973 void ar9003_hw_attach_ops(struct ath_hw *ah);
00974 
00975 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
00976 /*
00977  * ANI work can be shared between all families but a next
00978  * generation implementation of ANI will be used only for AR9003 only
00979  * for now as the other families still need to be tested with the same
00980  * next generation ANI. Feel free to start testing it though for the
00981  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
00982  */
00983 extern int modparam_force_new_ani;
00984 void ath9k_ani_reset(struct ath_hw *ah, int is_scanning);
00985 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
00986 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
00987 
00988 #define ATH_PCIE_CAP_LINK_CTRL  0x70
00989 #define ATH_PCIE_CAP_LINK_L0S   1
00990 #define ATH_PCIE_CAP_LINK_L1    2
00991 
00992 #define ATH9K_CLOCK_RATE_CCK            22
00993 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
00994 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
00995 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
00996 
00997 #endif