iPXE
eepro.c
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00001 #ifdef ALLMULTI
00002 #error multicast support is not yet implemented
00003 #endif
00004 /**************************************************************************
00005 Etherboot -  BOOTP/TFTP Bootstrap Program
00006 Intel EEPRO/10 NIC driver for Etherboot
00007 Adapted from Linux eepro.c from kernel 2.2.17
00008 
00009 This board accepts a 32 pin EEPROM (29C256), however a test with a
00010 27C010 shows that this EPROM also works in the socket, but it's not clear
00011 how repeatably. The two top address pins appear to be held low, thus
00012 the bottom 32kB of the 27C010 is visible in the CPU's address space.
00013 To be sure you could put 4 copies of the code in the 27C010, then
00014 it doesn't matter whether the extra lines are held low or high, just
00015 hopefully not floating as CMOS chips don't like floating inputs.
00016 
00017 Be careful with seating the EPROM as the socket on my board actually
00018 has 34 pins, the top row of 2 are not used.
00019 ***************************************************************************/
00020 
00021 /*
00022 
00023  timlegge       2005-05-18      remove the relocation changes cards that 
00024                                 write directly to the hardware don't need it
00025 */
00026 
00027 /*
00028  * This program is free software; you can redistribute it and/or
00029  * modify it under the terms of the GNU General Public License as
00030  * published by the Free Software Foundation; either version 2 of the
00031  * License, or (at your option) any later version.
00032  *
00033  * This program is distributed in the hope that it will be useful, but
00034  * WITHOUT ANY WARRANTY; without even the implied warranty of
00035  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00036  * General Public License for more details.
00037  *
00038  * You should have received a copy of the GNU General Public License
00039  * along with this program; if not, write to the Free Software
00040  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00041  * 02110-1301, USA.
00042  */
00043 
00044 FILE_LICENCE ( GPL2_OR_LATER );
00045 
00046 #include "etherboot.h"
00047 #include <errno.h>
00048 #include "nic.h"
00049 #include <ipxe/isa.h>
00050 #include <ipxe/ethernet.h>
00051 
00052 /* Different 82595 chips */
00053 #define LAN595          0
00054 #define LAN595TX        1
00055 #define LAN595FX        2
00056 #define LAN595FX_10ISA  3
00057 
00058 #define SLOW_DOWN       inb(0x80);
00059 
00060 /* The station (ethernet) address prefix, used for IDing the board. */
00061 #define SA_ADDR0 0x00   /* Etherexpress Pro/10 */
00062 #define SA_ADDR1 0xaa
00063 #define SA_ADDR2 0x00
00064 
00065 #define GetBit(x,y) ((x & (1<<y))>>y)
00066 
00067 /* EEPROM Word 0: */
00068 #define ee_PnP       0  /* Plug 'n Play enable bit */
00069 #define ee_Word1     1  /* Word 1? */
00070 #define ee_BusWidth  2  /* 8/16 bit */
00071 #define ee_FlashAddr 3  /* Flash Address */
00072 #define ee_FlashMask 0x7   /* Mask */
00073 #define ee_AutoIO    6  /* */
00074 #define ee_reserved0 7  /* =0! */
00075 #define ee_Flash     8  /* Flash there? */
00076 #define ee_AutoNeg   9  /* Auto Negotiation enabled? */
00077 #define ee_IO0       10 /* IO Address LSB */
00078 #define ee_IO0Mask   0x /*...*/
00079 #define ee_IO1       15 /* IO MSB */
00080 
00081 /* EEPROM Word 1: */
00082 #define ee_IntSel    0   /* Interrupt */
00083 #define ee_IntMask   0x7
00084 #define ee_LI        3   /* Link Integrity 0= enabled */
00085 #define ee_PC        4   /* Polarity Correction 0= enabled */
00086 #define ee_TPE_AUI   5   /* PortSelection 1=TPE */
00087 #define ee_Jabber    6   /* Jabber prevention 0= enabled */
00088 #define ee_AutoPort  7   /* Auto Port Selection 1= Disabled */
00089 #define ee_SMOUT     8   /* SMout Pin Control 0= Input */
00090 #define ee_PROM      9   /* Flash EPROM / PROM 0=Flash */
00091 #define ee_reserved1 10  /* .. 12 =0! */
00092 #define ee_AltReady  13  /* Alternate Ready, 0=normal */
00093 #define ee_reserved2 14  /* =0! */
00094 #define ee_Duplex    15
00095 
00096 /* Word2,3,4: */
00097 #define ee_IA5       0 /*bit start for individual Addr Byte 5 */
00098 #define ee_IA4       8 /*bit start for individual Addr Byte 5 */
00099 #define ee_IA3       0 /*bit start for individual Addr Byte 5 */
00100 #define ee_IA2       8 /*bit start for individual Addr Byte 5 */
00101 #define ee_IA1       0 /*bit start for individual Addr Byte 5 */
00102 #define ee_IA0       8 /*bit start for individual Addr Byte 5 */
00103 
00104 /* Word 5: */
00105 #define ee_BNC_TPE   0 /* 0=TPE */
00106 #define ee_BootType  1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
00107 #define ee_BootTypeMask 0x3 
00108 #define ee_NumConn   3  /* Number of Connections 0= One or Two */
00109 #define ee_FlashSock 4  /* Presence of Flash Socket 0= Present */
00110 #define ee_PortTPE   5
00111 #define ee_PortBNC   6
00112 #define ee_PortAUI   7
00113 #define ee_PowerMgt  10 /* 0= disabled */
00114 #define ee_CP        13 /* Concurrent Processing */
00115 #define ee_CPMask    0x7
00116 
00117 /* Word 6: */
00118 #define ee_Stepping  0 /* Stepping info */
00119 #define ee_StepMask  0x0F
00120 #define ee_BoardID   4 /* Manucaturer Board ID, reserved */
00121 #define ee_BoardMask 0x0FFF
00122 
00123 /* Word 7: */
00124 #define ee_INT_TO_IRQ 0 /* int to IRQ Mapping  = 0x1EB8 for Pro/10+ */
00125 #define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
00126 
00127 /*..*/
00128 #define ee_SIZE 0x40 /* total EEprom Size */
00129 #define ee_Checksum 0xBABA /* initial and final value for adding checksum */
00130 
00131 
00132 /* Card identification via EEprom:   */
00133 #define ee_addr_vendor 0x10  /* Word offset for EISA Vendor ID */
00134 #define ee_addr_id 0x11      /* Word offset for Card ID */
00135 #define ee_addr_SN 0x12      /* Serial Number */
00136 #define ee_addr_CRC_8 0x14   /* CRC over last thee Bytes */
00137 
00138 
00139 #define ee_vendor_intel0 0x25  /* Vendor ID Intel */
00140 #define ee_vendor_intel1 0xD4
00141 #define ee_id_eepro10p0 0x10   /* ID for eepro/10+ */
00142 #define ee_id_eepro10p1 0x31
00143 
00144 /* now this section could be used by both boards: the oldies and the ee10:
00145  * ee10 uses tx buffer before of rx buffer and the oldies the inverse.
00146  * (aris)
00147  */
00148 #define RAM_SIZE        0x8000
00149 
00150 #define RCV_HEADER      8
00151 #define RCV_DEFAULT_RAM 0x6000
00152 #define RCV_RAM         rcv_ram
00153 
00154 static unsigned rcv_ram = RCV_DEFAULT_RAM;
00155 
00156 #define XMT_HEADER      8
00157 #define XMT_RAM         (RAM_SIZE - RCV_RAM)
00158 
00159 #define XMT_START       ((rcv_start + RCV_RAM) % RAM_SIZE)
00160 
00161 #define RCV_LOWER_LIMIT (rcv_start >> 8)
00162 #define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
00163 #define XMT_LOWER_LIMIT (XMT_START >> 8)
00164 #define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
00165 
00166 #define RCV_START_PRO   0x00
00167 #define RCV_START_10    XMT_RAM
00168                                         /* by default the old driver */
00169 static unsigned rcv_start = RCV_START_PRO;
00170 
00171 #define RCV_DONE        0x0008
00172 #define RX_OK           0x2000
00173 #define RX_ERROR        0x0d81
00174 
00175 #define TX_DONE_BIT     0x0080
00176 #define CHAIN_BIT       0x8000
00177 #define XMT_STATUS      0x02
00178 #define XMT_CHAIN       0x04
00179 #define XMT_COUNT       0x06
00180 
00181 #define BANK0_SELECT    0x00            
00182 #define BANK1_SELECT    0x40            
00183 #define BANK2_SELECT    0x80            
00184 
00185 /* Bank 0 registers */
00186 #define COMMAND_REG     0x00    /* Register 0 */
00187 #define MC_SETUP        0x03
00188 #define XMT_CMD         0x04
00189 #define DIAGNOSE_CMD    0x07
00190 #define RCV_ENABLE_CMD  0x08
00191 #define RCV_DISABLE_CMD 0x0a
00192 #define STOP_RCV_CMD    0x0b
00193 #define RESET_CMD       0x0e
00194 #define POWER_DOWN_CMD  0x18
00195 #define RESUME_XMT_CMD  0x1c
00196 #define SEL_RESET_CMD   0x1e
00197 #define STATUS_REG      0x01    /* Register 1 */
00198 #define RX_INT          0x02
00199 #define TX_INT          0x04
00200 #define EXEC_STATUS     0x30
00201 #define ID_REG          0x02    /* Register 2   */
00202 #define R_ROBIN_BITS    0xc0    /* round robin counter */
00203 #define ID_REG_MASK     0x2c
00204 #define ID_REG_SIG      0x24
00205 #define AUTO_ENABLE     0x10
00206 #define INT_MASK_REG    0x03    /* Register 3   */
00207 #define RX_STOP_MASK    0x01
00208 #define RX_MASK         0x02
00209 #define TX_MASK         0x04
00210 #define EXEC_MASK       0x08
00211 #define ALL_MASK        0x0f
00212 #define IO_32_BIT       0x10
00213 #define RCV_BAR         0x04    /* The following are word (16-bit) registers */
00214 #define RCV_STOP        0x06
00215 
00216 #define XMT_BAR_PRO     0x0a
00217 #define XMT_BAR_10      0x0b
00218 static unsigned xmt_bar = XMT_BAR_PRO;
00219 
00220 #define HOST_ADDRESS_REG        0x0c
00221 #define IO_PORT         0x0e
00222 #define IO_PORT_32_BIT  0x0c
00223 
00224 /* Bank 1 registers */
00225 #define REG1    0x01
00226 #define WORD_WIDTH      0x02
00227 #define INT_ENABLE      0x80
00228 #define INT_NO_REG      0x02
00229 #define RCV_LOWER_LIMIT_REG     0x08
00230 #define RCV_UPPER_LIMIT_REG     0x09
00231 
00232 #define XMT_LOWER_LIMIT_REG_PRO 0x0a
00233 #define XMT_UPPER_LIMIT_REG_PRO 0x0b
00234 #define XMT_LOWER_LIMIT_REG_10  0x0b
00235 #define XMT_UPPER_LIMIT_REG_10  0x0a
00236 static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
00237 static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
00238 
00239 /* Bank 2 registers */
00240 #define XMT_Chain_Int   0x20    /* Interrupt at the end of the transmit chain */
00241 #define XMT_Chain_ErrStop       0x40 /* Interrupt at the end of the chain even if there are errors */
00242 #define RCV_Discard_BadFrame    0x80 /* Throw bad frames away, and continue to receive others */
00243 #define REG2            0x02
00244 #define PRMSC_Mode      0x01
00245 #define Multi_IA        0x20
00246 #define REG3            0x03
00247 #define TPE_BIT         0x04
00248 #define BNC_BIT         0x20
00249 #define REG13           0x0d
00250 #define FDX             0x00
00251 #define A_N_ENABLE      0x02
00252         
00253 #define I_ADD_REG0      0x04
00254 #define I_ADD_REG1      0x05
00255 #define I_ADD_REG2      0x06
00256 #define I_ADD_REG3      0x07
00257 #define I_ADD_REG4      0x08
00258 #define I_ADD_REG5      0x09
00259 
00260 #define EEPROM_REG_PRO  0x0a
00261 #define EEPROM_REG_10   0x0b
00262 static unsigned eeprom_reg = EEPROM_REG_PRO;
00263 
00264 #define EESK 0x01
00265 #define EECS 0x02
00266 #define EEDI 0x04
00267 #define EEDO 0x08
00268 
00269 /* The horrible routine to read a word from the serial EEPROM. */
00270 /* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
00271 
00272 /* The delay between EEPROM clock transitions. */
00273 #define eeprom_delay() { udelay(40); }
00274 #define EE_READ_CMD (6 << 6)
00275 
00276 /* do a full reset; data sheet asks for 250us delay */
00277 #define eepro_full_reset(ioaddr)        outb(RESET_CMD, ioaddr); udelay(255);
00278 
00279 /* do a nice reset */
00280 #define eepro_sel_reset(ioaddr) \
00281   do {  \
00282     outb ( SEL_RESET_CMD, ioaddr ); \
00283     (void) SLOW_DOWN; \
00284     (void) SLOW_DOWN; \
00285   } while (0)
00286 
00287 /* clear all interrupts */
00288 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
00289 
00290 /* enable rx */
00291 #define eepro_en_rx(ioaddr)     outb(RCV_ENABLE_CMD, ioaddr)
00292 
00293 /* disable rx */
00294 #define eepro_dis_rx(ioaddr)    outb(RCV_DISABLE_CMD, ioaddr)
00295 
00296 /* switch bank */
00297 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
00298 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
00299 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
00300 
00301 static unsigned int     rx_start, tx_start;
00302 static int              tx_last;
00303 static unsigned int     tx_end;
00304 static int              eepro = 0;
00305 static unsigned int     mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
00306 
00307 /**************************************************************************
00308 RESET - Reset adapter
00309 ***************************************************************************/
00310 static void eepro_reset(struct nic *nic)
00311 {
00312         int             temp_reg, i;
00313 
00314         /* put the card in its initial state */
00315         eepro_sw2bank2(nic->ioaddr);    /* be careful, bank2 now */
00316         temp_reg = inb(nic->ioaddr + eeprom_reg);
00317         DBG("Stepping %d\n", temp_reg >> 5);
00318         if (temp_reg & 0x10)    /* check the TurnOff Enable bit */
00319                 outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);
00320         for (i = 0; i < ETH_ALEN; i++)  /* fill the MAC address */
00321                 outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);
00322         temp_reg = inb(nic->ioaddr + REG1);
00323         /* setup Transmit Chaining and discard bad RCV frames */
00324         outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop
00325                 | RCV_Discard_BadFrame, nic->ioaddr + REG1);
00326         temp_reg = inb(nic->ioaddr + REG2);             /* match broadcast */
00327         outb(temp_reg | 0x14, nic->ioaddr + REG2);
00328         temp_reg = inb(nic->ioaddr + REG3);
00329         outb(temp_reg & 0x3F, nic->ioaddr + REG3);      /* clear test mode */
00330         /* set the receiving mode */
00331         eepro_sw2bank1(nic->ioaddr);    /* be careful, bank1 now */
00332         /* initialise the RCV and XMT upper and lower limits */
00333         outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG);
00334         outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG);
00335         outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg);
00336         outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg);
00337         eepro_sw2bank0(nic->ioaddr);    /* Switch back to bank 0 */
00338         eepro_clear_int(nic->ioaddr);
00339         /* Initialise RCV */
00340         outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
00341         outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
00342         /* Make sure 1st poll won't find a valid packet header */
00343         outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
00344         outw(0,                      nic->ioaddr + IO_PORT);
00345         /* Intialise XMT */
00346         outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
00347         eepro_sel_reset(nic->ioaddr);
00348         tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8);
00349         tx_last = 0;
00350         eepro_en_rx(nic->ioaddr);
00351 }
00352 
00353 /**************************************************************************
00354 POLL - Wait for a frame
00355 ***************************************************************************/
00356 static int eepro_poll(struct nic *nic, int retrieve)
00357 {
00358         unsigned int    rcv_car = rx_start;
00359         unsigned int    rcv_event, rcv_status, rcv_next_frame, rcv_size;
00360 
00361         /* return true if there's an ethernet packet ready to read */
00362         /* nic->packet should contain data on return */
00363         /* nic->packetlen should contain length of data */
00364 #if     0
00365         if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0)
00366                 return (0);
00367         outb(0x40, nic->ioaddr + STATUS_REG);
00368 #endif
00369         outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
00370         rcv_event = inw(nic->ioaddr + IO_PORT);
00371         if (rcv_event != RCV_DONE)
00372                 return (0);
00373 
00374         /* FIXME: I'm guessing this might not work with this card, since
00375            it looks like once a rcv_event is started it must be completed.
00376            maybe there's another way. */
00377         if ( ! retrieve ) return 1;
00378 
00379         rcv_status = inw(nic->ioaddr + IO_PORT);
00380         rcv_next_frame = inw(nic->ioaddr + IO_PORT);
00381         rcv_size = inw(nic->ioaddr + IO_PORT);
00382 #if     0
00383         printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
00384                 inb(nic->ioaddr + STATUS_REG));
00385 #endif
00386         if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
00387                 printf("Receive error %hX\n", rcv_status);
00388                 return (0);
00389         }
00390         rcv_size &= 0x3FFF;
00391         insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
00392 #if     0
00393 {
00394         int i;
00395         for (i = 0; i < 48; i++) {
00396                 printf("%hhX", nic->packet[i]);
00397                 putchar(i % 16 == 15 ? '\n' : ' ');
00398         }
00399 }
00400 #endif
00401         nic->packetlen = rcv_size;
00402         rcv_car  = (rx_start + RCV_HEADER + rcv_size);
00403         rx_start = rcv_next_frame;
00404 /* 
00405         hex_dump(rcv_car, nic->packetlen); 
00406 */
00407 
00408         if (rcv_car == 0)
00409                 rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
00410         outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
00411         return (1);
00412 }
00413 
00414 /**************************************************************************
00415 TRANSMIT - Transmit a frame
00416 ***************************************************************************/
00417 static void eepro_transmit(
00418         struct nic *nic,
00419         const char *d,                  /* Destination */
00420         unsigned int t,                 /* Type */
00421         unsigned int s,                 /* size */
00422         const char *p)                  /* Packet */
00423 {
00424         unsigned int    status, tx_available, last, end, length;
00425         unsigned short  type;
00426         int             boguscount = 20;
00427 
00428         length = s + ETH_HLEN;
00429         if (tx_end > tx_start)
00430                 tx_available = XMT_RAM - (tx_end - tx_start);
00431         else if (tx_end < tx_start)
00432                 tx_available = tx_start - tx_end;
00433         else
00434                 tx_available = XMT_RAM;
00435         assert ( length <= tx_available );
00436         last = tx_end;
00437         end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
00438         if (end >= (XMT_UPPER_LIMIT << 8)) {
00439                 last = (XMT_LOWER_LIMIT << 8);
00440                 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
00441         }
00442         outw(last, nic->ioaddr + HOST_ADDRESS_REG);
00443         outw(XMT_CMD, nic->ioaddr + IO_PORT);
00444         outw(0, nic->ioaddr + IO_PORT);
00445         outw(end, nic->ioaddr + IO_PORT);
00446         outw(length, nic->ioaddr + IO_PORT);
00447         outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2);
00448         outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
00449         type = htons(t);
00450         outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2);
00451         outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1);
00452         /* A dummy read to flush the DRAM write pipeline */
00453         status = inw(nic->ioaddr + IO_PORT);
00454         outw(last, nic->ioaddr + xmt_bar);
00455         outb(XMT_CMD, nic->ioaddr);
00456         tx_start = last;
00457         tx_last = last;
00458         tx_end = end;
00459 #if     0
00460         printf("%d %d\n", tx_start, tx_end);
00461 #endif
00462         while (boguscount > 0) {
00463                 if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
00464                         udelay(40);
00465                         boguscount--;
00466                         continue;
00467                 }
00468                 if ((status & 0x2000) == 0) {
00469                         DBG("Transmit status %hX\n", status);
00470                 }
00471         }
00472 }
00473 
00474 /**************************************************************************
00475 DISABLE - Turn off ethernet interface
00476 ***************************************************************************/
00477 static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) {
00478         eepro_sw2bank0(nic->ioaddr);    /* Switch to bank 0 */
00479         /* Flush the Tx and disable Rx */
00480         outb(STOP_RCV_CMD, nic->ioaddr);
00481         tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
00482         tx_last = 0;
00483         /* Reset the 82595 */
00484         eepro_full_reset(nic->ioaddr);
00485 }
00486 
00487 /**************************************************************************
00488 DISABLE - Enable, Disable, or Force interrupts
00489 ***************************************************************************/
00490 static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
00491 {
00492   switch ( action ) {
00493   case DISABLE :
00494     break;
00495   case ENABLE :
00496     break;
00497   case FORCE :
00498     break;
00499   }
00500 }
00501 
00502 static int read_eeprom(uint16_t ioaddr, int location)
00503 {
00504         int             i;
00505         unsigned short  retval = 0;
00506         int             ee_addr = ioaddr + eeprom_reg;
00507         int             read_cmd = location | EE_READ_CMD;
00508         int             ctrl_val = EECS;
00509 
00510         if (eepro == LAN595FX_10ISA) {
00511                 eepro_sw2bank1(ioaddr);
00512                 outb(0x00, ioaddr + STATUS_REG);
00513         }
00514         eepro_sw2bank2(ioaddr);
00515         outb(ctrl_val, ee_addr);
00516         /* shift the read command bits out */
00517         for (i = 8; i >= 0; i--) {
00518                 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
00519                 outb(outval, ee_addr);
00520                 outb(outval | EESK, ee_addr);   /* EEPROM clock tick */
00521                 eeprom_delay();
00522                 outb(outval, ee_addr);          /* finish EEPROM clock tick */
00523                 eeprom_delay();
00524         }
00525         outb(ctrl_val, ee_addr);
00526         for (i = 16; i > 0; i--) {
00527                 outb(ctrl_val | EESK, ee_addr);
00528                 eeprom_delay();
00529                 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
00530                 outb(ctrl_val, ee_addr);
00531                 eeprom_delay();
00532         }
00533         /* terminate the EEPROM access */
00534         ctrl_val &= ~EECS;
00535         outb(ctrl_val | EESK, ee_addr);
00536         eeprom_delay();
00537         outb(ctrl_val, ee_addr);
00538         eeprom_delay();
00539         eepro_sw2bank0(ioaddr);
00540         return (retval);
00541 }
00542 
00543 static int eepro_probe1 ( isa_probe_addr_t ioaddr ) {
00544         int             id, counter;
00545 
00546         id = inb(ioaddr + ID_REG);
00547         if ((id & ID_REG_MASK) != ID_REG_SIG)
00548                 return (0);
00549         counter = id & R_ROBIN_BITS;
00550         if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
00551                 return (0);
00552         /* yes the 82595 has been found */
00553         return (1);
00554 }
00555 
00556 static struct nic_operations eepro_operations = {
00557         .connect        = dummy_connect,
00558         .poll           = eepro_poll,
00559         .transmit       = eepro_transmit,
00560         .irq            = eepro_irq,
00561 
00562 };
00563 
00564 /**************************************************************************
00565 PROBE - Look for an adapter, this routine's visible to the outside
00566 ***************************************************************************/
00567 static int eepro_probe ( struct nic *nic, struct isa_device *isa ) {
00568 
00569         int             i, l_eepro = 0;
00570         union {
00571                 unsigned char   caddr[ETH_ALEN];
00572                 unsigned short  saddr[ETH_ALEN/2];
00573         } station_addr;
00574         const char *name;
00575 
00576         nic->irqno  = 0;
00577         nic->ioaddr = isa->ioaddr;
00578 
00579         station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
00580         if ( ( station_addr.saddr[2] == 0x0000 ) ||
00581              ( station_addr.saddr[2] == 0xFFFF ) ) {
00582                 l_eepro = 3;
00583                 eepro = LAN595FX_10ISA;
00584                 eeprom_reg= EEPROM_REG_10;
00585                 rcv_start = RCV_START_10;
00586                 xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
00587                 xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
00588                 station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
00589         }
00590         station_addr.saddr[1] = read_eeprom(nic->ioaddr,3);
00591         station_addr.saddr[0] = read_eeprom(nic->ioaddr,4);
00592         if (l_eepro)
00593                 name = "Intel EtherExpress 10 ISA";
00594         else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) {
00595                 name = "Intel EtherExpress Pro/10+ ISA";
00596                 l_eepro = 2;
00597         } else if (station_addr.saddr[0] == SA_ADDR1) {
00598                 name = "Intel EtherExpress Pro/10 ISA";
00599                 l_eepro = 1;
00600         } else {
00601                 l_eepro = 0;
00602                 name = "Intel 82595-based LAN card";
00603         }
00604         station_addr.saddr[0] = bswap_16(station_addr.saddr[0]);
00605         station_addr.saddr[1] = bswap_16(station_addr.saddr[1]);
00606         station_addr.saddr[2] = bswap_16(station_addr.saddr[2]);
00607         for (i = 0; i < ETH_ALEN; i++) {
00608                 nic->node_addr[i] = station_addr.caddr[i];
00609         }
00610 
00611         DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) );
00612 
00613         mem_start = RCV_LOWER_LIMIT << 8;
00614         if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
00615                 mem_end = RCV_UPPER_LIMIT << 8;
00616         else {
00617                 mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
00618                 rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
00619         }
00620         printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
00621                 GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP");
00622 
00623         eepro_reset(nic);
00624 
00625         /* point to NIC specific routines */
00626         nic->nic_op     = &eepro_operations;
00627         return 1;
00628 }
00629 
00630 static isa_probe_addr_t eepro_probe_addrs[] = {
00631         0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360,
00632 };
00633 
00634 ISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1,
00635                      GENERIC_ISAPNP_VENDOR, 0x828a );
00636 
00637 DRIVER ( "eepro", nic_driver, isa_driver, eepro_driver,
00638          eepro_probe, eepro_disable );
00639 
00640 ISA_ROM ( "eepro", "Intel Etherexpress Pro/10" );
00641 
00642 /*
00643  * Local variables:
00644  *  c-basic-offset: 8
00645  *  c-indent-level: 8
00646  *  tab-width: 8
00647  * End:
00648  */