iPXE
Data Structures | Defines | Enumerations | Functions | Variables
davicom.c File Reference
#include "etherboot.h"
#include "nic.h"
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>

Go to the source code of this file.

Data Structures

struct  txdesc
struct  rxdesc

Defines

#define TX_TIME_OUT   2*TICKS_PER_SEC
#define EEPROM_ADDRLEN   6
#define EEPROM_SIZE   32 /* 1 << EEPROM_ADDRLEN */
#define EE_WRITE_CMD   (5 << addr_len)
#define EE_READ_CMD   (6 << addr_len)
#define EE_ERASE_CMD   (7 << addr_len)
#define EE_SHIFT_CLK   0x02 /* EEPROM shift clock. */
#define EE_CS   0x01 /* EEPROM chip select. */
#define EE_DATA_WRITE   0x04 /* EEPROM chip data in. */
#define EE_WRITE_0   0x01
#define EE_WRITE_1   0x05
#define EE_DATA_READ   0x08 /* EEPROM chip data out. */
#define EE_ENB   (0x4800 | EE_CS)
#define PHY_DATA_0   0x0
#define PHY_DATA_1   0x20000
#define MDCLKH   0x10000
#define eeprom_delay()   inl(ee_addr)
#define BUFLEN   1536
#define NTXD   2
#define NRXD   4
#define txd   davicom_bufs.txd
#define txb   davicom_bufs.txb
#define rxd   davicom_bufs.rxd
#define rxb   davicom_bufs.rxb
#define PCI_VENDOR_ID_DAVICOM   0x1282
#define PCI_DEVICE_ID_DM9009   0x9009

Enumerations

enum  davicom_offsets {
  CSR0 = 0, CSR1 = 0x08, CSR2 = 0x10, CSR3 = 0x18,
  CSR4 = 0x20, CSR5 = 0x28, CSR6 = 0x30, CSR7 = 0x38,
  CSR8 = 0x40, CSR9 = 0x48, CSR10 = 0x50, CSR11 = 0x58,
  CSR12 = 0x60, CSR13 = 0x68, CSR14 = 0x70, CSR15 = 0x78,
  CSR16 = 0x80, CSR20 = 0xA0
}

Functions

 FILE_LICENCE (GPL_ANY)
static void whereami (const char *str)
static int read_eeprom (unsigned long ioaddr, int location, int addr_len)
static int davicom_probe (struct nic *nic, struct pci_device *pci)
static void davicom_init_chain (struct nic *nic)
static void davicom_reset (struct nic *nic)
static void davicom_transmit (struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
static int davicom_poll (struct nic *nic, int retrieve)
static void davicom_disable (struct nic *nic)
static void davicom_wait (unsigned int nticks)
static int phy_read (int)
static void phy_write (int, u16)
static void phy_write_1bit (u32, u32)
static int phy_read_1bit (u32)
static void davicom_media_chk (struct nic *)
static void HPNA_process (void)
static void davicom_media_chk (struct nic *nic __unused)
static void davicom_irq (struct nic *nic __unused, irq_action_t action __unused)
 PCI_DRIVER (davicom_driver, davicom_nics, PCI_NO_CLASS)
 DRIVER ("DAVICOM", nic_driver, pci_driver, davicom_driver, davicom_probe, davicom_disable)

Variables

static unsigned char ee_data [EEPROM_SIZE]
static struct nic_operations davicom_operations
static unsigned short vendor
static unsigned short dev_id
static unsigned long ioaddr
struct {
   struct txdesc   txd [NTXD]
   unsigned char   txb [BUFLEN]
   struct rxdesc   rxd [NRXD]
   unsigned char   rxb [NRXD *BUFLEN]
__shared
static int rxd_tail
static int TxPtr
static struct pci_device_id davicom_nics []

Define Documentation

#define TX_TIME_OUT   2*TICKS_PER_SEC

Definition at line 51 of file davicom.c.

Referenced by davicom_reset(), and davicom_transmit().

#define EEPROM_ADDRLEN   6

Definition at line 61 of file davicom.c.

Referenced by davicom_probe().

#define EEPROM_SIZE   32 /* 1 << EEPROM_ADDRLEN */

Definition at line 62 of file davicom.c.

#define EE_WRITE_CMD   (5 << addr_len)

Definition at line 70 of file davicom.c.

#define EE_READ_CMD   (6 << addr_len)

Definition at line 71 of file davicom.c.

Referenced by read_eeprom().

#define EE_ERASE_CMD   (7 << addr_len)

Definition at line 72 of file davicom.c.

#define EE_SHIFT_CLK   0x02 /* EEPROM shift clock. */

Definition at line 75 of file davicom.c.

Referenced by read_eeprom().

#define EE_CS   0x01 /* EEPROM chip select. */

Definition at line 76 of file davicom.c.

Referenced by read_eeprom().

#define EE_DATA_WRITE   0x04 /* EEPROM chip data in. */

Definition at line 77 of file davicom.c.

Referenced by read_eeprom().

#define EE_WRITE_0   0x01

Definition at line 78 of file davicom.c.

#define EE_WRITE_1   0x05

Definition at line 79 of file davicom.c.

#define EE_DATA_READ   0x08 /* EEPROM chip data out. */

Definition at line 80 of file davicom.c.

Referenced by read_eeprom().

#define EE_ENB   (0x4800 | EE_CS)

Definition at line 81 of file davicom.c.

Referenced by read_eeprom().

#define PHY_DATA_0   0x0

Definition at line 84 of file davicom.c.

Referenced by phy_read(), and phy_write().

#define PHY_DATA_1   0x20000

Definition at line 85 of file davicom.c.

Referenced by phy_read(), and phy_write().

#define MDCLKH   0x10000

Definition at line 86 of file davicom.c.

Referenced by phy_write_1bit().

#define eeprom_delay ( )    inl(ee_addr)

Definition at line 91 of file davicom.c.

Referenced by phy_read_1bit(), phy_write_1bit(), and read_eeprom().

#define BUFLEN   1536

Definition at line 119 of file davicom.c.

Referenced by davicom_init_chain(), and davicom_poll().

#define NTXD   2

Definition at line 135 of file davicom.c.

Referenced by davicom_init_chain(), davicom_reset(), and davicom_transmit().

#define NRXD   4

Definition at line 136 of file davicom.c.

Referenced by davicom_init_chain(), and davicom_poll().

#define txd   davicom_bufs.txd
#define txb   davicom_bufs.txb
#define rxd   davicom_bufs.rxd
#define rxb   davicom_bufs.rxb
#define PCI_VENDOR_ID_DAVICOM   0x1282

Referenced by davicom_media_chk().

#define PCI_DEVICE_ID_DM9009   0x9009

Referenced by davicom_media_chk().


Enumeration Type Documentation

Enumerator:
CSR0 
CSR1 
CSR2 
CSR3 
CSR4 
CSR5 
CSR6 
CSR7 
CSR8 
CSR9 
CSR10 
CSR11 
CSR12 
CSR13 
CSR14 
CSR15 
CSR16 
CSR20 

Definition at line 54 of file davicom.c.

                     {
   CSR0=0,     CSR1=0x08,  CSR2=0x10,  CSR3=0x18,  CSR4=0x20,  CSR5=0x28,
   CSR6=0x30,  CSR7=0x38,  CSR8=0x40,  CSR9=0x48, CSR10=0x50, CSR11=0x58,
  CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
};

Function Documentation

FILE_LICENCE ( GPL_ANY  )
static void whereami ( const char *  str) [inline, static]

Definition at line 174 of file davicom.c.

References DBGP.

Referenced by davicom_disable(), davicom_poll(), davicom_probe(), davicom_reset(), davicom_transmit(), phy_read(), phy_read_1bit(), phy_write(), phy_write_1bit(), and read_eeprom().

{
  DBGP("%s\n", str);
  /* sleep(2); */
}
static int read_eeprom ( unsigned long  ioaddr,
int  location,
int  addr_len 
) [static]

Definition at line 377 of file davicom.c.

References CSR9, EE_CS, EE_DATA_READ, EE_DATA_WRITE, EE_ENB, EE_READ_CMD, EE_SHIFT_CLK, eeprom_delay, inl(), outl(), and whereami().

Referenced by davicom_probe(), and epic100_probe().

{
  int i;
  unsigned short retval = 0;
  long ee_addr = ioaddr + CSR9;
  int read_cmd = location | EE_READ_CMD;

  whereami("read_eeprom\n");

  outl(EE_ENB & ~EE_CS, ee_addr);
  outl(EE_ENB, ee_addr);

  /* Shift the read command bits out. */
  for (i = 4 + addr_len; i >= 0; i--) {
    short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
    outl(EE_ENB | dataval, ee_addr);
    eeprom_delay();
    outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
    eeprom_delay();
  }
  outl(EE_ENB, ee_addr);

  for (i = 16; i > 0; i--) {
    outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
    eeprom_delay();
    retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
    outl(EE_ENB, ee_addr);
    eeprom_delay();
  }

  /* Terminate the EEPROM access. */
  outl(EE_ENB & ~EE_CS, ee_addr);
  return retval;
}
static int davicom_probe ( struct nic nic,
struct pci_device pci 
) [static]

Definition at line 640 of file davicom.c.

References CSR6, CSR8, davicom_operations, davicom_reset(), DBG, dev_id, pci_device::device, ee_data, EEPROM_ADDRLEN, ETH_ALEN, eth_ntoa(), inl(), ioaddr, pci_device::ioaddr, le16_to_cpu, outl(), pci_write_config_dword(), read_eeprom(), vendor, pci_device::vendor, and whereami().

                                                                     {

  unsigned int i;

  whereami("davicom_probe\n");

  if (pci->ioaddr == 0)
    return 0;

  vendor  = pci->vendor;
  dev_id  = pci->device;
  ioaddr  = pci->ioaddr;

  nic->ioaddr = pci->ioaddr;
  nic->irqno = 0;

  /* wakeup chip */
  pci_write_config_dword(pci, 0x40, 0x00000000);

  /* Stop the chip's Tx and Rx processes. */
  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);

  /* Clear the missed-packet counter. */
  inl(ioaddr + CSR8);

  /* Get MAC Address */
  /* read EEPROM data */
  for (i = 0; i < sizeof(ee_data)/2; i++)
    ((unsigned short *)ee_data)[i] =
        le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));

  /* extract MAC address from EEPROM buffer */
  for (i=0; i<ETH_ALEN; i++)
    nic->node_addr[i] = ee_data[20+i];

  DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );

  /* initialize device */
  davicom_reset(nic);
  nic->nic_op   = &davicom_operations;
  return 1;
}
static void davicom_init_chain ( struct nic nic) [static]

Definition at line 416 of file davicom.c.

References BUFLEN, NRXD, NTXD, rxb, rxd, txb, txd, and virt_to_bus().

Referenced by davicom_reset().

{
  int i;

  /* setup the transmit descriptor */
  /* Sten: Set 2 TX descriptor but use one TX buffer because
           it transmit a packet and wait complete every time. */
  for (i=0; i<NTXD; i++) {
    txd[i].buf1addr = (void *)virt_to_bus(&txb[0]);     /* Used same TX buffer */
    txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]);   /*  Point to Next TX desc */
    txd[i].buf1sz   = 0;
    txd[i].buf2sz   = 0;
    txd[i].control  = 0x184;           /* Begin/End/Chain */
    txd[i].status   = 0x00000000;      /* give ownership to Host */
  }

  /* construct perfect filter frame with mac address as first match
     and broadcast address for all others */
  for (i=0; i<192; i++) txb[i] = 0xFF;
  txb[0] = nic->node_addr[0];
  txb[1] = nic->node_addr[1];
  txb[4] = nic->node_addr[2];
  txb[5] = nic->node_addr[3];
  txb[8] = nic->node_addr[4];
  txb[9] = nic->node_addr[5];

  /* setup receive descriptor */
  for (i=0; i<NRXD; i++) {
    rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
    rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
    rxd[i].buf1sz   = BUFLEN;
    rxd[i].buf2sz   = 0;        /* not used */
    rxd[i].control  = 0x4;              /* Chain Structure */
    rxd[i].status   = 0x80000000;   /* give ownership to device */
  }

  /* Chain the last descriptor to first */
  txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
  rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
  TxPtr = 0;
  rxd_tail = 0;
}
static void davicom_reset ( struct nic nic) [static]

Definition at line 463 of file davicom.c.

References CSR0, CSR1, CSR2, CSR3, CSR4, CSR6, currticks(), davicom_init_chain(), davicom_media_chk(), davicom_wait(), DBG, DBG_MORE, inl(), ioaddr, NTXD, outl(), rxd, status, TICKS_PER_SEC, TX_TIME_OUT, txd, TxPtr, virt_to_bus(), and whereami().

Referenced by davicom_disable(), and davicom_probe().

{
  unsigned long to;

  whereami("davicom_reset\n");

  /* Stop Tx and RX */
  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);

  /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
  outl(0x00000001, ioaddr + CSR0);

  davicom_wait(TICKS_PER_SEC);

  /* TX/RX descriptor burst */
  outl(0x0C00000, ioaddr + CSR0);       /* Sten 10/9 */

  /* set up transmit and receive descriptors */
  davicom_init_chain(nic);      /* Sten 10/9 */

  /* Point to receive descriptor */
  outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
  outl(virt_to_bus(&txd[0]), ioaddr + CSR4);    /* Sten 10/9 */

  /* According phyxcer media mode to set CR6,
     DM9102/A phyxcer can auto-detect media mode */
  davicom_media_chk(nic);

  /* Prepare Setup Frame Sten 10/9 */
  txd[TxPtr].buf1sz = 192;
  txd[TxPtr].control = 0x024;           /* SF/CE */
  txd[TxPtr].status = 0x80000000;       /* Give ownership to device */

  /* Start Tx */
  outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
  /* immediate transmit demand */
  outl(0, ioaddr + CSR1);

  to = currticks() + TX_TIME_OUT;
  while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
    /* wait */ ;

  if (currticks() >= to) {
    DBG ("TX Setup Timeout!\n");
  }
  /* Point to next TX descriptor */
 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr;   /* Sten 10/9 */

  DBG("txd.status = %lX\n", txd[TxPtr].status);
  DBG("ticks = %ld\n", currticks() - (to - TX_TIME_OUT));
  DBG_MORE();

  /* enable RX */
  outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
  /* immediate poll demand */
  outl(0, ioaddr + CSR2);
}
static void davicom_transmit ( struct nic nic,
const char *  d,
unsigned int  t,
unsigned int  s,
const char *  p 
) [static]

Definition at line 525 of file davicom.c.

References CSR1, currticks(), DBG, ETH_ALEN, ETH_HLEN, ioaddr, memcpy(), NTXD, outl(), status, TX_TIME_OUT, txb, txd, TxPtr, and whereami().

{
  unsigned long to;

  whereami("davicom_transmit\n");

  /* Stop Tx */
  /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */

  /* setup ethernet header */
  memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
  memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
  txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
  txb[ETH_ALEN*2+1] = t & 0xFF;
  memcpy(&txb[ETH_HLEN], p, s); /* Frame data */

  /* setup the transmit descriptor */
  txd[TxPtr].buf1sz   = ETH_HLEN+s;
  txd[TxPtr].control  = 0x00000184;      /* LS+FS+CE */
  txd[TxPtr].status   = 0x80000000;      /* give ownership to device */

  /* immediate transmit demand */
  outl(0, ioaddr + CSR1);

  to = currticks() + TX_TIME_OUT;
  while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
    /* wait */ ;

  if (currticks() >= to) {
    DBG ("TX Timeout!\n");
  }
 
  /* Point to next TX descriptor */
  TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr;  /* Sten 10/9 */

}
static int davicom_poll ( struct nic nic,
int  retrieve 
) [static]

Definition at line 566 of file davicom.c.

References BUFLEN, memcpy(), NRXD, rxb, rxd, rxd_tail, status, and whereami().

{
  whereami("davicom_poll\n");

  if (rxd[rxd_tail].status & 0x80000000)
    return 0;

  if ( ! retrieve ) return 1;

  whereami("davicom_poll got one\n");

  nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;

  if( rxd[rxd_tail].status & 0x00008000){
      rxd[rxd_tail].status = 0x80000000;
      rxd_tail++;
      if (rxd_tail == NRXD) rxd_tail = 0;
      return 0;
  }

  /* copy packet to working buffer */
  /* XXX - this copy could be avoided with a little more work
     but for now we are content with it because the optimised
     memcpy is quite fast */

  memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);

  /* return the descriptor and buffer to receive ring */
  rxd[rxd_tail].status = 0x80000000;
  rxd_tail++;
  if (rxd_tail == NRXD) rxd_tail = 0;

  return 1;
}
static void davicom_disable ( struct nic nic) [static]

Definition at line 604 of file davicom.c.

References CSR6, CSR7, CSR8, davicom_reset(), inl(), ioaddr, outl(), and whereami().

                                                {

  whereami("davicom_disable\n");

  davicom_reset(nic);

  /* disable interrupts */
  outl(0x00000000, ioaddr + CSR7);

  /* Stop the chip's Tx and Rx processes. */
  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);

  /* Clear the missed-packet counter. */
  inl(ioaddr + CSR8);
}
static void davicom_wait ( unsigned int  nticks) [static]

Definition at line 180 of file davicom.c.

References currticks().

Referenced by davicom_reset().

{
  unsigned int to = currticks() + nticks;
  while (currticks() < to)
    /* wait */ ;
}
static int phy_read ( int  location) [static]

Definition at line 194 of file davicom.c.

References CSR9, ioaddr, PHY_DATA_0, PHY_DATA_1, phy_read_1bit(), phy_write_1bit(), and whereami().

Referenced by davicom_media_chk(), and HPNA_process().

{
 int i, phy_addr=1;
 u16 phy_data;
 u32 io_dcr9;

 whereami("phy_read\n");

 io_dcr9 = ioaddr + CSR9;

 /* Send 33 synchronization clock to Phy controller */
 for (i=0; i<34; i++)
     phy_write_1bit(io_dcr9, PHY_DATA_1);

 /* Send start command(01) to Phy */
 phy_write_1bit(io_dcr9, PHY_DATA_0);
 phy_write_1bit(io_dcr9, PHY_DATA_1);

 /* Send read command(10) to Phy */
 phy_write_1bit(io_dcr9, PHY_DATA_1);
 phy_write_1bit(io_dcr9, PHY_DATA_0);

 /* Send Phy address */
 for (i=0x10; i>0; i=i>>1)
     phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
   
 /* Send register address */
 for (i=0x10; i>0; i=i>>1)
     phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);

 /* Skip transition state */
 phy_read_1bit(io_dcr9);

 /* read 16bit data */
 for (phy_data=0, i=0; i<16; i++) {
   phy_data<<=1;
   phy_data|=phy_read_1bit(io_dcr9);
 }

 return phy_data;
}
static void phy_write ( int  location,
u16  phy_data 
) [static]

Definition at line 239 of file davicom.c.

References CSR9, ioaddr, PHY_DATA_0, PHY_DATA_1, phy_write_1bit(), and whereami().

Referenced by davicom_media_chk(), and HPNA_process().

{
 u16 i, phy_addr=1;
 u32 io_dcr9; 

 whereami("phy_write\n");

 io_dcr9 = ioaddr + CSR9;

 /* Send 33 synchronization clock to Phy controller */
 for (i=0; i<34; i++)
   phy_write_1bit(io_dcr9, PHY_DATA_1);

 /* Send start command(01) to Phy */
 phy_write_1bit(io_dcr9, PHY_DATA_0);
 phy_write_1bit(io_dcr9, PHY_DATA_1);

 /* Send write command(01) to Phy */
 phy_write_1bit(io_dcr9, PHY_DATA_0);
 phy_write_1bit(io_dcr9, PHY_DATA_1);

 /* Send Phy address */
 for (i=0x10; i>0; i=i>>1)
   phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);

 /* Send register address */
 for (i=0x10; i>0; i=i>>1)
   phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);

 /* written trasnition */
 phy_write_1bit(io_dcr9, PHY_DATA_1);
 phy_write_1bit(io_dcr9, PHY_DATA_0);

 /* Write a word data to PHY controller */
 for (i=0x8000; i>0; i>>=1)
   phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
}
static void phy_write_1bit ( u32  ee_addr,
u32  phy_data 
) [static]

Definition at line 280 of file davicom.c.

References eeprom_delay, MDCLKH, outl(), and whereami().

Referenced by phy_read(), and phy_write().

{
 whereami("phy_write_1bit\n");
 outl(phy_data, ee_addr);                        /* MII Clock Low */
 eeprom_delay();
 outl(phy_data|MDCLKH, ee_addr);                 /* MII Clock High */
 eeprom_delay();
 outl(phy_data, ee_addr);                        /* MII Clock Low */
 eeprom_delay();
}
static int phy_read_1bit ( u32  ee_addr) [static]

Definition at line 294 of file davicom.c.

References eeprom_delay, inl(), outl(), and whereami().

Referenced by phy_read().

{
 int phy_data;

 whereami("phy_read_1bit\n");

 outl(0x50000, ee_addr);
 eeprom_delay();

 phy_data=(inl(ee_addr)>>19) & 0x1;

 outl(0x40000, ee_addr);
 eeprom_delay();

 return phy_data;
}
static void davicom_media_chk ( struct nic ) [static]

Referenced by davicom_reset().

static void HPNA_process ( void  ) [static]

Definition at line 314 of file davicom.c.

References phy_read(), and phy_write().

Referenced by davicom_media_chk().

{

 if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
   if ( phy_read(31) == 0x4404 ) {
     /* DM9801 present */
     if (phy_read(3) == 0xb901)
       phy_write(16, 0x5);      /* DM9801 E4 */
     else
       phy_write(16, 0x1005); /* DM9801 E3 and others */
     phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
   } else {
     /* DM9802 present */
     phy_write(16, 0x5);
     phy_write(25, (phy_read(25) & 0xff00) + 2);
   }
 }
}
static void davicom_media_chk ( struct nic *nic  __unused) [static]

Definition at line 336 of file davicom.c.

References CSR6, currticks(), dev_id, HPNA_process(), ioaddr, outl(), PCI_DEVICE_ID_DM9009, PCI_VENDOR_ID_DAVICOM, phy_read(), phy_write(), TICKS_PER_SEC, and vendor.

{
  unsigned long to, csr6;

  csr6 = 0x00200000;    /* SF */
  outl(csr6, ioaddr + CSR6);

#define PCI_VENDOR_ID_DAVICOM           0x1282
#define PCI_DEVICE_ID_DM9009            0x9009
  if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
    /* Set to 10BaseT mode for DM9009 */
    phy_write(0, 0);
  } else {
    /* For DM9102/DM9102A */
    to = currticks() + 2 * TICKS_PER_SEC;
    while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
      /* wait */ ;

    if ( (phy_read(1) & 0x24) == 0x24 ) {
      if (phy_read(17) & 0xa000)  
        csr6 |= 0x00000200;     /* Full Duplex mode */
    } else
      csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
  }

  /* set the chip's operating mode */
  outl(csr6, ioaddr + CSR6);

  /* DM9801/DM9802 present check & program */
  if (csr6 & 0x40000)
    HPNA_process();
}
static void davicom_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
) [static]

Definition at line 624 of file davicom.c.

{
  switch ( action ) {
  case DISABLE :
    break;
  case ENABLE :
    break;
  case FORCE :
    break;
  }
}
PCI_DRIVER ( davicom_driver  ,
davicom_nics  ,
PCI_NO_CLASS   
)
DRIVER ( "DAVICOM"  ,
nic_driver  ,
pci_driver  ,
davicom_driver  ,
davicom_probe  ,
davicom_disable   
)

Variable Documentation

unsigned char ee_data[EEPROM_SIZE] [static]

Definition at line 67 of file davicom.c.

Referenced by davicom_probe(), parse_eeprom(), sundance_probe(), and tulip_probe().

static struct nic_operations davicom_operations [static]
Initial value:
 {
        .connect        = dummy_connect,
        .poll           = davicom_poll,
        .transmit       = davicom_transmit,
        .irq            = davicom_irq,

}

Definition at line 125 of file davicom.c.

Referenced by davicom_probe().

unsigned short vendor [static]

Definition at line 128 of file davicom.c.

Referenced by davicom_media_chk(), davicom_probe(), and sis900_probe().

unsigned short dev_id [static]

Definition at line 128 of file davicom.c.

Referenced by davicom_media_chk(), and davicom_probe().

unsigned long ioaddr [static]

Definition at line 129 of file davicom.c.

Referenced by davicom_disable(), davicom_media_chk(), davicom_probe(), davicom_reset(), davicom_transmit(), dm9132_id_table(), dmfe_init_dm910x(), forcedeth_link_status(), forcedeth_map_regs(), forcedeth_open(), forcedeth_poll(), forcedeth_probe(), forcedeth_transmit(), ifec_mdio_read(), ifec_mdio_write(), ifec_net_close(), ifec_net_irq(), ifec_net_transmit(), ifec_reset(), ifec_scb_cmd(), ifec_tx_wake(), mii_rw(), nv_disable_hw_interrupts(), nv_enable_hw_interrupts(), nv_init_rings(), nv_mac_reset(), nv_mgmt_acquire_sema(), nv_mgmt_get_version(), nv_mgmt_release_sema(), nv_setup_mac_addr(), nv_setup_phy(), nv_start_rx(), nv_start_tx(), nv_stop_rx(), nv_stop_tx(), nv_txrx_gate(), nv_txrx_reset(), nv_update_linkspeed(), nv_update_pause(), pcnet32_chip_detect(), pcnet32_close(), pcnet32_hw_start(), pcnet32_irq_disable(), pcnet32_irq_enable(), pcnet32_mdio_read(), pcnet32_mdio_write(), pcnet32_open(), pcnet32_poll(), pcnet32_probe(), pcnet32_remove(), pcnet32_set_ops(), pcnet32_setup_if_duplex(), pcnet32_setup_mac_addr(), pcnet32_setup_probe_phy(), pcnet32_transmit(), phy_init(), phy_read(), phy_write(), reg_delay(), sis190_default_phy(), sis190_down(), sis190_get_mac_addr_from_eeprom(), sis190_hw_start(), sis190_init_board(), sis190_init_phy(), sis190_init_rxfilter(), sis190_irq(), sis190_mii_probe(), sis190_mii_probe_88e1111_fixup(), sis190_phy_task(), sis190_poll(), sis190_remove(), sis190_set_rx_mode(), sis190_set_speed_auto(), sis190_transmit(), virtnet_open_legacy(), and virtnet_probe_legacy().

struct txdesc txd[NTXD]

Definition at line 138 of file davicom.c.

unsigned char txb[BUFLEN]

Definition at line 139 of file davicom.c.

struct rxdesc rxd[NRXD]

Definition at line 140 of file davicom.c.

unsigned char rxb[NRXD *BUFLEN]

Definition at line 141 of file davicom.c.

struct { ... } __shared
int rxd_tail [static]

Definition at line 147 of file davicom.c.

Referenced by davicom_poll().

int TxPtr [static]

Definition at line 148 of file davicom.c.

Referenced by davicom_reset(), and davicom_transmit().

struct pci_device_id davicom_nics[] [static]
Initial value:
 {
PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0),      
}

Definition at line 691 of file davicom.c.