iPXE
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00001 /* 00002 * Copyright (c) 2008-2011 Atheros Communications Inc. 00003 * 00004 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011 00005 * Original from Linux kernel 3.0.1 00006 * 00007 * Permission to use, copy, modify, and/or distribute this software for any 00008 * purpose with or without fee is hereby granted, provided that the above 00009 * copyright notice and this permission notice appear in all copies. 00010 * 00011 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 00012 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 00013 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 00014 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 00015 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 00016 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 00017 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 00018 */ 00019 00020 #include <ipxe/vsprintf.h> 00021 #include <ipxe/io.h> 00022 00023 #include "hw.h" 00024 #include "hw-ops.h" 00025 #include "ar9003_mac.h" 00026 00027 static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 00028 00029 /* Private hardware callbacks */ 00030 00031 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 00032 { 00033 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 00034 } 00035 00036 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 00037 { 00038 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 00039 } 00040 00041 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 00042 struct ath9k_channel *chan) 00043 { 00044 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 00045 } 00046 00047 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 00048 { 00049 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 00050 return; 00051 00052 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 00053 } 00054 00055 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 00056 { 00057 /* You will not have this callback if using the old ANI */ 00058 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 00059 return; 00060 00061 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 00062 } 00063 00064 /********************/ 00065 /* Helper Functions */ 00066 /********************/ 00067 00068 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 00069 { 00070 struct ath_common *common = ath9k_hw_common(ah); 00071 struct net80211_device *dev = common->dev; 00072 unsigned int clockrate; 00073 00074 if (!ah->curchan) /* should really check for CCK instead */ 00075 clockrate = ATH9K_CLOCK_RATE_CCK; 00076 else if ((dev->channels + dev->channel)->band == NET80211_BAND_2GHZ) 00077 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 00078 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 00079 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 00080 else 00081 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 00082 00083 common->clockrate = clockrate; 00084 } 00085 00086 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 00087 { 00088 struct ath_common *common = ath9k_hw_common(ah); 00089 00090 return usecs * common->clockrate; 00091 } 00092 00093 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 00094 { 00095 unsigned int i; 00096 00097 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 00098 if ((REG_READ(ah, reg) & mask) == val) 00099 return 1; 00100 00101 udelay(AH_TIME_QUANTUM); 00102 } 00103 00104 DBG("ath9k: " 00105 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 00106 timeout, reg, REG_READ(ah, reg), mask, val); 00107 00108 return 0; 00109 } 00110 00111 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 00112 int column, unsigned int *writecnt) 00113 { 00114 unsigned int r; 00115 00116 ENABLE_REGWRITE_BUFFER(ah); 00117 for (r = 0; r < array->ia_rows; r++) { 00118 REG_WRITE(ah, INI_RA(array, r, 0), 00119 INI_RA(array, r, column)); 00120 DO_DELAY(*writecnt); 00121 } 00122 REGWRITE_BUFFER_FLUSH(ah); 00123 } 00124 00125 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 00126 { 00127 u32 retval; 00128 unsigned int i; 00129 00130 for (i = 0, retval = 0; i < n; i++) { 00131 retval = (retval << 1) | (val & 1); 00132 val >>= 1; 00133 } 00134 return retval; 00135 } 00136 00137 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 00138 u8 phy, int kbps, 00139 u32 frameLen, u16 rateix, 00140 int shortPreamble) 00141 { 00142 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 00143 00144 if (kbps == 0) 00145 return 0; 00146 00147 switch (phy) { 00148 case CHANNEL_CCK: 00149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 00150 if (shortPreamble) 00151 phyTime >>= 1; 00152 numBits = frameLen << 3; 00153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 00154 break; 00155 case CHANNEL_OFDM: 00156 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 00157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 00158 numBits = OFDM_PLCP_BITS + (frameLen << 3); 00159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 00160 txTime = OFDM_SIFS_TIME_QUARTER 00161 + OFDM_PREAMBLE_TIME_QUARTER 00162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 00163 } else if (ah->curchan && 00164 IS_CHAN_HALF_RATE(ah->curchan)) { 00165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 00166 numBits = OFDM_PLCP_BITS + (frameLen << 3); 00167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 00168 txTime = OFDM_SIFS_TIME_HALF + 00169 OFDM_PREAMBLE_TIME_HALF 00170 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 00171 } else { 00172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 00173 numBits = OFDM_PLCP_BITS + (frameLen << 3); 00174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 00175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 00176 + (numSymbols * OFDM_SYMBOL_TIME); 00177 } 00178 break; 00179 default: 00180 DBG("ath9k: " 00181 "Unknown phy %d (rate ix %d)\n", phy, rateix); 00182 txTime = 0; 00183 break; 00184 } 00185 00186 return txTime; 00187 } 00188 00189 void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, 00190 struct ath9k_channel *chan, 00191 struct chan_centers *centers) 00192 { 00193 int8_t extoff; 00194 00195 if (!IS_CHAN_HT40(chan)) { 00196 centers->ctl_center = centers->ext_center = 00197 centers->synth_center = chan->channel; 00198 return; 00199 } 00200 00201 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 00202 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 00203 centers->synth_center = 00204 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 00205 extoff = 1; 00206 } else { 00207 centers->synth_center = 00208 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 00209 extoff = -1; 00210 } 00211 00212 centers->ctl_center = 00213 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 00214 /* 25 MHz spacing is supported by hw but not on upper layers */ 00215 centers->ext_center = 00216 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 00217 } 00218 00219 /******************/ 00220 /* Chip Revisions */ 00221 /******************/ 00222 00223 static void ath9k_hw_read_revisions(struct ath_hw *ah) 00224 { 00225 u32 val; 00226 00227 switch (ah->hw_version.devid) { 00228 case AR5416_AR9100_DEVID: 00229 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 00230 break; 00231 case AR9300_DEVID_AR9340: 00232 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 00233 val = REG_READ(ah, AR_SREV); 00234 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 00235 return; 00236 } 00237 00238 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 00239 00240 if (val == 0xFF) { 00241 val = REG_READ(ah, AR_SREV); 00242 ah->hw_version.macVersion = 00243 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 00244 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 00245 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 00246 } else { 00247 if (!AR_SREV_9100(ah)) 00248 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 00249 00250 ah->hw_version.macRev = val & AR_SREV_REVISION; 00251 00252 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 00253 ah->is_pciexpress = 1; 00254 } 00255 } 00256 00257 /************************************/ 00258 /* HW Attach, Detach, Init Routines */ 00259 /************************************/ 00260 00261 static void ath9k_hw_disablepcie(struct ath_hw *ah) 00262 { 00263 if (!AR_SREV_5416(ah)) 00264 return; 00265 00266 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 00267 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 00268 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 00269 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 00270 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 00271 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 00272 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 00273 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 00274 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 00275 00276 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 00277 } 00278 00279 /* This should work for all families including legacy */ 00280 static int ath9k_hw_chip_test(struct ath_hw *ah) 00281 { 00282 u32 regAddr[2] = { AR_STA_ID0 }; 00283 u32 regHold[2]; 00284 static const u32 patternData[4] = { 00285 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 00286 }; 00287 int i, j, loop_max; 00288 00289 if (!AR_SREV_9300_20_OR_LATER(ah)) { 00290 loop_max = 2; 00291 regAddr[1] = AR_PHY_BASE + (8 << 2); 00292 } else 00293 loop_max = 1; 00294 00295 for (i = 0; i < loop_max; i++) { 00296 u32 addr = regAddr[i]; 00297 u32 wrData, rdData; 00298 00299 regHold[i] = REG_READ(ah, addr); 00300 for (j = 0; j < 0x100; j++) { 00301 wrData = (j << 16) | j; 00302 REG_WRITE(ah, addr, wrData); 00303 rdData = REG_READ(ah, addr); 00304 if (rdData != wrData) { 00305 DBG("ath9k: " 00306 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 00307 addr, wrData, rdData); 00308 return 0; 00309 } 00310 } 00311 for (j = 0; j < 4; j++) { 00312 wrData = patternData[j]; 00313 REG_WRITE(ah, addr, wrData); 00314 rdData = REG_READ(ah, addr); 00315 if (wrData != rdData) { 00316 DBG("ath9k: " 00317 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 00318 addr, wrData, rdData); 00319 return 0; 00320 } 00321 } 00322 REG_WRITE(ah, regAddr[i], regHold[i]); 00323 } 00324 udelay(100); 00325 00326 return 1; 00327 } 00328 00329 static void ath9k_hw_init_config(struct ath_hw *ah) 00330 { 00331 int i; 00332 00333 ah->config.dma_beacon_response_time = 2; 00334 ah->config.sw_beacon_response_time = 10; 00335 ah->config.additional_swba_backoff = 0; 00336 ah->config.ack_6mb = 0x0; 00337 ah->config.cwm_ignore_extcca = 0; 00338 ah->config.pcie_powersave_enable = 0; 00339 ah->config.pcie_clock_req = 0; 00340 ah->config.pcie_waen = 0; 00341 ah->config.analog_shiftreg = 1; 00342 ah->config.enable_ani = 1; 00343 00344 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 00345 ah->config.spurchans[i][0] = AR_NO_SPUR; 00346 ah->config.spurchans[i][1] = AR_NO_SPUR; 00347 } 00348 00349 /* PAPRD needs some more work to be enabled */ 00350 ah->config.paprd_disable = 1; 00351 00352 ah->config.rx_intr_mitigation = 1; 00353 ah->config.pcieSerDesWrite = 1; 00354 } 00355 00356 static void ath9k_hw_init_defaults(struct ath_hw *ah) 00357 { 00358 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 00359 00360 regulatory->country_code = CTRY_DEFAULT; 00361 regulatory->power_limit = MAX_RATE_POWER; 00362 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 00363 00364 ah->hw_version.magic = AR5416_MAGIC; 00365 ah->hw_version.subvendorid = 0; 00366 00367 ah->atim_window = 0; 00368 ah->sta_id1_defaults = 00369 AR_STA_ID1_CRPT_MIC_ENABLE | 00370 AR_STA_ID1_MCAST_KSRCH; 00371 if (AR_SREV_9100(ah)) 00372 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 00373 ah->enable_32kHz_clock = DONT_USE_32KHZ; 00374 ah->slottime = 20; 00375 ah->globaltxtimeout = (u32) -1; 00376 ah->power_mode = ATH9K_PM_UNDEFINED; 00377 } 00378 00379 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 00380 { 00381 struct ath_common *common = ath9k_hw_common(ah); 00382 u32 sum; 00383 int i; 00384 u16 eeval; 00385 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 00386 00387 sum = 0; 00388 for (i = 0; i < 3; i++) { 00389 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 00390 sum += eeval; 00391 common->macaddr[2 * i] = eeval >> 8; 00392 common->macaddr[2 * i + 1] = eeval & 0xff; 00393 } 00394 if (sum == 0 || sum == 0xffff * 3) 00395 return -EADDRNOTAVAIL; 00396 00397 return 0; 00398 } 00399 00400 static int ath9k_hw_post_init(struct ath_hw *ah) 00401 { 00402 struct ath_common *common = ath9k_hw_common(ah); 00403 int ecode; 00404 00405 if (common->bus_ops->ath_bus_type != ATH_USB) { 00406 if (!ath9k_hw_chip_test(ah)) 00407 return -ENODEV; 00408 } 00409 00410 if (!AR_SREV_9300_20_OR_LATER(ah)) { 00411 ecode = ar9002_hw_rf_claim(ah); 00412 if (ecode != 0) 00413 return ecode; 00414 } 00415 00416 ecode = ath9k_hw_eeprom_init(ah); 00417 if (ecode != 0) 00418 return ecode; 00419 00420 DBG("ath9k: " 00421 "Eeprom VER: %d, REV: %d\n", 00422 ah->eep_ops->get_eeprom_ver(ah), 00423 ah->eep_ops->get_eeprom_rev(ah)); 00424 00425 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 00426 if (ecode) { 00427 DBG("ath9k: " 00428 "Failed allocating banks for external radio\n"); 00429 ath9k_hw_rf_free_ext_banks(ah); 00430 return ecode; 00431 } 00432 00433 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { 00434 ath9k_hw_ani_setup(ah); 00435 ath9k_hw_ani_init(ah); 00436 } 00437 00438 return 0; 00439 } 00440 00441 static void ath9k_hw_attach_ops(struct ath_hw *ah) 00442 { 00443 if (AR_SREV_9300_20_OR_LATER(ah)) 00444 ar9003_hw_attach_ops(ah); 00445 else 00446 ar9002_hw_attach_ops(ah); 00447 } 00448 00449 /* Called for all hardware families */ 00450 static int __ath9k_hw_init(struct ath_hw *ah) 00451 { 00452 struct ath_common *common = ath9k_hw_common(ah); 00453 int r = 0; 00454 00455 ath9k_hw_read_revisions(ah); 00456 00457 /* 00458 * Read back AR_WA into a permanent copy and set bits 14 and 17. 00459 * We need to do this to avoid RMW of this register. We cannot 00460 * read the reg when chip is asleep. 00461 */ 00462 ah->WARegVal = REG_READ(ah, AR_WA); 00463 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 00464 AR_WA_ASPM_TIMER_BASED_DISABLE); 00465 00466 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 00467 DBG("ath9k: Couldn't reset chip\n"); 00468 return -EIO; 00469 } 00470 00471 ath9k_hw_init_defaults(ah); 00472 ath9k_hw_init_config(ah); 00473 00474 ath9k_hw_attach_ops(ah); 00475 00476 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 00477 DBG("ath9k: Couldn't wakeup chip\n"); 00478 return -EIO; 00479 } 00480 00481 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 00482 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 00483 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 00484 !ah->is_pciexpress)) { 00485 ah->config.serialize_regmode = 00486 SER_REG_MODE_ON; 00487 } else { 00488 ah->config.serialize_regmode = 00489 SER_REG_MODE_OFF; 00490 } 00491 } 00492 00493 DBG2("ath9k: serialize_regmode is %d\n", 00494 ah->config.serialize_regmode); 00495 00496 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 00497 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 00498 else 00499 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 00500 00501 switch (ah->hw_version.macVersion) { 00502 case AR_SREV_VERSION_5416_PCI: 00503 case AR_SREV_VERSION_5416_PCIE: 00504 case AR_SREV_VERSION_9160: 00505 case AR_SREV_VERSION_9100: 00506 case AR_SREV_VERSION_9280: 00507 case AR_SREV_VERSION_9285: 00508 case AR_SREV_VERSION_9287: 00509 case AR_SREV_VERSION_9271: 00510 case AR_SREV_VERSION_9300: 00511 case AR_SREV_VERSION_9485: 00512 case AR_SREV_VERSION_9340: 00513 break; 00514 default: 00515 DBG("ath9k: " 00516 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 00517 ah->hw_version.macVersion, ah->hw_version.macRev); 00518 return -EOPNOTSUPP; 00519 } 00520 00521 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah)) 00522 ah->is_pciexpress = 0; 00523 00524 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 00525 ath9k_hw_init_cal_settings(ah); 00526 00527 ah->ani_function = ATH9K_ANI_ALL; 00528 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 00529 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 00530 if (!AR_SREV_9300_20_OR_LATER(ah)) 00531 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 00532 00533 ath9k_hw_init_mode_regs(ah); 00534 00535 00536 if (ah->is_pciexpress) 00537 ath9k_hw_configpcipowersave(ah, 0, 0); 00538 else 00539 ath9k_hw_disablepcie(ah); 00540 00541 if (!AR_SREV_9300_20_OR_LATER(ah)) 00542 ar9002_hw_cck_chan14_spread(ah); 00543 00544 r = ath9k_hw_post_init(ah); 00545 if (r) 00546 return r; 00547 00548 ath9k_hw_init_mode_gain_regs(ah); 00549 r = ath9k_hw_fill_cap_info(ah); 00550 if (r) 00551 return r; 00552 00553 r = ath9k_hw_init_macaddr(ah); 00554 if (r) { 00555 DBG("ath9k: Failed to initialize MAC address\n"); 00556 return r; 00557 } 00558 00559 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 00560 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 00561 else 00562 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 00563 00564 common->state = ATH_HW_INITIALIZED; 00565 00566 return 0; 00567 } 00568 00569 int ath9k_hw_init(struct ath_hw *ah) 00570 { 00571 int ret; 00572 struct ath_common *common = ath9k_hw_common(ah); 00573 00574 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 00575 switch (ah->hw_version.devid) { 00576 case AR5416_DEVID_PCI: 00577 case AR5416_DEVID_PCIE: 00578 case AR5416_AR9100_DEVID: 00579 case AR9160_DEVID_PCI: 00580 case AR9280_DEVID_PCI: 00581 case AR9280_DEVID_PCIE: 00582 case AR9285_DEVID_PCIE: 00583 case AR9287_DEVID_PCI: 00584 case AR9287_DEVID_PCIE: 00585 case AR2427_DEVID_PCIE: 00586 case AR9300_DEVID_PCIE: 00587 case AR9300_DEVID_AR9485_PCIE: 00588 case AR9300_DEVID_AR9340: 00589 break; 00590 default: 00591 if (common->bus_ops->ath_bus_type == ATH_USB) 00592 break; 00593 DBG("ath9k: Hardware device ID 0x%04x not supported\n", 00594 ah->hw_version.devid); 00595 return -EOPNOTSUPP; 00596 } 00597 00598 ret = __ath9k_hw_init(ah); 00599 if (ret) { 00600 DBG("ath9k: " 00601 "Unable to initialize hardware; initialization status: %d\n", 00602 ret); 00603 return ret; 00604 } 00605 00606 return 0; 00607 } 00608 00609 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 00610 { 00611 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 00612 udelay(100); 00613 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 00614 00615 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 00616 udelay(100); 00617 00618 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 00619 } 00620 00621 static void ath9k_hw_init_pll(struct ath_hw *ah, 00622 struct ath9k_channel *chan) 00623 { 00624 u32 pll; 00625 00626 if (AR_SREV_9485(ah)) { 00627 00628 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 00629 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00630 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 00631 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00632 AR_CH0_DPLL2_KD, 0x40); 00633 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00634 AR_CH0_DPLL2_KI, 0x4); 00635 00636 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 00637 AR_CH0_BB_DPLL1_REFDIV, 0x5); 00638 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 00639 AR_CH0_BB_DPLL1_NINI, 0x58); 00640 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 00641 AR_CH0_BB_DPLL1_NFRAC, 0x0); 00642 00643 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00644 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 00645 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00646 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 00647 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00648 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 00649 00650 /* program BB PLL phase_shift to 0x6 */ 00651 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 00652 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 00653 00654 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 00655 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 00656 udelay(1000); 00657 } else if (AR_SREV_9340(ah)) { 00658 u32 regval, pll2_divint, pll2_divfrac, refdiv; 00659 00660 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 00661 udelay(1000); 00662 00663 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 00664 udelay(100); 00665 00666 if (ah->is_clk_25mhz) { 00667 pll2_divint = 0x54; 00668 pll2_divfrac = 0x1eb85; 00669 refdiv = 3; 00670 } else { 00671 pll2_divint = 88; 00672 pll2_divfrac = 0; 00673 refdiv = 5; 00674 } 00675 00676 regval = REG_READ(ah, AR_PHY_PLL_MODE); 00677 regval |= (0x1 << 16); 00678 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 00679 udelay(100); 00680 00681 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 00682 (pll2_divint << 18) | pll2_divfrac); 00683 udelay(100); 00684 00685 regval = REG_READ(ah, AR_PHY_PLL_MODE); 00686 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 00687 (0x4 << 26) | (0x18 << 19); 00688 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 00689 REG_WRITE(ah, AR_PHY_PLL_MODE, 00690 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 00691 udelay(1000); 00692 } 00693 00694 pll = ath9k_hw_compute_pll_control(ah, chan); 00695 00696 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 00697 00698 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 00699 udelay(1000); 00700 00701 /* Switch the core clock for ar9271 to 117Mhz */ 00702 if (AR_SREV_9271(ah)) { 00703 udelay(500); 00704 REG_WRITE(ah, 0x50040, 0x304); 00705 } 00706 00707 udelay(RTC_PLL_SETTLE_DELAY); 00708 00709 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 00710 00711 if (AR_SREV_9340(ah)) { 00712 if (ah->is_clk_25mhz) { 00713 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 00714 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 00715 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 00716 } else { 00717 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 00718 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 00719 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 00720 } 00721 udelay(100); 00722 } 00723 } 00724 00725 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah) 00726 { 00727 u32 sync_default = AR_INTR_SYNC_DEFAULT; 00728 u32 imr_reg = AR_IMR_TXERR | 00729 AR_IMR_TXURN | 00730 AR_IMR_RXERR | 00731 AR_IMR_RXORN;; 00732 00733 if (AR_SREV_9340(ah)) 00734 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 00735 00736 if (AR_SREV_9300_20_OR_LATER(ah)) { 00737 imr_reg |= AR_IMR_RXOK_HP; 00738 if (ah->config.rx_intr_mitigation) 00739 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 00740 else 00741 imr_reg |= AR_IMR_RXOK_LP; 00742 00743 } else { 00744 if (ah->config.rx_intr_mitigation) 00745 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 00746 else 00747 imr_reg |= AR_IMR_RXOK; 00748 } 00749 00750 if (ah->config.tx_intr_mitigation) 00751 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 00752 else 00753 imr_reg |= AR_IMR_TXOK; 00754 00755 ENABLE_REGWRITE_BUFFER(ah); 00756 00757 REG_WRITE(ah, AR_IMR, imr_reg); 00758 // ah->imrs2_reg |= AR_IMR_S2_GTT; 00759 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 00760 00761 if (!AR_SREV_9100(ah)) { 00762 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 00763 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 00764 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 00765 } 00766 00767 REGWRITE_BUFFER_FLUSH(ah); 00768 00769 if (AR_SREV_9300_20_OR_LATER(ah)) { 00770 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 00771 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 00772 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 00773 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 00774 } 00775 } 00776 00777 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 00778 { 00779 u32 val = ath9k_hw_mac_to_clks(ah, us); 00780 val = min(val, (u32) 0xFFFF); 00781 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 00782 } 00783 00784 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 00785 { 00786 u32 val = ath9k_hw_mac_to_clks(ah, us); 00787 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 00788 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 00789 } 00790 00791 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 00792 { 00793 u32 val = ath9k_hw_mac_to_clks(ah, us); 00794 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 00795 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 00796 } 00797 00798 static int ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 00799 { 00800 if (tu > 0xFFFF) { 00801 DBG("ath9k: " 00802 "bad global tx timeout %d\n", tu); 00803 ah->globaltxtimeout = (u32) -1; 00804 return 0; 00805 } else { 00806 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 00807 ah->globaltxtimeout = tu; 00808 return 1; 00809 } 00810 } 00811 00812 void ath9k_hw_init_global_settings(struct ath_hw *ah) 00813 { 00814 int acktimeout; 00815 int slottime; 00816 int sifstime; 00817 00818 DBG2("ath9k: ah->misc_mode 0x%x\n", 00819 ah->misc_mode); 00820 00821 if (ah->misc_mode != 0) 00822 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 00823 00824 if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_5GHZ) 00825 sifstime = 16; 00826 else 00827 sifstime = 10; 00828 00829 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 00830 slottime = ah->slottime + 3 * ah->coverage_class; 00831 acktimeout = slottime + sifstime; 00832 00833 /* 00834 * Workaround for early ACK timeouts, add an offset to match the 00835 * initval's 64us ack timeout value. 00836 * This was initially only meant to work around an issue with delayed 00837 * BA frames in some implementations, but it has been found to fix ACK 00838 * timeout issues in other cases as well. 00839 */ 00840 if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_2GHZ) 00841 acktimeout += 64 - sifstime - ah->slottime; 00842 00843 ath9k_hw_setslottime(ah, ah->slottime); 00844 ath9k_hw_set_ack_timeout(ah, acktimeout); 00845 ath9k_hw_set_cts_timeout(ah, acktimeout); 00846 if (ah->globaltxtimeout != (u32) -1) 00847 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 00848 } 00849 00850 void ath9k_hw_deinit(struct ath_hw *ah) 00851 { 00852 struct ath_common *common = ath9k_hw_common(ah); 00853 00854 if (common->state < ATH_HW_INITIALIZED) 00855 goto free_hw; 00856 00857 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 00858 00859 free_hw: 00860 ath9k_hw_rf_free_ext_banks(ah); 00861 } 00862 00863 /*******/ 00864 /* INI */ 00865 /*******/ 00866 00867 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 00868 { 00869 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 00870 00871 if (IS_CHAN_B(chan)) 00872 ctl |= CTL_11B; 00873 else if (IS_CHAN_G(chan)) 00874 ctl |= CTL_11G; 00875 else 00876 ctl |= CTL_11A; 00877 00878 return ctl; 00879 } 00880 00881 /****************************************/ 00882 /* Reset and Channel Switching Routines */ 00883 /****************************************/ 00884 00885 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 00886 { 00887 struct ath_common *common = ath9k_hw_common(ah); 00888 00889 ENABLE_REGWRITE_BUFFER(ah); 00890 00891 /* 00892 * set AHB_MODE not to do cacheline prefetches 00893 */ 00894 if (!AR_SREV_9300_20_OR_LATER(ah)) 00895 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 00896 00897 /* 00898 * let mac dma reads be in 128 byte chunks 00899 */ 00900 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 00901 00902 REGWRITE_BUFFER_FLUSH(ah); 00903 00904 /* 00905 * Restore TX Trigger Level to its pre-reset value. 00906 * The initial value depends on whether aggregation is enabled, and is 00907 * adjusted whenever underruns are detected. 00908 */ 00909 if (!AR_SREV_9300_20_OR_LATER(ah)) 00910 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 00911 00912 ENABLE_REGWRITE_BUFFER(ah); 00913 00914 /* 00915 * let mac dma writes be in 128 byte chunks 00916 */ 00917 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 00918 00919 /* 00920 * Setup receive FIFO threshold to hold off TX activities 00921 */ 00922 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 00923 00924 if (AR_SREV_9300_20_OR_LATER(ah)) { 00925 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 00926 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 00927 00928 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 00929 ah->caps.rx_status_len); 00930 } 00931 00932 /* 00933 * reduce the number of usable entries in PCU TXBUF to avoid 00934 * wrap around issues. 00935 */ 00936 if (AR_SREV_9285(ah)) { 00937 /* For AR9285 the number of Fifos are reduced to half. 00938 * So set the usable tx buf size also to half to 00939 * avoid data/delimiter underruns 00940 */ 00941 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 00942 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 00943 } else if (!AR_SREV_9271(ah)) { 00944 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 00945 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 00946 } 00947 00948 REGWRITE_BUFFER_FLUSH(ah); 00949 00950 if (AR_SREV_9300_20_OR_LATER(ah)) 00951 ath9k_hw_reset_txstatus_ring(ah); 00952 } 00953 00954 static void ath9k_hw_set_operating_mode(struct ath_hw *ah) 00955 { 00956 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 00957 u32 set = AR_STA_ID1_KSRCH_MODE; 00958 00959 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 00960 00961 REG_RMW(ah, AR_STA_ID1, set, mask); 00962 } 00963 00964 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled, 00965 u32 *coef_mantissa, u32 *coef_exponent) 00966 { 00967 u32 coef_exp, coef_man; 00968 00969 for (coef_exp = 31; coef_exp > 0; coef_exp--) 00970 if ((coef_scaled >> coef_exp) & 0x1) 00971 break; 00972 00973 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 00974 00975 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 00976 00977 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 00978 *coef_exponent = coef_exp - 16; 00979 } 00980 00981 static int ath9k_hw_set_reset(struct ath_hw *ah, int type) 00982 { 00983 u32 rst_flags; 00984 u32 tmpReg; 00985 00986 if (AR_SREV_9100(ah)) { 00987 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 00988 AR_RTC_DERIVED_CLK_PERIOD, 1); 00989 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 00990 } 00991 00992 ENABLE_REGWRITE_BUFFER(ah); 00993 00994 if (AR_SREV_9300_20_OR_LATER(ah)) { 00995 REG_WRITE(ah, AR_WA, ah->WARegVal); 00996 udelay(10); 00997 } 00998 00999 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 01000 AR_RTC_FORCE_WAKE_ON_INT); 01001 01002 if (AR_SREV_9100(ah)) { 01003 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 01004 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 01005 } else { 01006 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 01007 if (tmpReg & 01008 (AR_INTR_SYNC_LOCAL_TIMEOUT | 01009 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 01010 u32 val; 01011 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 01012 01013 val = AR_RC_HOSTIF; 01014 if (!AR_SREV_9300_20_OR_LATER(ah)) 01015 val |= AR_RC_AHB; 01016 REG_WRITE(ah, AR_RC, val); 01017 01018 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 01019 REG_WRITE(ah, AR_RC, AR_RC_AHB); 01020 01021 rst_flags = AR_RTC_RC_MAC_WARM; 01022 if (type == ATH9K_RESET_COLD) 01023 rst_flags |= AR_RTC_RC_MAC_COLD; 01024 } 01025 01026 REG_WRITE(ah, AR_RTC_RC, rst_flags); 01027 01028 REGWRITE_BUFFER_FLUSH(ah); 01029 01030 udelay(50); 01031 01032 REG_WRITE(ah, AR_RTC_RC, 0); 01033 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 01034 DBG("ath9k: " 01035 "RTC stuck in MAC reset\n"); 01036 return 0; 01037 } 01038 01039 if (!AR_SREV_9100(ah)) 01040 REG_WRITE(ah, AR_RC, 0); 01041 01042 if (AR_SREV_9100(ah)) 01043 udelay(50); 01044 01045 return 1; 01046 } 01047 01048 static int ath9k_hw_set_reset_power_on(struct ath_hw *ah) 01049 { 01050 ENABLE_REGWRITE_BUFFER(ah); 01051 01052 if (AR_SREV_9300_20_OR_LATER(ah)) { 01053 REG_WRITE(ah, AR_WA, ah->WARegVal); 01054 udelay(10); 01055 } 01056 01057 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 01058 AR_RTC_FORCE_WAKE_ON_INT); 01059 01060 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 01061 REG_WRITE(ah, AR_RC, AR_RC_AHB); 01062 01063 REG_WRITE(ah, AR_RTC_RESET, 0); 01064 01065 REGWRITE_BUFFER_FLUSH(ah); 01066 01067 if (!AR_SREV_9300_20_OR_LATER(ah)) 01068 udelay(2); 01069 01070 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 01071 REG_WRITE(ah, AR_RC, 0); 01072 01073 REG_WRITE(ah, AR_RTC_RESET, 1); 01074 01075 if (!ath9k_hw_wait(ah, 01076 AR_RTC_STATUS, 01077 AR_RTC_STATUS_M, 01078 AR_RTC_STATUS_ON, 01079 AH_WAIT_TIMEOUT)) { 01080 DBG("ath9k: " 01081 "RTC not waking up\n"); 01082 return 0; 01083 } 01084 01085 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 01086 } 01087 01088 static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 01089 { 01090 if (AR_SREV_9300_20_OR_LATER(ah)) { 01091 REG_WRITE(ah, AR_WA, ah->WARegVal); 01092 udelay(10); 01093 } 01094 01095 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 01096 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 01097 01098 switch (type) { 01099 case ATH9K_RESET_POWER_ON: 01100 return ath9k_hw_set_reset_power_on(ah); 01101 case ATH9K_RESET_WARM: 01102 case ATH9K_RESET_COLD: 01103 return ath9k_hw_set_reset(ah, type); 01104 default: 01105 return 0; 01106 } 01107 } 01108 01109 static int ath9k_hw_chip_reset(struct ath_hw *ah, 01110 struct ath9k_channel *chan) 01111 { 01112 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 01113 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 01114 return 0; 01115 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 01116 return 0; 01117 01118 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 01119 return 0; 01120 01121 ah->chip_fullsleep = 0; 01122 ath9k_hw_init_pll(ah, chan); 01123 ath9k_hw_set_rfmode(ah, chan); 01124 01125 return 1; 01126 } 01127 01128 static int ath9k_hw_channel_change(struct ath_hw *ah, 01129 struct ath9k_channel *chan) 01130 { 01131 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 01132 struct net80211_channel *channel = chan->chan; 01133 u32 qnum; 01134 int r; 01135 01136 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 01137 if (ath9k_hw_numtxpending(ah, qnum)) { 01138 DBG("ath9k: " 01139 "Transmit frames pending on queue %d\n", qnum); 01140 return 0; 01141 } 01142 } 01143 01144 if (!ath9k_hw_rfbus_req(ah)) { 01145 DBG("ath9k: Could not kill baseband RX\n"); 01146 return 0; 01147 } 01148 01149 ath9k_hw_set_channel_regs(ah, chan); 01150 01151 r = ath9k_hw_rf_set_freq(ah, chan); 01152 if (r) { 01153 DBG("ath9k: Failed to set channel\n"); 01154 return 0; 01155 } 01156 ath9k_hw_set_clockrate(ah); 01157 01158 ah->eep_ops->set_txpower(ah, chan, 01159 ath9k_regd_get_ctl(regulatory, chan), 01160 0, 01161 channel->maxpower * 2, 01162 min((u32) MAX_RATE_POWER, 01163 (u32) regulatory->power_limit), 0); 01164 01165 ath9k_hw_rfbus_done(ah); 01166 01167 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 01168 ath9k_hw_set_delta_slope(ah, chan); 01169 01170 ath9k_hw_spur_mitigate_freq(ah, chan); 01171 01172 return 1; 01173 } 01174 01175 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 01176 { 01177 u32 gpio_mask = ah->gpio_mask; 01178 int i; 01179 01180 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 01181 if (!(gpio_mask & 1)) 01182 continue; 01183 01184 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 01185 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 01186 } 01187 } 01188 01189 int ath9k_hw_check_alive(struct ath_hw *ah) 01190 { 01191 int count = 50; 01192 u32 reg; 01193 01194 if (AR_SREV_9285_12_OR_LATER(ah)) 01195 return 1; 01196 01197 do { 01198 reg = REG_READ(ah, AR_OBS_BUS_1); 01199 01200 if ((reg & 0x7E7FFFEF) == 0x00702400) 01201 continue; 01202 01203 switch (reg & 0x7E000B00) { 01204 case 0x1E000000: 01205 case 0x52000B00: 01206 case 0x18000B00: 01207 continue; 01208 default: 01209 return 1; 01210 } 01211 } while (count-- > 0); 01212 01213 return 0; 01214 } 01215 01216 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 01217 struct ath9k_hw_cal_data *caldata, int bChannelChange) 01218 { 01219 struct ath_common *common = ath9k_hw_common(ah); 01220 u32 saveLedState; 01221 struct ath9k_channel *curchan = ah->curchan; 01222 u32 saveDefAntenna; 01223 u32 macStaId1; 01224 int i, r; 01225 01226 ah->txchainmask = common->tx_chainmask; 01227 ah->rxchainmask = common->rx_chainmask; 01228 01229 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 01230 return -EIO; 01231 01232 if (curchan && !ah->chip_fullsleep) 01233 ath9k_hw_getnf(ah, curchan); 01234 01235 ah->caldata = caldata; 01236 if (caldata && 01237 (chan->channel != caldata->channel || 01238 (chan->channelFlags & ~CHANNEL_CW_INT) != 01239 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 01240 /* Operating channel changed, reset channel calibration data */ 01241 memset(caldata, 0, sizeof(*caldata)); 01242 ath9k_init_nfcal_hist_buffer(ah, chan); 01243 } 01244 01245 if (bChannelChange && 01246 (ah->chip_fullsleep != 1) && 01247 (ah->curchan != NULL) && 01248 (chan->channel != ah->curchan->channel) && 01249 ((chan->channelFlags & CHANNEL_ALL) == 01250 (ah->curchan->channelFlags & CHANNEL_ALL)) && 01251 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 01252 01253 if (ath9k_hw_channel_change(ah, chan)) { 01254 ath9k_hw_loadnf(ah, ah->curchan); 01255 ath9k_hw_start_nfcal(ah, 1); 01256 if (AR_SREV_9271(ah)) 01257 ar9002_hw_load_ani_reg(ah, chan); 01258 return 0; 01259 } 01260 } 01261 01262 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 01263 if (saveDefAntenna == 0) 01264 saveDefAntenna = 1; 01265 01266 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 01267 01268 saveLedState = REG_READ(ah, AR_CFG_LED) & 01269 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 01270 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 01271 01272 ath9k_hw_mark_phy_inactive(ah); 01273 01274 ah->paprd_table_write_done = 0; 01275 01276 /* Only required on the first reset */ 01277 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 01278 REG_WRITE(ah, 01279 AR9271_RESET_POWER_DOWN_CONTROL, 01280 AR9271_RADIO_RF_RST); 01281 udelay(50); 01282 } 01283 01284 if (!ath9k_hw_chip_reset(ah, chan)) { 01285 DBG("ath9k: Chip reset failed\n"); 01286 return -EINVAL; 01287 } 01288 01289 /* Only required on the first reset */ 01290 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 01291 ah->htc_reset_init = 0; 01292 REG_WRITE(ah, 01293 AR9271_RESET_POWER_DOWN_CONTROL, 01294 AR9271_GATE_MAC_CTL); 01295 udelay(50); 01296 } 01297 01298 if (AR_SREV_9280_20_OR_LATER(ah)) 01299 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 01300 01301 if (!AR_SREV_9300_20_OR_LATER(ah)) 01302 ar9002_hw_enable_async_fifo(ah); 01303 01304 r = ath9k_hw_process_ini(ah, chan); 01305 if (r) 01306 return r; 01307 01308 /* Setup MFP options for CCMP */ 01309 if (AR_SREV_9280_20_OR_LATER(ah)) { 01310 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 01311 * frames when constructing CCMP AAD. */ 01312 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 01313 0xc7ff); 01314 ah->sw_mgmt_crypto = 0; 01315 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 01316 /* Disable hardware crypto for management frames */ 01317 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 01318 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 01319 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 01320 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 01321 ah->sw_mgmt_crypto = 1; 01322 } else 01323 ah->sw_mgmt_crypto = 1; 01324 01325 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 01326 ath9k_hw_set_delta_slope(ah, chan); 01327 01328 ath9k_hw_spur_mitigate_freq(ah, chan); 01329 ah->eep_ops->set_board_values(ah, chan); 01330 01331 ENABLE_REGWRITE_BUFFER(ah); 01332 01333 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 01334 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 01335 | macStaId1 01336 | AR_STA_ID1_RTS_USE_DEF 01337 | (ah->config. 01338 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 01339 | ah->sta_id1_defaults); 01340 ath_hw_setbssidmask(common); 01341 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 01342 ath9k_hw_write_associd(ah); 01343 REG_WRITE(ah, AR_ISR, ~0); 01344 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 01345 01346 REGWRITE_BUFFER_FLUSH(ah); 01347 01348 ath9k_hw_set_operating_mode(ah); 01349 01350 r = ath9k_hw_rf_set_freq(ah, chan); 01351 if (r) 01352 return r; 01353 01354 ath9k_hw_set_clockrate(ah); 01355 01356 ENABLE_REGWRITE_BUFFER(ah); 01357 01358 for (i = 0; i < AR_NUM_DCU; i++) 01359 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 01360 01361 REGWRITE_BUFFER_FLUSH(ah); 01362 01363 ah->intr_txqs = 0; 01364 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 01365 ath9k_hw_resettxqueue(ah, i); 01366 01367 ath9k_hw_init_interrupt_masks(ah); 01368 ath9k_hw_ani_cache_ini_regs(ah); 01369 01370 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 01371 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 01372 01373 ath9k_hw_init_global_settings(ah); 01374 01375 if (!AR_SREV_9300_20_OR_LATER(ah)) { 01376 ar9002_hw_update_async_fifo(ah); 01377 ar9002_hw_enable_wep_aggregation(ah); 01378 } 01379 01380 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 01381 01382 ath9k_hw_set_dma(ah); 01383 01384 REG_WRITE(ah, AR_OBS, 8); 01385 01386 if (ah->config.rx_intr_mitigation) { 01387 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 01388 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 01389 } 01390 01391 if (ah->config.tx_intr_mitigation) { 01392 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 01393 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 01394 } 01395 01396 ath9k_hw_init_bb(ah, chan); 01397 01398 if (!ath9k_hw_init_cal(ah, chan)) 01399 return -EIO; 01400 01401 ENABLE_REGWRITE_BUFFER(ah); 01402 01403 ath9k_hw_restore_chainmask(ah); 01404 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 01405 01406 REGWRITE_BUFFER_FLUSH(ah); 01407 01408 /* 01409 * For big endian systems turn on swapping for descriptors 01410 */ 01411 if (AR_SREV_9100(ah)) { 01412 u32 mask; 01413 mask = REG_READ(ah, AR_CFG); 01414 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 01415 DBG2("ath9k: " 01416 "CFG Byte Swap Set 0x%x\n", mask); 01417 } else { 01418 mask = 01419 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 01420 REG_WRITE(ah, AR_CFG, mask); 01421 DBG2("ath9k: " 01422 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 01423 } 01424 } else { 01425 if (common->bus_ops->ath_bus_type == ATH_USB) { 01426 /* Configure AR9271 target WLAN */ 01427 if (AR_SREV_9271(ah)) 01428 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 01429 else 01430 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 01431 } 01432 #if __BYTE_ORDER == __BIG_ENDIAN 01433 else if (AR_SREV_9340(ah)) 01434 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 01435 else 01436 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 01437 #endif 01438 } 01439 01440 if (AR_SREV_9300_20_OR_LATER(ah)) { 01441 ar9003_hw_disable_phy_restart(ah); 01442 } 01443 01444 ath9k_hw_apply_gpio_override(ah); 01445 01446 return 0; 01447 } 01448 01449 /******************************/ 01450 /* Power Management (Chipset) */ 01451 /******************************/ 01452 01453 /* 01454 * Notify Power Mgt is disabled in self-generated frames. 01455 * If requested, force chip to sleep. 01456 */ 01457 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 01458 { 01459 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 01460 if (setChip) { 01461 /* 01462 * Clear the RTC force wake bit to allow the 01463 * mac to go to sleep. 01464 */ 01465 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 01466 AR_RTC_FORCE_WAKE_EN); 01467 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 01468 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 01469 01470 /* Shutdown chip. Active low */ 01471 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 01472 REG_CLR_BIT(ah, (AR_RTC_RESET), 01473 AR_RTC_RESET_EN); 01474 } 01475 01476 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 01477 if (AR_SREV_9300_20_OR_LATER(ah)) 01478 REG_WRITE(ah, AR_WA, 01479 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 01480 } 01481 01482 static int ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 01483 { 01484 u32 val; 01485 int i; 01486 01487 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 01488 if (AR_SREV_9300_20_OR_LATER(ah)) { 01489 REG_WRITE(ah, AR_WA, ah->WARegVal); 01490 udelay(10); 01491 } 01492 01493 if (setChip) { 01494 if ((REG_READ(ah, AR_RTC_STATUS) & 01495 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 01496 if (ath9k_hw_set_reset_reg(ah, 01497 ATH9K_RESET_POWER_ON) != 1) { 01498 return 0; 01499 } 01500 if (!AR_SREV_9300_20_OR_LATER(ah)) 01501 ath9k_hw_init_pll(ah, NULL); 01502 } 01503 if (AR_SREV_9100(ah)) 01504 REG_SET_BIT(ah, AR_RTC_RESET, 01505 AR_RTC_RESET_EN); 01506 01507 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 01508 AR_RTC_FORCE_WAKE_EN); 01509 udelay(50); 01510 01511 for (i = POWER_UP_TIME / 50; i > 0; i--) { 01512 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 01513 if (val == AR_RTC_STATUS_ON) 01514 break; 01515 udelay(50); 01516 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 01517 AR_RTC_FORCE_WAKE_EN); 01518 } 01519 if (i == 0) { 01520 DBG("ath9k: " 01521 "Failed to wakeup in %dus\n", 01522 POWER_UP_TIME / 20); 01523 return 0; 01524 } 01525 } 01526 01527 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 01528 01529 return 1; 01530 } 01531 01532 int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 01533 { 01534 int status = 1, setChip = 1; 01535 static const char *modes[] = { 01536 "AWAKE", 01537 "FULL-SLEEP", 01538 "NETWORK SLEEP", 01539 "UNDEFINED" 01540 }; 01541 01542 if (ah->power_mode == mode) 01543 return status; 01544 01545 DBG2("ath9k: %s -> %s\n", 01546 modes[ah->power_mode], modes[mode]); 01547 01548 switch (mode) { 01549 case ATH9K_PM_AWAKE: 01550 status = ath9k_hw_set_power_awake(ah, setChip); 01551 break; 01552 case ATH9K_PM_FULL_SLEEP: 01553 ath9k_set_power_sleep(ah, setChip); 01554 ah->chip_fullsleep = 1; 01555 break; 01556 default: 01557 DBG("ath9k: Unknown power mode %d\n", mode); 01558 return 0; 01559 } 01560 ah->power_mode = mode; 01561 01562 return status; 01563 } 01564 01565 /*******************/ 01566 /* HW Capabilities */ 01567 /*******************/ 01568 01569 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 01570 { 01571 struct ath9k_hw_capabilities *pCap = &ah->caps; 01572 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 01573 struct ath_common *common = ath9k_hw_common(ah); 01574 01575 u16 eeval; 01576 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 01577 01578 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 01579 regulatory->current_rd = eeval; 01580 01581 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 01582 if (AR_SREV_9285_12_OR_LATER(ah)) 01583 eeval |= AR9285_RDEXT_DEFAULT; 01584 regulatory->current_rd_ext = eeval; 01585 01586 if (ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 01587 if (regulatory->current_rd == 0x64 || 01588 regulatory->current_rd == 0x65) 01589 regulatory->current_rd += 5; 01590 else if (regulatory->current_rd == 0x41) 01591 regulatory->current_rd = 0x43; 01592 DBG2("ath9k: " 01593 "regdomain mapped to 0x%x\n", regulatory->current_rd); 01594 } 01595 01596 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 01597 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 01598 DBG("ath9k: " 01599 "no band has been marked as supported in EEPROM\n"); 01600 return -EINVAL; 01601 } 01602 01603 if (eeval & AR5416_OPFLAGS_11A) 01604 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 01605 01606 if (eeval & AR5416_OPFLAGS_11G) 01607 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 01608 01609 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 01610 /* 01611 * For AR9271 we will temporarilly uses the rx chainmax as read from 01612 * the EEPROM. 01613 */ 01614 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 01615 !(eeval & AR5416_OPFLAGS_11A) && 01616 !(AR_SREV_9271(ah))) 01617 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 01618 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 01619 else if (AR_SREV_9100(ah)) 01620 pCap->rx_chainmask = 0x7; 01621 else 01622 /* Use rx_chainmask from EEPROM. */ 01623 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 01624 01625 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 01626 01627 /* enable key search for every frame in an aggregate */ 01628 if (AR_SREV_9300_20_OR_LATER(ah)) 01629 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 01630 01631 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 01632 01633 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 01634 01635 if (AR_SREV_9271(ah)) 01636 pCap->num_gpio_pins = AR9271_NUM_GPIO; 01637 else if (AR_DEVID_7010(ah)) 01638 pCap->num_gpio_pins = AR7010_NUM_GPIO; 01639 else if (AR_SREV_9285_12_OR_LATER(ah)) 01640 pCap->num_gpio_pins = AR9285_NUM_GPIO; 01641 else if (AR_SREV_9280_20_OR_LATER(ah)) 01642 pCap->num_gpio_pins = AR928X_NUM_GPIO; 01643 else 01644 pCap->num_gpio_pins = AR_NUM_GPIO; 01645 01646 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 01647 pCap->hw_caps |= ATH9K_HW_CAP_CST; 01648 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 01649 } else { 01650 pCap->rts_aggr_limit = (8 * 1024); 01651 } 01652 01653 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 01654 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 01655 ah->rfkill_gpio = 01656 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 01657 ah->rfkill_polarity = 01658 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 01659 01660 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 01661 } 01662 01663 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 01664 01665 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 01666 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 01667 else 01668 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 01669 01670 if (AR_SREV_9300_20_OR_LATER(ah)) { 01671 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 01672 if (!AR_SREV_9485(ah)) 01673 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 01674 01675 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 01676 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 01677 pCap->rx_status_len = sizeof(struct ar9003_rxs); 01678 pCap->tx_desc_len = sizeof(struct ar9003_txc); 01679 pCap->txs_len = sizeof(struct ar9003_txs); 01680 if (!ah->config.paprd_disable && 01681 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 01682 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 01683 } else { 01684 pCap->tx_desc_len = sizeof(struct ath_desc); 01685 if (AR_SREV_9280_20(ah) && 01686 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 01687 AR5416_EEP_MINOR_VER_16) || 01688 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 01689 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 01690 } 01691 01692 if (AR_SREV_9300_20_OR_LATER(ah)) 01693 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 01694 01695 if (AR_SREV_9300_20_OR_LATER(ah)) 01696 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 01697 01698 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 01699 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 01700 01701 if (AR_SREV_9285(ah)) 01702 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 01703 ant_div_ctl1 = 01704 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 01705 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 01706 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 01707 } 01708 if (AR_SREV_9300_20_OR_LATER(ah)) { 01709 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 01710 pCap->hw_caps |= ATH9K_HW_CAP_APM; 01711 } 01712 01713 01714 if (AR_SREV_9485(ah)) { 01715 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 01716 /* 01717 * enable the diversity-combining algorithm only when 01718 * both enable_lna_div and enable_fast_div are set 01719 * Table for Diversity 01720 * ant_div_alt_lnaconf bit 0-1 01721 * ant_div_main_lnaconf bit 2-3 01722 * ant_div_alt_gaintb bit 4 01723 * ant_div_main_gaintb bit 5 01724 * enable_ant_div_lnadiv bit 6 01725 * enable_ant_fast_div bit 7 01726 */ 01727 if ((ant_div_ctl1 >> 0x6) == 0x3) 01728 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 01729 } 01730 01731 if (AR_SREV_9485_10(ah)) { 01732 pCap->pcie_lcr_extsync_en = 1; 01733 pCap->pcie_lcr_offset = 0x80; 01734 } 01735 01736 tx_chainmask = pCap->tx_chainmask; 01737 rx_chainmask = pCap->rx_chainmask; 01738 while (tx_chainmask || rx_chainmask) { 01739 if (tx_chainmask & BIT(0)) 01740 pCap->max_txchains++; 01741 if (rx_chainmask & BIT(0)) 01742 pCap->max_rxchains++; 01743 01744 tx_chainmask >>= 1; 01745 rx_chainmask >>= 1; 01746 } 01747 01748 return 0; 01749 } 01750 01751 /****************************/ 01752 /* GPIO / RFKILL / Antennae */ 01753 /****************************/ 01754 01755 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 01756 u32 gpio, u32 type) 01757 { 01758 int addr; 01759 u32 gpio_shift, tmp; 01760 01761 if (gpio > 11) 01762 addr = AR_GPIO_OUTPUT_MUX3; 01763 else if (gpio > 5) 01764 addr = AR_GPIO_OUTPUT_MUX2; 01765 else 01766 addr = AR_GPIO_OUTPUT_MUX1; 01767 01768 gpio_shift = (gpio % 6) * 5; 01769 01770 if (AR_SREV_9280_20_OR_LATER(ah) 01771 || (addr != AR_GPIO_OUTPUT_MUX1)) { 01772 REG_RMW(ah, addr, (type << gpio_shift), 01773 (0x1f << gpio_shift)); 01774 } else { 01775 tmp = REG_READ(ah, addr); 01776 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 01777 tmp &= ~(0x1f << gpio_shift); 01778 tmp |= (type << gpio_shift); 01779 REG_WRITE(ah, addr, tmp); 01780 } 01781 } 01782 01783 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 01784 { 01785 u32 gpio_shift; 01786 01787 if (AR_DEVID_7010(ah)) { 01788 gpio_shift = gpio; 01789 REG_RMW(ah, AR7010_GPIO_OE, 01790 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 01791 (AR7010_GPIO_OE_MASK << gpio_shift)); 01792 return; 01793 } 01794 01795 gpio_shift = gpio << 1; 01796 REG_RMW(ah, 01797 AR_GPIO_OE_OUT, 01798 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 01799 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 01800 } 01801 01802 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 01803 { 01804 #define MS_REG_READ(x, y) \ 01805 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 01806 01807 if (gpio >= ah->caps.num_gpio_pins) 01808 return 0xffffffff; 01809 01810 if (AR_DEVID_7010(ah)) { 01811 u32 val; 01812 val = REG_READ(ah, AR7010_GPIO_IN); 01813 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 01814 } else if (AR_SREV_9300_20_OR_LATER(ah)) 01815 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 01816 AR_GPIO_BIT(gpio)) != 0; 01817 else if (AR_SREV_9271(ah)) 01818 return MS_REG_READ(AR9271, gpio) != 0; 01819 else if (AR_SREV_9287_11_OR_LATER(ah)) 01820 return MS_REG_READ(AR9287, gpio) != 0; 01821 else if (AR_SREV_9285_12_OR_LATER(ah)) 01822 return MS_REG_READ(AR9285, gpio) != 0; 01823 else if (AR_SREV_9280_20_OR_LATER(ah)) 01824 return MS_REG_READ(AR928X, gpio) != 0; 01825 else 01826 return MS_REG_READ(AR, gpio) != 0; 01827 } 01828 01829 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 01830 u32 ah_signal_type) 01831 { 01832 u32 gpio_shift; 01833 01834 if (AR_DEVID_7010(ah)) { 01835 gpio_shift = gpio; 01836 REG_RMW(ah, AR7010_GPIO_OE, 01837 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 01838 (AR7010_GPIO_OE_MASK << gpio_shift)); 01839 return; 01840 } 01841 01842 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 01843 gpio_shift = 2 * gpio; 01844 REG_RMW(ah, 01845 AR_GPIO_OE_OUT, 01846 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 01847 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 01848 } 01849 01850 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 01851 { 01852 if (AR_DEVID_7010(ah)) { 01853 val = val ? 0 : 1; 01854 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 01855 AR_GPIO_BIT(gpio)); 01856 return; 01857 } 01858 01859 if (AR_SREV_9271(ah)) 01860 val = ~val; 01861 01862 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 01863 AR_GPIO_BIT(gpio)); 01864 } 01865 01866 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 01867 { 01868 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 01869 } 01870 01871 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 01872 { 01873 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 01874 } 01875 01876 /*********************/ 01877 /* General Operation */ 01878 /*********************/ 01879 01880 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 01881 { 01882 u32 bits = REG_READ(ah, AR_RX_FILTER); 01883 u32 phybits = REG_READ(ah, AR_PHY_ERR); 01884 01885 if (phybits & AR_PHY_ERR_RADAR) 01886 bits |= ATH9K_RX_FILTER_PHYRADAR; 01887 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 01888 bits |= ATH9K_RX_FILTER_PHYERR; 01889 01890 return bits; 01891 } 01892 01893 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 01894 { 01895 u32 phybits; 01896 01897 ENABLE_REGWRITE_BUFFER(ah); 01898 01899 REG_WRITE(ah, AR_RX_FILTER, bits); 01900 01901 phybits = 0; 01902 if (bits & ATH9K_RX_FILTER_PHYRADAR) 01903 phybits |= AR_PHY_ERR_RADAR; 01904 if (bits & ATH9K_RX_FILTER_PHYERR) 01905 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 01906 REG_WRITE(ah, AR_PHY_ERR, phybits); 01907 01908 if (phybits) 01909 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 01910 else 01911 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 01912 01913 REGWRITE_BUFFER_FLUSH(ah); 01914 } 01915 01916 int ath9k_hw_phy_disable(struct ath_hw *ah) 01917 { 01918 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 01919 return 0; 01920 01921 ath9k_hw_init_pll(ah, NULL); 01922 return 1; 01923 } 01924 01925 int ath9k_hw_disable(struct ath_hw *ah) 01926 { 01927 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 01928 return 0; 01929 01930 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 01931 return 0; 01932 01933 ath9k_hw_init_pll(ah, NULL); 01934 return 1; 01935 } 01936 01937 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test) 01938 { 01939 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 01940 struct ath9k_channel *chan = ah->curchan; 01941 struct net80211_channel *channel = chan->chan; 01942 01943 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 01944 01945 ah->eep_ops->set_txpower(ah, chan, 01946 ath9k_regd_get_ctl(regulatory, chan), 01947 0, 01948 channel->maxpower * 2, 01949 min((u32) MAX_RATE_POWER, 01950 (u32) regulatory->power_limit), test); 01951 } 01952 01953 void ath9k_hw_setopmode(struct ath_hw *ah) 01954 { 01955 ath9k_hw_set_operating_mode(ah); 01956 } 01957 01958 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 01959 { 01960 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 01961 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 01962 } 01963 01964 void ath9k_hw_write_associd(struct ath_hw *ah) 01965 { 01966 struct ath_common *common = ath9k_hw_common(ah); 01967 01968 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 01969 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 01970 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 01971 } 01972 01973 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 01974 { 01975 u32 macmode; 01976 01977 macmode = 0; 01978 01979 REG_WRITE(ah, AR_2040_MODE, macmode); 01980 } 01981 01982 static struct { 01983 u32 version; 01984 const char * name; 01985 } ath_mac_bb_names[] = { 01986 /* Devices with external radios */ 01987 { AR_SREV_VERSION_5416_PCI, "5416" }, 01988 { AR_SREV_VERSION_5416_PCIE, "5418" }, 01989 { AR_SREV_VERSION_9100, "9100" }, 01990 { AR_SREV_VERSION_9160, "9160" }, 01991 /* Single-chip solutions */ 01992 { AR_SREV_VERSION_9280, "9280" }, 01993 { AR_SREV_VERSION_9285, "9285" }, 01994 { AR_SREV_VERSION_9287, "9287" }, 01995 { AR_SREV_VERSION_9271, "9271" }, 01996 { AR_SREV_VERSION_9300, "9300" }, 01997 { AR_SREV_VERSION_9485, "9485" }, 01998 }; 01999 02000 /* For devices with external radios */ 02001 static struct { 02002 u16 version; 02003 const char * name; 02004 } ath_rf_names[] = { 02005 { 0, "5133" }, 02006 { AR_RAD5133_SREV_MAJOR, "5133" }, 02007 { AR_RAD5122_SREV_MAJOR, "5122" }, 02008 { AR_RAD2133_SREV_MAJOR, "2133" }, 02009 { AR_RAD2122_SREV_MAJOR, "2122" } 02010 }; 02011 02012 /* 02013 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 02014 */ 02015 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 02016 { 02017 unsigned int i; 02018 02019 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 02020 if (ath_mac_bb_names[i].version == mac_bb_version) { 02021 return ath_mac_bb_names[i].name; 02022 } 02023 } 02024 02025 return "????"; 02026 } 02027 02028 /* 02029 * Return the RF name. "????" is returned if the RF is unknown. 02030 * Used for devices with external radios. 02031 */ 02032 static const char *ath9k_hw_rf_name(u16 rf_version) 02033 { 02034 unsigned int i; 02035 02036 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 02037 if (ath_rf_names[i].version == rf_version) { 02038 return ath_rf_names[i].name; 02039 } 02040 } 02041 02042 return "????"; 02043 } 02044 02045 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 02046 { 02047 int used; 02048 02049 /* chipsets >= AR9280 are single-chip */ 02050 if (AR_SREV_9280_20_OR_LATER(ah)) { 02051 used = snprintf(hw_name, len, 02052 "Atheros AR%s Rev:%x", 02053 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 02054 ah->hw_version.macRev); 02055 } 02056 else { 02057 used = snprintf(hw_name, len, 02058 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 02059 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 02060 ah->hw_version.macRev, 02061 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 02062 AR_RADIO_SREV_MAJOR)), 02063 ah->hw_version.phyRev); 02064 } 02065 02066 hw_name[used] = '\0'; 02067 }