iPXE
Data Structures | Defines | Functions
intelxl.h File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/pcimsix.h>

Go to the source code of this file.

Data Structures

struct  intelxl_admin_offsets
 Admin queue register offsets. More...
struct  intelxl_admin_buffer_params
 Admin queue data buffer command parameters. More...
struct  intelxl_admin_version
 Admin queue version number. More...
struct  intelxl_admin_version_params
 Admin queue Get Version command parameters. More...
struct  intelxl_admin_driver_params
 Admin queue Driver Version command parameters. More...
struct  intelxl_admin_driver_buffer
 Admin queue Driver Version data buffer. More...
struct  intelxl_admin_shutdown_params
 Admin queue Shutdown command parameters. More...
struct  intelxl_admin_clear_pxe_params
 Admin queue Clear PXE Mode command parameters. More...
struct  intelxl_admin_switch_config
 Switching element configuration. More...
struct  intelxl_admin_switch_params
 Admin queue Get Switch Configuration command parameters. More...
struct  intelxl_admin_switch_buffer
 Admin queue Get Switch Configuration data buffer. More...
struct  intelxl_admin_vsi_params
 Admin queue Get VSI Parameters command parameters. More...
struct  intelxl_admin_vsi_buffer
 Admin queue Get VSI Parameters data buffer. More...
struct  intelxl_admin_promisc_params
 Admin queue Set VSI Promiscuous Modes command parameters. More...
struct  intelxl_admin_autoneg_params
 Admin queue Restart Autonegotiation command parameters. More...
struct  intelxl_admin_link_params
 Admin queue Get Link Status command parameters. More...
struct  intelxl_admin_vf_get_resources_buffer
 Admin Queue VF Get Resources data buffer. More...
struct  intelxl_admin_vf_status_link
 Link status change event data. More...
struct  intelxl_admin_vf_status_buffer
 Admin Queue VF Status Change Event data buffer. More...
struct  intelxl_admin_vf_configure_buffer
 Admin Queue VF Configure Queues data buffer. More...
struct  intelxl_admin_vf_irq_map_buffer
 Admin Queue VF IRQ Map data buffer. More...
struct  intelxl_admin_vf_queues_buffer
 Admin Queue VF Enable/Disable Queues data buffer. More...
struct  intelxl_admin_vf_promisc_buffer
 Admin Queue VF Configure Promiscuous Mode data buffer. More...
union  intelxl_admin_params
 Admin queue command parameters. More...
union  intelxl_admin_buffer
 Admin queue data buffer. More...
struct  intelxl_admin_descriptor
 Admin queue descriptor. More...
struct  intelxl_admin
 Admin queue. More...
struct  intelxl_context_line
 Queue context line. More...
struct  intelxl_context_tx
 Transmit queue context. More...
struct  intelxl_context_rx
 Receive queue context. More...
struct  intelxl_tx_data_descriptor
 Transmit data descriptor. More...
struct  intelxl_tx_writeback_descriptor
 Transmit writeback descriptor. More...
union  intelxl_tx_descriptor
 Transmit descriptor. More...
struct  intelxl_rx_data_descriptor
 Receive data descriptor. More...
struct  intelxl_rx_writeback_descriptor
 Receive writeback descriptor. More...
union  intelxl_rx_descriptor
 Packet descriptor. More...
struct  intelxl_ring
 Descriptor ring. More...
union  intelxl_receive_address
 Receive address. More...
struct  intelxl_nic
 An Intel 40Gigabit network card. More...

Defines

#define INTELXL_BAR_SIZE   0x200000
 BAR size.
#define INTELXL_ALIGN   256
 Alignment.
#define INTELXL_ADMIN_CMD   0x080000
 PF Admin Command Queue register block.
#define INTELXL_ADMIN_EVT   0x080080
 PF Admin Event Queue register block.
#define INTELXL_ADMIN_BAL   0x000
 Admin Queue Base Address Low Register (offset)
#define INTELXL_ADMIN_BAH   0x100
 Admin Queue Base Address High Register (offset)
#define INTELXL_ADMIN_LEN   0x200
 Admin Queue Length Register (offset)
#define INTELXL_ADMIN_LEN_LEN(x)   ( (x) << 0 )
 Queue length.
#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL
 Queue enable.
#define INTELXL_ADMIN_HEAD   0x300
 Admin Queue Head Register (offset)
#define INTELXL_ADMIN_TAIL   0x400
 Admin Queue Tail Register (offset)
#define INTELXL_ADMIN_VERSION   0x0001
 Admin queue Get Version command.
#define INTELXL_ADMIN_DRIVER   0x0002
 Admin queue Driver Version command.
#define INTELXL_ADMIN_SHUTDOWN   0x0003
 Admin queue Shutdown command.
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING   0x01
 Driver is unloading.
#define INTELXL_ADMIN_CLEAR_PXE   0x0110
 Admin queue Clear PXE Mode command.
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02
 Clear PXE Mode magic value.
#define INTELXL_ADMIN_SWITCH   0x0200
 Admin queue Get Switch Configuration command.
#define INTELXL_ADMIN_SWITCH_TYPE_VSI   19
 Virtual Station Inferface element type.
#define INTELXL_ADMIN_VSI   0x0212
 Admin queue Get VSI Parameters command.
#define INTELXL_ADMIN_PROMISC   0x0254
 Admin queue Set VSI Promiscuous Modes command.
#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001
 Promiscuous unicast mode.
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST   0x0002
 Promiscuous multicast mode.
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST   0x0004
 Promiscuous broadcast mode.
#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010
 Promiscuous VLAN mode.
#define INTELXL_ADMIN_AUTONEG   0x0605
 Admin queue Restart Autonegotiation command.
#define INTELXL_ADMIN_AUTONEG_FL_RESTART   0x02
 Restart autonegotiation.
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE   0x04
 Enable link.
#define INTELXL_ADMIN_LINK   0x0607
 Admin queue Get Link Status command.
#define INTELXL_ADMIN_LINK_NOTIFY   0x03
 Notify driver of link status changes.
#define INTELXL_ADMIN_LINK_UP   0x01
 Link is up.
#define INTELXL_ADMIN_SEND_TO_PF   0x0801
 Admin queue Send Message to PF command.
#define INTELXL_ADMIN_SEND_TO_VF   0x0802
 Admin queue Send Message to VF command.
#define INTELXL_ADMIN_VF_RESET   0x00000002
 Admin Queue VF Reset opcode.
#define INTELXL_ADMIN_VF_GET_RESOURCES   0x00000003
 Admin Queue VF Get Resources opcode.
#define INTELXL_ADMIN_VF_STATUS   0x00000011
 Admin Queue VF Status Change Event opcode.
#define INTELXL_ADMIN_VF_STATUS_LINK   0x00000001
 Link status change event type.
#define INTELXL_ADMIN_VF_CONFIGURE   0x00000006
 Admin Queue VF Configure Queues opcode.
#define INTELXL_ADMIN_VF_IRQ_MAP   0x00000007
 Admin Queue VF IRQ Map opcode.
#define INTELXL_ADMIN_VF_ENABLE   0x00000008
 Admin Queue VF Enable Queues opcode.
#define INTELXL_ADMIN_VF_DISABLE   0x00000009
 Admin Queue VF Disable Queues opcode.
#define INTELXL_ADMIN_VF_PROMISC   0x0000000e
 Admin Queue VF Configure Promiscuous Mode opcode.
#define INTELXL_ADMIN_FL_DD   0x0001
 Admin descriptor done.
#define INTELXL_ADMIN_FL_CMP   0x0002
 Admin descriptor contains a completion.
#define INTELXL_ADMIN_FL_ERR   0x0004
 Admin descriptor completed in error.
#define INTELXL_ADMIN_FL_RD   0x0400
 Admin descriptor uses data buffer for command parameters.
#define INTELXL_ADMIN_FL_BUF   0x1000
 Admin descriptor uses data buffer.
#define INTELXL_ADMIN_NUM_DESC   4
 Number of admin queue descriptors.
#define INTELXL_ADMIN_MAX_WAIT_MS   100
 Maximum time to wait for an admin request to complete.
#define INTELXL_ADMIN_API_MAJOR   1
 Admin queue API major version.
#define INTELXL_PFCM_LANCTXDATA(x)   ( 0x10c100 + ( 0x80 * (x) ) )
 CMLAN Context Data Register.
#define INTELXL_PFCM_LANCTXCTL   0x10c300
 CMLAN Context Control Register.
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)   ( (x) << 0 )
 Queue number.
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)   ( (x) << 12 )
 Sub-line.
#define INTELXL_PFCM_LANCTXCTL_TYPE(x)   ( (x) << 15 )
 Queue type.
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )
 RX queue type.
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )
 TX queue type.
#define INTELXL_PFCM_LANCTXCTL_OP_CODE(x)   ( (x) << 17 )
 Op code.
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )
 Read context.
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )
 Write context.
#define INTELXL_PFCM_LANCTXSTAT   0x10c380
 CMLAN Context Status Register.
#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL
 Complete.
#define INTELXL_CTX_TX_FL_NEW   0x4000
 New transmit queue context.
#define INTELXL_CTX_TX_BASE(base)   ( (base) >> 7 )
 Transmit queue base address.
#define INTELXL_CTX_TX_COUNT(count)   ( (count) << 1 )
 Transmit queue count.
#define INTELXL_CTX_TX_QSET(qset)   ( (qset) << 4 )
 Transmit queue set.
#define INTELXL_CTX_RX_BASE_COUNT(base, count)   ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
 Receive queue base address and queue count.
#define INTELXL_CTX_RX_LEN(len)   ( (len) >> 1 )
 Receive queue data buffer length.
#define INTELXL_CTX_RX_FL_DSIZE   0x10
 Use 32-byte receive descriptors.
#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20
 Strip CRC from received packets.
#define INTELXL_CTX_RX_MFS(mfs)   ( (mfs) >> 2 )
 Receive queue maximum frame size.
#define INTELXL_CTX_MAX_WAIT_MS   100
 Maximum time to wait for a context operation to complete.
#define INTELXL_QUEUE_ENABLE_DELAY_US   20
 Time to wait for a queue to become enabled.
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US   400
 Time to wait for a transmit queue to become pre-disabled.
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS   1000
 Maximum time to wait for a queue to become disabled.
#define INTELXL_QTX_HEAD(x)   ( 0x0e4000 + ( 0x4 * (x) ) )
 Global Transmit Queue Head register.
#define INTELXL_GLLAN_TXPRE_QDIS(x)   ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
 Global Transmit Pre Queue Disable register.
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)   ( (x) << 0 )
 Queue index.
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL
 Set disable.
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL
 Clear disable.
#define INTELXL_QTX(x)   ( 0x100000 + ( 0x4 * (x) ) )
 Global Transmit Queue register block.
#define INTELXL_QRX(x)   ( 0x120000 + ( 0x4 * (x) ) )
 Global Receive Queue register block.
#define INTELXL_QXX_ENA   0x0000
 Queue Enable Register (offset)
#define INTELXL_QXX_ENA_REQ   0x00000001UL
 Enable request.
#define INTELXL_QXX_ENA_STAT   0x00000004UL
 Enabled status.
#define INTELXL_QXX_CTL   0x4000
 Queue Control Register (offset)
#define INTELXL_QXX_CTL_PFVF_Q(x)   ( (x) << 0 )
 PF/VF queue.
#define INTELXL_QXX_CTL_PFVF_Q_PF   INTELXL_QXX_CTL_PFVF_Q ( 0x2 )
 PF queue.
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)   ( (x) << 2 )
 PF index.
#define INTELXL_QXX_TAIL   0x8000
 Queue Tail Pointer Register (offset)
#define INTELXL_GLLAN_RCTL_0   0x12a500
 Global RLAN Control 0 register.
#define INTELXL_GLLAN_RCTL_0_PXE_MODE   0x00000001UL
 PXE mode.
#define INTELXL_TX_DATA_DTYP   0x0
 Transmit data descriptor type.
#define INTELXL_TX_DATA_EOP   0x10
 Transmit data descriptor end of packet.
#define INTELXL_TX_DATA_RS   0x20
 Transmit data descriptor report status.
#define INTELXL_TX_DATA_JFDI   0x40
 Transmit data descriptor pretty please.
#define INTELXL_TX_DATA_LEN(len)   ( (len) << 2 )
 Transmit data descriptor length.
#define INTELXL_TX_WB_FL_DD   0x01
 Transmit writeback descriptor complete.
#define INTELXL_RX_WB_FL_DD   0x00000001UL
 Receive writeback descriptor complete.
#define INTELXL_RX_WB_FL_VLAN   0x00000004UL
 Receive writeback descriptor VLAN tag present.
#define INTELXL_RX_WB_FL_RXE   0x00080000UL
 Receive writeback descriptor error.
#define INTELXL_RX_WB_LEN(len)   ( ( (len) >> 6 ) & 0x3fff )
 Receive writeback descriptor length.
#define INTELXL_TX_NUM_DESC   64
 Number of transmit descriptors.
#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )
 Transmit descriptor ring maximum fill level.
#define INTELXL_RX_NUM_DESC   32
 Number of receive descriptors.
#define INTELXL_RX_FILL   16
 Receive descriptor ring fill level.
#define INTELXL_PFINT_DYN_CTL0   0x038480
 PF Interrupt Zero Dynamic Control Register.
#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL
 Enable.
#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL
 Acknowledge.
#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL
 Ignore enable.
#define INTELXL_PFINT_LNKLST0   0x038500
 PF Interrupt Zero Linked List Register.
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)   ( (x) << 0 )
 Queue index.
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE   INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )
 End of list.
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x)   ( (x) << 11 )
 Queue type.
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )
 Receive queue.
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )
 Transmit queue.
#define INTELXL_PFINT_ICR0_ENA   0x038800
 PF Interrupt Zero Cause Enablement Register.
#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL
 Admin event.
#define INTELXL_QINT_RQCTL(x)   ( 0x03a000 + ( 0x4 * (x) ) )
 Receive Queue Interrupt Cause Control Register.
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index.
#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )
 End of list.
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type.
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue.
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue.
#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL
 Enable.
#define INTELXL_QINT_TQCTL(x)   ( 0x03c000 + ( 0x4 * (x) ) )
 Transmit Queue Interrupt Cause Control Register.
#define INTELXL_QINT_TQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index.
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )
 End of list.
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type.
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue.
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue.
#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL
 Enable.
#define INTELXL_PFGEN_CTRL   0x092400
 PF Control Register.
#define INTELXL_PFGEN_CTRL_PFSWR   0x00000001UL
 Software Reset.
#define INTELXL_RESET_DELAY_MS   100
 Time to delay for device reset, in milliseconds.
#define INTELXL_PFLAN_QALLOC   0x1c0400
 PF Queue Allocation Register.
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)   ( ( (x) >> 0 ) & 0x7ff )
 First queue.
#define INTELXL_PFLAN_QALLOC_LASTQ(x)   ( ( (x) >> 16 ) & 0x7ff )
 Last queue.
#define INTELXL_PFGEN_PORTNUM   0x1c0480
 PF LAN Port Number Register.
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)   ( ( (x) >> 0 ) & 0x3 )
 Port number.
#define INTELXL_PRTGL_SAL   0x1e2120
 Port MAC Address Low Register.
#define INTELXL_PRTGL_SAH   0x1e2140
 Port MAC Address High Register.
#define INTELXL_PRTGL_SAH_MFS_GET(x)   ( (x) >> 16 )
 Max frame size.
#define INTELXL_PRTGL_SAH_MFS_SET(x)   ( (x) << 16 )
 Max frame size.

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
static void intelxl_init_admin (struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
 Initialise admin queue.
static void intelxl_init_ring (struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
 Initialise descriptor ring.
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci)
 Enable MSI-X dummy interrupt.
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci)
 Disable MSI-X dummy interrupt.
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor.
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer.
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command.
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue.
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues.
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset)
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues.
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring.
void intelxl_free_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers.
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet.
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets.
void intelxlvf_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
 Handle virtual function event.

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.h.


Define Documentation

#define INTELXL_BAR_SIZE   0x200000

BAR size.

Definition at line 19 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_ALIGN   256

Alignment.

No data structure requires greater than 256 byte alignment.

Definition at line 25 of file intelxl.h.

Referenced by intelxl_alloc_admin(), intelxl_alloc_ring(), intelxl_open(), and intelxlvf_open().

#define INTELXL_ADMIN_CMD   0x080000

PF Admin Command Queue register block.

Definition at line 35 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_ADMIN_EVT   0x080080

PF Admin Event Queue register block.

Definition at line 38 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_ADMIN_BAL   0x000

Admin Queue Base Address Low Register (offset)

Definition at line 41 of file intelxl.h.

#define INTELXL_ADMIN_BAH   0x100

Admin Queue Base Address High Register (offset)

Definition at line 44 of file intelxl.h.

#define INTELXL_ADMIN_LEN   0x200

Admin Queue Length Register (offset)

Definition at line 47 of file intelxl.h.

#define INTELXL_ADMIN_LEN_LEN (   x)    ( (x) << 0 )

Queue length.

Definition at line 48 of file intelxl.h.

Referenced by intelxl_enable_admin().

#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL

Queue enable.

Definition at line 49 of file intelxl.h.

Referenced by intelxl_enable_admin(), and intelxlvf_reset_wait_teardown().

#define INTELXL_ADMIN_HEAD   0x300

Admin Queue Head Register (offset)

Definition at line 52 of file intelxl.h.

#define INTELXL_ADMIN_TAIL   0x400

Admin Queue Tail Register (offset)

Definition at line 55 of file intelxl.h.

#define INTELXL_ADMIN_VERSION   0x0001

Admin queue Get Version command.

Definition at line 86 of file intelxl.h.

Referenced by intelxl_admin_version().

#define INTELXL_ADMIN_DRIVER   0x0002

Admin queue Driver Version command.

Definition at line 109 of file intelxl.h.

Referenced by intelxl_admin_driver().

#define INTELXL_ADMIN_SHUTDOWN   0x0003

Admin queue Shutdown command.

Definition at line 134 of file intelxl.h.

Referenced by intelxl_admin_shutdown().

Driver is unloading.

Definition at line 145 of file intelxl.h.

Referenced by intelxl_admin_shutdown().

#define INTELXL_ADMIN_CLEAR_PXE   0x0110

Admin queue Clear PXE Mode command.

Definition at line 148 of file intelxl.h.

Referenced by intelxl_admin_clear_pxe().

#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02

Clear PXE Mode magic value.

Definition at line 159 of file intelxl.h.

Referenced by intelxl_admin_clear_pxe().

#define INTELXL_ADMIN_SWITCH   0x0200

Admin queue Get Switch Configuration command.

Definition at line 162 of file intelxl.h.

Referenced by intelxl_admin_switch().

Virtual Station Inferface element type.

Definition at line 187 of file intelxl.h.

Referenced by intelxl_admin_switch().

#define INTELXL_ADMIN_VSI   0x0212

Admin queue Get VSI Parameters command.

Definition at line 212 of file intelxl.h.

Referenced by intelxl_admin_vsi().

#define INTELXL_ADMIN_PROMISC   0x0254

Admin queue Set VSI Promiscuous Modes command.

Definition at line 239 of file intelxl.h.

Referenced by intelxl_admin_promisc().

#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001

Promiscuous unicast mode.

Definition at line 254 of file intelxl.h.

Referenced by intelxl_admin_promisc(), and intelxlvf_admin_promisc().

Promiscuous multicast mode.

Definition at line 257 of file intelxl.h.

Referenced by intelxl_admin_promisc(), and intelxlvf_admin_promisc().

Promiscuous broadcast mode.

Definition at line 260 of file intelxl.h.

Referenced by intelxl_admin_promisc().

#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010

Promiscuous VLAN mode.

Definition at line 263 of file intelxl.h.

Referenced by intelxl_admin_promisc().

#define INTELXL_ADMIN_AUTONEG   0x0605

Admin queue Restart Autonegotiation command.

Definition at line 266 of file intelxl.h.

Referenced by intelxl_admin_autoneg().

Restart autonegotiation.

Definition at line 277 of file intelxl.h.

Referenced by intelxl_admin_autoneg().

Enable link.

Definition at line 280 of file intelxl.h.

Referenced by intelxl_admin_autoneg().

#define INTELXL_ADMIN_LINK   0x0607

Admin queue Get Link Status command.

Definition at line 283 of file intelxl.h.

Referenced by intelxl_admin_link(), and intelxl_poll_admin().

#define INTELXL_ADMIN_LINK_NOTIFY   0x03

Notify driver of link status changes.

Definition at line 302 of file intelxl.h.

Referenced by intelxl_admin_link().

#define INTELXL_ADMIN_LINK_UP   0x01

Link is up.

Definition at line 305 of file intelxl.h.

Referenced by intelxl_admin_link().

#define INTELXL_ADMIN_SEND_TO_PF   0x0801

Admin queue Send Message to PF command.

Definition at line 308 of file intelxl.h.

Referenced by intelxlvf_admin_command(), and intelxlvf_reset_admin().

#define INTELXL_ADMIN_SEND_TO_VF   0x0802

Admin queue Send Message to VF command.

Definition at line 311 of file intelxl.h.

Referenced by intelxl_poll_admin().

#define INTELXL_ADMIN_VF_RESET   0x00000002

Admin Queue VF Reset opcode.

Definition at line 314 of file intelxl.h.

Referenced by intelxlvf_reset_admin().

#define INTELXL_ADMIN_VF_GET_RESOURCES   0x00000003

Admin Queue VF Get Resources opcode.

Definition at line 317 of file intelxl.h.

Referenced by intelxlvf_admin_get_resources().

#define INTELXL_ADMIN_VF_STATUS   0x00000011

Admin Queue VF Status Change Event opcode.

Definition at line 332 of file intelxl.h.

Referenced by intelxlvf_admin_event().

#define INTELXL_ADMIN_VF_STATUS_LINK   0x00000001

Link status change event type.

Definition at line 335 of file intelxl.h.

Referenced by intelxlvf_admin_status().

#define INTELXL_ADMIN_VF_CONFIGURE   0x00000006

Admin Queue VF Configure Queues opcode.

Definition at line 361 of file intelxl.h.

Referenced by intelxlvf_admin_configure().

#define INTELXL_ADMIN_VF_IRQ_MAP   0x00000007

Admin Queue VF IRQ Map opcode.

Definition at line 417 of file intelxl.h.

Referenced by intelxlvf_admin_irq_map().

#define INTELXL_ADMIN_VF_ENABLE   0x00000008

Admin Queue VF Enable Queues opcode.

Definition at line 445 of file intelxl.h.

Referenced by intelxlvf_admin_queues().

#define INTELXL_ADMIN_VF_DISABLE   0x00000009

Admin Queue VF Disable Queues opcode.

Definition at line 448 of file intelxl.h.

Referenced by intelxlvf_admin_queues(), and intelxlvf_open().

#define INTELXL_ADMIN_VF_PROMISC   0x0000000e

Admin Queue VF Configure Promiscuous Mode opcode.

Definition at line 463 of file intelxl.h.

Referenced by intelxlvf_admin_promisc().

#define INTELXL_ADMIN_FL_DD   0x0001

Admin descriptor done.

Definition at line 545 of file intelxl.h.

Referenced by intelxl_admin_command(), and intelxl_poll_admin().

#define INTELXL_ADMIN_FL_CMP   0x0002

Admin descriptor contains a completion.

Definition at line 548 of file intelxl.h.

Referenced by intelxl_admin_command().

#define INTELXL_ADMIN_FL_ERR   0x0004

Admin descriptor completed in error.

Definition at line 551 of file intelxl.h.

Referenced by intelxl_admin_command().

#define INTELXL_ADMIN_FL_RD   0x0400

Admin descriptor uses data buffer for command parameters.

Definition at line 554 of file intelxl.h.

Referenced by intelxl_admin_driver(), intelxlvf_admin_configure(), intelxlvf_admin_irq_map(), intelxlvf_admin_promisc(), and intelxlvf_admin_queues().

#define INTELXL_ADMIN_FL_BUF   0x1000
#define INTELXL_ADMIN_NUM_DESC   4
#define INTELXL_ADMIN_MAX_WAIT_MS   100

Maximum time to wait for an admin request to complete.

Definition at line 593 of file intelxl.h.

Referenced by intelxl_admin_command().

#define INTELXL_ADMIN_API_MAJOR   1

Admin queue API major version.

Definition at line 596 of file intelxl.h.

Referenced by intelxl_admin_version().

#define INTELXL_PFCM_LANCTXDATA (   x)    ( 0x10c100 + ( 0x80 * (x) ) )

CMLAN Context Data Register.

Definition at line 606 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_PFCM_LANCTXCTL   0x10c300

CMLAN Context Control Register.

Definition at line 609 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM (   x)    ( (x) << 0 )

Queue number.

Definition at line 610 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_PFCM_LANCTXCTL_SUB_LINE (   x)    ( (x) << 12 )

Sub-line.

Definition at line 613 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_PFCM_LANCTXCTL_TYPE (   x)    ( (x) << 15 )

Queue type.

Definition at line 616 of file intelxl.h.

RX queue type.

Definition at line 619 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_context_rx().

TX queue type.

Definition at line 621 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_context_tx().

#define INTELXL_PFCM_LANCTXCTL_OP_CODE (   x)    ( (x) << 17 )

Op code.

Definition at line 623 of file intelxl.h.

Read context.

Definition at line 626 of file intelxl.h.

Referenced by intelxl_context_dump().

Write context.

Definition at line 628 of file intelxl.h.

Referenced by intelxl_context_line().

#define INTELXL_PFCM_LANCTXSTAT   0x10c380

CMLAN Context Status Register.

Definition at line 632 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL

Complete.

Definition at line 633 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

#define INTELXL_CTX_TX_FL_NEW   0x4000

New transmit queue context.

Definition at line 662 of file intelxl.h.

Referenced by intelxl_context_tx().

#define INTELXL_CTX_TX_BASE (   base)    ( (base) >> 7 )

Transmit queue base address.

Definition at line 665 of file intelxl.h.

Referenced by intelxl_context_tx().

#define INTELXL_CTX_TX_COUNT (   count)    ( (count) << 1 )

Transmit queue count.

Definition at line 668 of file intelxl.h.

Referenced by intelxl_context_tx().

#define INTELXL_CTX_TX_QSET (   qset)    ( (qset) << 4 )

Transmit queue set.

Definition at line 671 of file intelxl.h.

Referenced by intelxl_context_tx().

#define INTELXL_CTX_RX_BASE_COUNT (   base,
  count 
)    ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )

Receive queue base address and queue count.

Definition at line 692 of file intelxl.h.

Referenced by intelxl_context_rx().

#define INTELXL_CTX_RX_LEN (   len)    ( (len) >> 1 )

Receive queue data buffer length.

Definition at line 696 of file intelxl.h.

Referenced by intelxl_context_rx().

#define INTELXL_CTX_RX_FL_DSIZE   0x10

Use 32-byte receive descriptors.

Definition at line 699 of file intelxl.h.

Referenced by intelxl_context_rx().

#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20

Strip CRC from received packets.

Definition at line 702 of file intelxl.h.

Referenced by intelxl_context_rx().

#define INTELXL_CTX_RX_MFS (   mfs)    ( (mfs) >> 2 )

Receive queue maximum frame size.

Definition at line 705 of file intelxl.h.

Referenced by intelxl_context_rx().

#define INTELXL_CTX_MAX_WAIT_MS   100

Maximum time to wait for a context operation to complete.

Definition at line 708 of file intelxl.h.

Referenced by intelxl_context_dump(), and intelxl_context_line().

Time to wait for a queue to become enabled.

Definition at line 711 of file intelxl.h.

Referenced by intelxl_enable_ring().

Time to wait for a transmit queue to become pre-disabled.

Definition at line 714 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_open().

Maximum time to wait for a queue to become disabled.

Definition at line 717 of file intelxl.h.

Referenced by intelxl_disable_ring().

#define INTELXL_QTX_HEAD (   x)    ( 0x0e4000 + ( 0x4 * (x) ) )

Global Transmit Queue Head register.

Definition at line 727 of file intelxl.h.

Referenced by intelxl_open().

#define INTELXL_GLLAN_TXPRE_QDIS (   x)    ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )

Global Transmit Pre Queue Disable register.

Definition at line 730 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_open().

#define INTELXL_GLLAN_TXPRE_QDIS_QINDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 731 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_open().

#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL

Set disable.

Definition at line 734 of file intelxl.h.

Referenced by intelxl_close(), and intelxl_open().

#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL

Clear disable.

Definition at line 736 of file intelxl.h.

Referenced by intelxl_open().

#define INTELXL_QTX (   x)    ( 0x100000 + ( 0x4 * (x) ) )

Global Transmit Queue register block.

Definition at line 740 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QRX (   x)    ( 0x120000 + ( 0x4 * (x) ) )

Global Receive Queue register block.

Definition at line 743 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QXX_ENA   0x0000

Queue Enable Register (offset)

Definition at line 746 of file intelxl.h.

Referenced by intelxl_disable_ring(), and intelxl_enable_ring().

#define INTELXL_QXX_ENA_REQ   0x00000001UL

Enable request.

Definition at line 747 of file intelxl.h.

Referenced by intelxl_enable_ring().

#define INTELXL_QXX_ENA_STAT   0x00000004UL

Enabled status.

Definition at line 748 of file intelxl.h.

Referenced by intelxl_disable_ring(), and intelxl_enable_ring().

#define INTELXL_QXX_CTL   0x4000

Queue Control Register (offset)

Definition at line 751 of file intelxl.h.

Referenced by intelxl_open().

#define INTELXL_QXX_CTL_PFVF_Q (   x)    ( (x) << 0 )

PF/VF queue.

Definition at line 752 of file intelxl.h.

PF queue.

Definition at line 753 of file intelxl.h.

Referenced by intelxl_open().

#define INTELXL_QXX_CTL_PFVF_PF_INDX (   x)    ( (x) << 2 )

PF index.

Definition at line 755 of file intelxl.h.

Referenced by intelxl_open().

#define INTELXL_QXX_TAIL   0x8000

Queue Tail Pointer Register (offset)

Definition at line 758 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_GLLAN_RCTL_0   0x12a500

Global RLAN Control 0 register.

Definition at line 761 of file intelxl.h.

Referenced by intelxl_admin_clear_pxe().

#define INTELXL_GLLAN_RCTL_0_PXE_MODE   0x00000001UL

PXE mode.

Definition at line 762 of file intelxl.h.

Referenced by intelxl_admin_clear_pxe().

#define INTELXL_TX_DATA_DTYP   0x0

Transmit data descriptor type.

Definition at line 775 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_TX_DATA_EOP   0x10

Transmit data descriptor end of packet.

Definition at line 778 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_TX_DATA_RS   0x20

Transmit data descriptor report status.

Definition at line 781 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_TX_DATA_JFDI   0x40

Transmit data descriptor pretty please.

This bit is completely missing from older versions of the XL710 datasheet. Later versions describe it innocuously as "reserved, must be 1". Without this bit, everything will appear to work (up to and including the port "transmit good octets" counter), but no packet will actually be sent.

Definition at line 791 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_TX_DATA_LEN (   len)    ( (len) << 2 )

Transmit data descriptor length.

Definition at line 794 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_TX_WB_FL_DD   0x01

Transmit writeback descriptor complete.

Definition at line 807 of file intelxl.h.

Referenced by intelxl_poll_tx().

#define INTELXL_RX_WB_FL_DD   0x00000001UL

Receive writeback descriptor complete.

Definition at line 844 of file intelxl.h.

Referenced by intelxl_poll_rx().

#define INTELXL_RX_WB_FL_VLAN   0x00000004UL

Receive writeback descriptor VLAN tag present.

Definition at line 847 of file intelxl.h.

Referenced by intelxl_poll_rx().

#define INTELXL_RX_WB_FL_RXE   0x00080000UL

Receive writeback descriptor error.

Definition at line 850 of file intelxl.h.

Referenced by intelxl_poll_rx().

#define INTELXL_RX_WB_LEN (   len)    ( ( (len) >> 6 ) & 0x3fff )

Receive writeback descriptor length.

Definition at line 853 of file intelxl.h.

Referenced by intelxl_poll_rx().

#define INTELXL_TX_NUM_DESC   64

Number of transmit descriptors.

Chosen to exceed the receive ring fill level, in order to avoid running out of transmit descriptors when sending TCP ACKs.

Definition at line 915 of file intelxl.h.

Referenced by intelxl_context_tx(), intelxl_poll_tx(), intelxl_probe(), intelxl_transmit(), intelxlvf_admin_configure(), and intelxlvf_probe().

#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 918 of file intelxl.h.

Referenced by intelxl_transmit().

#define INTELXL_RX_NUM_DESC   32

Number of receive descriptors.

Must be a multiple of 32.

Definition at line 924 of file intelxl.h.

Referenced by intelxl_context_rx(), intelxl_empty_rx(), intelxl_poll_rx(), intelxl_probe(), intelxl_refill_rx(), intelxlvf_admin_configure(), and intelxlvf_probe().

#define INTELXL_RX_FILL   16

Receive descriptor ring fill level.

Must be a multiple of 8 and greater than 8.

Definition at line 930 of file intelxl.h.

Referenced by intelxl_refill_rx().

#define INTELXL_PFINT_DYN_CTL0   0x038480

PF Interrupt Zero Dynamic Control Register.

Definition at line 940 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL

Enable.

Definition at line 941 of file intelxl.h.

Referenced by intelxl_poll().

#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL

Acknowledge.

Definition at line 942 of file intelxl.h.

#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL

Ignore enable.

Definition at line 943 of file intelxl.h.

#define INTELXL_PFINT_LNKLST0   0x038500

PF Interrupt Zero Linked List Register.

Definition at line 946 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 947 of file intelxl.h.

Referenced by intelxl_probe().

End of list.

Definition at line 950 of file intelxl.h.

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE (   x)    ( (x) << 11 )

Queue type.

Definition at line 952 of file intelxl.h.

Receive queue.

Definition at line 955 of file intelxl.h.

Referenced by intelxl_probe().

Transmit queue.

Definition at line 957 of file intelxl.h.

#define INTELXL_PFINT_ICR0_ENA   0x038800

PF Interrupt Zero Cause Enablement Register.

Definition at line 961 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL

Admin event.

Definition at line 962 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_RQCTL (   x)    ( 0x03a000 + ( 0x4 * (x) ) )

Receive Queue Interrupt Cause Control Register.

Definition at line 965 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_RQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 966 of file intelxl.h.

Referenced by intelxl_probe().

End of list.

Definition at line 967 of file intelxl.h.

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 969 of file intelxl.h.

Receive queue.

Definition at line 970 of file intelxl.h.

Transmit queue.

Definition at line 972 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 974 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_TQCTL (   x)    ( 0x03c000 + ( 0x4 * (x) ) )

Transmit Queue Interrupt Cause Control Register.

Definition at line 977 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_TQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 978 of file intelxl.h.

End of list.

Definition at line 979 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 981 of file intelxl.h.

Receive queue.

Definition at line 982 of file intelxl.h.

Transmit queue.

Definition at line 984 of file intelxl.h.

#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 986 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFGEN_CTRL   0x092400

PF Control Register.

Definition at line 989 of file intelxl.h.

Referenced by intelxl_reset().

#define INTELXL_PFGEN_CTRL_PFSWR   0x00000001UL

Software Reset.

Definition at line 990 of file intelxl.h.

Referenced by intelxl_reset().

#define INTELXL_RESET_DELAY_MS   100

Time to delay for device reset, in milliseconds.

Definition at line 993 of file intelxl.h.

Referenced by intelxl_reset(), intelxlvf_reset_admin(), and intelxlvf_reset_flr().

#define INTELXL_PFLAN_QALLOC   0x1c0400

PF Queue Allocation Register.

Definition at line 996 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFLAN_QALLOC_FIRSTQ (   x)    ( ( (x) >> 0 ) & 0x7ff )

First queue.

Definition at line 997 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFLAN_QALLOC_LASTQ (   x)    ( ( (x) >> 16 ) & 0x7ff )

Last queue.

Definition at line 1000 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFGEN_PORTNUM   0x1c0480

PF LAN Port Number Register.

Definition at line 1005 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PFGEN_PORTNUM_PORT_NUM (   x)    ( ( (x) >> 0 ) & 0x3 )

Port number.

Definition at line 1006 of file intelxl.h.

Referenced by intelxl_probe().

#define INTELXL_PRTGL_SAL   0x1e2120

Port MAC Address Low Register.

Definition at line 1011 of file intelxl.h.

Referenced by intelxl_fetch_mac(), and intelxl_open().

#define INTELXL_PRTGL_SAH   0x1e2140

Port MAC Address High Register.

Definition at line 1014 of file intelxl.h.

Referenced by intelxl_fetch_mac(), and intelxl_open().

#define INTELXL_PRTGL_SAH_MFS_GET (   x)    ( (x) >> 16 )

Max frame size.

Definition at line 1015 of file intelxl.h.

Referenced by intelxl_fetch_mac().

#define INTELXL_PRTGL_SAH_MFS_SET (   x)    ( (x) << 16 )

Max frame size.

Definition at line 1016 of file intelxl.h.

Referenced by intelxl_open().


Function Documentation

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )
static void intelxl_init_admin ( struct intelxl_admin admin,
unsigned int  base,
const struct intelxl_admin_offsets regs 
) [inline, static]

Initialise admin queue.

Parameters:
adminAdmin queue
baseRegister block base
regsRegister offsets

Definition at line 582 of file intelxl.h.

References intelxl_admin_vf_configure_buffer::base, and regs.

Referenced by intelxl_probe(), and intelxlvf_probe().

                                                                {

        admin->base = base;
        admin->regs = regs;
}
static void intelxl_init_ring ( struct intelxl_ring ring,
unsigned int  count,
size_t  len,
int(*)(struct intelxl_nic *intelxl, physaddr_t address context 
) [inline, static]

Initialise descriptor ring.

Parameters:
ringDescriptor ring
countNumber of descriptors
lenLength of a single descriptor
contextMethod to program queue context

Definition at line 902 of file intelxl.h.

Referenced by intelxl_probe().

                              {
int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci 
)

Enable MSI-X dummy interrupt.

Parameters:
intelxlIntel device
pciPCI device
Return values:
rcReturn status code

Definition at line 133 of file intelxl.c.

References DBGC, intelxl_nic::msg, intelxl_nic::msix, pci_msix_enable(), pci_msix_map(), pci_msix_unmask(), rc, strerror(), and virt_to_bus().

Referenced by intelxl_probe(), and intelxlvf_probe().

                                                   {
        int rc;

        /* Enable MSI-X capability */
        if ( ( rc = pci_msix_enable ( pci, &intelxl->msix ) ) != 0 ) {
                DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
                       intelxl, strerror ( rc ) );
                return rc;
        }

        /* Configure interrupt zero to write to dummy location */
        pci_msix_map ( &intelxl->msix, 0, virt_to_bus ( &intelxl->msg ), 0 );

        /* Enable dummy interrupt zero */
        pci_msix_unmask ( &intelxl->msix, 0 );

        return 0;
}
void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci 
)

Disable MSI-X dummy interrupt.

Parameters:
intelxlIntel device
pciPCI device

Definition at line 159 of file intelxl.c.

References intelxl_nic::msix, pci_msix_disable(), and pci_msix_mask().

Referenced by intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

                                                     {

        /* Disable dummy interrupt zero */
        pci_msix_mask ( &intelxl->msix, 0 );

        /* Disable MSI-X capability */
        pci_msix_disable ( pci, &intelxl->msix );
}

Get next admin command queue descriptor.

Parameters:
intelxlIntel device
Return values:
cmdCommand descriptor

Definition at line 290 of file intelxl.c.

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_configure(), intelxlvf_admin_get_resources(), intelxlvf_admin_irq_map(), intelxlvf_admin_promisc(), intelxlvf_admin_queues(), and intelxlvf_reset_admin().

                                                                 {
        struct intelxl_admin *admin = &intelxl->command;
        struct intelxl_admin_descriptor *cmd;

        /* Get and initialise next descriptor */
        cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
        memset ( cmd, 0, sizeof ( *cmd ) );
        return cmd;
}
union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl) [write]

Get next admin command queue data buffer.

Parameters:
intelxlIntel device
Return values:
bufData buffer

Definition at line 307 of file intelxl.c.

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by intelxl_admin_driver(), intelxl_admin_switch(), intelxl_admin_vsi(), intelxlvf_admin_configure(), intelxlvf_admin_irq_map(), intelxlvf_admin_promisc(), and intelxlvf_admin_queues().

                                                             {
        struct intelxl_admin *admin = &intelxl->command;
        union intelxl_admin_buffer *buf;

        /* Get next data buffer */
        buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
        memset ( buf, 0, sizeof ( *buf ) );
        return buf;
}
int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters:
intelxlIntel device
Return values:
rcReturn status code

Definition at line 346 of file intelxl.c.

References address, assert, intelxl_admin::base, intelxl_admin::buf, intelxl_admin_params::buffer, cmd, intelxl_nic::command, intelxl_admin_descriptor::cookie, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, EIO, EPROTO, ETIMEDOUT, intelxl_admin_descriptor::flags, intelxl_admin_buffer_params::high, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin_descriptor::len, intelxl_admin_buffer_params::low, mdelay(), intelxl_admin_descriptor::opcode, intelxl_admin_descriptor::params, rc, regs, intelxl_admin::regs, intelxl_nic::regs, intelxl_admin_descriptor::ret, intelxl_admin_offsets::tail, virt_to_bus(), virt_to_phys(), intelxl_admin_descriptor::vopcode, wmb, and writel().

Referenced by intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), and intelxlvf_reset_admin().

                                                          {
        struct intelxl_admin *admin = &intelxl->command;
        const struct intelxl_admin_offsets *regs = admin->regs;
        void *admin_regs = ( intelxl->regs + admin->base );
        struct intelxl_admin_descriptor *cmd;
        union intelxl_admin_buffer *buf;
        uint64_t address;
        uint32_t cookie;
        unsigned int index;
        unsigned int tail;
        unsigned int i;
        int rc;

        /* Get next queue entry */
        index = admin->index++;
        tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
        cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
        buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
        DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
                intelxl, index, le16_to_cpu ( cmd->opcode ) );
        if ( cmd->vopcode )
                DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->vopcode ) );
        DBGC2 ( intelxl, ":\n" );

        /* Sanity checks */
        assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
        assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
        assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
        assert ( cmd->ret == 0 );

        /* Populate data buffer address if applicable */
        if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                address = virt_to_bus ( buf );
                cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
                cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
        }

        /* Populate cookie, if not being (ab)used for VF opcode */
        if ( ! cmd->vopcode )
                cmd->cookie = cpu_to_le32 ( index );

        /* Record cookie */
        cookie = cmd->cookie;

        /* Post command descriptor */
        DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
        if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
                            le16_to_cpu ( cmd->len ) );
        }
        wmb();
        writel ( tail, admin_regs + regs->tail );

        /* Wait for completion */
        for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {

                /* If response is not complete, delay 1ms and retry */
                if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
                        mdelay ( 1 );
                        continue;
                }
                DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
                        intelxl, index );
                DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
                            sizeof ( *cmd ) );

                /* Check for cookie mismatch */
                if ( cmd->cookie != cookie ) {
                        DBGC ( intelxl, "INTELXL %p admin command %#x bad "
                               "cookie %#x\n", intelxl, index,
                               le32_to_cpu ( cmd->cookie ) );
                        rc = -EPROTO;
                        goto err;
                }

                /* Check for errors */
                if ( cmd->ret != 0 ) {
                        DBGC ( intelxl, "INTELXL %p admin command %#x error "
                               "%d\n", intelxl, index,
                               le16_to_cpu ( cmd->ret ) );
                        rc = -EIO;
                        goto err;
                }

                /* Success */
                return 0;
        }

        rc = -ETIMEDOUT;
        DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
               intelxl, index );
 err:
        DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
        return rc;
}
void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters:
netdevNetwork device

Definition at line 780 of file intelxl.c.

References intelxl_admin::buf, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_LINK, intelxl_admin_link(), INTELXL_ADMIN_NUM_DESC, INTELXL_ADMIN_SEND_TO_VF, intelxl_refill_admin(), intelxlvf_admin_event(), le16_to_cpu, intelxl_admin_descriptor::len, intelxl_admin_descriptor::opcode, net_device::priv, and virt_to_phys().

Referenced by intelxl_poll(), and intelxlvf_admin_command().

                                                      {
        struct intelxl_nic *intelxl = netdev->priv;
        struct intelxl_admin *admin = &intelxl->event;
        struct intelxl_admin_descriptor *evt;
        union intelxl_admin_buffer *buf;

        /* Check for events */
        while ( 1 ) {

                /* Get next event descriptor and data buffer */
                evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
                buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];

                /* Stop if descriptor is not yet completed */
                if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
                        return;
                DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
                        intelxl, admin->index );
                DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
                            sizeof ( *evt ) );
                if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                        DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
                                    le16_to_cpu ( evt->len ) );
                }

                /* Handle event */
                switch ( evt->opcode ) {
                case cpu_to_le16 ( INTELXL_ADMIN_LINK ):
                        intelxl_admin_link ( netdev );
                        break;
                case cpu_to_le16 ( INTELXL_ADMIN_SEND_TO_VF ):
                        intelxlvf_admin_event ( netdev, evt, buf );
                        break;
                default:
                        DBGC ( intelxl, "INTELXL %p admin event %#x "
                               "unrecognised opcode %#04x\n", intelxl,
                               admin->index, le16_to_cpu ( evt->opcode ) );
                        break;
                }

                /* Reset descriptor and refill queue */
                intelxl_admin_event_init ( intelxl, admin->index );
                admin->index++;
                intelxl_refill_admin ( intelxl );
        }
}
int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters:
intelxlIntel device
Return values:
rcReturn status code

Definition at line 833 of file intelxl.c.

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_driver(), intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by intelxl_probe(), and intelxlvf_probe().

                                                       {
        int rc;

        /* Allocate admin event queue */
        if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
                goto err_alloc_event;

        /* Allocate admin command queue */
        if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
                goto err_alloc_command;

        /* (Re)open admin queues */
        intelxl_reopen_admin ( intelxl );

        /* Get firmware version */
        if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
                goto err_version;

        /* Report driver version */
        if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
                goto err_driver;

        return 0;

 err_driver:
 err_version:
        intelxl_disable_admin ( intelxl, &intelxl->command );
        intelxl_disable_admin ( intelxl, &intelxl->event );
        intelxl_free_admin ( intelxl, &intelxl->command );
 err_alloc_command:
        intelxl_free_admin ( intelxl, &intelxl->event );
 err_alloc_event:
        return rc;
}
void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters:
intelxlIntel device

Definition at line 873 of file intelxl.c.

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_admin().

                                                          {
        unsigned int i;

        /* Enable admin event queue */
        intelxl_enable_admin ( intelxl, &intelxl->event );

        /* Enable admin command queue */
        intelxl_enable_admin ( intelxl, &intelxl->command );

        /* Initialise all admin event queue descriptors */
        for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
                intelxl_admin_event_init ( intelxl, i );

        /* Post all descriptors to event queue */
        intelxl_refill_admin ( intelxl );
}
void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters:
intelxlIntel device

Definition at line 895 of file intelxl.c.

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

                                                         {

        /* Shut down admin queues */
        intelxl_admin_shutdown ( intelxl );

        /* Disable admin queues */
        intelxl_disable_admin ( intelxl, &intelxl->command );
        intelxl_disable_admin ( intelxl, &intelxl->event );

        /* Free admin queues */
        intelxl_free_admin ( intelxl, &intelxl->command );
        intelxl_free_admin ( intelxl, &intelxl->event );
}
int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters:
intelxlIntel device
ringDescriptor ring
Return values:
rcReturn status code

Definition at line 923 of file intelxl.c.

References address, intelxl_ring::cons, DBGC, intelxl_ring::desc, ENOMEM, free_dma(), INTELXL_ALIGN, intelxl_ring::len, malloc_dma(), memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, virt_to_bus(), and writel().

Referenced by intelxl_create_ring(), and intelxlvf_open().

                                                     {
        physaddr_t address;
        int rc;

        /* Allocate descriptor ring */
        ring->desc.raw = malloc_dma ( ring->len, INTELXL_ALIGN );
        if ( ! ring->desc.raw ) {
                rc = -ENOMEM;
                goto err_alloc;
        }
        address = virt_to_bus ( ring->desc.raw );

        /* Initialise descriptor ring */
        memset ( ring->desc.raw, 0, ring->len );

        /* Reset tail pointer */
        writel ( 0, ( intelxl->regs + ring->tail ) );

        /* Reset counters */
        ring->prod = 0;
        ring->cons = 0;

        DBGC ( intelxl, "INTELXL %p ring %06x is at [%08llx,%08llx)\n",
               intelxl, ( ring->reg + ring->tail ),
               ( ( unsigned long long ) address ),
               ( ( unsigned long long ) address + ring->len ) );

        return 0;

        free_dma ( ring->desc.raw, ring->len );
 err_alloc:
        return rc;
}
void intelxl_free_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters:
intelxlIntel device

Definition at line 1337 of file intelxl.c.

References free_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by intelxl_close(), and intelxlvf_close().

                                                      {
        unsigned int i;

        /* Discard any unused receive buffers */
        for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
                if ( intelxl->rx_iobuf[i] )
                        free_iob ( intelxl->rx_iobuf[i] );
                intelxl->rx_iobuf[i] = NULL;
        }
}
int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters:
netdevNetwork device
iobufI/O buffer
Return values:
rcReturn status code

Definition at line 1465 of file intelxl.c.

References address, intelxl_tx_data_descriptor::address, intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, intelxl_tx_data_descriptor::flags, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_len(), len, intelxl_tx_data_descriptor::len, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, virt_to_bus(), wmb, and writel().

                                                                            {
        struct intelxl_nic *intelxl = netdev->priv;
        struct intelxl_tx_data_descriptor *tx;
        unsigned int tx_idx;
        unsigned int tx_tail;
        physaddr_t address;
        size_t len;

        /* Get next transmit descriptor */
        if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
                DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
                       intelxl );
                return -ENOBUFS;
        }
        tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
        tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
        tx = &intelxl->tx.desc.tx[tx_idx].data;

        /* Populate transmit descriptor */
        address = virt_to_bus ( iobuf->data );
        len = iob_len ( iobuf );
        tx->address = cpu_to_le64 ( address );
        tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
        tx->flags = cpu_to_le32 ( INTELXL_TX_DATA_DTYP | INTELXL_TX_DATA_EOP |
                                  INTELXL_TX_DATA_RS | INTELXL_TX_DATA_JFDI );
        wmb();

        /* Notify card that there are packets ready to transmit */
        writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );

        DBGC2 ( intelxl, "INTELXL %p TX %d is [%llx,%llx)\n", intelxl, tx_idx,
                ( ( unsigned long long ) address ),
                ( ( unsigned long long ) address + len ) );
        return 0;
}
void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters:
netdevNetwork device

Definition at line 1587 of file intelxl.c.

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, net_device::priv, intelxl_nic::regs, and writel().

                                                {
        struct intelxl_nic *intelxl = netdev->priv;

        /* Poll for completed packets */
        intelxl_poll_tx ( netdev );

        /* Poll for received packets */
        intelxl_poll_rx ( netdev );

        /* Poll for admin events */
        intelxl_poll_admin ( netdev );

        /* Refill RX ring */
        intelxl_refill_rx ( intelxl );

        /* Rearm interrupt, since otherwise receive descriptors will
         * be written back only after a complete cacheline (four
         * packets) have been received.
         *
         * There is unfortunately no efficient way to determine
         * whether or not rearming the interrupt is necessary.  If we
         * are running inside a hypervisor (e.g. using a VF or PF as a
         * passed-through PCI device), then the MSI-X write is
         * redirected by the hypervisor to the real host APIC and the
         * host ISR then raises an interrupt within the guest.  We
         * therefore cannot poll the nominal MSI-X target location to
         * watch for the value being written.  We could read from the
         * INT_DYN_CTL register, but this is even less efficient than
         * just unconditionally rearming the interrupt.
         */
        writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
}
void intelxlvf_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor evt,
union intelxl_admin_buffer buf 
)

Handle virtual function event.

Parameters:
netdevNetwork device
evtAdmin queue event descriptor
bufAdmin queue event data buffer

Definition at line 287 of file intelxlvf.c.

References DBGC, DBGC_HDA, INTELXL_ADMIN_VF_STATUS, intelxlvf_admin_status(), le16_to_cpu, le32_to_cpu, intelxl_admin_descriptor::len, memcpy(), net_device::priv, intelxl_admin_buffer::stat, intelxl_nic::vbuf, virt_to_bus(), intelxl_admin_descriptor::vopcode, intelxl_nic::vopcode, intelxl_admin_descriptor::vret, and intelxl_nic::vret.

                                                               {
        struct intelxl_nic *intelxl = netdev->priv;
        unsigned int vopcode = le32_to_cpu ( evt->vopcode );

        /* Record command response if applicable */
        if ( vopcode == intelxl->vopcode ) {
                memcpy ( &intelxl->vbuf, buf, sizeof ( intelxl->vbuf ) );
                intelxl->vopcode = 0;
                intelxl->vret = le32_to_cpu ( evt->vret );
                if ( intelxl->vret != 0 ) {
                        DBGC ( intelxl, "INTELXL %p admin VF command %#x "
                               "error %d\n", intelxl, vopcode, intelxl->vret );
                        DBGC_HDA ( intelxl, virt_to_bus ( evt ), evt,
                                   sizeof ( *evt ) );
                        DBGC_HDA ( intelxl, virt_to_bus ( buf ), buf,
                                   le16_to_cpu ( evt->len ) );
                }
                return;
        }

        /* Handle unsolicited events */
        switch ( vopcode ) {
        case INTELXL_ADMIN_VF_STATUS:
                intelxlvf_admin_status ( netdev, &buf->stat );
                break;
        default:
                DBGC ( intelxl, "INTELXL %p unrecognised VF event %#x:\n",
                       intelxl, vopcode );
                DBGC_HDA ( intelxl, 0, evt, sizeof ( *evt ) );
                DBGC_HDA ( intelxl, 0, buf, le16_to_cpu ( evt->len ) );
                break;
        }
}