iPXE
mlx_pci_priv.c
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00001 /*
00002  * MlxPciPriv.c
00003  *
00004  *  Created on: Jan 21, 2015
00005  *      Author: maord
00006  */
00007 
00008 #include <ipxe/pci.h>
00009 
00010 #include "../../mlx_utils/include/private/mlx_pci_priv.h"
00011 
00012 
00013 static
00014 mlx_status
00015 mlx_pci_config_byte(
00016                 IN mlx_utils *utils,
00017                 IN mlx_boolean read,
00018                 IN mlx_uint32 offset,
00019                 IN OUT mlx_uint8 *buffer
00020                 )
00021 {
00022         mlx_status status = MLX_SUCCESS;
00023         if (read) {
00024                 status = pci_read_config_byte(utils->pci, offset, buffer);
00025         }else {
00026                 status = pci_write_config_byte(utils->pci, offset, *buffer);
00027         }
00028         return status;
00029 }
00030 
00031 static
00032 mlx_status
00033 mlx_pci_config_word(
00034                 IN mlx_utils *utils,
00035                 IN mlx_boolean read,
00036                 IN mlx_uint32 offset,
00037                 IN OUT mlx_uint16 *buffer
00038                 )
00039 {
00040         mlx_status status = MLX_SUCCESS;
00041         if (read) {
00042                 status = pci_read_config_word(utils->pci, offset, buffer);
00043         }else {
00044                 status = pci_write_config_word(utils->pci, offset, *buffer);
00045         }
00046         return status;
00047 }
00048 
00049 static
00050 mlx_status
00051 mlx_pci_config_dword(
00052                 IN mlx_utils *utils,
00053                 IN mlx_boolean read,
00054                 IN mlx_uint32 offset,
00055                 IN OUT mlx_uint32 *buffer
00056                 )
00057 {
00058         mlx_status status = MLX_SUCCESS;
00059         if (read) {
00060                 status = pci_read_config_dword(utils->pci, offset, buffer);
00061         }else {
00062                 status = pci_write_config_dword(utils->pci, offset, *buffer);
00063         }
00064         return status;
00065 }
00066 static
00067 mlx_status
00068 mlx_pci_config(
00069                 IN mlx_utils *utils,
00070                 IN mlx_boolean read,
00071                 IN mlx_pci_width width,
00072                 IN mlx_uint32 offset,
00073                 IN mlx_uintn count,
00074                 IN OUT mlx_void *buffer
00075                 )
00076 {
00077         mlx_status status = MLX_SUCCESS;
00078         mlx_uint8 *tmp =  (mlx_uint8*)buffer;
00079         mlx_uintn iteration = 0;
00080         if( width == MlxPciWidthUint64) {
00081                 width = MlxPciWidthUint32;
00082                 count = count * 2;
00083         }
00084 
00085         for(;iteration < count ; iteration++) {
00086                 switch (width){
00087                 case MlxPciWidthUint8:
00088                         status = mlx_pci_config_byte(utils, read , offset++, tmp++);
00089                         break;
00090                 case MlxPciWidthUint16:
00091                         status = mlx_pci_config_word(utils, read , offset, (mlx_uint16*)tmp);
00092                         tmp += 2;
00093                         offset += 2;
00094                         break;
00095                 case MlxPciWidthUint32:
00096                         status = mlx_pci_config_dword(utils, read , offset, (mlx_uint32*)tmp);
00097                         tmp += 4;
00098                         offset += 4;
00099                         break;
00100                 default:
00101                         status = MLX_INVALID_PARAMETER;
00102                 }
00103                 if(status != MLX_SUCCESS) {
00104                         goto config_error;
00105                 }
00106         }
00107 config_error:
00108         return status;
00109 }
00110 mlx_status
00111 mlx_pci_init_priv(
00112                         IN mlx_utils *utils
00113                         )
00114 {
00115         mlx_status status = MLX_SUCCESS;
00116         adjust_pci_device ( utils->pci );
00117 #ifdef DEVICE_CX3
00118         utils->config = ioremap ( pci_bar_start ( utils->pci, PCI_BASE_ADDRESS_0),
00119                         0x100000 );
00120 #endif
00121         return status;
00122 }
00123 
00124 mlx_status
00125 mlx_pci_teardown_priv(
00126                         IN mlx_utils *utils __attribute__ ((unused))
00127                         )
00128 {
00129         mlx_status status = MLX_SUCCESS;
00130 #ifdef DEVICE_CX3
00131         iounmap( utils->config );
00132 #endif
00133         return status;
00134 }
00135 
00136 mlx_status
00137 mlx_pci_read_priv(
00138                         IN mlx_utils *utils,
00139                         IN mlx_pci_width width,
00140                         IN mlx_uint32 offset,
00141                         IN mlx_uintn count,
00142                         OUT mlx_void *buffer
00143                         )
00144 {
00145         mlx_status status = MLX_SUCCESS;
00146         status = mlx_pci_config(utils, TRUE, width, offset, count, buffer);
00147         return status;
00148 }
00149 
00150 mlx_status
00151 mlx_pci_write_priv(
00152                         IN mlx_utils *utils,
00153                         IN mlx_pci_width width,
00154                         IN mlx_uint32 offset,
00155                         IN mlx_uintn count,
00156                         IN mlx_void *buffer
00157                         )
00158 {
00159         mlx_status status = MLX_SUCCESS;
00160         status = mlx_pci_config(utils, FALSE, width, offset, count, buffer);
00161         return status;
00162 }
00163 
00164 mlx_status
00165 mlx_pci_mem_read_priv(
00166                                 IN mlx_utils *utils  __attribute__ ((unused)),
00167                                 IN mlx_pci_width width  __attribute__ ((unused)),
00168                                 IN mlx_uint8 bar_index  __attribute__ ((unused)),
00169                                 IN mlx_uint64 offset,
00170                                 IN mlx_uintn count  __attribute__ ((unused)),
00171                                 OUT mlx_void *buffer
00172                                 )
00173 {
00174         if (buffer == NULL || width != MlxPciWidthUint32)
00175                 return MLX_INVALID_PARAMETER;
00176         *((mlx_uint32 *)buffer) = readl(offset);
00177         return MLX_SUCCESS;
00178 }
00179 
00180 mlx_status
00181 mlx_pci_mem_write_priv(
00182                                 IN mlx_utils *utils  __attribute__ ((unused)),
00183                                 IN mlx_pci_width width  __attribute__ ((unused)),
00184                                 IN mlx_uint8 bar_index  __attribute__ ((unused)),
00185                                 IN mlx_uint64 offset,
00186                                 IN mlx_uintn count  __attribute__ ((unused)),
00187                                 IN mlx_void *buffer
00188                                 )
00189 {
00190         if (buffer == NULL || width != MlxPciWidthUint32)
00191                 return MLX_INVALID_PARAMETER;
00192         barrier();
00193         writel(*((mlx_uint32 *)buffer), offset);
00194         return MLX_SUCCESS;
00195 }