iPXE
ath5k_initvals.c
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1/*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 *
22 */
23
24FILE_LICENCE ( MIT );
25FILE_SECBOOT ( FORBIDDEN );
26
27#include <unistd.h>
28
29#include "ath5k.h"
30#include "reg.h"
31#include "base.h"
32
33/*
34 * Mode-independent initial register writes
35 */
36
37struct ath5k_ini {
38 u16 ini_register;
39 u32 ini_value;
40
41 enum {
42 AR5K_INI_WRITE = 0, /* Default */
43 AR5K_INI_READ = 1, /* Cleared on read */
44 } ini_mode;
45};
46
47/*
48 * Mode specific initial register values
49 */
50
55
56/* Initial register settings for AR5210 */
57static const struct ath5k_ini ar5210_ini[] = {
58 /* PCU and MAC registers */
59 { AR5K_NOQCU_TXDP0, 0, AR5K_INI_WRITE },
60 { AR5K_NOQCU_TXDP1, 0, AR5K_INI_WRITE },
61 { AR5K_RXDP, 0, AR5K_INI_WRITE },
62 { AR5K_CR, 0, AR5K_INI_WRITE },
63 { AR5K_ISR, 0, AR5K_INI_READ },
64 { AR5K_IMR, 0, AR5K_INI_WRITE },
65 { AR5K_IER, AR5K_IER_DISABLE, AR5K_INI_WRITE },
66 { AR5K_BSR, 0, AR5K_INI_READ },
67 { AR5K_TXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE },
68 { AR5K_RXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE },
69 { AR5K_CFG, AR5K_INIT_CFG, AR5K_INI_WRITE },
70 { AR5K_TOPS, 8, AR5K_INI_WRITE },
71 { AR5K_RXNOFRM, 8, AR5K_INI_WRITE },
72 { AR5K_RPGTO, 0, AR5K_INI_WRITE },
73 { AR5K_TXNOFRM, 0, AR5K_INI_WRITE },
74 { AR5K_SFR, 0, AR5K_INI_WRITE },
75 { AR5K_MIBC, 0, AR5K_INI_WRITE },
76 { AR5K_MISC, 0, AR5K_INI_WRITE },
77 { AR5K_RX_FILTER_5210, 0, AR5K_INI_WRITE },
78 { AR5K_MCAST_FILTER0_5210, 0, AR5K_INI_WRITE },
79 { AR5K_MCAST_FILTER1_5210, 0, AR5K_INI_WRITE },
80 { AR5K_TX_MASK0, 0, AR5K_INI_WRITE },
81 { AR5K_TX_MASK1, 0, AR5K_INI_WRITE },
82 { AR5K_CLR_TMASK, 0, AR5K_INI_WRITE },
83 { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_INI_WRITE },
84 { AR5K_DIAG_SW_5210, 0, AR5K_INI_WRITE },
85 { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES, AR5K_INI_WRITE },
86 { AR5K_TSF_L32_5210, 0, AR5K_INI_WRITE },
87 { AR5K_TIMER0_5210, 0, AR5K_INI_WRITE },
88 { AR5K_TIMER1_5210, 0xffffffff, AR5K_INI_WRITE },
89 { AR5K_TIMER2_5210, 0xffffffff, AR5K_INI_WRITE },
90 { AR5K_TIMER3_5210, 1, AR5K_INI_WRITE },
91 { AR5K_CFP_DUR_5210, 0, AR5K_INI_WRITE },
92 { AR5K_CFP_PERIOD_5210, 0, AR5K_INI_WRITE },
93 /* PHY registers */
94 { AR5K_PHY(0), 0x00000047, AR5K_INI_WRITE },
95 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
96 { AR5K_PHY(3), 0x09848ea6, AR5K_INI_WRITE },
97 { AR5K_PHY(4), 0x3d32e000, AR5K_INI_WRITE },
98 { AR5K_PHY(5), 0x0000076b, AR5K_INI_WRITE },
99 { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_INI_WRITE },
100 { AR5K_PHY(8), 0x02020200, AR5K_INI_WRITE },
101 { AR5K_PHY(9), 0x00000e0e, AR5K_INI_WRITE },
102 { AR5K_PHY(10), 0x0a020201, AR5K_INI_WRITE },
103 { AR5K_PHY(11), 0x00036ffc, AR5K_INI_WRITE },
104 { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
105 { AR5K_PHY(13), 0x00000e0e, AR5K_INI_WRITE },
106 { AR5K_PHY(14), 0x00000007, AR5K_INI_WRITE },
107 { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
108 { AR5K_PHY(16), 0x89630000, AR5K_INI_WRITE },
109 { AR5K_PHY(17), 0x1372169c, AR5K_INI_WRITE },
110 { AR5K_PHY(18), 0x0018b633, AR5K_INI_WRITE },
111 { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
112 { AR5K_PHY(20), 0x0de8b8e0, AR5K_INI_WRITE },
113 { AR5K_PHY(21), 0x00074859, AR5K_INI_WRITE },
114 { AR5K_PHY(22), 0x7e80beba, AR5K_INI_WRITE },
115 { AR5K_PHY(23), 0x313a665e, AR5K_INI_WRITE },
116 { AR5K_PHY_AGCCTL, 0x00001d08, AR5K_INI_WRITE },
117 { AR5K_PHY(25), 0x0001ce00, AR5K_INI_WRITE },
118 { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },
119 { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
120 { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
121 { AR5K_PHY(30), 0x00000004, AR5K_INI_WRITE },
122 { AR5K_PHY(31), 0x00000018, AR5K_INI_WRITE }, /* 0x987c */
123 { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE }, /* 0x9900 */
124 { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
125 { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
126 { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
127 { AR5K_PHY(68), 0x00000003, AR5K_INI_WRITE },
128 /* BB gain table (64bytes) */
129 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
130 { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
131 { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
132 { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
133 { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
134 { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
135 { AR5K_BB_GAIN(6), 0x00000028, AR5K_INI_WRITE },
136 { AR5K_BB_GAIN(7), 0x00000004, AR5K_INI_WRITE },
137 { AR5K_BB_GAIN(8), 0x00000024, AR5K_INI_WRITE },
138 { AR5K_BB_GAIN(9), 0x00000014, AR5K_INI_WRITE },
139 { AR5K_BB_GAIN(10), 0x00000034, AR5K_INI_WRITE },
140 { AR5K_BB_GAIN(11), 0x0000000c, AR5K_INI_WRITE },
141 { AR5K_BB_GAIN(12), 0x0000002c, AR5K_INI_WRITE },
142 { AR5K_BB_GAIN(13), 0x00000002, AR5K_INI_WRITE },
143 { AR5K_BB_GAIN(14), 0x00000022, AR5K_INI_WRITE },
144 { AR5K_BB_GAIN(15), 0x00000012, AR5K_INI_WRITE },
145 { AR5K_BB_GAIN(16), 0x00000032, AR5K_INI_WRITE },
146 { AR5K_BB_GAIN(17), 0x0000000a, AR5K_INI_WRITE },
147 { AR5K_BB_GAIN(18), 0x0000002a, AR5K_INI_WRITE },
148 { AR5K_BB_GAIN(19), 0x00000001, AR5K_INI_WRITE },
149 { AR5K_BB_GAIN(20), 0x00000021, AR5K_INI_WRITE },
150 { AR5K_BB_GAIN(21), 0x00000011, AR5K_INI_WRITE },
151 { AR5K_BB_GAIN(22), 0x00000031, AR5K_INI_WRITE },
152 { AR5K_BB_GAIN(23), 0x00000009, AR5K_INI_WRITE },
153 { AR5K_BB_GAIN(24), 0x00000029, AR5K_INI_WRITE },
154 { AR5K_BB_GAIN(25), 0x00000005, AR5K_INI_WRITE },
155 { AR5K_BB_GAIN(26), 0x00000025, AR5K_INI_WRITE },
156 { AR5K_BB_GAIN(27), 0x00000015, AR5K_INI_WRITE },
157 { AR5K_BB_GAIN(28), 0x00000035, AR5K_INI_WRITE },
158 { AR5K_BB_GAIN(29), 0x0000000d, AR5K_INI_WRITE },
159 { AR5K_BB_GAIN(30), 0x0000002d, AR5K_INI_WRITE },
160 { AR5K_BB_GAIN(31), 0x00000003, AR5K_INI_WRITE },
161 { AR5K_BB_GAIN(32), 0x00000023, AR5K_INI_WRITE },
162 { AR5K_BB_GAIN(33), 0x00000013, AR5K_INI_WRITE },
163 { AR5K_BB_GAIN(34), 0x00000033, AR5K_INI_WRITE },
164 { AR5K_BB_GAIN(35), 0x0000000b, AR5K_INI_WRITE },
165 { AR5K_BB_GAIN(36), 0x0000002b, AR5K_INI_WRITE },
166 { AR5K_BB_GAIN(37), 0x00000007, AR5K_INI_WRITE },
167 { AR5K_BB_GAIN(38), 0x00000027, AR5K_INI_WRITE },
168 { AR5K_BB_GAIN(39), 0x00000017, AR5K_INI_WRITE },
169 { AR5K_BB_GAIN(40), 0x00000037, AR5K_INI_WRITE },
170 { AR5K_BB_GAIN(41), 0x0000000f, AR5K_INI_WRITE },
171 { AR5K_BB_GAIN(42), 0x0000002f, AR5K_INI_WRITE },
172 { AR5K_BB_GAIN(43), 0x0000002f, AR5K_INI_WRITE },
173 { AR5K_BB_GAIN(44), 0x0000002f, AR5K_INI_WRITE },
174 { AR5K_BB_GAIN(45), 0x0000002f, AR5K_INI_WRITE },
175 { AR5K_BB_GAIN(46), 0x0000002f, AR5K_INI_WRITE },
176 { AR5K_BB_GAIN(47), 0x0000002f, AR5K_INI_WRITE },
177 { AR5K_BB_GAIN(48), 0x0000002f, AR5K_INI_WRITE },
178 { AR5K_BB_GAIN(49), 0x0000002f, AR5K_INI_WRITE },
179 { AR5K_BB_GAIN(50), 0x0000002f, AR5K_INI_WRITE },
180 { AR5K_BB_GAIN(51), 0x0000002f, AR5K_INI_WRITE },
181 { AR5K_BB_GAIN(52), 0x0000002f, AR5K_INI_WRITE },
182 { AR5K_BB_GAIN(53), 0x0000002f, AR5K_INI_WRITE },
183 { AR5K_BB_GAIN(54), 0x0000002f, AR5K_INI_WRITE },
184 { AR5K_BB_GAIN(55), 0x0000002f, AR5K_INI_WRITE },
185 { AR5K_BB_GAIN(56), 0x0000002f, AR5K_INI_WRITE },
186 { AR5K_BB_GAIN(57), 0x0000002f, AR5K_INI_WRITE },
187 { AR5K_BB_GAIN(58), 0x0000002f, AR5K_INI_WRITE },
188 { AR5K_BB_GAIN(59), 0x0000002f, AR5K_INI_WRITE },
189 { AR5K_BB_GAIN(60), 0x0000002f, AR5K_INI_WRITE },
190 { AR5K_BB_GAIN(61), 0x0000002f, AR5K_INI_WRITE },
191 { AR5K_BB_GAIN(62), 0x0000002f, AR5K_INI_WRITE },
192 { AR5K_BB_GAIN(63), 0x0000002f, AR5K_INI_WRITE },
193 /* 5110 RF gain table (64btes) */
194 { AR5K_RF_GAIN(0), 0x0000001d, AR5K_INI_WRITE },
195 { AR5K_RF_GAIN(1), 0x0000005d, AR5K_INI_WRITE },
196 { AR5K_RF_GAIN(2), 0x0000009d, AR5K_INI_WRITE },
197 { AR5K_RF_GAIN(3), 0x000000dd, AR5K_INI_WRITE },
198 { AR5K_RF_GAIN(4), 0x0000011d, AR5K_INI_WRITE },
199 { AR5K_RF_GAIN(5), 0x00000021, AR5K_INI_WRITE },
200 { AR5K_RF_GAIN(6), 0x00000061, AR5K_INI_WRITE },
201 { AR5K_RF_GAIN(7), 0x000000a1, AR5K_INI_WRITE },
202 { AR5K_RF_GAIN(8), 0x000000e1, AR5K_INI_WRITE },
203 { AR5K_RF_GAIN(9), 0x00000031, AR5K_INI_WRITE },
204 { AR5K_RF_GAIN(10), 0x00000071, AR5K_INI_WRITE },
205 { AR5K_RF_GAIN(11), 0x000000b1, AR5K_INI_WRITE },
206 { AR5K_RF_GAIN(12), 0x0000001c, AR5K_INI_WRITE },
207 { AR5K_RF_GAIN(13), 0x0000005c, AR5K_INI_WRITE },
208 { AR5K_RF_GAIN(14), 0x00000029, AR5K_INI_WRITE },
209 { AR5K_RF_GAIN(15), 0x00000069, AR5K_INI_WRITE },
210 { AR5K_RF_GAIN(16), 0x000000a9, AR5K_INI_WRITE },
211 { AR5K_RF_GAIN(17), 0x00000020, AR5K_INI_WRITE },
212 { AR5K_RF_GAIN(18), 0x00000019, AR5K_INI_WRITE },
213 { AR5K_RF_GAIN(19), 0x00000059, AR5K_INI_WRITE },
214 { AR5K_RF_GAIN(20), 0x00000099, AR5K_INI_WRITE },
215 { AR5K_RF_GAIN(21), 0x00000030, AR5K_INI_WRITE },
216 { AR5K_RF_GAIN(22), 0x00000005, AR5K_INI_WRITE },
217 { AR5K_RF_GAIN(23), 0x00000025, AR5K_INI_WRITE },
218 { AR5K_RF_GAIN(24), 0x00000065, AR5K_INI_WRITE },
219 { AR5K_RF_GAIN(25), 0x000000a5, AR5K_INI_WRITE },
220 { AR5K_RF_GAIN(26), 0x00000028, AR5K_INI_WRITE },
221 { AR5K_RF_GAIN(27), 0x00000068, AR5K_INI_WRITE },
222 { AR5K_RF_GAIN(28), 0x0000001f, AR5K_INI_WRITE },
223 { AR5K_RF_GAIN(29), 0x0000001e, AR5K_INI_WRITE },
224 { AR5K_RF_GAIN(30), 0x00000018, AR5K_INI_WRITE },
225 { AR5K_RF_GAIN(31), 0x00000058, AR5K_INI_WRITE },
226 { AR5K_RF_GAIN(32), 0x00000098, AR5K_INI_WRITE },
227 { AR5K_RF_GAIN(33), 0x00000003, AR5K_INI_WRITE },
228 { AR5K_RF_GAIN(34), 0x00000004, AR5K_INI_WRITE },
229 { AR5K_RF_GAIN(35), 0x00000044, AR5K_INI_WRITE },
230 { AR5K_RF_GAIN(36), 0x00000084, AR5K_INI_WRITE },
231 { AR5K_RF_GAIN(37), 0x00000013, AR5K_INI_WRITE },
232 { AR5K_RF_GAIN(38), 0x00000012, AR5K_INI_WRITE },
233 { AR5K_RF_GAIN(39), 0x00000052, AR5K_INI_WRITE },
234 { AR5K_RF_GAIN(40), 0x00000092, AR5K_INI_WRITE },
235 { AR5K_RF_GAIN(41), 0x000000d2, AR5K_INI_WRITE },
236 { AR5K_RF_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
237 { AR5K_RF_GAIN(43), 0x0000002a, AR5K_INI_WRITE },
238 { AR5K_RF_GAIN(44), 0x0000006a, AR5K_INI_WRITE },
239 { AR5K_RF_GAIN(45), 0x000000aa, AR5K_INI_WRITE },
240 { AR5K_RF_GAIN(46), 0x0000001b, AR5K_INI_WRITE },
241 { AR5K_RF_GAIN(47), 0x0000001a, AR5K_INI_WRITE },
242 { AR5K_RF_GAIN(48), 0x0000005a, AR5K_INI_WRITE },
243 { AR5K_RF_GAIN(49), 0x0000009a, AR5K_INI_WRITE },
244 { AR5K_RF_GAIN(50), 0x000000da, AR5K_INI_WRITE },
245 { AR5K_RF_GAIN(51), 0x00000006, AR5K_INI_WRITE },
246 { AR5K_RF_GAIN(52), 0x00000006, AR5K_INI_WRITE },
247 { AR5K_RF_GAIN(53), 0x00000006, AR5K_INI_WRITE },
248 { AR5K_RF_GAIN(54), 0x00000006, AR5K_INI_WRITE },
249 { AR5K_RF_GAIN(55), 0x00000006, AR5K_INI_WRITE },
250 { AR5K_RF_GAIN(56), 0x00000006, AR5K_INI_WRITE },
251 { AR5K_RF_GAIN(57), 0x00000006, AR5K_INI_WRITE },
252 { AR5K_RF_GAIN(58), 0x00000006, AR5K_INI_WRITE },
253 { AR5K_RF_GAIN(59), 0x00000006, AR5K_INI_WRITE },
254 { AR5K_RF_GAIN(60), 0x00000006, AR5K_INI_WRITE },
255 { AR5K_RF_GAIN(61), 0x00000006, AR5K_INI_WRITE },
256 { AR5K_RF_GAIN(62), 0x00000006, AR5K_INI_WRITE },
257 { AR5K_RF_GAIN(63), 0x00000006, AR5K_INI_WRITE },
258 /* PHY activation */
259 { AR5K_PHY(53), 0x00000020, AR5K_INI_WRITE },
260 { AR5K_PHY(51), 0x00000004, AR5K_INI_WRITE },
261 { AR5K_PHY(50), 0x00060106, AR5K_INI_WRITE },
262 { AR5K_PHY(39), 0x0000006d, AR5K_INI_WRITE },
263 { AR5K_PHY(48), 0x00000000, AR5K_INI_WRITE },
264 { AR5K_PHY(52), 0x00000014, AR5K_INI_WRITE },
265 { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE, AR5K_INI_WRITE },
266};
267
268/* Initial register settings for AR5211 */
269static const struct ath5k_ini ar5211_ini[] = {
270 { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
271 { AR5K_RTSD0, 0x84849c9c, AR5K_INI_WRITE },
272 { AR5K_RTSD1, 0x7c7c7c7c, AR5K_INI_WRITE },
273 { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
274 { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
275 { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
276 { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
277 { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
278 { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
279 { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
280 { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
281 { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
282 { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
283 { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
284 { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
285 { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
286 { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
287 { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
288 { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
289 { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
290 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
291 { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
292 { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
293 { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
294 { AR5K_RSSI_THR, 0x00000000, AR5K_INI_WRITE },
295 { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
296 { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
297 { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
298 { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
299 { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
300 { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
301 { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
302 { AR5K_MCAST_FILTER0_5211, 0x00000000, AR5K_INI_WRITE },
303 { AR5K_MCAST_FILTER1_5211, 0x00000002, AR5K_INI_WRITE },
304 { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
305 { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
306 { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
307 /* PHY registers */
308 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
309 { AR5K_PHY(3), 0x2d849093, AR5K_INI_WRITE },
310 { AR5K_PHY(4), 0x7d32e000, AR5K_INI_WRITE },
311 { AR5K_PHY(5), 0x00000f6b, AR5K_INI_WRITE },
312 { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
313 { AR5K_PHY(11), 0x00026ffe, AR5K_INI_WRITE },
314 { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
315 { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
316 { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
317 { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
318 { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
319 { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE }, /* 0x9868 */
320 { AR5K_PHY(27), 0x050cb081, AR5K_INI_WRITE },
321 { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
322 { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
323 { AR5K_PHY(30), 0x0000000c, AR5K_INI_WRITE },
324 { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },
325 { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
326 { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
327 { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
328 { AR5K_PHY(68), 0x00000001, AR5K_INI_WRITE },
329 { AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },
330 { AR5K_PHY_IQ, 0x00000000, AR5K_INI_WRITE },
331 { AR5K_PHY(73), 0x00058a05, AR5K_INI_WRITE },
332 { AR5K_PHY(74), 0x00000001, AR5K_INI_WRITE },
333 { AR5K_PHY(75), 0x00000000, AR5K_INI_WRITE },
334 { AR5K_PHY_PAPD_PROBE, 0x00000000, AR5K_INI_WRITE },
335 { AR5K_PHY(77), 0x00000000, AR5K_INI_WRITE }, /* 0x9934 */
336 { AR5K_PHY(78), 0x00000000, AR5K_INI_WRITE }, /* 0x9938 */
337 { AR5K_PHY(79), 0x0000003f, AR5K_INI_WRITE }, /* 0x993c */
338 { AR5K_PHY(80), 0x00000004, AR5K_INI_WRITE },
339 { AR5K_PHY(82), 0x00000000, AR5K_INI_WRITE },
340 { AR5K_PHY(83), 0x00000000, AR5K_INI_WRITE },
341 { AR5K_PHY(84), 0x00000000, AR5K_INI_WRITE },
342 { AR5K_PHY_RADAR, 0x5d50f14c, AR5K_INI_WRITE },
343 { AR5K_PHY(86), 0x00000018, AR5K_INI_WRITE },
344 { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
345 /* Initial Power table (32bytes)
346 * common on all cards/modes.
347 * Note: Table is rewritten during
348 * txpower setup later using calibration
349 * data etc. so next write is non-common */
350 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff, AR5K_INI_WRITE },
351 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff, AR5K_INI_WRITE },
352 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff, AR5K_INI_WRITE },
353 { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff, AR5K_INI_WRITE },
354 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff, AR5K_INI_WRITE },
355 { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff, AR5K_INI_WRITE },
356 { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff, AR5K_INI_WRITE },
357 { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff, AR5K_INI_WRITE },
358 { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff, AR5K_INI_WRITE },
359 { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff, AR5K_INI_WRITE },
360 { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff, AR5K_INI_WRITE },
361 { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff, AR5K_INI_WRITE },
362 { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff, AR5K_INI_WRITE },
363 { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff, AR5K_INI_WRITE },
364 { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff, AR5K_INI_WRITE },
365 { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff, AR5K_INI_WRITE },
366 { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff, AR5K_INI_WRITE },
367 { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff, AR5K_INI_WRITE },
368 { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff, AR5K_INI_WRITE },
369 { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff, AR5K_INI_WRITE },
370 { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff, AR5K_INI_WRITE },
371 { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff, AR5K_INI_WRITE },
372 { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff, AR5K_INI_WRITE },
373 { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff, AR5K_INI_WRITE },
374 { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff, AR5K_INI_WRITE },
375 { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff, AR5K_INI_WRITE },
376 { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff, AR5K_INI_WRITE },
377 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff, AR5K_INI_WRITE },
378 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff, AR5K_INI_WRITE },
379 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff, AR5K_INI_WRITE },
380 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff, AR5K_INI_WRITE },
381 { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
382 { AR5K_PHY(642), 0x503e4646, AR5K_INI_WRITE },
383 { AR5K_PHY_GAIN_2GHZ, 0x6480416c, AR5K_INI_WRITE },
384 { AR5K_PHY(644), 0x0199a003, AR5K_INI_WRITE },
385 { AR5K_PHY(645), 0x044cd610, AR5K_INI_WRITE },
386 { AR5K_PHY(646), 0x13800040, AR5K_INI_WRITE },
387 { AR5K_PHY(647), 0x1be00060, AR5K_INI_WRITE },
388 { AR5K_PHY(648), 0x0c53800a, AR5K_INI_WRITE },
389 { AR5K_PHY(649), 0x0014df3b, AR5K_INI_WRITE },
390 { AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },
391 { AR5K_PHY(651), 0x00000020, AR5K_INI_WRITE },
392};
393
394/* Initial mode-specific settings for AR5211
395 * 5211 supports OFDM-only g (draft g) but we
396 * need to test it !
397 */
398static const struct ath5k_ini_mode ar5211_ini_mode[] = {
399 { AR5K_TXCFG,
400 /* a aTurbo b g (OFDM) */
401 { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
402 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
403 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
404 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
405 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
406 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
407 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
408 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
409 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
410 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
411 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
412 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
413 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
414 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
415 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
416 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
417 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
418 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
419 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
420 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
421 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
422 { AR5K_DCU_GBL_IFS_SLOT,
423 { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
424 { AR5K_DCU_GBL_IFS_SIFS,
425 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
426 { AR5K_DCU_GBL_IFS_EIFS,
427 { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
428 { AR5K_DCU_GBL_IFS_MISC,
429 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
430 { AR5K_TIME_OUT,
431 { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
432 { AR5K_USEC_5211,
433 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
434 { AR5K_PHY_TURBO,
435 { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
436 { AR5K_PHY(8),
437 { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
438 { AR5K_PHY(9),
439 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
440 { AR5K_PHY(10),
441 { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
442 { AR5K_PHY(13),
443 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
444 { AR5K_PHY(14),
445 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
446 { AR5K_PHY(17),
447 { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
448 { AR5K_PHY(18),
449 { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
450 { AR5K_PHY(20),
451 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
452 { AR5K_PHY_SIG,
453 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
454 { AR5K_PHY_AGCCOARSE,
455 { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
456 { AR5K_PHY_AGCCTL,
457 { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
458 { AR5K_PHY_NF,
459 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
460 { AR5K_PHY_RX_DELAY,
461 { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
462 { AR5K_PHY(70),
463 { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
464 { AR5K_PHY_FRAME_CTL_5211,
465 { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
466 { AR5K_PHY_PCDAC_TXPOWER_BASE,
467 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
468 { AR5K_RF_BUFFER_CONTROL_4,
469 { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
470};
471
472/* Initial register settings for AR5212 */
473static const struct ath5k_ini ar5212_ini_common_start[] = {
474 { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
475 { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
476 { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
477 { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
478 { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
479 { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
480 { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
481 { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
482 { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
483 { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
484 { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
485 { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
486 { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
487 { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
488 { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
489 { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
490 { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
491 { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
492 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
493 { AR5K_DCU_TXP, 0x00000000, AR5K_INI_WRITE },
494 /* Tx filter table 0 (32 entries) */
495 { AR5K_DCU_TX_FILTER_0(0), 0x00000000, AR5K_INI_WRITE }, /* DCU 0 */
496 { AR5K_DCU_TX_FILTER_0(1), 0x00000000, AR5K_INI_WRITE },
497 { AR5K_DCU_TX_FILTER_0(2), 0x00000000, AR5K_INI_WRITE },
498 { AR5K_DCU_TX_FILTER_0(3), 0x00000000, AR5K_INI_WRITE },
499 { AR5K_DCU_TX_FILTER_0(4), 0x00000000, AR5K_INI_WRITE }, /* DCU 1 */
500 { AR5K_DCU_TX_FILTER_0(5), 0x00000000, AR5K_INI_WRITE },
501 { AR5K_DCU_TX_FILTER_0(6), 0x00000000, AR5K_INI_WRITE },
502 { AR5K_DCU_TX_FILTER_0(7), 0x00000000, AR5K_INI_WRITE },
503 { AR5K_DCU_TX_FILTER_0(8), 0x00000000, AR5K_INI_WRITE }, /* DCU 2 */
504 { AR5K_DCU_TX_FILTER_0(9), 0x00000000, AR5K_INI_WRITE },
505 { AR5K_DCU_TX_FILTER_0(10), 0x00000000, AR5K_INI_WRITE },
506 { AR5K_DCU_TX_FILTER_0(11), 0x00000000, AR5K_INI_WRITE },
507 { AR5K_DCU_TX_FILTER_0(12), 0x00000000, AR5K_INI_WRITE }, /* DCU 3 */
508 { AR5K_DCU_TX_FILTER_0(13), 0x00000000, AR5K_INI_WRITE },
509 { AR5K_DCU_TX_FILTER_0(14), 0x00000000, AR5K_INI_WRITE },
510 { AR5K_DCU_TX_FILTER_0(15), 0x00000000, AR5K_INI_WRITE },
511 { AR5K_DCU_TX_FILTER_0(16), 0x00000000, AR5K_INI_WRITE }, /* DCU 4 */
512 { AR5K_DCU_TX_FILTER_0(17), 0x00000000, AR5K_INI_WRITE },
513 { AR5K_DCU_TX_FILTER_0(18), 0x00000000, AR5K_INI_WRITE },
514 { AR5K_DCU_TX_FILTER_0(19), 0x00000000, AR5K_INI_WRITE },
515 { AR5K_DCU_TX_FILTER_0(20), 0x00000000, AR5K_INI_WRITE }, /* DCU 5 */
516 { AR5K_DCU_TX_FILTER_0(21), 0x00000000, AR5K_INI_WRITE },
517 { AR5K_DCU_TX_FILTER_0(22), 0x00000000, AR5K_INI_WRITE },
518 { AR5K_DCU_TX_FILTER_0(23), 0x00000000, AR5K_INI_WRITE },
519 { AR5K_DCU_TX_FILTER_0(24), 0x00000000, AR5K_INI_WRITE }, /* DCU 6 */
520 { AR5K_DCU_TX_FILTER_0(25), 0x00000000, AR5K_INI_WRITE },
521 { AR5K_DCU_TX_FILTER_0(26), 0x00000000, AR5K_INI_WRITE },
522 { AR5K_DCU_TX_FILTER_0(27), 0x00000000, AR5K_INI_WRITE },
523 { AR5K_DCU_TX_FILTER_0(28), 0x00000000, AR5K_INI_WRITE }, /* DCU 7 */
524 { AR5K_DCU_TX_FILTER_0(29), 0x00000000, AR5K_INI_WRITE },
525 { AR5K_DCU_TX_FILTER_0(30), 0x00000000, AR5K_INI_WRITE },
526 { AR5K_DCU_TX_FILTER_0(31), 0x00000000, AR5K_INI_WRITE },
527 /* Tx filter table 1 (16 entries) */
528 { AR5K_DCU_TX_FILTER_1(0), 0x00000000, AR5K_INI_WRITE },
529 { AR5K_DCU_TX_FILTER_1(1), 0x00000000, AR5K_INI_WRITE },
530 { AR5K_DCU_TX_FILTER_1(2), 0x00000000, AR5K_INI_WRITE },
531 { AR5K_DCU_TX_FILTER_1(3), 0x00000000, AR5K_INI_WRITE },
532 { AR5K_DCU_TX_FILTER_1(4), 0x00000000, AR5K_INI_WRITE },
533 { AR5K_DCU_TX_FILTER_1(5), 0x00000000, AR5K_INI_WRITE },
534 { AR5K_DCU_TX_FILTER_1(6), 0x00000000, AR5K_INI_WRITE },
535 { AR5K_DCU_TX_FILTER_1(7), 0x00000000, AR5K_INI_WRITE },
536 { AR5K_DCU_TX_FILTER_1(8), 0x00000000, AR5K_INI_WRITE },
537 { AR5K_DCU_TX_FILTER_1(9), 0x00000000, AR5K_INI_WRITE },
538 { AR5K_DCU_TX_FILTER_1(10), 0x00000000, AR5K_INI_WRITE },
539 { AR5K_DCU_TX_FILTER_1(11), 0x00000000, AR5K_INI_WRITE },
540 { AR5K_DCU_TX_FILTER_1(12), 0x00000000, AR5K_INI_WRITE },
541 { AR5K_DCU_TX_FILTER_1(13), 0x00000000, AR5K_INI_WRITE },
542 { AR5K_DCU_TX_FILTER_1(14), 0x00000000, AR5K_INI_WRITE },
543 { AR5K_DCU_TX_FILTER_1(15), 0x00000000, AR5K_INI_WRITE },
544 { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
545 { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
546 { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
547 { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
548 { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
549 { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
550 { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
551 { AR5K_BEACON_5211, 0x00000000, AR5K_INI_WRITE },
552 { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
553 { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
554 { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
555 { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
556 { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
557 { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
558 { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
559 { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
560 { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
561 { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
562 { AR5K_FRAME_CTL_QOSM, 0x000fc78f, AR5K_INI_WRITE },
563 { AR5K_XRMODE, 0x2a82301a, AR5K_INI_WRITE },
564 { AR5K_XRDELAY, 0x05dc01e0, AR5K_INI_WRITE },
565 { AR5K_XRTIMEOUT, 0x1f402710, AR5K_INI_WRITE },
566 { AR5K_XRCHIRP, 0x01f40000, AR5K_INI_WRITE },
567 { AR5K_XRSTOMP, 0x00001e1c, AR5K_INI_WRITE },
568 { AR5K_SLEEP0, 0x0002aaaa, AR5K_INI_WRITE },
569 { AR5K_SLEEP1, 0x02005555, AR5K_INI_WRITE },
570 { AR5K_SLEEP2, 0x00000000, AR5K_INI_WRITE },
571 { AR5K_BSS_IDM0, 0xffffffff, AR5K_INI_WRITE },
572 { AR5K_BSS_IDM1, 0x0000ffff, AR5K_INI_WRITE },
573 { AR5K_TXPC, 0x00000000, AR5K_INI_WRITE },
574 { AR5K_PROFCNT_TX, 0x00000000, AR5K_INI_WRITE },
575 { AR5K_PROFCNT_RX, 0x00000000, AR5K_INI_WRITE },
576 { AR5K_PROFCNT_RXCLR, 0x00000000, AR5K_INI_WRITE },
577 { AR5K_PROFCNT_CYCLE, 0x00000000, AR5K_INI_WRITE },
578 { AR5K_QUIET_CTL1, 0x00000088, AR5K_INI_WRITE },
579 /* Initial rate duration table (32 entries )*/
580 { AR5K_RATE_DUR(0), 0x00000000, AR5K_INI_WRITE },
581 { AR5K_RATE_DUR(1), 0x0000008c, AR5K_INI_WRITE },
582 { AR5K_RATE_DUR(2), 0x000000e4, AR5K_INI_WRITE },
583 { AR5K_RATE_DUR(3), 0x000002d5, AR5K_INI_WRITE },
584 { AR5K_RATE_DUR(4), 0x00000000, AR5K_INI_WRITE },
585 { AR5K_RATE_DUR(5), 0x00000000, AR5K_INI_WRITE },
586 { AR5K_RATE_DUR(6), 0x000000a0, AR5K_INI_WRITE },
587 { AR5K_RATE_DUR(7), 0x000001c9, AR5K_INI_WRITE },
588 { AR5K_RATE_DUR(8), 0x0000002c, AR5K_INI_WRITE },
589 { AR5K_RATE_DUR(9), 0x0000002c, AR5K_INI_WRITE },
590 { AR5K_RATE_DUR(10), 0x00000030, AR5K_INI_WRITE },
591 { AR5K_RATE_DUR(11), 0x0000003c, AR5K_INI_WRITE },
592 { AR5K_RATE_DUR(12), 0x0000002c, AR5K_INI_WRITE },
593 { AR5K_RATE_DUR(13), 0x0000002c, AR5K_INI_WRITE },
594 { AR5K_RATE_DUR(14), 0x00000030, AR5K_INI_WRITE },
595 { AR5K_RATE_DUR(15), 0x0000003c, AR5K_INI_WRITE },
596 { AR5K_RATE_DUR(16), 0x00000000, AR5K_INI_WRITE },
597 { AR5K_RATE_DUR(17), 0x00000000, AR5K_INI_WRITE },
598 { AR5K_RATE_DUR(18), 0x00000000, AR5K_INI_WRITE },
599 { AR5K_RATE_DUR(19), 0x00000000, AR5K_INI_WRITE },
600 { AR5K_RATE_DUR(20), 0x00000000, AR5K_INI_WRITE },
601 { AR5K_RATE_DUR(21), 0x00000000, AR5K_INI_WRITE },
602 { AR5K_RATE_DUR(22), 0x00000000, AR5K_INI_WRITE },
603 { AR5K_RATE_DUR(23), 0x00000000, AR5K_INI_WRITE },
604 { AR5K_RATE_DUR(24), 0x000000d5, AR5K_INI_WRITE },
605 { AR5K_RATE_DUR(25), 0x000000df, AR5K_INI_WRITE },
606 { AR5K_RATE_DUR(26), 0x00000102, AR5K_INI_WRITE },
607 { AR5K_RATE_DUR(27), 0x0000013a, AR5K_INI_WRITE },
608 { AR5K_RATE_DUR(28), 0x00000075, AR5K_INI_WRITE },
609 { AR5K_RATE_DUR(29), 0x0000007f, AR5K_INI_WRITE },
610 { AR5K_RATE_DUR(30), 0x000000a2, AR5K_INI_WRITE },
611 { AR5K_RATE_DUR(31), 0x00000000, AR5K_INI_WRITE },
612 { AR5K_QUIET_CTL2, 0x00010002, AR5K_INI_WRITE },
613 { AR5K_TSF_PARM, 0x00000001, AR5K_INI_WRITE },
614 { AR5K_QOS_NOACK, 0x000000c0, AR5K_INI_WRITE },
615 { AR5K_PHY_ERR_FIL, 0x00000000, AR5K_INI_WRITE },
616 { AR5K_XRLAT_TX, 0x00000168, AR5K_INI_WRITE },
617 { AR5K_ACKSIFS, 0x00000000, AR5K_INI_WRITE },
618 /* Rate -> db table
619 * notice ...03<-02<-01<-00 ! */
620 { AR5K_RATE2DB(0), 0x03020100, AR5K_INI_WRITE },
621 { AR5K_RATE2DB(1), 0x07060504, AR5K_INI_WRITE },
622 { AR5K_RATE2DB(2), 0x0b0a0908, AR5K_INI_WRITE },
623 { AR5K_RATE2DB(3), 0x0f0e0d0c, AR5K_INI_WRITE },
624 { AR5K_RATE2DB(4), 0x13121110, AR5K_INI_WRITE },
625 { AR5K_RATE2DB(5), 0x17161514, AR5K_INI_WRITE },
626 { AR5K_RATE2DB(6), 0x1b1a1918, AR5K_INI_WRITE },
627 { AR5K_RATE2DB(7), 0x1f1e1d1c, AR5K_INI_WRITE },
628 /* Db -> Rate table */
629 { AR5K_DB2RATE(0), 0x03020100, AR5K_INI_WRITE },
630 { AR5K_DB2RATE(1), 0x07060504, AR5K_INI_WRITE },
631 { AR5K_DB2RATE(2), 0x0b0a0908, AR5K_INI_WRITE },
632 { AR5K_DB2RATE(3), 0x0f0e0d0c, AR5K_INI_WRITE },
633 { AR5K_DB2RATE(4), 0x13121110, AR5K_INI_WRITE },
634 { AR5K_DB2RATE(5), 0x17161514, AR5K_INI_WRITE },
635 { AR5K_DB2RATE(6), 0x1b1a1918, AR5K_INI_WRITE },
636 { AR5K_DB2RATE(7), 0x1f1e1d1c, AR5K_INI_WRITE },
637 /* PHY registers (Common settings
638 * for all chips/modes) */
639 { AR5K_PHY(3), 0xad848e19, AR5K_INI_WRITE },
640 { AR5K_PHY(4), 0x7d28e000, AR5K_INI_WRITE },
641 { AR5K_PHY_TIMING_3, 0x9c0a9f6b, AR5K_INI_WRITE },
642 { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
643 { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
644 { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
645 { AR5K_PHY_BIN_MASK_1, 0x00000000, AR5K_INI_WRITE },
646 { AR5K_PHY_BIN_MASK_2, 0x00000000, AR5K_INI_WRITE },
647 { AR5K_PHY_BIN_MASK_3, 0x00000000, AR5K_INI_WRITE },
648 { AR5K_PHY_BIN_MASK_CTL, 0x00800000, AR5K_INI_WRITE },
649 { AR5K_PHY_ANT_CTL, 0x00000001, AR5K_INI_WRITE },
650 /*{ AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },*/ /* Old value */
651 { AR5K_PHY_MAX_RX_LEN, 0x00000c80, AR5K_INI_WRITE },
652 { AR5K_PHY_IQ, 0x05100000, AR5K_INI_WRITE },
653 { AR5K_PHY_WARM_RESET, 0x00000001, AR5K_INI_WRITE },
654 { AR5K_PHY_CTL, 0x00000004, AR5K_INI_WRITE },
655 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022, AR5K_INI_WRITE },
656 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d, AR5K_INI_WRITE },
657 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f, AR5K_INI_WRITE },
658 { AR5K_PHY(82), 0x9280b212, AR5K_INI_WRITE },
659 { AR5K_PHY_RADAR, 0x5d50e188, AR5K_INI_WRITE },
660 /*{ AR5K_PHY(86), 0x000000ff, AR5K_INI_WRITE },*/
661 { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
662 { AR5K_PHY_NFTHRES, 0x000003ce, AR5K_INI_WRITE },
663 { AR5K_PHY_RESTART, 0x192fb515, AR5K_INI_WRITE },
664 { AR5K_PHY(94), 0x00000001, AR5K_INI_WRITE },
665 { AR5K_PHY_RFBUS_REQ, 0x00000000, AR5K_INI_WRITE },
666 /*{ AR5K_PHY(644), 0x0080a333, AR5K_INI_WRITE },*/ /* Old value */
667 /*{ AR5K_PHY(645), 0x00206c10, AR5K_INI_WRITE },*/ /* Old value */
668 { AR5K_PHY(644), 0x00806333, AR5K_INI_WRITE },
669 { AR5K_PHY(645), 0x00106c10, AR5K_INI_WRITE },
670 { AR5K_PHY(646), 0x009c4060, AR5K_INI_WRITE },
671 /* { AR5K_PHY(647), 0x1483800a, AR5K_INI_WRITE }, */
672 /* { AR5K_PHY(648), 0x01831061, AR5K_INI_WRITE }, */ /* Old value */
673 { AR5K_PHY(648), 0x018830c6, AR5K_INI_WRITE },
674 { AR5K_PHY(649), 0x00000400, AR5K_INI_WRITE },
675 /*{ AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },*/
676 { AR5K_PHY(651), 0x00000000, AR5K_INI_WRITE },
677 { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
678 { AR5K_PHY_TXPOWER_RATE2, 0x20202020, AR5K_INI_WRITE },
679 /*{ AR5K_PHY(655), 0x13c889af, AR5K_INI_WRITE },*/
680 { AR5K_PHY(656), 0x38490a20, AR5K_INI_WRITE },
681 { AR5K_PHY(657), 0x00007bb6, AR5K_INI_WRITE },
682 { AR5K_PHY(658), 0x0fff3ffc, AR5K_INI_WRITE },
683};
684
685/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
686static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
687 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
688 /* a/XR aTurbo b g (DYN) gTurbo */
689 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
690 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
691 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
692 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
693 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
694 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
695 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
696 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
697 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
698 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
699 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
700 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
701 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
702 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
703 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
704 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
705 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
706 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
707 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
708 { AR5K_DCU_GBL_IFS_SIFS,
709 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
710 { AR5K_DCU_GBL_IFS_SLOT,
711 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
712 { AR5K_DCU_GBL_IFS_EIFS,
713 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
714 { AR5K_DCU_GBL_IFS_MISC,
715 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
716 { AR5K_TIME_OUT,
717 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
718 { AR5K_PHY_TURBO,
719 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
720 { AR5K_PHY(8),
721 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
722 { AR5K_PHY_RF_CTL2,
723 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
724 { AR5K_PHY_SETTLING,
725 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
726 { AR5K_PHY_AGCCTL,
727 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
728 { AR5K_PHY_NF,
729 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
730 { AR5K_PHY_WEAK_OFDM_HIGH_THR,
731 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
732 { AR5K_PHY(70),
733 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
734 { AR5K_PHY_OFDM_SELFCORR,
735 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
736 { 0xa230,
737 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
738};
739
740/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
741static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
742 { AR5K_TXCFG,
743 /* a/XR aTurbo b g (DYN) gTurbo */
744 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
745 { AR5K_USEC_5211,
746 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
747 { AR5K_PHY_RF_CTL3,
748 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
749 { AR5K_PHY_RF_CTL4,
750 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
751 { AR5K_PHY_PA_CTL,
752 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
753 { AR5K_PHY_GAIN,
754 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
755 { AR5K_PHY_DESIRED_SIZE,
756 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
757 { AR5K_PHY_SIG,
758 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
759 { AR5K_PHY_AGCCOARSE,
760 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
761 { AR5K_PHY_WEAK_OFDM_LOW_THR,
762 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
763 { AR5K_PHY_RX_DELAY,
764 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
765 { AR5K_PHY_FRAME_CTL_5211,
766 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
767 { AR5K_PHY_GAIN_2GHZ,
768 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
769 { AR5K_PHY_CCK_RX_CTL_4,
770 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
771};
772
773static const struct ath5k_ini rf5111_ini_common_end[] = {
774 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
775 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
776 { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
777 { 0x983c, 0x00020100, AR5K_INI_WRITE },
778 { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
779 { AR5K_PHY_PAPD_PROBE, 0x00004883, AR5K_INI_WRITE },
780 { 0x9940, 0x00000004, AR5K_INI_WRITE },
781 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
782 { 0x9974, 0x00000000, AR5K_INI_WRITE },
783 { AR5K_PHY_SPENDING, 0x00000018, AR5K_INI_WRITE },
784 { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
785 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE },
786 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
787 { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
788};
789
790/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
791static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
792 { AR5K_TXCFG,
793 /* a/XR aTurbo b g (DYN) gTurbo */
794 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
795 { AR5K_USEC_5211,
796 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
797 { AR5K_PHY_RF_CTL3,
798 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
799 { AR5K_PHY_RF_CTL4,
800 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
801 { AR5K_PHY_PA_CTL,
802 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
803 { AR5K_PHY_GAIN,
804 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
805 { AR5K_PHY_DESIRED_SIZE,
806 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
807 { AR5K_PHY_SIG,
808 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
809 { AR5K_PHY_AGCCOARSE,
810 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
811 { AR5K_PHY_WEAK_OFDM_LOW_THR,
812 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
813 { AR5K_PHY_RX_DELAY,
814 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
815 { AR5K_PHY_FRAME_CTL_5211,
816 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
817 { AR5K_PHY_CCKTXCTL,
818 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
819 { AR5K_PHY_CCK_CROSSCORR,
820 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
821 { AR5K_PHY_GAIN_2GHZ,
822 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
823 { AR5K_PHY_CCK_RX_CTL_4,
824 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
825};
826
827static const struct ath5k_ini rf5112_ini_common_end[] = {
828 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
829 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
830 { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
831 { 0x983c, 0x00020100, AR5K_INI_WRITE },
832 { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
833 { AR5K_PHY_PAPD_PROBE, 0x00004882, AR5K_INI_WRITE },
834 { 0x9940, 0x00000004, AR5K_INI_WRITE },
835 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
836 { 0x9974, 0x00000000, AR5K_INI_WRITE },
837 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
838 { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
839};
840
841/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
842static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
843 { AR5K_TXCFG,
844 /* a/XR aTurbo b g (DYN) gTurbo */
845 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
846 { AR5K_USEC_5211,
847 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
848 { AR5K_PHY_RF_CTL3,
849 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
850 { AR5K_PHY_RF_CTL4,
851 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
852 { AR5K_PHY_PA_CTL,
853 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
854 { AR5K_PHY_GAIN,
855 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
856 { AR5K_PHY_DESIRED_SIZE,
857 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
858 { AR5K_PHY_SIG,
859 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
860 { AR5K_PHY_AGCCOARSE,
861 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
862 { AR5K_PHY_WEAK_OFDM_LOW_THR,
863 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
864 { AR5K_PHY_RX_DELAY,
865 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
866 { AR5K_PHY_FRAME_CTL_5211,
867 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
868 { AR5K_PHY_CCKTXCTL,
869 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
870 { AR5K_PHY_CCK_CROSSCORR,
871 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
872 { AR5K_PHY_GAIN_2GHZ,
873 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
874 { AR5K_PHY_CCK_RX_CTL_4,
875 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
876 { 0xa300,
877 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
878 { 0xa304,
879 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
880 { 0xa308,
881 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
882 { 0xa30c,
883 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
884 { 0xa310,
885 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
886 { 0xa314,
887 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
888 { 0xa318,
889 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
890 { 0xa31c,
891 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
892 { 0xa320,
893 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
894 { 0xa324,
895 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
896 { 0xa328,
897 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
898 { 0xa32c,
899 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
900 { 0xa330,
901 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
902 { 0xa334,
903 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
904};
905
906static const struct ath5k_ini rf5413_ini_common_end[] = {
907 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
908 { AR5K_5414_CBCFG, 0x00000010, AR5K_INI_WRITE },
909 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
910 { 0x809c, 0x00000000, AR5K_INI_WRITE },
911 { 0x80a0, 0x00000000, AR5K_INI_WRITE },
912 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
913 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
914 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
915 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
916 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
917 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
918 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
919 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
920 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
921 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
922 { 0x8140, 0x800003f9, AR5K_INI_WRITE },
923 { 0x8144, 0x00000000, AR5K_INI_WRITE },
924 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
925 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
926 { 0x983c, 0x00200400, AR5K_INI_WRITE },
927 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
928 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
929 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
930 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
931 { 0x9958, 0x00081fff, AR5K_INI_WRITE },
932 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
933 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
934 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
935 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
936 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
937 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
938 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
939 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
940 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
941 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
942 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
943 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
944 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
945 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
946 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
947 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
948 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
949 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
950 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
951 { 0xa268, 0x00000000, AR5K_INI_WRITE },
952 { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
953 { 0xa270, 0x00820820, AR5K_INI_WRITE },
954 { 0xa274, 0x081b7caa, AR5K_INI_WRITE },
955 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
956 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
957 { 0xa338, 0x00000000, AR5K_INI_WRITE },
958 { 0xa33c, 0x00000000, AR5K_INI_WRITE },
959 { 0xa340, 0x00000000, AR5K_INI_WRITE },
960 { 0xa344, 0x00000000, AR5K_INI_WRITE },
961 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
962 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
963 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
964 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
965 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
966 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
967 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
968 { 0xa364, 0x17601685, AR5K_INI_WRITE },
969 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
970 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
971 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
972 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
973 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
974 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
975 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
976 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
977};
978
979/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
980/* XXX: a mode ? */
981static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
982 { AR5K_TXCFG,
983 /* a/XR aTurbo b g (DYN) gTurbo */
984 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
985 { AR5K_USEC_5211,
986 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
987 { AR5K_PHY_RF_CTL3,
988 { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
989 { AR5K_PHY_RF_CTL4,
990 { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
991 { AR5K_PHY_PA_CTL,
992 { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
993 { AR5K_PHY_GAIN,
994 { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
995 { AR5K_PHY_DESIRED_SIZE,
996 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
997 { AR5K_PHY_SIG,
998 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
999 { AR5K_PHY_AGCCOARSE,
1000 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
1001 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1002 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1003 { AR5K_PHY_RX_DELAY,
1004 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1005 { AR5K_PHY_FRAME_CTL_5211,
1006 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1007 { AR5K_PHY_CCKTXCTL,
1008 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1009 { AR5K_PHY_CCK_CROSSCORR,
1010 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1011 { AR5K_PHY_GAIN_2GHZ,
1012 { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
1013 { AR5K_PHY_CCK_RX_CTL_4,
1014 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1015};
1016
1017static const struct ath5k_ini rf2413_ini_common_end[] = {
1018 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
1019 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
1020 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
1021 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
1022 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
1023 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1024 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1025 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
1026 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
1027 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
1028 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
1029 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
1030 { 0x8140, 0x800000a8, AR5K_INI_WRITE },
1031 { 0x8144, 0x00000000, AR5K_INI_WRITE },
1032 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
1033 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
1034 { 0x983c, 0x00200400, AR5K_INI_WRITE },
1035 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
1036 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
1037 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1038 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
1039 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
1040 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
1041 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
1042 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
1043 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
1044 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
1045 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
1046 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
1047 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
1048 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
1049 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
1050 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
1051 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
1052 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
1053 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
1054 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
1055 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
1056 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
1057 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
1058 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
1059 { 0xa268, 0x00000000, AR5K_INI_WRITE },
1060 { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
1061 { 0xa270, 0x00820820, AR5K_INI_WRITE },
1062 { 0xa274, 0x001b7caa, AR5K_INI_WRITE },
1063 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
1064 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
1065 { 0xa300, 0x18010000, AR5K_INI_WRITE },
1066 { 0xa304, 0x30032602, AR5K_INI_WRITE },
1067 { 0xa308, 0x48073e06, AR5K_INI_WRITE },
1068 { 0xa30c, 0x560b4c0a, AR5K_INI_WRITE },
1069 { 0xa310, 0x641a600f, AR5K_INI_WRITE },
1070 { 0xa314, 0x784f6e1b, AR5K_INI_WRITE },
1071 { 0xa318, 0x868f7c5a, AR5K_INI_WRITE },
1072 { 0xa31c, 0x8ecf865b, AR5K_INI_WRITE },
1073 { 0xa320, 0x9d4f970f, AR5K_INI_WRITE },
1074 { 0xa324, 0xa5cfa18f, AR5K_INI_WRITE },
1075 { 0xa328, 0xb55faf1f, AR5K_INI_WRITE },
1076 { 0xa32c, 0xbddfb99f, AR5K_INI_WRITE },
1077 { 0xa330, 0xcd7fc73f, AR5K_INI_WRITE },
1078 { 0xa334, 0xd5ffd1bf, AR5K_INI_WRITE },
1079 { 0xa338, 0x00000000, AR5K_INI_WRITE },
1080 { 0xa33c, 0x00000000, AR5K_INI_WRITE },
1081 { 0xa340, 0x00000000, AR5K_INI_WRITE },
1082 { 0xa344, 0x00000000, AR5K_INI_WRITE },
1083 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
1084 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
1085 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
1086 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
1087 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
1088 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
1089 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
1090 { 0xa364, 0x17601685, AR5K_INI_WRITE },
1091 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
1092 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
1093 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
1094 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
1095 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
1096 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
1097 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
1098 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
1099};
1100
1101/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1102/* XXX: a mode ? */
1103static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1104 { AR5K_TXCFG,
1105 /* a/XR aTurbo b g (DYN) gTurbo */
1106 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
1107 { AR5K_USEC_5211,
1108 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
1109 { AR5K_PHY_TURBO,
1110 { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
1111 { AR5K_PHY_RF_CTL3,
1112 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
1113 { AR5K_PHY_RF_CTL4,
1114 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1115 { AR5K_PHY_PA_CTL,
1116 { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
1117 { AR5K_PHY_SETTLING,
1118 { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
1119 { AR5K_PHY_GAIN,
1120 { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
1121 { AR5K_PHY_DESIRED_SIZE,
1122 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
1123 { AR5K_PHY_SIG,
1124 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1125 { AR5K_PHY_AGCCOARSE,
1126 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
1127 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1128 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1129 { AR5K_PHY_RX_DELAY,
1130 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1131 { AR5K_PHY_FRAME_CTL_5211,
1132 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1133 { AR5K_PHY_CCKTXCTL,
1134 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1135 { AR5K_PHY_CCK_CROSSCORR,
1136 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1137 { AR5K_PHY_GAIN_2GHZ,
1138 { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
1139 { AR5K_PHY_CCK_RX_CTL_4,
1140 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1141 { 0xa324,
1142 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1143 { 0xa328,
1144 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1145 { 0xa32c,
1146 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1147 { 0xa330,
1148 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1149 { 0xa334,
1150 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1151};
1152
1153static const struct ath5k_ini rf2425_ini_common_end[] = {
1154 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
1155 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
1156 { 0x809c, 0x00000000, AR5K_INI_WRITE },
1157 { 0x80a0, 0x00000000, AR5K_INI_WRITE },
1158 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
1159 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
1160 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
1161 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1162 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1163 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
1164 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
1165 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
1166 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
1167 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
1168 { 0x8140, 0x800003f9, AR5K_INI_WRITE },
1169 { 0x8144, 0x00000000, AR5K_INI_WRITE },
1170 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
1171 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
1172 { 0x983c, 0x00200400, AR5K_INI_WRITE },
1173 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
1174 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
1175 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1176 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
1177 { 0x9958, 0x00081fff, AR5K_INI_WRITE },
1178 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
1179 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
1180 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
1181 { 0x99dc, 0xfebadbe8, AR5K_INI_WRITE },
1182 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
1183 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
1184 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
1185 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
1186 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
1187 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
1188 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
1189 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
1190 { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
1191 { AR5K_PHY_TXPOWER_RATE4, 0x20202020, AR5K_INI_WRITE },
1192 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
1193 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
1194 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
1195 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
1196 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
1197 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
1198 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
1199 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
1200 { 0xa268, 0x00000000, AR5K_INI_WRITE },
1201 { AR5K_PHY_TPC_RG5, 0x0c30c166, AR5K_INI_WRITE },
1202 { 0xa270, 0x00820820, AR5K_INI_WRITE },
1203 { 0xa274, 0x081a3caa, AR5K_INI_WRITE },
1204 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
1205 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
1206 { 0xa300, 0x16010000, AR5K_INI_WRITE },
1207 { 0xa304, 0x2c032402, AR5K_INI_WRITE },
1208 { 0xa308, 0x48433e42, AR5K_INI_WRITE },
1209 { 0xa30c, 0x5a0f500b, AR5K_INI_WRITE },
1210 { 0xa310, 0x6c4b624a, AR5K_INI_WRITE },
1211 { 0xa314, 0x7e8b748a, AR5K_INI_WRITE },
1212 { 0xa318, 0x96cf8ccb, AR5K_INI_WRITE },
1213 { 0xa31c, 0xa34f9d0f, AR5K_INI_WRITE },
1214 { 0xa320, 0xa7cfa58f, AR5K_INI_WRITE },
1215 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
1216 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
1217 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
1218 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
1219 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
1220 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
1221 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
1222 { 0xa364, 0x17601685, AR5K_INI_WRITE },
1223 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
1224 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
1225 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
1226 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
1227 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
1228 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
1229 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
1230 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
1231};
1232
1233/*
1234 * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
1235 * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
1236 */
1237
1238/* RF5111 Initial BaseBand Gain settings */
1239static const struct ath5k_ini rf5111_ini_bbgain[] = {
1240 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
1241 { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
1242 { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
1243 { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
1244 { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
1245 { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
1246 { AR5K_BB_GAIN(6), 0x00000004, AR5K_INI_WRITE },
1247 { AR5K_BB_GAIN(7), 0x00000024, AR5K_INI_WRITE },
1248 { AR5K_BB_GAIN(8), 0x00000014, AR5K_INI_WRITE },
1249 { AR5K_BB_GAIN(9), 0x00000034, AR5K_INI_WRITE },
1250 { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
1251 { AR5K_BB_GAIN(11), 0x0000002c, AR5K_INI_WRITE },
1252 { AR5K_BB_GAIN(12), 0x00000002, AR5K_INI_WRITE },
1253 { AR5K_BB_GAIN(13), 0x00000022, AR5K_INI_WRITE },
1254 { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
1255 { AR5K_BB_GAIN(15), 0x00000032, AR5K_INI_WRITE },
1256 { AR5K_BB_GAIN(16), 0x0000000a, AR5K_INI_WRITE },
1257 { AR5K_BB_GAIN(17), 0x0000002a, AR5K_INI_WRITE },
1258 { AR5K_BB_GAIN(18), 0x00000006, AR5K_INI_WRITE },
1259 { AR5K_BB_GAIN(19), 0x00000026, AR5K_INI_WRITE },
1260 { AR5K_BB_GAIN(20), 0x00000016, AR5K_INI_WRITE },
1261 { AR5K_BB_GAIN(21), 0x00000036, AR5K_INI_WRITE },
1262 { AR5K_BB_GAIN(22), 0x0000000e, AR5K_INI_WRITE },
1263 { AR5K_BB_GAIN(23), 0x0000002e, AR5K_INI_WRITE },
1264 { AR5K_BB_GAIN(24), 0x00000001, AR5K_INI_WRITE },
1265 { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
1266 { AR5K_BB_GAIN(26), 0x00000011, AR5K_INI_WRITE },
1267 { AR5K_BB_GAIN(27), 0x00000031, AR5K_INI_WRITE },
1268 { AR5K_BB_GAIN(28), 0x00000009, AR5K_INI_WRITE },
1269 { AR5K_BB_GAIN(29), 0x00000029, AR5K_INI_WRITE },
1270 { AR5K_BB_GAIN(30), 0x00000005, AR5K_INI_WRITE },
1271 { AR5K_BB_GAIN(31), 0x00000025, AR5K_INI_WRITE },
1272 { AR5K_BB_GAIN(32), 0x00000015, AR5K_INI_WRITE },
1273 { AR5K_BB_GAIN(33), 0x00000035, AR5K_INI_WRITE },
1274 { AR5K_BB_GAIN(34), 0x0000000d, AR5K_INI_WRITE },
1275 { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
1276 { AR5K_BB_GAIN(36), 0x00000003, AR5K_INI_WRITE },
1277 { AR5K_BB_GAIN(37), 0x00000023, AR5K_INI_WRITE },
1278 { AR5K_BB_GAIN(38), 0x00000013, AR5K_INI_WRITE },
1279 { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
1280 { AR5K_BB_GAIN(40), 0x0000000b, AR5K_INI_WRITE },
1281 { AR5K_BB_GAIN(41), 0x0000002b, AR5K_INI_WRITE },
1282 { AR5K_BB_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
1283 { AR5K_BB_GAIN(43), 0x0000002b, AR5K_INI_WRITE },
1284 { AR5K_BB_GAIN(44), 0x0000002b, AR5K_INI_WRITE },
1285 { AR5K_BB_GAIN(45), 0x0000002b, AR5K_INI_WRITE },
1286 { AR5K_BB_GAIN(46), 0x0000002b, AR5K_INI_WRITE },
1287 { AR5K_BB_GAIN(47), 0x0000002b, AR5K_INI_WRITE },
1288 { AR5K_BB_GAIN(48), 0x0000002b, AR5K_INI_WRITE },
1289 { AR5K_BB_GAIN(49), 0x0000002b, AR5K_INI_WRITE },
1290 { AR5K_BB_GAIN(50), 0x0000002b, AR5K_INI_WRITE },
1291 { AR5K_BB_GAIN(51), 0x0000002b, AR5K_INI_WRITE },
1292 { AR5K_BB_GAIN(52), 0x0000002b, AR5K_INI_WRITE },
1293 { AR5K_BB_GAIN(53), 0x0000002b, AR5K_INI_WRITE },
1294 { AR5K_BB_GAIN(54), 0x0000002b, AR5K_INI_WRITE },
1295 { AR5K_BB_GAIN(55), 0x0000002b, AR5K_INI_WRITE },
1296 { AR5K_BB_GAIN(56), 0x0000002b, AR5K_INI_WRITE },
1297 { AR5K_BB_GAIN(57), 0x0000002b, AR5K_INI_WRITE },
1298 { AR5K_BB_GAIN(58), 0x0000002b, AR5K_INI_WRITE },
1299 { AR5K_BB_GAIN(59), 0x0000002b, AR5K_INI_WRITE },
1300 { AR5K_BB_GAIN(60), 0x0000002b, AR5K_INI_WRITE },
1301 { AR5K_BB_GAIN(61), 0x0000002b, AR5K_INI_WRITE },
1302 { AR5K_BB_GAIN(62), 0x00000002, AR5K_INI_WRITE },
1303 { AR5K_BB_GAIN(63), 0x00000016, AR5K_INI_WRITE },
1304};
1305
1306/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
1307static const struct ath5k_ini rf5112_ini_bbgain[] = {
1308 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
1309 { AR5K_BB_GAIN(1), 0x00000001, AR5K_INI_WRITE },
1310 { AR5K_BB_GAIN(2), 0x00000002, AR5K_INI_WRITE },
1311 { AR5K_BB_GAIN(3), 0x00000003, AR5K_INI_WRITE },
1312 { AR5K_BB_GAIN(4), 0x00000004, AR5K_INI_WRITE },
1313 { AR5K_BB_GAIN(5), 0x00000005, AR5K_INI_WRITE },
1314 { AR5K_BB_GAIN(6), 0x00000008, AR5K_INI_WRITE },
1315 { AR5K_BB_GAIN(7), 0x00000009, AR5K_INI_WRITE },
1316 { AR5K_BB_GAIN(8), 0x0000000a, AR5K_INI_WRITE },
1317 { AR5K_BB_GAIN(9), 0x0000000b, AR5K_INI_WRITE },
1318 { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
1319 { AR5K_BB_GAIN(11), 0x0000000d, AR5K_INI_WRITE },
1320 { AR5K_BB_GAIN(12), 0x00000010, AR5K_INI_WRITE },
1321 { AR5K_BB_GAIN(13), 0x00000011, AR5K_INI_WRITE },
1322 { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
1323 { AR5K_BB_GAIN(15), 0x00000013, AR5K_INI_WRITE },
1324 { AR5K_BB_GAIN(16), 0x00000014, AR5K_INI_WRITE },
1325 { AR5K_BB_GAIN(17), 0x00000015, AR5K_INI_WRITE },
1326 { AR5K_BB_GAIN(18), 0x00000018, AR5K_INI_WRITE },
1327 { AR5K_BB_GAIN(19), 0x00000019, AR5K_INI_WRITE },
1328 { AR5K_BB_GAIN(20), 0x0000001a, AR5K_INI_WRITE },
1329 { AR5K_BB_GAIN(21), 0x0000001b, AR5K_INI_WRITE },
1330 { AR5K_BB_GAIN(22), 0x0000001c, AR5K_INI_WRITE },
1331 { AR5K_BB_GAIN(23), 0x0000001d, AR5K_INI_WRITE },
1332 { AR5K_BB_GAIN(24), 0x00000020, AR5K_INI_WRITE },
1333 { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
1334 { AR5K_BB_GAIN(26), 0x00000022, AR5K_INI_WRITE },
1335 { AR5K_BB_GAIN(27), 0x00000023, AR5K_INI_WRITE },
1336 { AR5K_BB_GAIN(28), 0x00000024, AR5K_INI_WRITE },
1337 { AR5K_BB_GAIN(29), 0x00000025, AR5K_INI_WRITE },
1338 { AR5K_BB_GAIN(30), 0x00000028, AR5K_INI_WRITE },
1339 { AR5K_BB_GAIN(31), 0x00000029, AR5K_INI_WRITE },
1340 { AR5K_BB_GAIN(32), 0x0000002a, AR5K_INI_WRITE },
1341 { AR5K_BB_GAIN(33), 0x0000002b, AR5K_INI_WRITE },
1342 { AR5K_BB_GAIN(34), 0x0000002c, AR5K_INI_WRITE },
1343 { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
1344 { AR5K_BB_GAIN(36), 0x00000030, AR5K_INI_WRITE },
1345 { AR5K_BB_GAIN(37), 0x00000031, AR5K_INI_WRITE },
1346 { AR5K_BB_GAIN(38), 0x00000032, AR5K_INI_WRITE },
1347 { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
1348 { AR5K_BB_GAIN(40), 0x00000034, AR5K_INI_WRITE },
1349 { AR5K_BB_GAIN(41), 0x00000035, AR5K_INI_WRITE },
1350 { AR5K_BB_GAIN(42), 0x00000035, AR5K_INI_WRITE },
1351 { AR5K_BB_GAIN(43), 0x00000035, AR5K_INI_WRITE },
1352 { AR5K_BB_GAIN(44), 0x00000035, AR5K_INI_WRITE },
1353 { AR5K_BB_GAIN(45), 0x00000035, AR5K_INI_WRITE },
1354 { AR5K_BB_GAIN(46), 0x00000035, AR5K_INI_WRITE },
1355 { AR5K_BB_GAIN(47), 0x00000035, AR5K_INI_WRITE },
1356 { AR5K_BB_GAIN(48), 0x00000035, AR5K_INI_WRITE },
1357 { AR5K_BB_GAIN(49), 0x00000035, AR5K_INI_WRITE },
1358 { AR5K_BB_GAIN(50), 0x00000035, AR5K_INI_WRITE },
1359 { AR5K_BB_GAIN(51), 0x00000035, AR5K_INI_WRITE },
1360 { AR5K_BB_GAIN(52), 0x00000035, AR5K_INI_WRITE },
1361 { AR5K_BB_GAIN(53), 0x00000035, AR5K_INI_WRITE },
1362 { AR5K_BB_GAIN(54), 0x00000035, AR5K_INI_WRITE },
1363 { AR5K_BB_GAIN(55), 0x00000035, AR5K_INI_WRITE },
1364 { AR5K_BB_GAIN(56), 0x00000035, AR5K_INI_WRITE },
1365 { AR5K_BB_GAIN(57), 0x00000035, AR5K_INI_WRITE },
1366 { AR5K_BB_GAIN(58), 0x00000035, AR5K_INI_WRITE },
1367 { AR5K_BB_GAIN(59), 0x00000035, AR5K_INI_WRITE },
1368 { AR5K_BB_GAIN(60), 0x00000035, AR5K_INI_WRITE },
1369 { AR5K_BB_GAIN(61), 0x00000035, AR5K_INI_WRITE },
1370 { AR5K_BB_GAIN(62), 0x00000010, AR5K_INI_WRITE },
1371 { AR5K_BB_GAIN(63), 0x0000001a, AR5K_INI_WRITE },
1372};
1373
1374
1375/*
1376 * Write initial register dump
1377 */
1378static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1379 const struct ath5k_ini *ini_regs, int change_channel)
1380{
1381 unsigned int i;
1382
1383 /* Write initial registers */
1384 for (i = 0; i < size; i++) {
1385 /* On channel change there is
1386 * no need to mess with PCU */
1387 if (change_channel &&
1388 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1389 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1390 continue;
1391
1392 switch (ini_regs[i].ini_mode) {
1393 case AR5K_INI_READ:
1394 /* Cleared on read */
1395 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
1396 break;
1397 case AR5K_INI_WRITE:
1398 default:
1399 AR5K_REG_WAIT(i);
1400 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1401 ini_regs[i].ini_register);
1402 }
1403 }
1404}
1405
1406static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1407 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1408 u8 mode)
1409{
1410 unsigned int i;
1411
1412 for (i = 0; i < size; i++) {
1413 AR5K_REG_WAIT(i);
1414 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1415 (u32)ini_mode[i].mode_register);
1416 }
1417}
1418
1419int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
1420{
1421 /*
1422 * Write initial register settings
1423 */
1424
1425 /* For AR5212 and combatible */
1426 if (ah->ah_version == AR5K_AR5212) {
1427
1428 /* First set of mode-specific settings */
1429 ath5k_hw_ini_mode_registers(ah,
1430 ARRAY_SIZE(ar5212_ini_mode_start),
1431 ar5212_ini_mode_start, mode);
1432
1433 /*
1434 * Write initial settings common for all modes
1435 */
1436 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
1437 ar5212_ini_common_start, change_channel);
1438
1439 /* Second set of mode-specific settings */
1440 switch (ah->ah_radio) {
1441 case AR5K_RF5111:
1442
1443 ath5k_hw_ini_mode_registers(ah,
1444 ARRAY_SIZE(rf5111_ini_mode_end),
1445 rf5111_ini_mode_end, mode);
1446
1447 ath5k_hw_ini_registers(ah,
1448 ARRAY_SIZE(rf5111_ini_common_end),
1449 rf5111_ini_common_end, change_channel);
1450
1451 /* Baseband gain table */
1452 ath5k_hw_ini_registers(ah,
1453 ARRAY_SIZE(rf5111_ini_bbgain),
1454 rf5111_ini_bbgain, change_channel);
1455
1456 break;
1457 case AR5K_RF5112:
1458
1459 ath5k_hw_ini_mode_registers(ah,
1460 ARRAY_SIZE(rf5112_ini_mode_end),
1461 rf5112_ini_mode_end, mode);
1462
1463 ath5k_hw_ini_registers(ah,
1464 ARRAY_SIZE(rf5112_ini_common_end),
1465 rf5112_ini_common_end, change_channel);
1466
1467 ath5k_hw_ini_registers(ah,
1468 ARRAY_SIZE(rf5112_ini_bbgain),
1469 rf5112_ini_bbgain, change_channel);
1470
1471 break;
1472 case AR5K_RF5413:
1473
1474 ath5k_hw_ini_mode_registers(ah,
1475 ARRAY_SIZE(rf5413_ini_mode_end),
1476 rf5413_ini_mode_end, mode);
1477
1478 ath5k_hw_ini_registers(ah,
1479 ARRAY_SIZE(rf5413_ini_common_end),
1480 rf5413_ini_common_end, change_channel);
1481
1482 ath5k_hw_ini_registers(ah,
1483 ARRAY_SIZE(rf5112_ini_bbgain),
1484 rf5112_ini_bbgain, change_channel);
1485
1486 break;
1487 case AR5K_RF2316:
1488 case AR5K_RF2413:
1489
1490 ath5k_hw_ini_mode_registers(ah,
1491 ARRAY_SIZE(rf2413_ini_mode_end),
1492 rf2413_ini_mode_end, mode);
1493
1494 ath5k_hw_ini_registers(ah,
1495 ARRAY_SIZE(rf2413_ini_common_end),
1496 rf2413_ini_common_end, change_channel);
1497
1498 /* Override settings from rf2413_ini_common_end */
1499 if (ah->ah_radio == AR5K_RF2316) {
1500 ath5k_hw_reg_write(ah, 0x00004000,
1501 AR5K_PHY_AGC);
1502 ath5k_hw_reg_write(ah, 0x081b7caa,
1503 0xa274);
1504 }
1505
1506 ath5k_hw_ini_registers(ah,
1507 ARRAY_SIZE(rf5112_ini_bbgain),
1508 rf5112_ini_bbgain, change_channel);
1509 break;
1510 case AR5K_RF2317:
1511 case AR5K_RF2425:
1512
1513 ath5k_hw_ini_mode_registers(ah,
1514 ARRAY_SIZE(rf2425_ini_mode_end),
1515 rf2425_ini_mode_end, mode);
1516
1517 ath5k_hw_ini_registers(ah,
1518 ARRAY_SIZE(rf2425_ini_common_end),
1519 rf2425_ini_common_end, change_channel);
1520
1521 ath5k_hw_ini_registers(ah,
1522 ARRAY_SIZE(rf5112_ini_bbgain),
1523 rf5112_ini_bbgain, change_channel);
1524 break;
1525 default:
1526 return -EINVAL;
1527
1528 }
1529
1530 /* For AR5211 */
1531 } else if (ah->ah_version == AR5K_AR5211) {
1532
1533 /* AR5K_MODE_11B */
1534 if (mode > 2) {
1535 DBG("ath5k: unsupported channel mode %d\n", mode);
1536 return -EINVAL;
1537 }
1538
1539 /* Mode-specific settings */
1540 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1541 ar5211_ini_mode, mode);
1542
1543 /*
1544 * Write initial settings common for all modes
1545 */
1546 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1547 ar5211_ini, change_channel);
1548
1549 /* AR5211 only comes with 5111 */
1550
1551 /* Baseband gain table */
1552 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1553 rf5111_ini_bbgain, change_channel);
1554 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1555 } else if (ah->ah_version == AR5K_AR5210) {
1556 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1557 ar5210_ini, change_channel);
1558 }
1559
1560 return 0;
1561}
AR5K_PHY_SCR
#define AR5K_PHY_SCR
Definition reg.h:2079
AR5K_PHY_CTL
#define AR5K_PHY_CTL
Definition reg.h:2222
AR5K_RX_FILTER_5211
#define AR5K_RX_FILTER_5211
Definition reg.h:1319
AR5K_BSS_IDM0
#define AR5K_BSS_IDM0
Definition reg.h:1645
AR5K_PHY_RF_CTL3
#define AR5K_PHY_RF_CTL3
Definition reg.h:1938
AR5K_PHY_SETTLING
#define AR5K_PHY_SETTLING
Definition reg.h:1970
AR5K_RSSI_THR
#define AR5K_RSSI_THR
Definition reg.h:1177
AR5K_RTSD1
#define AR5K_RTSD1
Definition reg.h:157
AR5K_RATE2DB
#define AR5K_RATE2DB(_n)
Definition reg.h:1794
AR5K_FRAME_CTL_QOSM
#define AR5K_FRAME_CTL_QOSM
Definition reg.h:1477
AR5K_DCU_FP
#define AR5K_DCU_FP
Definition reg.h:798
AR5K_NOQCU_TXDP0
#define AR5K_NOQCU_TXDP0
Definition reg.h:49
AR5K_PHY_IQ
#define AR5K_PHY_IQ
Definition reg.h:2185
AR5K_PHY_TIMING_11
#define AR5K_PHY_TIMING_11
Definition reg.h:2381
AR5K_QUIET_CTL2
#define AR5K_QUIET_CTL2
Definition reg.h:1681
AR5K_PHY_WARM_RESET
#define AR5K_PHY_WARM_RESET
Definition reg.h:2217
AR5K_PHY_ANT_CTL
#define AR5K_PHY_ANT_CTL
Definition reg.h:2163
AR5K_PHY_RFBUS_REQ
#define AR5K_PHY_RFBUS_REQ
Definition reg.h:2354
AR5K_XRTIMEOUT
#define AR5K_XRTIMEOUT
Definition reg.h:1589
AR5K_DB2RATE
#define AR5K_DB2RATE(_n)
Definition reg.h:1801
AR5K_CFP_PERIOD_5211
#define AR5K_CFP_PERIOD_5211
Definition reg.h:1250
AR5K_TIME_OUT
#define AR5K_TIME_OUT
Definition reg.h:1168
AR5K_PHY_TXPOWER_RATE4
#define AR5K_PHY_TXPOWER_RATE4
Definition reg.h:2261
AR5K_PHY_RF_CTL4
#define AR5K_PHY_RF_CTL4
Definition reg.h:1951
AR5K_XRDELAY
#define AR5K_XRDELAY
Definition reg.h:1580
AR5K_PHY_SCAL
#define AR5K_PHY_SCAL
Definition reg.h:2084
AR5K_MISC
#define AR5K_MISC
Definition reg.h:259
AR5K_PHY_GAIN_OFFSET
#define AR5K_PHY_GAIN_OFFSET
Definition reg.h:1985
AR5K_TIMER1_5211
#define AR5K_TIMER1_5211
Definition reg.h:1266
AR5K_MCAST_FILTER0_5210
#define AR5K_MCAST_FILTER0_5210
Definition reg.h:1344
AR5K_BEACON_5211
#define AR5K_BEACON_5211
Definition reg.h:1236
AR5K_PHY_RADAR
#define AR5K_PHY_RADAR
Definition reg.h:2302
AR5K_TOPS
#define AR5K_TOPS
Definition reg.h:225
AR5K_PHY_BLUETOOTH
#define AR5K_PHY_BLUETOOTH
Definition reg.h:2541
AR5K_CFP_PERIOD_5210
#define AR5K_CFP_PERIOD_5210
Definition reg.h:1249
AR5K_TSF_PARM
#define AR5K_TSF_PARM
Definition reg.h:1690
AR5K_IMR
#define AR5K_IMR
Definition reg.h:380
AR5K_MCAST_FILTER1_5211
#define AR5K_MCAST_FILTER1_5211
Definition reg.h:1353
AR5K_PHY_TURBO
#define AR5K_PHY_TURBO
Definition reg.h:1891
AR5K_PHY_NF
#define AR5K_PHY_NF
Definition reg.h:2032
AR5K_PHYERR_CNT1_MASK
#define AR5K_PHYERR_CNT1_MASK
Definition reg.h:1760
AR5K_MIC_QOS_CTL
#define AR5K_MIC_QOS_CTL
Definition reg.h:1727
AR5K_SLEEP2
#define AR5K_SLEEP2
Definition reg.h:1636
AR5K_DCU_TX_FILTER_CLR
#define AR5K_DCU_TX_FILTER_CLR
Definition reg.h:827
AR5K_XRSTOMP
#define AR5K_XRSTOMP
Definition reg.h:1605
AR5K_BSR
#define AR5K_BSR
Definition reg.h:142
AR5K_PHY_NFTHRES
#define AR5K_PHY_NFTHRES
Definition reg.h:2329
AR5K_PHY_DESIRED_SIZE
#define AR5K_PHY_DESIRED_SIZE
Definition reg.h:1992
AR5K_PHY_GAIN
#define AR5K_PHY_GAIN
Definition reg.h:1979
AR5K_PHY_CCK_CROSSCORR
#define AR5K_PHY_CCK_CROSSCORR
Definition reg.h:2514
AR5K_DCU_GBL_IFS_EIFS
#define AR5K_DCU_GBL_IFS_EIFS
Definition reg.h:771
AR5K_PHY_TXPOWER_RATE3
#define AR5K_PHY_TXPOWER_RATE3
Definition reg.h:2260
AR5K_BSS_IDM1
#define AR5K_BSS_IDM1
Definition reg.h:1646
AR5K_TX_MASK0
#define AR5K_TX_MASK0
Definition reg.h:1361
AR5K_MCAST_FILTER1_5210
#define AR5K_MCAST_FILTER1_5210
Definition reg.h:1352
AR5K_CLR_TMASK
#define AR5K_CLR_TMASK
Definition reg.h:1371
AR5K_DCU_TX_FILTER_0
#define AR5K_DCU_TX_FILTER_0(_n)
Definition reg.h:816
AR5K_DCU_GBL_IFS_SIFS
#define AR5K_DCU_GBL_IFS_SIFS
Definition reg.h:759
AR5K_PHY_ACT_ENABLE
#define AR5K_PHY_ACT_ENABLE
Definition reg.h:1928
AR5K_OFDM_FIL_CNT
#define AR5K_OFDM_FIL_CNT
Definition reg.h:1749
AR5K_PROFCNT_CYCLE
#define AR5K_PROFCNT_CYCLE
Definition reg.h:1670
AR5K_IER_DISABLE
#define AR5K_IER_DISABLE
Definition reg.h:93
AR5K_TIMER0_5210
#define AR5K_TIMER0_5210
Definition reg.h:1257
AR5K_PHY_AGCCTL
#define AR5K_PHY_AGCCTL
Definition reg.h:2023
AR5K_PHY_TXPOWER_RATE1
#define AR5K_PHY_TXPOWER_RATE1
Definition reg.h:2256
AR5K_QUIET_CTL1
#define AR5K_QUIET_CTL1
Definition reg.h:1675
AR5K_MIBC
#define AR5K_MIBC
Definition reg.h:216
AR5K_RXCFG
#define AR5K_RXCFG
Definition reg.h:198
AR5K_DCU_TX_FILTER_SET
#define AR5K_DCU_TX_FILTER_SET
Definition reg.h:832
AR5K_DCU_GBL_IFS_SLOT
#define AR5K_DCU_GBL_IFS_SLOT
Definition reg.h:765
AR5K_XRLAT_TX
#define AR5K_XRLAT_TX
Definition reg.h:1716
AR5K_TIMER0_5211
#define AR5K_TIMER0_5211
Definition reg.h:1258
AR5K_PHY_ACT
#define AR5K_PHY_ACT
Definition reg.h:1927
AR5K_QUEUE_DFS_LOCAL_IFS
#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)
Definition reg.h:686
AR5K_TSF_L32_5210
#define AR5K_TSF_L32_5210
Definition reg.h:1434
AR5K_TIMER3_5211
#define AR5K_TIMER3_5211
Definition reg.h:1282
AR5K_CFP_DUR_5210
#define AR5K_CFP_DUR_5210
Definition reg.h:1310
AR5K_PHY_TIMING_8
#define AR5K_PHY_TIMING_8
Definition reg.h:2361
AR5K_PHY_DAG_CCK_CTL
#define AR5K_PHY_DAG_CCK_CTL
Definition reg.h:2534
AR5K_TIMER3_5210
#define AR5K_TIMER3_5210
Definition reg.h:1281
AR5K_MISC_MODE
#define AR5K_MISC_MODE
Definition reg.h:1740
AR5K_RXDP
#define AR5K_RXDP
Definition reg.h:67
AR5K_CR
#define AR5K_CR
Definition reg.h:55
AR5K_SFR
#define AR5K_SFR
Definition reg.h:870
AR5K_TXNOFRM
#define AR5K_TXNOFRM
Definition reg.h:237
AR5K_PHY_TIMING_3
#define AR5K_PHY_TIMING_3
Definition reg.h:1913
AR5K_DCU_TX_FILTER_1
#define AR5K_DCU_TX_FILTER_1(_n)
Definition reg.h:822
AR5K_PHY_RESTART
#define AR5K_PHY_RESTART
Definition reg.h:2347
AR5K_USEC_5211
#define AR5K_USEC_5211
Definition reg.h:1216
AR5K_PHYERR_CNT2
#define AR5K_PHYERR_CNT2
Definition reg.h:1762
AR5K_TSF_THRES
#define AR5K_TSF_THRES
Definition reg.h:1768
AR5K_RATE_DUR
#define AR5K_RATE_DUR(_n)
Definition reg.h:1787
AR5K_MCAST_FILTER0_5211
#define AR5K_MCAST_FILTER0_5211
Definition reg.h:1345
AR5K_PHY_FRAME_CTL_5211
#define AR5K_PHY_FRAME_CTL_5211
Definition reg.h:2267
AR5K_ACKSIFS
#define AR5K_ACKSIFS
Definition reg.h:1721
AR5K_PHY_HEAVY_CLIP_ENABLE
#define AR5K_PHY_HEAVY_CLIP_ENABLE
Definition reg.h:2459
AR5K_PHY_PA_CTL
#define AR5K_PHY_PA_CTL
Definition reg.h:1961
AR5K_PHY_SDELAY
#define AR5K_PHY_SDELAY
Definition reg.h:2466
AR5K_PHY_PCDAC_TXPOWER_BASE
#define AR5K_PHY_PCDAC_TXPOWER_BASE
Definition reg.h:2481
AR5K_PHY_ADC_CTL
#define AR5K_PHY_ADC_CTL
Definition reg.h:1942
AR5K_PHY_TPC_RG1
#define AR5K_PHY_TPC_RG1
Definition reg.h:2547
AR5K_PHY_BIN_MASK_3
#define AR5K_PHY_BIN_MASK_3
Definition reg.h:2152
AR5K_XRMODE
#define AR5K_XRMODE
Definition reg.h:1567
AR5K_PHYERR_CNT1
#define AR5K_PHYERR_CNT1
Definition reg.h:1759
AR5K_RPGTO
#define AR5K_RPGTO
Definition reg.h:245
AR5K_PHY_SLMT
#define AR5K_PHY_SLMT
Definition reg.h:2081
AR5K_PHY_ACT_DISABLE
#define AR5K_PHY_ACT_DISABLE
Definition reg.h:1929
AR5K_TIMER2_5211
#define AR5K_TIMER2_5211
Definition reg.h:1274
AR5K_MIC_QOS_SEL
#define AR5K_MIC_QOS_SEL
Definition reg.h:1734
AR5K_PHY_TPC_RG5
#define AR5K_PHY_TPC_RG5
Definition reg.h:2557
AR5K_PHY_BIN_MASK_1
#define AR5K_PHY_BIN_MASK_1
Definition reg.h:2150
AR5K_TXCFG
#define AR5K_TXCFG
Definition reg.h:171
AR5K_PHY_SCLOCK
#define AR5K_PHY_SCLOCK
Definition reg.h:2464
AR5K_RTSD0
#define AR5K_RTSD0
Definition reg.h:116
AR5K_CFG
#define AR5K_CFG
Definition reg.h:72
AR5K_TRIG_LVL
#define AR5K_TRIG_LVL
Definition reg.h:1376
AR5K_PHY_PAPD_PROBE
#define AR5K_PHY_PAPD_PROBE
Definition reg.h:2235
AR5K_PROFCNT_TX
#define AR5K_PROFCNT_TX
Definition reg.h:1667
AR5K_PCU_MIN
#define AR5K_PCU_MIN
Definition reg.h:1111
AR5K_RXNOFRM
#define AR5K_RXNOFRM
Definition reg.h:231
AR5K_DIAG_SW_5211
#define AR5K_DIAG_SW_5211
Definition reg.h:1386
AR5K_STA_ID1
#define AR5K_STA_ID1
Definition reg.h:1123
AR5K_PHYERR_CNT2_MASK
#define AR5K_PHYERR_CNT2_MASK
Definition reg.h:1763
AR5K_PHY_TXPOWER_RATE2
#define AR5K_PHY_TXPOWER_RATE2
Definition reg.h:2257
AR5K_BSS_ID0
#define AR5K_BSS_ID0
Definition reg.h:1149
AR5K_PHY_AGCCOARSE
#define AR5K_PHY_AGCCOARSE
Definition reg.h:2014
AR5K_PHY_SIG
#define AR5K_PHY_SIG
Definition reg.h:2004
AR5K_PHY_RX_DELAY
#define AR5K_PHY_RX_DELAY
Definition reg.h:2173
AR5K_ADDAC_TEST
#define AR5K_ADDAC_TEST
Definition reg.h:1455
AR5K_PHY_CCKTXCTL
#define AR5K_PHY_CCKTXCTL
Definition reg.h:2505
AR5K_RF_BUFFER_CONTROL_4
#define AR5K_RF_BUFFER_CONTROL_4
Definition reg.h:2129
AR5K_PHY_MAX_RX_LEN
#define AR5K_PHY_MAX_RX_LEN
Definition reg.h:2179
AR5K_PROFCNT_RXCLR
#define AR5K_PROFCNT_RXCLR
Definition reg.h:1669
AR5K_RF_GAIN
#define AR5K_RF_GAIN(_n)
Definition reg.h:2395
AR5K_BSS_ID1
#define AR5K_BSS_ID1
Definition reg.h:1156
AR5K_DIAG_SW_5210
#define AR5K_DIAG_SW_5210
Definition reg.h:1385
AR5K_TX_MASK1
#define AR5K_TX_MASK1
Definition reg.h:1366
AR5K_PHY
#define AR5K_PHY(_n)
Definition reg.h:1856
AR5K_PHY_OFDM_SELFCORR
#define AR5K_PHY_OFDM_SELFCORR
Definition reg.h:2205
AR5K_NOQCU_TXDP1
#define AR5K_NOQCU_TXDP1
Definition reg.h:50
AR5K_PHY_FAST_ADC
#define AR5K_PHY_FAST_ADC
Definition reg.h:2539
AR5K_CCK_FIL_CNT
#define AR5K_CCK_FIL_CNT
Definition reg.h:1754
AR5K_PHY_BIN_MASK_2
#define AR5K_PHY_BIN_MASK_2
Definition reg.h:2151
AR5K_PHY_TXPOWER_RATE_MAX
#define AR5K_PHY_TXPOWER_RATE_MAX
Definition reg.h:2258
AR5K_PHY_RF_CTL2
#define AR5K_PHY_RF_CTL2
Definition reg.h:1934
AR5K_SEQ_MASK
#define AR5K_SEQ_MASK
Definition reg.h:1482
AR5K_TIMER2_5210
#define AR5K_TIMER2_5210
Definition reg.h:1273
AR5K_SLEEP1
#define AR5K_SLEEP1
Definition reg.h:1627
AR5K_PHY_AGC
#define AR5K_PHY_AGC
Definition reg.h:1900
AR5K_XRCHIRP
#define AR5K_XRCHIRP
Definition reg.h:1598
AR5K_PCU_MAX
#define AR5K_PCU_MAX
Definition reg.h:1112
AR5K_IER
#define AR5K_IER
Definition reg.h:92
AR5K_PHY_WEAK_OFDM_HIGH_THR
#define AR5K_PHY_WEAK_OFDM_HIGH_THR
Definition reg.h:2057
AR5K_PHY_WEAK_OFDM_LOW_THR
#define AR5K_PHY_WEAK_OFDM_LOW_THR
Definition reg.h:2066
AR5K_TXPC
#define AR5K_TXPC
Definition reg.h:1654
AR5K_QOS_NOACK
#define AR5K_QOS_NOACK
Definition reg.h:1697
AR5K_BB_GAIN
#define AR5K_BB_GAIN(_n)
Definition reg.h:2393
AR5K_DCU_TXP
#define AR5K_DCU_TXP
Definition reg.h:806
AR5K_TIMER1_5210
#define AR5K_TIMER1_5210
Definition reg.h:1265
AR5K_CFP_DUR_5211
#define AR5K_CFP_DUR_5211
Definition reg.h:1311
AR5K_QUEUE_TXDP
#define AR5K_QUEUE_TXDP(_q)
Definition reg.h:554
AR5K_PHY_ERR_FIL
#define AR5K_PHY_ERR_FIL
Definition reg.h:1708
AR5K_ISR
#define AR5K_ISR
Definition reg.h:287
AR5K_RFCNT
#define AR5K_RFCNT
Definition reg.h:251
AR5K_PHY_TIMING_7
#define AR5K_PHY_TIMING_7
Definition reg.h:2360
AR5K_PHY_PCDAC_TXPOWER
#define AR5K_PHY_PCDAC_TXPOWER(_n)
Definition reg.h:2482
AR5K_RX_FILTER_5210
#define AR5K_RX_FILTER_5210
Definition reg.h:1318
AR5K_PHY_CCK_RX_CTL_4
#define AR5K_PHY_CCK_RX_CTL_4
Definition reg.h:2530
AR5K_PHY_GAIN_2GHZ
#define AR5K_PHY_GAIN_2GHZ
Definition reg.h:2525
AR5K_PHY_BIN_MASK_CTL
#define AR5K_PHY_BIN_MASK_CTL
Definition reg.h:2154
AR5K_PHY_SPENDING
#define AR5K_PHY_SPENDING
Definition reg.h:2468
AR5K_PROFCNT_RX
#define AR5K_PROFCNT_RX
Definition reg.h:1668
AR5K_SLEEP0
#define AR5K_SLEEP0
Definition reg.h:1616
AR5K_DEFAULT_ANTENNA
#define AR5K_DEFAULT_ANTENNA
Definition reg.h:1471
AR5K_5414_CBCFG
#define AR5K_5414_CBCFG
Definition reg.h:978
AR5K_DCU_GBL_IFS_MISC
#define AR5K_DCU_GBL_IFS_MISC
Definition reg.h:784
AR5K_INIT_CFG
#define AR5K_INIT_CFG
Definition ath5k.h:203
AR5K_TUNE_MIN_TX_FIFO_THRES
#define AR5K_TUNE_MIN_TX_FIFO_THRES
Definition ath5k.h:169
ath5k_hw_reg_read
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition ath5k.h:1216
AR5K_TUNE_RSSI_THRES
#define AR5K_TUNE_RSSI_THRES
Definition ath5k.h:174
AR5K_DMASIZE_128B
@ AR5K_DMASIZE_128B
Definition ath5k.h:556
AR5K_AR5210
@ AR5K_AR5210
Definition ath5k.h:256
AR5K_AR5212
@ AR5K_AR5212
Definition ath5k.h:258
AR5K_AR5211
@ AR5K_AR5211
Definition ath5k.h:257
AR5K_RF2425
@ AR5K_RF2425
Definition ath5k.h:270
AR5K_RF5111
@ AR5K_RF5111
Definition ath5k.h:264
AR5K_RF5112
@ AR5K_RF5112
Definition ath5k.h:265
AR5K_RF2316
@ AR5K_RF2316
Definition ath5k.h:268
AR5K_RF5413
@ AR5K_RF5413
Definition ath5k.h:267
AR5K_RF2317
@ AR5K_RF2317
Definition ath5k.h:269
AR5K_RF2413
@ AR5K_RF2413
Definition ath5k.h:266
ath5k_hw_reg_write
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition ath5k.h:1224
AR5K_REG_WAIT
#define AR5K_REG_WAIT(_i)
Definition ath5k.h:135
rf5112_ini_bbgain
static const struct ath5k_ini rf5112_ini_bbgain[]
Definition ath5k_initvals.c:1307
ar5211_ini_mode
static const struct ath5k_ini_mode ar5211_ini_mode[]
Definition ath5k_initvals.c:398
rf2425_ini_common_end
static const struct ath5k_ini rf2425_ini_common_end[]
Definition ath5k_initvals.c:1153
rf2413_ini_common_end
static const struct ath5k_ini rf2413_ini_common_end[]
Definition ath5k_initvals.c:1017
ath5k_hw_write_initvals
int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
Definition ath5k_initvals.c:1419
rf5111_ini_bbgain
static const struct ath5k_ini rf5111_ini_bbgain[]
Definition ath5k_initvals.c:1239
rf5413_ini_common_end
static const struct ath5k_ini rf5413_ini_common_end[]
Definition ath5k_initvals.c:906
rf5111_ini_common_end
static const struct ath5k_ini rf5111_ini_common_end[]
Definition ath5k_initvals.c:773
rf5112_ini_mode_end
static const struct ath5k_ini_mode rf5112_ini_mode_end[]
Definition ath5k_initvals.c:791
ar5212_ini_mode_start
static const struct ath5k_ini_mode ar5212_ini_mode_start[]
Definition ath5k_initvals.c:686
rf5111_ini_mode_end
static const struct ath5k_ini_mode rf5111_ini_mode_end[]
Definition ath5k_initvals.c:741
ath5k_hw_ini_registers
static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, const struct ath5k_ini *ini_regs, int change_channel)
Definition ath5k_initvals.c:1378
rf5413_ini_mode_end
static const struct ath5k_ini_mode rf5413_ini_mode_end[]
Definition ath5k_initvals.c:842
ath5k_hw_ini_mode_registers
static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, unsigned int size, const struct ath5k_ini_mode *ini_mode, u8 mode)
Definition ath5k_initvals.c:1406
ar5212_ini_common_start
static const struct ath5k_ini ar5212_ini_common_start[]
Definition ath5k_initvals.c:473
ar5211_ini
static const struct ath5k_ini ar5211_ini[]
Definition ath5k_initvals.c:269
rf2413_ini_mode_end
static const struct ath5k_ini_mode rf2413_ini_mode_end[]
Definition ath5k_initvals.c:981
rf5112_ini_common_end
static const struct ath5k_ini rf5112_ini_common_end[]
Definition ath5k_initvals.c:827
ar5210_ini
static const struct ath5k_ini ar5210_ini[]
Definition ath5k_initvals.c:57
rf2425_ini_mode_end
static const struct ath5k_ini_mode rf2425_ini_mode_end[]
Definition ath5k_initvals.c:1103
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition efx_common.h:43
mode
uint16_t mode
Acceleration mode.
Definition ena.h:15
DBG
#define DBG(...)
Print a debugging message.
Definition compiler.h:498
size
uint16_t size
Buffer size.
Definition dwmac.h:3
FILE_LICENCE
#define FILE_LICENCE(_licence)
Declare a particular licence as applying to a file.
Definition compiler.h:896
EINVAL
#define EINVAL
Invalid argument.
Definition errno.h:429
FILE_SECBOOT
#define FILE_SECBOOT(_status)
Declare a file's UEFI Secure Boot permission status.
Definition compiler.h:926
u8
#define u8
Definition igbvf_osdep.h:40
ah
uint8_t ah
Definition registers.h:1
ath5k_hw
ath5k_hw_get_isr - Get interrupt status
Definition ath5k.h:955
ath5k_ini_mode
Definition ath5k_initvals.c:51
ath5k_ini_mode::mode_register
u16 mode_register
Definition ath5k_initvals.c:52
ath5k_ini_mode::mode_value
u32 mode_value[5]
Definition ath5k_initvals.c:53
ath5k_ini
Definition ath5k_initvals.c:37
ath5k_ini::ini_register
u16 ini_register
Definition ath5k_initvals.c:38
ath5k_ini::AR5K_INI_WRITE
@ AR5K_INI_WRITE
Definition ath5k_initvals.c:42
ath5k_ini::AR5K_INI_READ
@ AR5K_INI_READ
Definition ath5k_initvals.c:43
ath5k_ini::ini_mode
enum ath5k_ini::@247073007326100300372335165101375311232011300134 ini_mode
ath5k_ini::ini_value
u32 ini_value
Definition ath5k_initvals.c:39
u16
#define u16
Definition vga.h:20
u32
#define u32
Definition vga.h:21
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