iPXE
ath5k_initvals.c
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1 /*
2  * Initial register settings functions
3  *
4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7  *
8  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
9  *
10  * Permission to use, copy, modify, and distribute this software for any
11  * purpose with or without fee is hereby granted, provided that the above
12  * copyright notice and this permission notice appear in all copies.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21  *
22  */
23 
24 FILE_LICENCE ( MIT );
25 
26 #include <unistd.h>
27 
28 #include "ath5k.h"
29 #include "reg.h"
30 #include "base.h"
31 
32 /*
33  * Mode-independent initial register writes
34  */
35 
36 struct ath5k_ini {
39 
40  enum {
41  AR5K_INI_WRITE = 0, /* Default */
42  AR5K_INI_READ = 1, /* Cleared on read */
43  } ini_mode;
44 };
45 
46 /*
47  * Mode specific initial register values
48  */
49 
53 };
54 
55 /* Initial register settings for AR5210 */
56 static const struct ath5k_ini ar5210_ini[] = {
57  /* PCU and MAC registers */
60  { AR5K_RXDP, 0, AR5K_INI_WRITE },
61  { AR5K_CR, 0, AR5K_INI_WRITE },
62  { AR5K_ISR, 0, AR5K_INI_READ },
63  { AR5K_IMR, 0, AR5K_INI_WRITE },
65  { AR5K_BSR, 0, AR5K_INI_READ },
69  { AR5K_TOPS, 8, AR5K_INI_WRITE },
71  { AR5K_RPGTO, 0, AR5K_INI_WRITE },
73  { AR5K_SFR, 0, AR5K_INI_WRITE },
74  { AR5K_MIBC, 0, AR5K_INI_WRITE },
75  { AR5K_MISC, 0, AR5K_INI_WRITE },
87  { AR5K_TIMER1_5210, 0xffffffff, AR5K_INI_WRITE },
88  { AR5K_TIMER2_5210, 0xffffffff, AR5K_INI_WRITE },
92  /* PHY registers */
93  { AR5K_PHY(0), 0x00000047, AR5K_INI_WRITE },
94  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
95  { AR5K_PHY(3), 0x09848ea6, AR5K_INI_WRITE },
96  { AR5K_PHY(4), 0x3d32e000, AR5K_INI_WRITE },
97  { AR5K_PHY(5), 0x0000076b, AR5K_INI_WRITE },
99  { AR5K_PHY(8), 0x02020200, AR5K_INI_WRITE },
100  { AR5K_PHY(9), 0x00000e0e, AR5K_INI_WRITE },
101  { AR5K_PHY(10), 0x0a020201, AR5K_INI_WRITE },
102  { AR5K_PHY(11), 0x00036ffc, AR5K_INI_WRITE },
103  { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
104  { AR5K_PHY(13), 0x00000e0e, AR5K_INI_WRITE },
105  { AR5K_PHY(14), 0x00000007, AR5K_INI_WRITE },
106  { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
107  { AR5K_PHY(16), 0x89630000, AR5K_INI_WRITE },
108  { AR5K_PHY(17), 0x1372169c, AR5K_INI_WRITE },
109  { AR5K_PHY(18), 0x0018b633, AR5K_INI_WRITE },
110  { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
111  { AR5K_PHY(20), 0x0de8b8e0, AR5K_INI_WRITE },
112  { AR5K_PHY(21), 0x00074859, AR5K_INI_WRITE },
113  { AR5K_PHY(22), 0x7e80beba, AR5K_INI_WRITE },
114  { AR5K_PHY(23), 0x313a665e, AR5K_INI_WRITE },
115  { AR5K_PHY_AGCCTL, 0x00001d08, AR5K_INI_WRITE },
116  { AR5K_PHY(25), 0x0001ce00, AR5K_INI_WRITE },
117  { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },
118  { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
119  { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
120  { AR5K_PHY(30), 0x00000004, AR5K_INI_WRITE },
121  { AR5K_PHY(31), 0x00000018, AR5K_INI_WRITE }, /* 0x987c */
122  { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE }, /* 0x9900 */
123  { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
124  { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
125  { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
126  { AR5K_PHY(68), 0x00000003, AR5K_INI_WRITE },
127  /* BB gain table (64bytes) */
128  { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
129  { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
130  { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
131  { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
132  { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
133  { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
134  { AR5K_BB_GAIN(6), 0x00000028, AR5K_INI_WRITE },
135  { AR5K_BB_GAIN(7), 0x00000004, AR5K_INI_WRITE },
136  { AR5K_BB_GAIN(8), 0x00000024, AR5K_INI_WRITE },
137  { AR5K_BB_GAIN(9), 0x00000014, AR5K_INI_WRITE },
138  { AR5K_BB_GAIN(10), 0x00000034, AR5K_INI_WRITE },
139  { AR5K_BB_GAIN(11), 0x0000000c, AR5K_INI_WRITE },
140  { AR5K_BB_GAIN(12), 0x0000002c, AR5K_INI_WRITE },
141  { AR5K_BB_GAIN(13), 0x00000002, AR5K_INI_WRITE },
142  { AR5K_BB_GAIN(14), 0x00000022, AR5K_INI_WRITE },
143  { AR5K_BB_GAIN(15), 0x00000012, AR5K_INI_WRITE },
144  { AR5K_BB_GAIN(16), 0x00000032, AR5K_INI_WRITE },
145  { AR5K_BB_GAIN(17), 0x0000000a, AR5K_INI_WRITE },
146  { AR5K_BB_GAIN(18), 0x0000002a, AR5K_INI_WRITE },
147  { AR5K_BB_GAIN(19), 0x00000001, AR5K_INI_WRITE },
148  { AR5K_BB_GAIN(20), 0x00000021, AR5K_INI_WRITE },
149  { AR5K_BB_GAIN(21), 0x00000011, AR5K_INI_WRITE },
150  { AR5K_BB_GAIN(22), 0x00000031, AR5K_INI_WRITE },
151  { AR5K_BB_GAIN(23), 0x00000009, AR5K_INI_WRITE },
152  { AR5K_BB_GAIN(24), 0x00000029, AR5K_INI_WRITE },
153  { AR5K_BB_GAIN(25), 0x00000005, AR5K_INI_WRITE },
154  { AR5K_BB_GAIN(26), 0x00000025, AR5K_INI_WRITE },
155  { AR5K_BB_GAIN(27), 0x00000015, AR5K_INI_WRITE },
156  { AR5K_BB_GAIN(28), 0x00000035, AR5K_INI_WRITE },
157  { AR5K_BB_GAIN(29), 0x0000000d, AR5K_INI_WRITE },
158  { AR5K_BB_GAIN(30), 0x0000002d, AR5K_INI_WRITE },
159  { AR5K_BB_GAIN(31), 0x00000003, AR5K_INI_WRITE },
160  { AR5K_BB_GAIN(32), 0x00000023, AR5K_INI_WRITE },
161  { AR5K_BB_GAIN(33), 0x00000013, AR5K_INI_WRITE },
162  { AR5K_BB_GAIN(34), 0x00000033, AR5K_INI_WRITE },
163  { AR5K_BB_GAIN(35), 0x0000000b, AR5K_INI_WRITE },
164  { AR5K_BB_GAIN(36), 0x0000002b, AR5K_INI_WRITE },
165  { AR5K_BB_GAIN(37), 0x00000007, AR5K_INI_WRITE },
166  { AR5K_BB_GAIN(38), 0x00000027, AR5K_INI_WRITE },
167  { AR5K_BB_GAIN(39), 0x00000017, AR5K_INI_WRITE },
168  { AR5K_BB_GAIN(40), 0x00000037, AR5K_INI_WRITE },
169  { AR5K_BB_GAIN(41), 0x0000000f, AR5K_INI_WRITE },
170  { AR5K_BB_GAIN(42), 0x0000002f, AR5K_INI_WRITE },
171  { AR5K_BB_GAIN(43), 0x0000002f, AR5K_INI_WRITE },
172  { AR5K_BB_GAIN(44), 0x0000002f, AR5K_INI_WRITE },
173  { AR5K_BB_GAIN(45), 0x0000002f, AR5K_INI_WRITE },
174  { AR5K_BB_GAIN(46), 0x0000002f, AR5K_INI_WRITE },
175  { AR5K_BB_GAIN(47), 0x0000002f, AR5K_INI_WRITE },
176  { AR5K_BB_GAIN(48), 0x0000002f, AR5K_INI_WRITE },
177  { AR5K_BB_GAIN(49), 0x0000002f, AR5K_INI_WRITE },
178  { AR5K_BB_GAIN(50), 0x0000002f, AR5K_INI_WRITE },
179  { AR5K_BB_GAIN(51), 0x0000002f, AR5K_INI_WRITE },
180  { AR5K_BB_GAIN(52), 0x0000002f, AR5K_INI_WRITE },
181  { AR5K_BB_GAIN(53), 0x0000002f, AR5K_INI_WRITE },
182  { AR5K_BB_GAIN(54), 0x0000002f, AR5K_INI_WRITE },
183  { AR5K_BB_GAIN(55), 0x0000002f, AR5K_INI_WRITE },
184  { AR5K_BB_GAIN(56), 0x0000002f, AR5K_INI_WRITE },
185  { AR5K_BB_GAIN(57), 0x0000002f, AR5K_INI_WRITE },
186  { AR5K_BB_GAIN(58), 0x0000002f, AR5K_INI_WRITE },
187  { AR5K_BB_GAIN(59), 0x0000002f, AR5K_INI_WRITE },
188  { AR5K_BB_GAIN(60), 0x0000002f, AR5K_INI_WRITE },
189  { AR5K_BB_GAIN(61), 0x0000002f, AR5K_INI_WRITE },
190  { AR5K_BB_GAIN(62), 0x0000002f, AR5K_INI_WRITE },
191  { AR5K_BB_GAIN(63), 0x0000002f, AR5K_INI_WRITE },
192  /* 5110 RF gain table (64btes) */
193  { AR5K_RF_GAIN(0), 0x0000001d, AR5K_INI_WRITE },
194  { AR5K_RF_GAIN(1), 0x0000005d, AR5K_INI_WRITE },
195  { AR5K_RF_GAIN(2), 0x0000009d, AR5K_INI_WRITE },
196  { AR5K_RF_GAIN(3), 0x000000dd, AR5K_INI_WRITE },
197  { AR5K_RF_GAIN(4), 0x0000011d, AR5K_INI_WRITE },
198  { AR5K_RF_GAIN(5), 0x00000021, AR5K_INI_WRITE },
199  { AR5K_RF_GAIN(6), 0x00000061, AR5K_INI_WRITE },
200  { AR5K_RF_GAIN(7), 0x000000a1, AR5K_INI_WRITE },
201  { AR5K_RF_GAIN(8), 0x000000e1, AR5K_INI_WRITE },
202  { AR5K_RF_GAIN(9), 0x00000031, AR5K_INI_WRITE },
203  { AR5K_RF_GAIN(10), 0x00000071, AR5K_INI_WRITE },
204  { AR5K_RF_GAIN(11), 0x000000b1, AR5K_INI_WRITE },
205  { AR5K_RF_GAIN(12), 0x0000001c, AR5K_INI_WRITE },
206  { AR5K_RF_GAIN(13), 0x0000005c, AR5K_INI_WRITE },
207  { AR5K_RF_GAIN(14), 0x00000029, AR5K_INI_WRITE },
208  { AR5K_RF_GAIN(15), 0x00000069, AR5K_INI_WRITE },
209  { AR5K_RF_GAIN(16), 0x000000a9, AR5K_INI_WRITE },
210  { AR5K_RF_GAIN(17), 0x00000020, AR5K_INI_WRITE },
211  { AR5K_RF_GAIN(18), 0x00000019, AR5K_INI_WRITE },
212  { AR5K_RF_GAIN(19), 0x00000059, AR5K_INI_WRITE },
213  { AR5K_RF_GAIN(20), 0x00000099, AR5K_INI_WRITE },
214  { AR5K_RF_GAIN(21), 0x00000030, AR5K_INI_WRITE },
215  { AR5K_RF_GAIN(22), 0x00000005, AR5K_INI_WRITE },
216  { AR5K_RF_GAIN(23), 0x00000025, AR5K_INI_WRITE },
217  { AR5K_RF_GAIN(24), 0x00000065, AR5K_INI_WRITE },
218  { AR5K_RF_GAIN(25), 0x000000a5, AR5K_INI_WRITE },
219  { AR5K_RF_GAIN(26), 0x00000028, AR5K_INI_WRITE },
220  { AR5K_RF_GAIN(27), 0x00000068, AR5K_INI_WRITE },
221  { AR5K_RF_GAIN(28), 0x0000001f, AR5K_INI_WRITE },
222  { AR5K_RF_GAIN(29), 0x0000001e, AR5K_INI_WRITE },
223  { AR5K_RF_GAIN(30), 0x00000018, AR5K_INI_WRITE },
224  { AR5K_RF_GAIN(31), 0x00000058, AR5K_INI_WRITE },
225  { AR5K_RF_GAIN(32), 0x00000098, AR5K_INI_WRITE },
226  { AR5K_RF_GAIN(33), 0x00000003, AR5K_INI_WRITE },
227  { AR5K_RF_GAIN(34), 0x00000004, AR5K_INI_WRITE },
228  { AR5K_RF_GAIN(35), 0x00000044, AR5K_INI_WRITE },
229  { AR5K_RF_GAIN(36), 0x00000084, AR5K_INI_WRITE },
230  { AR5K_RF_GAIN(37), 0x00000013, AR5K_INI_WRITE },
231  { AR5K_RF_GAIN(38), 0x00000012, AR5K_INI_WRITE },
232  { AR5K_RF_GAIN(39), 0x00000052, AR5K_INI_WRITE },
233  { AR5K_RF_GAIN(40), 0x00000092, AR5K_INI_WRITE },
234  { AR5K_RF_GAIN(41), 0x000000d2, AR5K_INI_WRITE },
235  { AR5K_RF_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
236  { AR5K_RF_GAIN(43), 0x0000002a, AR5K_INI_WRITE },
237  { AR5K_RF_GAIN(44), 0x0000006a, AR5K_INI_WRITE },
238  { AR5K_RF_GAIN(45), 0x000000aa, AR5K_INI_WRITE },
239  { AR5K_RF_GAIN(46), 0x0000001b, AR5K_INI_WRITE },
240  { AR5K_RF_GAIN(47), 0x0000001a, AR5K_INI_WRITE },
241  { AR5K_RF_GAIN(48), 0x0000005a, AR5K_INI_WRITE },
242  { AR5K_RF_GAIN(49), 0x0000009a, AR5K_INI_WRITE },
243  { AR5K_RF_GAIN(50), 0x000000da, AR5K_INI_WRITE },
244  { AR5K_RF_GAIN(51), 0x00000006, AR5K_INI_WRITE },
245  { AR5K_RF_GAIN(52), 0x00000006, AR5K_INI_WRITE },
246  { AR5K_RF_GAIN(53), 0x00000006, AR5K_INI_WRITE },
247  { AR5K_RF_GAIN(54), 0x00000006, AR5K_INI_WRITE },
248  { AR5K_RF_GAIN(55), 0x00000006, AR5K_INI_WRITE },
249  { AR5K_RF_GAIN(56), 0x00000006, AR5K_INI_WRITE },
250  { AR5K_RF_GAIN(57), 0x00000006, AR5K_INI_WRITE },
251  { AR5K_RF_GAIN(58), 0x00000006, AR5K_INI_WRITE },
252  { AR5K_RF_GAIN(59), 0x00000006, AR5K_INI_WRITE },
253  { AR5K_RF_GAIN(60), 0x00000006, AR5K_INI_WRITE },
254  { AR5K_RF_GAIN(61), 0x00000006, AR5K_INI_WRITE },
255  { AR5K_RF_GAIN(62), 0x00000006, AR5K_INI_WRITE },
256  { AR5K_RF_GAIN(63), 0x00000006, AR5K_INI_WRITE },
257  /* PHY activation */
258  { AR5K_PHY(53), 0x00000020, AR5K_INI_WRITE },
259  { AR5K_PHY(51), 0x00000004, AR5K_INI_WRITE },
260  { AR5K_PHY(50), 0x00060106, AR5K_INI_WRITE },
261  { AR5K_PHY(39), 0x0000006d, AR5K_INI_WRITE },
262  { AR5K_PHY(48), 0x00000000, AR5K_INI_WRITE },
263  { AR5K_PHY(52), 0x00000014, AR5K_INI_WRITE },
265 };
266 
267 /* Initial register settings for AR5211 */
268 static const struct ath5k_ini ar5211_ini[] = {
269  { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
270  { AR5K_RTSD0, 0x84849c9c, AR5K_INI_WRITE },
271  { AR5K_RTSD1, 0x7c7c7c7c, AR5K_INI_WRITE },
272  { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
273  { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
274  { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
275  { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
276  { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
277  { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
278  { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
279  { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
280  { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
281  { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
282  { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
283  { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
284  { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
285  { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
286  { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
287  { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
288  { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
289  { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
290  { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
291  { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
292  { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
293  { AR5K_RSSI_THR, 0x00000000, AR5K_INI_WRITE },
294  { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
295  { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
296  { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
297  { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
298  { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
299  { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
300  { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
301  { AR5K_MCAST_FILTER0_5211, 0x00000000, AR5K_INI_WRITE },
302  { AR5K_MCAST_FILTER1_5211, 0x00000002, AR5K_INI_WRITE },
303  { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
304  { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
305  { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
306  /* PHY registers */
307  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
308  { AR5K_PHY(3), 0x2d849093, AR5K_INI_WRITE },
309  { AR5K_PHY(4), 0x7d32e000, AR5K_INI_WRITE },
310  { AR5K_PHY(5), 0x00000f6b, AR5K_INI_WRITE },
311  { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
312  { AR5K_PHY(11), 0x00026ffe, AR5K_INI_WRITE },
313  { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
314  { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
315  { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
316  { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
317  { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
318  { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE }, /* 0x9868 */
319  { AR5K_PHY(27), 0x050cb081, AR5K_INI_WRITE },
320  { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
321  { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
322  { AR5K_PHY(30), 0x0000000c, AR5K_INI_WRITE },
323  { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },
324  { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
325  { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
326  { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
327  { AR5K_PHY(68), 0x00000001, AR5K_INI_WRITE },
328  { AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },
329  { AR5K_PHY_IQ, 0x00000000, AR5K_INI_WRITE },
330  { AR5K_PHY(73), 0x00058a05, AR5K_INI_WRITE },
331  { AR5K_PHY(74), 0x00000001, AR5K_INI_WRITE },
332  { AR5K_PHY(75), 0x00000000, AR5K_INI_WRITE },
333  { AR5K_PHY_PAPD_PROBE, 0x00000000, AR5K_INI_WRITE },
334  { AR5K_PHY(77), 0x00000000, AR5K_INI_WRITE }, /* 0x9934 */
335  { AR5K_PHY(78), 0x00000000, AR5K_INI_WRITE }, /* 0x9938 */
336  { AR5K_PHY(79), 0x0000003f, AR5K_INI_WRITE }, /* 0x993c */
337  { AR5K_PHY(80), 0x00000004, AR5K_INI_WRITE },
338  { AR5K_PHY(82), 0x00000000, AR5K_INI_WRITE },
339  { AR5K_PHY(83), 0x00000000, AR5K_INI_WRITE },
340  { AR5K_PHY(84), 0x00000000, AR5K_INI_WRITE },
341  { AR5K_PHY_RADAR, 0x5d50f14c, AR5K_INI_WRITE },
342  { AR5K_PHY(86), 0x00000018, AR5K_INI_WRITE },
343  { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
344  /* Initial Power table (32bytes)
345  * common on all cards/modes.
346  * Note: Table is rewritten during
347  * txpower setup later using calibration
348  * data etc. so next write is non-common */
349  { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff, AR5K_INI_WRITE },
350  { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff, AR5K_INI_WRITE },
351  { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff, AR5K_INI_WRITE },
352  { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff, AR5K_INI_WRITE },
353  { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff, AR5K_INI_WRITE },
354  { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff, AR5K_INI_WRITE },
355  { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff, AR5K_INI_WRITE },
356  { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff, AR5K_INI_WRITE },
357  { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff, AR5K_INI_WRITE },
358  { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff, AR5K_INI_WRITE },
359  { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff, AR5K_INI_WRITE },
360  { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff, AR5K_INI_WRITE },
361  { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff, AR5K_INI_WRITE },
362  { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff, AR5K_INI_WRITE },
363  { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff, AR5K_INI_WRITE },
364  { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff, AR5K_INI_WRITE },
365  { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff, AR5K_INI_WRITE },
366  { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff, AR5K_INI_WRITE },
367  { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff, AR5K_INI_WRITE },
368  { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff, AR5K_INI_WRITE },
369  { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff, AR5K_INI_WRITE },
370  { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff, AR5K_INI_WRITE },
371  { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff, AR5K_INI_WRITE },
372  { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff, AR5K_INI_WRITE },
373  { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff, AR5K_INI_WRITE },
374  { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff, AR5K_INI_WRITE },
375  { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff, AR5K_INI_WRITE },
376  { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff, AR5K_INI_WRITE },
377  { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff, AR5K_INI_WRITE },
378  { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff, AR5K_INI_WRITE },
379  { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff, AR5K_INI_WRITE },
380  { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
381  { AR5K_PHY(642), 0x503e4646, AR5K_INI_WRITE },
382  { AR5K_PHY_GAIN_2GHZ, 0x6480416c, AR5K_INI_WRITE },
383  { AR5K_PHY(644), 0x0199a003, AR5K_INI_WRITE },
384  { AR5K_PHY(645), 0x044cd610, AR5K_INI_WRITE },
385  { AR5K_PHY(646), 0x13800040, AR5K_INI_WRITE },
386  { AR5K_PHY(647), 0x1be00060, AR5K_INI_WRITE },
387  { AR5K_PHY(648), 0x0c53800a, AR5K_INI_WRITE },
388  { AR5K_PHY(649), 0x0014df3b, AR5K_INI_WRITE },
389  { AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },
390  { AR5K_PHY(651), 0x00000020, AR5K_INI_WRITE },
391 };
392 
393 /* Initial mode-specific settings for AR5211
394  * 5211 supports OFDM-only g (draft g) but we
395  * need to test it !
396  */
397 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
398  { AR5K_TXCFG,
399  /* a aTurbo b g (OFDM) */
400  { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
402  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
404  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
406  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
408  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
410  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
412  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
414  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
416  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
418  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
420  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
422  { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
424  { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
426  { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
428  { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
429  { AR5K_TIME_OUT,
430  { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
431  { AR5K_USEC_5211,
432  { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
433  { AR5K_PHY_TURBO,
434  { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
435  { AR5K_PHY(8),
436  { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
437  { AR5K_PHY(9),
438  { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
439  { AR5K_PHY(10),
440  { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
441  { AR5K_PHY(13),
442  { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
443  { AR5K_PHY(14),
444  { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
445  { AR5K_PHY(17),
446  { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
447  { AR5K_PHY(18),
448  { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
449  { AR5K_PHY(20),
450  { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
451  { AR5K_PHY_SIG,
452  { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
454  { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
455  { AR5K_PHY_AGCCTL,
456  { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
457  { AR5K_PHY_NF,
458  { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
460  { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
461  { AR5K_PHY(70),
462  { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
464  { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
466  { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
468  { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
469 };
470 
471 /* Initial register settings for AR5212 */
472 static const struct ath5k_ini ar5212_ini_common_start[] = {
473  { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
474  { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
475  { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
476  { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
477  { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
478  { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
479  { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
480  { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
481  { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
482  { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
483  { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
484  { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
485  { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
486  { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
487  { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
488  { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
489  { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
490  { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
491  { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
492  { AR5K_DCU_TXP, 0x00000000, AR5K_INI_WRITE },
493  /* Tx filter table 0 (32 entries) */
494  { AR5K_DCU_TX_FILTER_0(0), 0x00000000, AR5K_INI_WRITE }, /* DCU 0 */
495  { AR5K_DCU_TX_FILTER_0(1), 0x00000000, AR5K_INI_WRITE },
496  { AR5K_DCU_TX_FILTER_0(2), 0x00000000, AR5K_INI_WRITE },
497  { AR5K_DCU_TX_FILTER_0(3), 0x00000000, AR5K_INI_WRITE },
498  { AR5K_DCU_TX_FILTER_0(4), 0x00000000, AR5K_INI_WRITE }, /* DCU 1 */
499  { AR5K_DCU_TX_FILTER_0(5), 0x00000000, AR5K_INI_WRITE },
500  { AR5K_DCU_TX_FILTER_0(6), 0x00000000, AR5K_INI_WRITE },
501  { AR5K_DCU_TX_FILTER_0(7), 0x00000000, AR5K_INI_WRITE },
502  { AR5K_DCU_TX_FILTER_0(8), 0x00000000, AR5K_INI_WRITE }, /* DCU 2 */
503  { AR5K_DCU_TX_FILTER_0(9), 0x00000000, AR5K_INI_WRITE },
504  { AR5K_DCU_TX_FILTER_0(10), 0x00000000, AR5K_INI_WRITE },
505  { AR5K_DCU_TX_FILTER_0(11), 0x00000000, AR5K_INI_WRITE },
506  { AR5K_DCU_TX_FILTER_0(12), 0x00000000, AR5K_INI_WRITE }, /* DCU 3 */
507  { AR5K_DCU_TX_FILTER_0(13), 0x00000000, AR5K_INI_WRITE },
508  { AR5K_DCU_TX_FILTER_0(14), 0x00000000, AR5K_INI_WRITE },
509  { AR5K_DCU_TX_FILTER_0(15), 0x00000000, AR5K_INI_WRITE },
510  { AR5K_DCU_TX_FILTER_0(16), 0x00000000, AR5K_INI_WRITE }, /* DCU 4 */
511  { AR5K_DCU_TX_FILTER_0(17), 0x00000000, AR5K_INI_WRITE },
512  { AR5K_DCU_TX_FILTER_0(18), 0x00000000, AR5K_INI_WRITE },
513  { AR5K_DCU_TX_FILTER_0(19), 0x00000000, AR5K_INI_WRITE },
514  { AR5K_DCU_TX_FILTER_0(20), 0x00000000, AR5K_INI_WRITE }, /* DCU 5 */
515  { AR5K_DCU_TX_FILTER_0(21), 0x00000000, AR5K_INI_WRITE },
516  { AR5K_DCU_TX_FILTER_0(22), 0x00000000, AR5K_INI_WRITE },
517  { AR5K_DCU_TX_FILTER_0(23), 0x00000000, AR5K_INI_WRITE },
518  { AR5K_DCU_TX_FILTER_0(24), 0x00000000, AR5K_INI_WRITE }, /* DCU 6 */
519  { AR5K_DCU_TX_FILTER_0(25), 0x00000000, AR5K_INI_WRITE },
520  { AR5K_DCU_TX_FILTER_0(26), 0x00000000, AR5K_INI_WRITE },
521  { AR5K_DCU_TX_FILTER_0(27), 0x00000000, AR5K_INI_WRITE },
522  { AR5K_DCU_TX_FILTER_0(28), 0x00000000, AR5K_INI_WRITE }, /* DCU 7 */
523  { AR5K_DCU_TX_FILTER_0(29), 0x00000000, AR5K_INI_WRITE },
524  { AR5K_DCU_TX_FILTER_0(30), 0x00000000, AR5K_INI_WRITE },
525  { AR5K_DCU_TX_FILTER_0(31), 0x00000000, AR5K_INI_WRITE },
526  /* Tx filter table 1 (16 entries) */
527  { AR5K_DCU_TX_FILTER_1(0), 0x00000000, AR5K_INI_WRITE },
528  { AR5K_DCU_TX_FILTER_1(1), 0x00000000, AR5K_INI_WRITE },
529  { AR5K_DCU_TX_FILTER_1(2), 0x00000000, AR5K_INI_WRITE },
530  { AR5K_DCU_TX_FILTER_1(3), 0x00000000, AR5K_INI_WRITE },
531  { AR5K_DCU_TX_FILTER_1(4), 0x00000000, AR5K_INI_WRITE },
532  { AR5K_DCU_TX_FILTER_1(5), 0x00000000, AR5K_INI_WRITE },
533  { AR5K_DCU_TX_FILTER_1(6), 0x00000000, AR5K_INI_WRITE },
534  { AR5K_DCU_TX_FILTER_1(7), 0x00000000, AR5K_INI_WRITE },
535  { AR5K_DCU_TX_FILTER_1(8), 0x00000000, AR5K_INI_WRITE },
536  { AR5K_DCU_TX_FILTER_1(9), 0x00000000, AR5K_INI_WRITE },
537  { AR5K_DCU_TX_FILTER_1(10), 0x00000000, AR5K_INI_WRITE },
538  { AR5K_DCU_TX_FILTER_1(11), 0x00000000, AR5K_INI_WRITE },
539  { AR5K_DCU_TX_FILTER_1(12), 0x00000000, AR5K_INI_WRITE },
540  { AR5K_DCU_TX_FILTER_1(13), 0x00000000, AR5K_INI_WRITE },
541  { AR5K_DCU_TX_FILTER_1(14), 0x00000000, AR5K_INI_WRITE },
542  { AR5K_DCU_TX_FILTER_1(15), 0x00000000, AR5K_INI_WRITE },
543  { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
544  { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
545  { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
546  { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
547  { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
548  { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
549  { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
550  { AR5K_BEACON_5211, 0x00000000, AR5K_INI_WRITE },
551  { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
552  { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
553  { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
554  { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
555  { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
556  { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
557  { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
558  { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
559  { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
560  { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
561  { AR5K_FRAME_CTL_QOSM, 0x000fc78f, AR5K_INI_WRITE },
562  { AR5K_XRMODE, 0x2a82301a, AR5K_INI_WRITE },
563  { AR5K_XRDELAY, 0x05dc01e0, AR5K_INI_WRITE },
564  { AR5K_XRTIMEOUT, 0x1f402710, AR5K_INI_WRITE },
565  { AR5K_XRCHIRP, 0x01f40000, AR5K_INI_WRITE },
566  { AR5K_XRSTOMP, 0x00001e1c, AR5K_INI_WRITE },
567  { AR5K_SLEEP0, 0x0002aaaa, AR5K_INI_WRITE },
568  { AR5K_SLEEP1, 0x02005555, AR5K_INI_WRITE },
569  { AR5K_SLEEP2, 0x00000000, AR5K_INI_WRITE },
570  { AR5K_BSS_IDM0, 0xffffffff, AR5K_INI_WRITE },
571  { AR5K_BSS_IDM1, 0x0000ffff, AR5K_INI_WRITE },
572  { AR5K_TXPC, 0x00000000, AR5K_INI_WRITE },
573  { AR5K_PROFCNT_TX, 0x00000000, AR5K_INI_WRITE },
574  { AR5K_PROFCNT_RX, 0x00000000, AR5K_INI_WRITE },
575  { AR5K_PROFCNT_RXCLR, 0x00000000, AR5K_INI_WRITE },
576  { AR5K_PROFCNT_CYCLE, 0x00000000, AR5K_INI_WRITE },
577  { AR5K_QUIET_CTL1, 0x00000088, AR5K_INI_WRITE },
578  /* Initial rate duration table (32 entries )*/
579  { AR5K_RATE_DUR(0), 0x00000000, AR5K_INI_WRITE },
580  { AR5K_RATE_DUR(1), 0x0000008c, AR5K_INI_WRITE },
581  { AR5K_RATE_DUR(2), 0x000000e4, AR5K_INI_WRITE },
582  { AR5K_RATE_DUR(3), 0x000002d5, AR5K_INI_WRITE },
583  { AR5K_RATE_DUR(4), 0x00000000, AR5K_INI_WRITE },
584  { AR5K_RATE_DUR(5), 0x00000000, AR5K_INI_WRITE },
585  { AR5K_RATE_DUR(6), 0x000000a0, AR5K_INI_WRITE },
586  { AR5K_RATE_DUR(7), 0x000001c9, AR5K_INI_WRITE },
587  { AR5K_RATE_DUR(8), 0x0000002c, AR5K_INI_WRITE },
588  { AR5K_RATE_DUR(9), 0x0000002c, AR5K_INI_WRITE },
589  { AR5K_RATE_DUR(10), 0x00000030, AR5K_INI_WRITE },
590  { AR5K_RATE_DUR(11), 0x0000003c, AR5K_INI_WRITE },
591  { AR5K_RATE_DUR(12), 0x0000002c, AR5K_INI_WRITE },
592  { AR5K_RATE_DUR(13), 0x0000002c, AR5K_INI_WRITE },
593  { AR5K_RATE_DUR(14), 0x00000030, AR5K_INI_WRITE },
594  { AR5K_RATE_DUR(15), 0x0000003c, AR5K_INI_WRITE },
595  { AR5K_RATE_DUR(16), 0x00000000, AR5K_INI_WRITE },
596  { AR5K_RATE_DUR(17), 0x00000000, AR5K_INI_WRITE },
597  { AR5K_RATE_DUR(18), 0x00000000, AR5K_INI_WRITE },
598  { AR5K_RATE_DUR(19), 0x00000000, AR5K_INI_WRITE },
599  { AR5K_RATE_DUR(20), 0x00000000, AR5K_INI_WRITE },
600  { AR5K_RATE_DUR(21), 0x00000000, AR5K_INI_WRITE },
601  { AR5K_RATE_DUR(22), 0x00000000, AR5K_INI_WRITE },
602  { AR5K_RATE_DUR(23), 0x00000000, AR5K_INI_WRITE },
603  { AR5K_RATE_DUR(24), 0x000000d5, AR5K_INI_WRITE },
604  { AR5K_RATE_DUR(25), 0x000000df, AR5K_INI_WRITE },
605  { AR5K_RATE_DUR(26), 0x00000102, AR5K_INI_WRITE },
606  { AR5K_RATE_DUR(27), 0x0000013a, AR5K_INI_WRITE },
607  { AR5K_RATE_DUR(28), 0x00000075, AR5K_INI_WRITE },
608  { AR5K_RATE_DUR(29), 0x0000007f, AR5K_INI_WRITE },
609  { AR5K_RATE_DUR(30), 0x000000a2, AR5K_INI_WRITE },
610  { AR5K_RATE_DUR(31), 0x00000000, AR5K_INI_WRITE },
611  { AR5K_QUIET_CTL2, 0x00010002, AR5K_INI_WRITE },
612  { AR5K_TSF_PARM, 0x00000001, AR5K_INI_WRITE },
613  { AR5K_QOS_NOACK, 0x000000c0, AR5K_INI_WRITE },
614  { AR5K_PHY_ERR_FIL, 0x00000000, AR5K_INI_WRITE },
615  { AR5K_XRLAT_TX, 0x00000168, AR5K_INI_WRITE },
616  { AR5K_ACKSIFS, 0x00000000, AR5K_INI_WRITE },
617  /* Rate -> db table
618  * notice ...03<-02<-01<-00 ! */
619  { AR5K_RATE2DB(0), 0x03020100, AR5K_INI_WRITE },
620  { AR5K_RATE2DB(1), 0x07060504, AR5K_INI_WRITE },
621  { AR5K_RATE2DB(2), 0x0b0a0908, AR5K_INI_WRITE },
622  { AR5K_RATE2DB(3), 0x0f0e0d0c, AR5K_INI_WRITE },
623  { AR5K_RATE2DB(4), 0x13121110, AR5K_INI_WRITE },
624  { AR5K_RATE2DB(5), 0x17161514, AR5K_INI_WRITE },
625  { AR5K_RATE2DB(6), 0x1b1a1918, AR5K_INI_WRITE },
626  { AR5K_RATE2DB(7), 0x1f1e1d1c, AR5K_INI_WRITE },
627  /* Db -> Rate table */
628  { AR5K_DB2RATE(0), 0x03020100, AR5K_INI_WRITE },
629  { AR5K_DB2RATE(1), 0x07060504, AR5K_INI_WRITE },
630  { AR5K_DB2RATE(2), 0x0b0a0908, AR5K_INI_WRITE },
631  { AR5K_DB2RATE(3), 0x0f0e0d0c, AR5K_INI_WRITE },
632  { AR5K_DB2RATE(4), 0x13121110, AR5K_INI_WRITE },
633  { AR5K_DB2RATE(5), 0x17161514, AR5K_INI_WRITE },
634  { AR5K_DB2RATE(6), 0x1b1a1918, AR5K_INI_WRITE },
635  { AR5K_DB2RATE(7), 0x1f1e1d1c, AR5K_INI_WRITE },
636  /* PHY registers (Common settings
637  * for all chips/modes) */
638  { AR5K_PHY(3), 0xad848e19, AR5K_INI_WRITE },
639  { AR5K_PHY(4), 0x7d28e000, AR5K_INI_WRITE },
640  { AR5K_PHY_TIMING_3, 0x9c0a9f6b, AR5K_INI_WRITE },
641  { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
642  { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
643  { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
644  { AR5K_PHY_BIN_MASK_1, 0x00000000, AR5K_INI_WRITE },
645  { AR5K_PHY_BIN_MASK_2, 0x00000000, AR5K_INI_WRITE },
646  { AR5K_PHY_BIN_MASK_3, 0x00000000, AR5K_INI_WRITE },
647  { AR5K_PHY_BIN_MASK_CTL, 0x00800000, AR5K_INI_WRITE },
648  { AR5K_PHY_ANT_CTL, 0x00000001, AR5K_INI_WRITE },
649  /*{ AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },*/ /* Old value */
650  { AR5K_PHY_MAX_RX_LEN, 0x00000c80, AR5K_INI_WRITE },
651  { AR5K_PHY_IQ, 0x05100000, AR5K_INI_WRITE },
652  { AR5K_PHY_WARM_RESET, 0x00000001, AR5K_INI_WRITE },
653  { AR5K_PHY_CTL, 0x00000004, AR5K_INI_WRITE },
654  { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022, AR5K_INI_WRITE },
655  { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d, AR5K_INI_WRITE },
656  { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f, AR5K_INI_WRITE },
657  { AR5K_PHY(82), 0x9280b212, AR5K_INI_WRITE },
658  { AR5K_PHY_RADAR, 0x5d50e188, AR5K_INI_WRITE },
659  /*{ AR5K_PHY(86), 0x000000ff, AR5K_INI_WRITE },*/
660  { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
661  { AR5K_PHY_NFTHRES, 0x000003ce, AR5K_INI_WRITE },
662  { AR5K_PHY_RESTART, 0x192fb515, AR5K_INI_WRITE },
663  { AR5K_PHY(94), 0x00000001, AR5K_INI_WRITE },
664  { AR5K_PHY_RFBUS_REQ, 0x00000000, AR5K_INI_WRITE },
665  /*{ AR5K_PHY(644), 0x0080a333, AR5K_INI_WRITE },*/ /* Old value */
666  /*{ AR5K_PHY(645), 0x00206c10, AR5K_INI_WRITE },*/ /* Old value */
667  { AR5K_PHY(644), 0x00806333, AR5K_INI_WRITE },
668  { AR5K_PHY(645), 0x00106c10, AR5K_INI_WRITE },
669  { AR5K_PHY(646), 0x009c4060, AR5K_INI_WRITE },
670  /* { AR5K_PHY(647), 0x1483800a, AR5K_INI_WRITE }, */
671  /* { AR5K_PHY(648), 0x01831061, AR5K_INI_WRITE }, */ /* Old value */
672  { AR5K_PHY(648), 0x018830c6, AR5K_INI_WRITE },
673  { AR5K_PHY(649), 0x00000400, AR5K_INI_WRITE },
674  /*{ AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },*/
675  { AR5K_PHY(651), 0x00000000, AR5K_INI_WRITE },
676  { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
677  { AR5K_PHY_TXPOWER_RATE2, 0x20202020, AR5K_INI_WRITE },
678  /*{ AR5K_PHY(655), 0x13c889af, AR5K_INI_WRITE },*/
679  { AR5K_PHY(656), 0x38490a20, AR5K_INI_WRITE },
680  { AR5K_PHY(657), 0x00007bb6, AR5K_INI_WRITE },
681  { AR5K_PHY(658), 0x0fff3ffc, AR5K_INI_WRITE },
682 };
683 
684 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
685 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
687  /* a/XR aTurbo b g (DYN) gTurbo */
688  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
690  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
692  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
694  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
696  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
698  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
700  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
702  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
704  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
706  { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
708  { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
710  { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
712  { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
714  { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
715  { AR5K_TIME_OUT,
716  { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
717  { AR5K_PHY_TURBO,
718  { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
719  { AR5K_PHY(8),
720  { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
722  { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
724  { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
725  { AR5K_PHY_AGCCTL,
726  { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
727  { AR5K_PHY_NF,
728  { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
730  { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
731  { AR5K_PHY(70),
732  { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
734  { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
735  { 0xa230,
736  { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
737 };
738 
739 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
740 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
741  { AR5K_TXCFG,
742  /* a/XR aTurbo b g (DYN) gTurbo */
743  { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
744  { AR5K_USEC_5211,
745  { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
747  { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
749  { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
750  { AR5K_PHY_PA_CTL,
751  { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
752  { AR5K_PHY_GAIN,
753  { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
755  { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
756  { AR5K_PHY_SIG,
757  { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
759  { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
761  { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
763  { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
765  { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
767  { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
769  { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
770 };
771 
772 static const struct ath5k_ini rf5111_ini_common_end[] = {
773  { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
774  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
775  { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
776  { 0x983c, 0x00020100, AR5K_INI_WRITE },
777  { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
778  { AR5K_PHY_PAPD_PROBE, 0x00004883, AR5K_INI_WRITE },
779  { 0x9940, 0x00000004, AR5K_INI_WRITE },
780  { 0x9958, 0x000000ff, AR5K_INI_WRITE },
781  { 0x9974, 0x00000000, AR5K_INI_WRITE },
782  { AR5K_PHY_SPENDING, 0x00000018, AR5K_INI_WRITE },
783  { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
784  { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE },
785  { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
786  { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
787 };
788 
789 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
790 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
791  { AR5K_TXCFG,
792  /* a/XR aTurbo b g (DYN) gTurbo */
793  { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
794  { AR5K_USEC_5211,
795  { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
797  { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
799  { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
800  { AR5K_PHY_PA_CTL,
801  { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
802  { AR5K_PHY_GAIN,
803  { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
805  { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
806  { AR5K_PHY_SIG,
807  { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
809  { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
811  { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
813  { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
815  { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
817  { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
819  { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
821  { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
823  { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
824 };
825 
826 static const struct ath5k_ini rf5112_ini_common_end[] = {
827  { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
828  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
829  { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
830  { 0x983c, 0x00020100, AR5K_INI_WRITE },
831  { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
832  { AR5K_PHY_PAPD_PROBE, 0x00004882, AR5K_INI_WRITE },
833  { 0x9940, 0x00000004, AR5K_INI_WRITE },
834  { 0x9958, 0x000000ff, AR5K_INI_WRITE },
835  { 0x9974, 0x00000000, AR5K_INI_WRITE },
836  { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
837  { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
838 };
839 
840 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
841 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
842  { AR5K_TXCFG,
843  /* a/XR aTurbo b g (DYN) gTurbo */
844  { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
845  { AR5K_USEC_5211,
846  { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
848  { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
850  { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
851  { AR5K_PHY_PA_CTL,
852  { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
853  { AR5K_PHY_GAIN,
854  { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
856  { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
857  { AR5K_PHY_SIG,
858  { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
860  { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
862  { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
864  { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
866  { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
868  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
870  { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
872  { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
874  { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
875  { 0xa300,
876  { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
877  { 0xa304,
878  { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
879  { 0xa308,
880  { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
881  { 0xa30c,
882  { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
883  { 0xa310,
884  { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
885  { 0xa314,
886  { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
887  { 0xa318,
888  { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
889  { 0xa31c,
890  { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
891  { 0xa320,
892  { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
893  { 0xa324,
894  { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
895  { 0xa328,
896  { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
897  { 0xa32c,
898  { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
899  { 0xa330,
900  { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
901  { 0xa334,
902  { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
903 };
904 
905 static const struct ath5k_ini rf5413_ini_common_end[] = {
906  { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
907  { AR5K_5414_CBCFG, 0x00000010, AR5K_INI_WRITE },
908  { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
909  { 0x809c, 0x00000000, AR5K_INI_WRITE },
910  { 0x80a0, 0x00000000, AR5K_INI_WRITE },
911  { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
912  { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
913  { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
914  { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
915  { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
916  { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
917  { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
918  { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
919  { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
920  { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
921  { 0x8140, 0x800003f9, AR5K_INI_WRITE },
922  { 0x8144, 0x00000000, AR5K_INI_WRITE },
923  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
924  { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
925  { 0x983c, 0x00200400, AR5K_INI_WRITE },
926  { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
927  { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
928  { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
929  { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
930  { 0x9958, 0x00081fff, AR5K_INI_WRITE },
931  { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
932  { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
933  { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
935  { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
936  { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
937  { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
938  { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
939  { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
940  { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
941  { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
942  { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
943  { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
944  { 0xa250, 0x0000a000, AR5K_INI_WRITE },
945  { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
946  { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
947  { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
948  { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
949  { 0xa264, 0x00418a11, AR5K_INI_WRITE },
950  { 0xa268, 0x00000000, AR5K_INI_WRITE },
951  { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
952  { 0xa270, 0x00820820, AR5K_INI_WRITE },
953  { 0xa274, 0x081b7caa, AR5K_INI_WRITE },
954  { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
955  { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
956  { 0xa338, 0x00000000, AR5K_INI_WRITE },
957  { 0xa33c, 0x00000000, AR5K_INI_WRITE },
958  { 0xa340, 0x00000000, AR5K_INI_WRITE },
959  { 0xa344, 0x00000000, AR5K_INI_WRITE },
960  { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
961  { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
962  { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
963  { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
964  { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
965  { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
966  { 0xa360, 0x0f282207, AR5K_INI_WRITE },
967  { 0xa364, 0x17601685, AR5K_INI_WRITE },
968  { 0xa368, 0x1f801104, AR5K_INI_WRITE },
969  { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
970  { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
971  { 0xa374, 0x57c00803, AR5K_INI_WRITE },
972  { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
973  { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
974  { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
975  { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
976 };
977 
978 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
979 /* XXX: a mode ? */
980 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
981  { AR5K_TXCFG,
982  /* a/XR aTurbo b g (DYN) gTurbo */
983  { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
984  { AR5K_USEC_5211,
985  { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
987  { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
989  { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
990  { AR5K_PHY_PA_CTL,
991  { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
992  { AR5K_PHY_GAIN,
993  { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
995  { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
996  { AR5K_PHY_SIG,
997  { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
999  { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
1001  { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1003  { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1005  { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1007  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1009  { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1011  { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
1013  { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1014 };
1015 
1016 static const struct ath5k_ini rf2413_ini_common_end[] = {
1017  { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
1018  { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
1019  { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
1020  { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
1021  { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
1022  { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1023  { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1024  { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
1025  { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
1026  { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
1027  { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
1028  { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
1029  { 0x8140, 0x800000a8, AR5K_INI_WRITE },
1030  { 0x8144, 0x00000000, AR5K_INI_WRITE },
1031  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
1032  { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
1033  { 0x983c, 0x00200400, AR5K_INI_WRITE },
1034  { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
1035  { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
1036  { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1037  { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
1038  { 0x9958, 0x000000ff, AR5K_INI_WRITE },
1039  { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
1040  { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
1041  { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
1042  { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
1043  { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
1044  { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
1045  { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
1046  { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
1047  { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
1048  { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
1049  { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
1050  { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
1051  { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
1052  { 0xa250, 0x0000a000, AR5K_INI_WRITE },
1053  { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
1054  { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
1055  { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
1056  { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
1057  { 0xa264, 0x00418a11, AR5K_INI_WRITE },
1058  { 0xa268, 0x00000000, AR5K_INI_WRITE },
1059  { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
1060  { 0xa270, 0x00820820, AR5K_INI_WRITE },
1061  { 0xa274, 0x001b7caa, AR5K_INI_WRITE },
1062  { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
1063  { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
1064  { 0xa300, 0x18010000, AR5K_INI_WRITE },
1065  { 0xa304, 0x30032602, AR5K_INI_WRITE },
1066  { 0xa308, 0x48073e06, AR5K_INI_WRITE },
1067  { 0xa30c, 0x560b4c0a, AR5K_INI_WRITE },
1068  { 0xa310, 0x641a600f, AR5K_INI_WRITE },
1069  { 0xa314, 0x784f6e1b, AR5K_INI_WRITE },
1070  { 0xa318, 0x868f7c5a, AR5K_INI_WRITE },
1071  { 0xa31c, 0x8ecf865b, AR5K_INI_WRITE },
1072  { 0xa320, 0x9d4f970f, AR5K_INI_WRITE },
1073  { 0xa324, 0xa5cfa18f, AR5K_INI_WRITE },
1074  { 0xa328, 0xb55faf1f, AR5K_INI_WRITE },
1075  { 0xa32c, 0xbddfb99f, AR5K_INI_WRITE },
1076  { 0xa330, 0xcd7fc73f, AR5K_INI_WRITE },
1077  { 0xa334, 0xd5ffd1bf, AR5K_INI_WRITE },
1078  { 0xa338, 0x00000000, AR5K_INI_WRITE },
1079  { 0xa33c, 0x00000000, AR5K_INI_WRITE },
1080  { 0xa340, 0x00000000, AR5K_INI_WRITE },
1081  { 0xa344, 0x00000000, AR5K_INI_WRITE },
1082  { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
1083  { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
1084  { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
1085  { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
1086  { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
1087  { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
1088  { 0xa360, 0x0f282207, AR5K_INI_WRITE },
1089  { 0xa364, 0x17601685, AR5K_INI_WRITE },
1090  { 0xa368, 0x1f801104, AR5K_INI_WRITE },
1091  { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
1092  { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
1093  { 0xa374, 0x57c00803, AR5K_INI_WRITE },
1094  { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
1095  { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
1096  { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
1097  { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
1098 };
1099 
1100 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1101 /* XXX: a mode ? */
1102 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1103  { AR5K_TXCFG,
1104  /* a/XR aTurbo b g (DYN) gTurbo */
1105  { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
1106  { AR5K_USEC_5211,
1107  { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
1108  { AR5K_PHY_TURBO,
1109  { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
1110  { AR5K_PHY_RF_CTL3,
1111  { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
1112  { AR5K_PHY_RF_CTL4,
1113  { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1114  { AR5K_PHY_PA_CTL,
1115  { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
1117  { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
1118  { AR5K_PHY_GAIN,
1119  { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
1121  { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
1122  { AR5K_PHY_SIG,
1123  { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1125  { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
1127  { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1129  { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1131  { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1133  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1135  { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1137  { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
1139  { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1140  { 0xa324,
1141  { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1142  { 0xa328,
1143  { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1144  { 0xa32c,
1145  { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1146  { 0xa330,
1147  { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1148  { 0xa334,
1149  { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1150 };
1151 
1152 static const struct ath5k_ini rf2425_ini_common_end[] = {
1153  { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
1154  { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
1155  { 0x809c, 0x00000000, AR5K_INI_WRITE },
1156  { 0x80a0, 0x00000000, AR5K_INI_WRITE },
1157  { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
1158  { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
1159  { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
1160  { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1161  { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
1162  { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
1163  { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
1164  { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
1165  { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
1166  { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
1167  { 0x8140, 0x800003f9, AR5K_INI_WRITE },
1168  { 0x8144, 0x00000000, AR5K_INI_WRITE },
1169  { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
1170  { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
1171  { 0x983c, 0x00200400, AR5K_INI_WRITE },
1172  { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
1173  { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
1174  { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1175  { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
1176  { 0x9958, 0x00081fff, AR5K_INI_WRITE },
1177  { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
1178  { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
1179  { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
1180  { 0x99dc, 0xfebadbe8, AR5K_INI_WRITE },
1181  { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
1182  { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
1183  { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
1184  { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
1185  { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
1186  { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
1187  { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
1188  { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
1189  { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
1190  { AR5K_PHY_TXPOWER_RATE4, 0x20202020, AR5K_INI_WRITE },
1191  { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
1192  { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
1193  { 0xa250, 0x0000a000, AR5K_INI_WRITE },
1194  { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
1195  { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
1196  { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
1197  { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
1198  { 0xa264, 0x00418a11, AR5K_INI_WRITE },
1199  { 0xa268, 0x00000000, AR5K_INI_WRITE },
1200  { AR5K_PHY_TPC_RG5, 0x0c30c166, AR5K_INI_WRITE },
1201  { 0xa270, 0x00820820, AR5K_INI_WRITE },
1202  { 0xa274, 0x081a3caa, AR5K_INI_WRITE },
1203  { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
1204  { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
1205  { 0xa300, 0x16010000, AR5K_INI_WRITE },
1206  { 0xa304, 0x2c032402, AR5K_INI_WRITE },
1207  { 0xa308, 0x48433e42, AR5K_INI_WRITE },
1208  { 0xa30c, 0x5a0f500b, AR5K_INI_WRITE },
1209  { 0xa310, 0x6c4b624a, AR5K_INI_WRITE },
1210  { 0xa314, 0x7e8b748a, AR5K_INI_WRITE },
1211  { 0xa318, 0x96cf8ccb, AR5K_INI_WRITE },
1212  { 0xa31c, 0xa34f9d0f, AR5K_INI_WRITE },
1213  { 0xa320, 0xa7cfa58f, AR5K_INI_WRITE },
1214  { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
1215  { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
1216  { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
1217  { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
1218  { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
1219  { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
1220  { 0xa360, 0x0f282207, AR5K_INI_WRITE },
1221  { 0xa364, 0x17601685, AR5K_INI_WRITE },
1222  { 0xa368, 0x1f801104, AR5K_INI_WRITE },
1223  { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
1224  { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
1225  { 0xa374, 0x57c00803, AR5K_INI_WRITE },
1226  { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
1227  { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
1228  { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
1229  { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
1230 };
1231 
1232 /*
1233  * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
1234  * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
1235  */
1236 
1237 /* RF5111 Initial BaseBand Gain settings */
1238 static const struct ath5k_ini rf5111_ini_bbgain[] = {
1239  { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
1240  { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
1241  { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
1242  { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
1243  { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
1244  { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
1245  { AR5K_BB_GAIN(6), 0x00000004, AR5K_INI_WRITE },
1246  { AR5K_BB_GAIN(7), 0x00000024, AR5K_INI_WRITE },
1247  { AR5K_BB_GAIN(8), 0x00000014, AR5K_INI_WRITE },
1248  { AR5K_BB_GAIN(9), 0x00000034, AR5K_INI_WRITE },
1249  { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
1250  { AR5K_BB_GAIN(11), 0x0000002c, AR5K_INI_WRITE },
1251  { AR5K_BB_GAIN(12), 0x00000002, AR5K_INI_WRITE },
1252  { AR5K_BB_GAIN(13), 0x00000022, AR5K_INI_WRITE },
1253  { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
1254  { AR5K_BB_GAIN(15), 0x00000032, AR5K_INI_WRITE },
1255  { AR5K_BB_GAIN(16), 0x0000000a, AR5K_INI_WRITE },
1256  { AR5K_BB_GAIN(17), 0x0000002a, AR5K_INI_WRITE },
1257  { AR5K_BB_GAIN(18), 0x00000006, AR5K_INI_WRITE },
1258  { AR5K_BB_GAIN(19), 0x00000026, AR5K_INI_WRITE },
1259  { AR5K_BB_GAIN(20), 0x00000016, AR5K_INI_WRITE },
1260  { AR5K_BB_GAIN(21), 0x00000036, AR5K_INI_WRITE },
1261  { AR5K_BB_GAIN(22), 0x0000000e, AR5K_INI_WRITE },
1262  { AR5K_BB_GAIN(23), 0x0000002e, AR5K_INI_WRITE },
1263  { AR5K_BB_GAIN(24), 0x00000001, AR5K_INI_WRITE },
1264  { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
1265  { AR5K_BB_GAIN(26), 0x00000011, AR5K_INI_WRITE },
1266  { AR5K_BB_GAIN(27), 0x00000031, AR5K_INI_WRITE },
1267  { AR5K_BB_GAIN(28), 0x00000009, AR5K_INI_WRITE },
1268  { AR5K_BB_GAIN(29), 0x00000029, AR5K_INI_WRITE },
1269  { AR5K_BB_GAIN(30), 0x00000005, AR5K_INI_WRITE },
1270  { AR5K_BB_GAIN(31), 0x00000025, AR5K_INI_WRITE },
1271  { AR5K_BB_GAIN(32), 0x00000015, AR5K_INI_WRITE },
1272  { AR5K_BB_GAIN(33), 0x00000035, AR5K_INI_WRITE },
1273  { AR5K_BB_GAIN(34), 0x0000000d, AR5K_INI_WRITE },
1274  { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
1275  { AR5K_BB_GAIN(36), 0x00000003, AR5K_INI_WRITE },
1276  { AR5K_BB_GAIN(37), 0x00000023, AR5K_INI_WRITE },
1277  { AR5K_BB_GAIN(38), 0x00000013, AR5K_INI_WRITE },
1278  { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
1279  { AR5K_BB_GAIN(40), 0x0000000b, AR5K_INI_WRITE },
1280  { AR5K_BB_GAIN(41), 0x0000002b, AR5K_INI_WRITE },
1281  { AR5K_BB_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
1282  { AR5K_BB_GAIN(43), 0x0000002b, AR5K_INI_WRITE },
1283  { AR5K_BB_GAIN(44), 0x0000002b, AR5K_INI_WRITE },
1284  { AR5K_BB_GAIN(45), 0x0000002b, AR5K_INI_WRITE },
1285  { AR5K_BB_GAIN(46), 0x0000002b, AR5K_INI_WRITE },
1286  { AR5K_BB_GAIN(47), 0x0000002b, AR5K_INI_WRITE },
1287  { AR5K_BB_GAIN(48), 0x0000002b, AR5K_INI_WRITE },
1288  { AR5K_BB_GAIN(49), 0x0000002b, AR5K_INI_WRITE },
1289  { AR5K_BB_GAIN(50), 0x0000002b, AR5K_INI_WRITE },
1290  { AR5K_BB_GAIN(51), 0x0000002b, AR5K_INI_WRITE },
1291  { AR5K_BB_GAIN(52), 0x0000002b, AR5K_INI_WRITE },
1292  { AR5K_BB_GAIN(53), 0x0000002b, AR5K_INI_WRITE },
1293  { AR5K_BB_GAIN(54), 0x0000002b, AR5K_INI_WRITE },
1294  { AR5K_BB_GAIN(55), 0x0000002b, AR5K_INI_WRITE },
1295  { AR5K_BB_GAIN(56), 0x0000002b, AR5K_INI_WRITE },
1296  { AR5K_BB_GAIN(57), 0x0000002b, AR5K_INI_WRITE },
1297  { AR5K_BB_GAIN(58), 0x0000002b, AR5K_INI_WRITE },
1298  { AR5K_BB_GAIN(59), 0x0000002b, AR5K_INI_WRITE },
1299  { AR5K_BB_GAIN(60), 0x0000002b, AR5K_INI_WRITE },
1300  { AR5K_BB_GAIN(61), 0x0000002b, AR5K_INI_WRITE },
1301  { AR5K_BB_GAIN(62), 0x00000002, AR5K_INI_WRITE },
1302  { AR5K_BB_GAIN(63), 0x00000016, AR5K_INI_WRITE },
1303 };
1304 
1305 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
1306 static const struct ath5k_ini rf5112_ini_bbgain[] = {
1307  { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
1308  { AR5K_BB_GAIN(1), 0x00000001, AR5K_INI_WRITE },
1309  { AR5K_BB_GAIN(2), 0x00000002, AR5K_INI_WRITE },
1310  { AR5K_BB_GAIN(3), 0x00000003, AR5K_INI_WRITE },
1311  { AR5K_BB_GAIN(4), 0x00000004, AR5K_INI_WRITE },
1312  { AR5K_BB_GAIN(5), 0x00000005, AR5K_INI_WRITE },
1313  { AR5K_BB_GAIN(6), 0x00000008, AR5K_INI_WRITE },
1314  { AR5K_BB_GAIN(7), 0x00000009, AR5K_INI_WRITE },
1315  { AR5K_BB_GAIN(8), 0x0000000a, AR5K_INI_WRITE },
1316  { AR5K_BB_GAIN(9), 0x0000000b, AR5K_INI_WRITE },
1317  { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
1318  { AR5K_BB_GAIN(11), 0x0000000d, AR5K_INI_WRITE },
1319  { AR5K_BB_GAIN(12), 0x00000010, AR5K_INI_WRITE },
1320  { AR5K_BB_GAIN(13), 0x00000011, AR5K_INI_WRITE },
1321  { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
1322  { AR5K_BB_GAIN(15), 0x00000013, AR5K_INI_WRITE },
1323  { AR5K_BB_GAIN(16), 0x00000014, AR5K_INI_WRITE },
1324  { AR5K_BB_GAIN(17), 0x00000015, AR5K_INI_WRITE },
1325  { AR5K_BB_GAIN(18), 0x00000018, AR5K_INI_WRITE },
1326  { AR5K_BB_GAIN(19), 0x00000019, AR5K_INI_WRITE },
1327  { AR5K_BB_GAIN(20), 0x0000001a, AR5K_INI_WRITE },
1328  { AR5K_BB_GAIN(21), 0x0000001b, AR5K_INI_WRITE },
1329  { AR5K_BB_GAIN(22), 0x0000001c, AR5K_INI_WRITE },
1330  { AR5K_BB_GAIN(23), 0x0000001d, AR5K_INI_WRITE },
1331  { AR5K_BB_GAIN(24), 0x00000020, AR5K_INI_WRITE },
1332  { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
1333  { AR5K_BB_GAIN(26), 0x00000022, AR5K_INI_WRITE },
1334  { AR5K_BB_GAIN(27), 0x00000023, AR5K_INI_WRITE },
1335  { AR5K_BB_GAIN(28), 0x00000024, AR5K_INI_WRITE },
1336  { AR5K_BB_GAIN(29), 0x00000025, AR5K_INI_WRITE },
1337  { AR5K_BB_GAIN(30), 0x00000028, AR5K_INI_WRITE },
1338  { AR5K_BB_GAIN(31), 0x00000029, AR5K_INI_WRITE },
1339  { AR5K_BB_GAIN(32), 0x0000002a, AR5K_INI_WRITE },
1340  { AR5K_BB_GAIN(33), 0x0000002b, AR5K_INI_WRITE },
1341  { AR5K_BB_GAIN(34), 0x0000002c, AR5K_INI_WRITE },
1342  { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
1343  { AR5K_BB_GAIN(36), 0x00000030, AR5K_INI_WRITE },
1344  { AR5K_BB_GAIN(37), 0x00000031, AR5K_INI_WRITE },
1345  { AR5K_BB_GAIN(38), 0x00000032, AR5K_INI_WRITE },
1346  { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
1347  { AR5K_BB_GAIN(40), 0x00000034, AR5K_INI_WRITE },
1348  { AR5K_BB_GAIN(41), 0x00000035, AR5K_INI_WRITE },
1349  { AR5K_BB_GAIN(42), 0x00000035, AR5K_INI_WRITE },
1350  { AR5K_BB_GAIN(43), 0x00000035, AR5K_INI_WRITE },
1351  { AR5K_BB_GAIN(44), 0x00000035, AR5K_INI_WRITE },
1352  { AR5K_BB_GAIN(45), 0x00000035, AR5K_INI_WRITE },
1353  { AR5K_BB_GAIN(46), 0x00000035, AR5K_INI_WRITE },
1354  { AR5K_BB_GAIN(47), 0x00000035, AR5K_INI_WRITE },
1355  { AR5K_BB_GAIN(48), 0x00000035, AR5K_INI_WRITE },
1356  { AR5K_BB_GAIN(49), 0x00000035, AR5K_INI_WRITE },
1357  { AR5K_BB_GAIN(50), 0x00000035, AR5K_INI_WRITE },
1358  { AR5K_BB_GAIN(51), 0x00000035, AR5K_INI_WRITE },
1359  { AR5K_BB_GAIN(52), 0x00000035, AR5K_INI_WRITE },
1360  { AR5K_BB_GAIN(53), 0x00000035, AR5K_INI_WRITE },
1361  { AR5K_BB_GAIN(54), 0x00000035, AR5K_INI_WRITE },
1362  { AR5K_BB_GAIN(55), 0x00000035, AR5K_INI_WRITE },
1363  { AR5K_BB_GAIN(56), 0x00000035, AR5K_INI_WRITE },
1364  { AR5K_BB_GAIN(57), 0x00000035, AR5K_INI_WRITE },
1365  { AR5K_BB_GAIN(58), 0x00000035, AR5K_INI_WRITE },
1366  { AR5K_BB_GAIN(59), 0x00000035, AR5K_INI_WRITE },
1367  { AR5K_BB_GAIN(60), 0x00000035, AR5K_INI_WRITE },
1368  { AR5K_BB_GAIN(61), 0x00000035, AR5K_INI_WRITE },
1369  { AR5K_BB_GAIN(62), 0x00000010, AR5K_INI_WRITE },
1370  { AR5K_BB_GAIN(63), 0x0000001a, AR5K_INI_WRITE },
1371 };
1372 
1373 
1374 /*
1375  * Write initial register dump
1376  */
1377 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1378  const struct ath5k_ini *ini_regs, int change_channel)
1379 {
1380  unsigned int i;
1381 
1382  /* Write initial registers */
1383  for (i = 0; i < size; i++) {
1384  /* On channel change there is
1385  * no need to mess with PCU */
1386  if (change_channel &&
1387  ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1388  ini_regs[i].ini_register <= AR5K_PCU_MAX)
1389  continue;
1390 
1391  switch (ini_regs[i].ini_mode) {
1392  case AR5K_INI_READ:
1393  /* Cleared on read */
1394  ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
1395  break;
1396  case AR5K_INI_WRITE:
1397  default:
1398  AR5K_REG_WAIT(i);
1399  ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1400  ini_regs[i].ini_register);
1401  }
1402  }
1403 }
1404 
1406  unsigned int size, const struct ath5k_ini_mode *ini_mode,
1407  u8 mode)
1408 {
1409  unsigned int i;
1410 
1411  for (i = 0; i < size; i++) {
1412  AR5K_REG_WAIT(i);
1413  ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1414  (u32)ini_mode[i].mode_register);
1415  }
1416 }
1417 
1418 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
1419 {
1420  /*
1421  * Write initial register settings
1422  */
1423 
1424  /* For AR5212 and combatible */
1425  if (ah->ah_version == AR5K_AR5212) {
1426 
1427  /* First set of mode-specific settings */
1430  ar5212_ini_mode_start, mode);
1431 
1432  /*
1433  * Write initial settings common for all modes
1434  */
1436  ar5212_ini_common_start, change_channel);
1437 
1438  /* Second set of mode-specific settings */
1439  switch (ah->ah_radio) {
1440  case AR5K_RF5111:
1441 
1444  rf5111_ini_mode_end, mode);
1445 
1448  rf5111_ini_common_end, change_channel);
1449 
1450  /* Baseband gain table */
1453  rf5111_ini_bbgain, change_channel);
1454 
1455  break;
1456  case AR5K_RF5112:
1457 
1460  rf5112_ini_mode_end, mode);
1461 
1464  rf5112_ini_common_end, change_channel);
1465 
1468  rf5112_ini_bbgain, change_channel);
1469 
1470  break;
1471  case AR5K_RF5413:
1472 
1475  rf5413_ini_mode_end, mode);
1476 
1479  rf5413_ini_common_end, change_channel);
1480 
1483  rf5112_ini_bbgain, change_channel);
1484 
1485  break;
1486  case AR5K_RF2316:
1487  case AR5K_RF2413:
1488 
1491  rf2413_ini_mode_end, mode);
1492 
1495  rf2413_ini_common_end, change_channel);
1496 
1497  /* Override settings from rf2413_ini_common_end */
1498  if (ah->ah_radio == AR5K_RF2316) {
1499  ath5k_hw_reg_write(ah, 0x00004000,
1500  AR5K_PHY_AGC);
1501  ath5k_hw_reg_write(ah, 0x081b7caa,
1502  0xa274);
1503  }
1504 
1507  rf5112_ini_bbgain, change_channel);
1508  break;
1509  case AR5K_RF2317:
1510  case AR5K_RF2425:
1511 
1514  rf2425_ini_mode_end, mode);
1515 
1518  rf2425_ini_common_end, change_channel);
1519 
1522  rf5112_ini_bbgain, change_channel);
1523  break;
1524  default:
1525  return -EINVAL;
1526 
1527  }
1528 
1529  /* For AR5211 */
1530  } else if (ah->ah_version == AR5K_AR5211) {
1531 
1532  /* AR5K_MODE_11B */
1533  if (mode > 2) {
1534  DBG("ath5k: unsupported channel mode %d\n", mode);
1535  return -EINVAL;
1536  }
1537 
1538  /* Mode-specific settings */
1540  ar5211_ini_mode, mode);
1541 
1542  /*
1543  * Write initial settings common for all modes
1544  */
1546  ar5211_ini, change_channel);
1547 
1548  /* AR5211 only comes with 5111 */
1549 
1550  /* Baseband gain table */
1552  rf5111_ini_bbgain, change_channel);
1553  /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1554  } else if (ah->ah_version == AR5K_AR5210) {
1556  ar5210_ini, change_channel);
1557  }
1558 
1559  return 0;
1560 }
#define AR5K_PHY_SPENDING
Definition: reg.h:2484
#define AR5K_TIMER2_5210
Definition: reg.h:1278
#define AR5K_DCU_GBL_IFS_EIFS
Definition: reg.h:774
#define AR5K_PHY_FRAME_CTL_5211
Definition: reg.h:2272
uint16_t u16
Definition: stdint.h:21
#define AR5K_PHY_SETTLING
Definition: reg.h:1975
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_BSS_ID0
Definition: reg.h:1154
#define AR5K_PROFCNT_TX
Definition: reg.h:1672
#define AR5K_TSF_PARM
Definition: reg.h:1695
#define AR5K_TUNE_RSSI_THRES
Definition: ath5k.h:172
#define AR5K_RX_FILTER_5210
Definition: reg.h:1323
#define AR5K_RATE_DUR(_n)
Definition: reg.h:1792
#define AR5K_QUIET_CTL1
Definition: reg.h:1680
#define AR5K_PHY_TIMING_3
Definition: reg.h:1918
#define AR5K_PHY_TXPOWER_RATE_MAX
Definition: reg.h:2263
#define AR5K_MIC_QOS_CTL
Definition: reg.h:1732
#define AR5K_PHY_AGCCOARSE
Definition: reg.h:2019
#define AR5K_PHY_PCDAC_TXPOWER_BASE
Definition: reg.h:2497
#define AR5K_RX_FILTER_5211
Definition: reg.h:1324
#define AR5K_INIT_CFG
Definition: ath5k.h:205
#define AR5K_PHY_TIMING_8
Definition: reg.h:2377
#define AR5K_RTSD1
Definition: reg.h:155
#define AR5K_REG_WAIT(_i)
Definition: ath5k.h:133
#define AR5K_PHY_WEAK_OFDM_HIGH_THR
Definition: reg.h:2062
#define AR5K_PHY_CCK_RX_CTL_4
Definition: reg.h:2546
#define AR5K_PHY_RESTART
Definition: reg.h:2363
#define AR5K_XRTIMEOUT
Definition: reg.h:1594
#define AR5K_PHY_PAPD_PROBE
Definition: reg.h:2240
#define AR5K_PHY_MAX_RX_LEN
Definition: reg.h:2184
static const struct ath5k_ini rf2413_ini_common_end[]
#define AR5K_DCU_TXP
Definition: reg.h:809
static const struct ath5k_ini_mode rf5111_ini_mode_end[]
#define AR5K_PHY_WEAK_OFDM_LOW_THR
Definition: reg.h:2071
#define AR5K_XRLAT_TX
Definition: reg.h:1721
#define AR5K_TIMER1_5211
Definition: reg.h:1271
#define AR5K_BSS_IDM0
Definition: reg.h:1650
#define AR5K_XRMODE
Definition: reg.h:1572
#define AR5K_TIME_OUT
Definition: reg.h:1173
#define AR5K_TSF_THRES
Definition: reg.h:1773
#define AR5K_MCAST_FILTER0_5210
Definition: reg.h:1349
#define AR5K_SEQ_MASK
Definition: reg.h:1487
#define AR5K_RPGTO
Definition: reg.h:243
#define AR5K_PHY_PA_CTL
Definition: reg.h:1966
#define AR5K_DCU_GBL_IFS_SLOT
Definition: reg.h:768
u16 ini_register
#define AR5K_CCK_FIL_CNT
Definition: reg.h:1759
static const struct ath5k_ini rf5112_ini_common_end[]
#define AR5K_PHY_RF_CTL4
Definition: reg.h:1956
#define AR5K_PHY_BLUETOOTH
Definition: reg.h:2557
#define AR5K_PHY_RF_CTL2
Definition: reg.h:1939
#define AR5K_PHY_IQ
Definition: reg.h:2190
#define AR5K_TXCFG
Definition: reg.h:169
#define AR5K_PHY_BIN_MASK_2
Definition: reg.h:2156
#define AR5K_DCU_GBL_IFS_MISC
Definition: reg.h:787
#define AR5K_XRSTOMP
Definition: reg.h:1610
#define AR5K_PHY_SDELAY
Definition: reg.h:2482
#define AR5K_PHY_CTL
Definition: reg.h:2227
#define AR5K_MCAST_FILTER1_5210
Definition: reg.h:1357
#define AR5K_PHY_GAIN
Definition: reg.h:1984
#define AR5K_BSR
Definition: reg.h:140
#define AR5K_RFCNT
Definition: reg.h:249
#define AR5K_PHY_TXPOWER_RATE1
Definition: reg.h:2261
#define AR5K_TIMER3_5211
Definition: reg.h:1287
#define AR5K_PHY_SCAL
Definition: reg.h:2089
static const struct ath5k_ini_mode rf2425_ini_mode_end[]
#define AR5K_MCAST_FILTER1_5211
Definition: reg.h:1358
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
#define AR5K_PHY_RADAR
Definition: reg.h:2307
int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
#define AR5K_PHY_NFTHRES
Definition: reg.h:2345
#define AR5K_PHY_SIG
Definition: reg.h:2009
#define AR5K_RF_BUFFER_CONTROL_4
Definition: reg.h:2134
static const struct ath5k_ini rf5111_ini_bbgain[]
#define AR5K_TIMER2_5211
Definition: reg.h:1279
#define AR5K_PHY_PCDAC_TXPOWER(_n)
Definition: reg.h:2498
#define AR5K_PHY_AGC
Definition: reg.h:1905
#define AR5K_OFDM_FIL_CNT
Definition: reg.h:1754
#define AR5K_PHY_AGCCTL
Definition: reg.h:2028
#define AR5K_PHY_ADC_CTL
Definition: reg.h:1947
#define AR5K_DCU_TX_FILTER_CLR
Definition: reg.h:830
static const struct ath5k_ini_mode ar5212_ini_mode_start[]
#define AR5K_PHY_TIMING_11
Definition: reg.h:2397
#define AR5K_PROFCNT_CYCLE
Definition: reg.h:1675
#define AR5K_TOPS
Definition: reg.h:223
#define AR5K_FRAME_CTL_QOSM
Definition: reg.h:1482
#define AR5K_STA_ID1
Definition: reg.h:1128
#define AR5K_TUNE_MIN_TX_FIFO_THRES
Definition: ath5k.h:167
#define AR5K_5414_CBCFG
Definition: reg.h:981
#define AR5K_PHY_ERR_FIL
Definition: reg.h:1713
#define AR5K_CFP_PERIOD_5211
Definition: reg.h:1255
FILE_LICENCE(MIT)
static const struct ath5k_ini_mode rf2413_ini_mode_end[]
#define AR5K_MIC_QOS_SEL
Definition: reg.h:1739
#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)
Definition: reg.h:686
#define AR5K_TSF_L32_5210
Definition: reg.h:1439
#define AR5K_CFP_DUR_5211
Definition: reg.h:1316
#define AR5K_TIMER1_5210
Definition: reg.h:1270
#define AR5K_PHY_TURBO
Definition: reg.h:1896
#define AR5K_PHY_NF
Definition: reg.h:2037
#define AR5K_PHY_SLMT
Definition: reg.h:2086
#define AR5K_PHY_TXPOWER_RATE3
Definition: reg.h:2265
#define AR5K_SLEEP0
Definition: reg.h:1621
#define AR5K_PHY_TPC_RG5
Definition: reg.h:2573
#define AR5K_TRIG_LVL
Definition: reg.h:1381
#define AR5K_ADDAC_TEST
Definition: reg.h:1460
static const struct ath5k_ini ar5211_ini[]
#define AR5K_PHY_RFBUS_REQ
Definition: reg.h:2370
#define AR5K_BEACON_5211
Definition: reg.h:1241
#define AR5K_TXPC
Definition: reg.h:1659
static const struct ath5k_ini rf5112_ini_bbgain[]
#define AR5K_PHY_ANT_CTL
Definition: reg.h:2168
#define AR5K_PHY_SCR
Definition: reg.h:2084
#define AR5K_DCU_FP
Definition: reg.h:801
#define AR5K_PHY_FAST_ADC
Definition: reg.h:2555
static const struct ath5k_ini ar5210_ini[]
#define AR5K_TXNOFRM
Definition: reg.h:235
#define AR5K_CFP_PERIOD_5210
Definition: reg.h:1254
#define AR5K_CR
Definition: reg.h:53
#define AR5K_PHYERR_CNT2_MASK
Definition: reg.h:1768
#define AR5K_DCU_TX_FILTER_1(_n)
Definition: reg.h:825
#define AR5K_RATE2DB(_n)
Definition: reg.h:1799
#define AR5K_NOQCU_TXDP0
Definition: reg.h:47
#define AR5K_CLR_TMASK
Definition: reg.h:1376
#define AR5K_DEFAULT_ANTENNA
Definition: reg.h:1476
#define AR5K_PHY_TIMING_7
Definition: reg.h:2376
#define AR5K_PHY_HEAVY_CLIP_ENABLE
Definition: reg.h:2475
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
static const struct ath5k_ini rf5111_ini_common_end[]
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_QOS_NOACK
Definition: reg.h:1702
#define AR5K_SLEEP1
Definition: reg.h:1632
#define AR5K_ACKSIFS
Definition: reg.h:1726
#define AR5K_PHYERR_CNT1_MASK
Definition: reg.h:1765
#define AR5K_PHY_ACT_DISABLE
Definition: reg.h:1934
#define AR5K_PHY_WARM_RESET
Definition: reg.h:2222
#define AR5K_RSSI_THR
Definition: reg.h:1182
#define AR5K_ISR
Definition: reg.h:285
#define AR5K_PROFCNT_RX
Definition: reg.h:1673
#define AR5K_PHY_BIN_MASK_CTL
Definition: reg.h:2159
static const struct ath5k_ini ar5212_ini_common_start[]
#define AR5K_TIMER0_5211
Definition: reg.h:1263
#define AR5K_DCU_TX_FILTER_SET
Definition: reg.h:835
#define AR5K_SFR
Definition: reg.h:873
static const struct ath5k_ini_mode rf5413_ini_mode_end[]
#define AR5K_BB_GAIN(_n)
Definition: reg.h:2409
#define AR5K_DIAG_SW_5211
Definition: reg.h:1391
#define AR5K_MISC
Definition: reg.h:257
#define AR5K_BSS_IDM1
Definition: reg.h:1651
#define AR5K_DCU_GBL_IFS_SIFS
Definition: reg.h:762
#define AR5K_PHY(_n)
Definition: reg.h:1861
#define AR5K_DIAG_SW_5210
Definition: reg.h:1390
#define AR5K_IER_DISABLE
Definition: reg.h:91
#define AR5K_BSS_ID1
Definition: reg.h:1161
#define AR5K_RXDP
Definition: reg.h:65
#define AR5K_PHY_SCLOCK
Definition: reg.h:2480
#define AR5K_RXNOFRM
Definition: reg.h:229
#define AR5K_SLEEP2
Definition: reg.h:1641
#define AR5K_NOQCU_TXDP1
Definition: reg.h:48
#define AR5K_TIMER3_5210
Definition: reg.h:1286
#define AR5K_QUIET_CTL2
Definition: reg.h:1686
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
#define AR5K_DCU_TX_FILTER_0(_n)
Definition: reg.h:819
static const struct ath5k_ini_mode rf5112_ini_mode_end[]
#define AR5K_RF_GAIN(_n)
Definition: reg.h:2411
#define AR5K_IMR
Definition: reg.h:379
#define AR5K_TX_MASK1
Definition: reg.h:1371
#define AR5K_RTSD0
Definition: reg.h:114
#define AR5K_XRCHIRP
Definition: reg.h:1603
#define AR5K_DB2RATE(_n)
Definition: reg.h:1806
enum ath5k_ini::@13 ini_mode
#define AR5K_PHY_GAIN_2GHZ
Definition: reg.h:2541
uint8_t ah
Definition: registers.h:85
#define AR5K_PHY_TPC_RG1
Definition: reg.h:2563
#define AR5K_IER
Definition: reg.h:90
#define AR5K_PHY_TXPOWER_RATE4
Definition: reg.h:2266
#define AR5K_PHY_BIN_MASK_1
Definition: reg.h:2155
#define AR5K_RXCFG
Definition: reg.h:196
#define AR5K_PHY_CCK_CROSSCORR
Definition: reg.h:2530
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
static const struct ath5k_ini rf5413_ini_common_end[]
#define AR5K_PHY_DAG_CCK_CTL
Definition: reg.h:2550
static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, const struct ath5k_ini *ini_regs, int change_channel)
#define AR5K_USEC_5211
Definition: reg.h:1221
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR5K_CFG
Definition: reg.h:70
#define AR5K_TIMER0_5210
Definition: reg.h:1262
#define AR5K_PHY_DESIRED_SIZE
Definition: reg.h:1997
#define AR5K_PHY_BIN_MASK_3
Definition: reg.h:2157
#define AR5K_QUEUE_TXDP(_q)
Definition: reg.h:554
static const struct ath5k_ini_mode ar5211_ini_mode[]
#define AR5K_XRDELAY
Definition: reg.h:1585
static const struct ath5k_ini rf2425_ini_common_end[]
static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, unsigned int size, const struct ath5k_ini_mode *ini_mode, u8 mode)
#define AR5K_MISC_MODE
Definition: reg.h:1745
#define AR5K_PHY_CCKTXCTL
Definition: reg.h:2521
#define AR5K_PHYERR_CNT1
Definition: reg.h:1764
#define AR5K_PHY_RX_DELAY
Definition: reg.h:2178
#define AR5K_PCU_MIN
Definition: reg.h:1116
#define AR5K_PROFCNT_RXCLR
Definition: reg.h:1674
#define AR5K_PHY_RF_CTL3
Definition: reg.h:1943
#define AR5K_MCAST_FILTER0_5211
Definition: reg.h:1350
#define AR5K_PHY_TXPOWER_RATE2
Definition: reg.h:2262
uint8_t u8
Definition: stdint.h:19
#define AR5K_MIBC
Definition: reg.h:214
#define AR5K_CFP_DUR_5210
Definition: reg.h:1315
#define AR5K_TX_MASK0
Definition: reg.h:1366
uint32_t u32
Definition: stdint.h:23
#define AR5K_PHY_ACT_ENABLE
Definition: reg.h:1933
#define AR5K_PCU_MAX
Definition: reg.h:1117
#define AR5K_PHY_GAIN_OFFSET
Definition: reg.h:1990
#define AR5K_PHYERR_CNT2
Definition: reg.h:1767
#define AR5K_PHY_ACT
Definition: reg.h:1932
#define AR5K_PHY_OFDM_SELFCORR
Definition: reg.h:2210