iPXE
ath5k.h
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1 /*
2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4  *
5  * Modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
6  * Original from Linux kernel 2.6.30.
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  */
20 
21 #ifndef _ATH5K_H
22 #define _ATH5K_H
23 
24 FILE_LICENCE ( MIT );
25 
26 #include <stddef.h>
27 #include <byteswap.h>
28 #include <ipxe/io.h>
29 #include <ipxe/netdevice.h>
30 #include <ipxe/net80211.h>
31 #include <errno.h>
32 
33 /* Keep all ath5k files under one errfile ID */
34 #undef ERRFILE
35 #define ERRFILE ERRFILE_ath5k
36 
37 /* RX/TX descriptor hw structs */
38 #include "desc.h"
39 
40 /* EEPROM structs/offsets */
41 #include "eeprom.h"
42 
43 /* PCI IDs */
44 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
45 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
46 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
47 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
48 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
49 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
60 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
65 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
66 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
67 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
68 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
69 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
70 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
71 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
72 
73 /****************************\
74  GENERIC DRIVER DEFINITIONS
75 \****************************/
76 
77 /*
78  * AR5K REGISTER ACCESS
79  */
80 
81 /* Some macros to read/write fields */
82 
83 /* First shift, then mask */
84 #define AR5K_REG_SM(_val, _flags) \
85  (((_val) << _flags##_S) & (_flags))
86 
87 /* First mask, then shift */
88 #define AR5K_REG_MS(_val, _flags) \
89  (((_val) & (_flags)) >> _flags##_S)
90 
91 /* Some registers can hold multiple values of interest. For this
92  * reason when we want to write to these registers we must first
93  * retrieve the values which we do not want to clear (lets call this
94  * old_data) and then set the register with this and our new_value:
95  * ( old_data | new_value) */
96 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
97  ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
98  (((_val) << _flags##_S) & (_flags)), _reg)
99 
100 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
101  ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
102  (_mask)) | (_flags), _reg)
103 
104 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
105  ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
106 
107 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
108  ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
109 
110 /* Access to PHY registers */
111 #define AR5K_PHY_READ(ah, _reg) \
112  ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
113 
114 #define AR5K_PHY_WRITE(ah, _reg, _val) \
115  ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
116 
117 /* Access QCU registers per queue */
118 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
119  (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
120 
121 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
122  ath5k_hw_reg_write(ah, (1 << _queue), _reg)
123 
124 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
125  _reg |= 1 << _queue; \
126 } while (0)
127 
128 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
129  _reg &= ~(1 << _queue); \
130 } while (0)
131 
132 /* Used while writing initvals */
133 #define AR5K_REG_WAIT(_i) do { \
134  if (_i % 64) \
135  udelay(1); \
136 } while (0)
137 
138 /* Register dumps are done per operation mode */
139 #define AR5K_INI_RFGAIN_5GHZ 0
140 #define AR5K_INI_RFGAIN_2GHZ 1
141 
142 /* TODO: Clean this up */
143 #define AR5K_INI_VAL_11A 0
144 #define AR5K_INI_VAL_11A_TURBO 1
145 #define AR5K_INI_VAL_11B 2
146 #define AR5K_INI_VAL_11G 3
147 #define AR5K_INI_VAL_11G_TURBO 4
148 #define AR5K_INI_VAL_XR 0
149 #define AR5K_INI_VAL_MAX 5
150 
151 /* Used for BSSID etc manipulation */
152 #define AR5K_LOW_ID(_a)( \
153 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
154 )
155 
156 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
157 
158 #define IEEE80211_MAX_LEN 2352
159 
160 /*
161  * Some tuneable values (these should be changeable by the user)
162  */
163 #define AR5K_TUNE_DMA_BEACON_RESP 2
164 #define AR5K_TUNE_SW_BEACON_RESP 10
165 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
166 #define AR5K_TUNE_RADAR_ALERT 0
167 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
168 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
169 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
170 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
171  * be the max value. */
172 #define AR5K_TUNE_RSSI_THRES 129
173 /* This must be set when setting the RSSI threshold otherwise it can
174  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
175  * the BMISS_THRES will be seen as 0, seems harware doesn't keep
176  * track of it. Max value depends on harware. For AR5210 this is just 7.
177  * For AR5211+ this seems to be up to 255. */
178 #define AR5K_TUNE_BMISS_THRES 7
179 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
180 #define AR5K_TUNE_BEACON_INTERVAL 100
181 #define AR5K_TUNE_AIFS 2
182 #define AR5K_TUNE_AIFS_11B 2
183 #define AR5K_TUNE_AIFS_XR 0
184 #define AR5K_TUNE_CWMIN 15
185 #define AR5K_TUNE_CWMIN_11B 31
186 #define AR5K_TUNE_CWMIN_XR 3
187 #define AR5K_TUNE_CWMAX 1023
188 #define AR5K_TUNE_CWMAX_11B 1023
189 #define AR5K_TUNE_CWMAX_XR 7
190 #define AR5K_TUNE_NOISE_FLOOR -72
191 #define AR5K_TUNE_MAX_TXPOWER 63
192 #define AR5K_TUNE_DEFAULT_TXPOWER 25
193 #define AR5K_TUNE_TPC_TXPOWER 0
194 #define AR5K_TUNE_ANT_DIVERSITY 1
195 #define AR5K_TUNE_HWTXTRIES 4
196 
197 #define AR5K_INIT_CARR_SENSE_EN 1
198 
199 /*Swap RX/TX Descriptor for big endian archs*/
200 #if __BYTE_ORDER == __BIG_ENDIAN
201 #define AR5K_INIT_CFG ( \
202  AR5K_CFG_SWTD | AR5K_CFG_SWRD \
203 )
204 #else
205 #define AR5K_INIT_CFG 0x00000000
206 #endif
207 
208 /* Initial values */
209 #define AR5K_INIT_CYCRSSI_THR1 2
210 #define AR5K_INIT_TX_LATENCY 502
211 #define AR5K_INIT_USEC 39
212 #define AR5K_INIT_USEC_TURBO 79
213 #define AR5K_INIT_USEC_32 31
214 #define AR5K_INIT_SLOT_TIME 396
215 #define AR5K_INIT_SLOT_TIME_TURBO 480
216 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
217 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
218 #define AR5K_INIT_PROG_IFS 920
219 #define AR5K_INIT_PROG_IFS_TURBO 960
220 #define AR5K_INIT_EIFS 3440
221 #define AR5K_INIT_EIFS_TURBO 6880
222 #define AR5K_INIT_SIFS 560
223 #define AR5K_INIT_SIFS_TURBO 480
224 #define AR5K_INIT_SH_RETRY 10
225 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
226 #define AR5K_INIT_SSH_RETRY 32
227 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
228 #define AR5K_INIT_TX_RETRY 10
229 
230 #define AR5K_INIT_TRANSMIT_LATENCY ( \
231  (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
232  (AR5K_INIT_USEC) \
233 )
234 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
235  (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
236  (AR5K_INIT_USEC_TURBO) \
237 )
238 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
239  (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
240  (AR5K_INIT_PROG_IFS) \
241 )
242 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
243  (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
244  (AR5K_INIT_PROG_IFS_TURBO) \
245 )
246 
247 /* token to use for aifs, cwmin, cwmax in MadWiFi */
248 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
249 
250 /* GENERIC CHIPSET DEFINITIONS */
251 
252 /* MAC Chips */
257 };
258 
259 /* PHY Chips */
269 };
270 
271 /*
272  * Common silicon revision/version values
273  */
274 
278 };
279 
281  const char *sr_name;
283  unsigned sr_val;
284 };
285 
286 #define AR5K_SREV_UNKNOWN 0xffff
287 
288 #define AR5K_SREV_AR5210 0x00 /* Crete */
289 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
290 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
291 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
292 #define AR5K_SREV_AR5211 0x40 /* Oahu */
293 #define AR5K_SREV_AR5212 0x50 /* Venice */
294 #define AR5K_SREV_AR5213 0x55 /* ??? */
295 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
296 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
297 #define AR5K_SREV_AR2414 0x70 /* Griffin */
298 #define AR5K_SREV_AR5424 0x90 /* Condor */
299 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
300 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
301 #define AR5K_SREV_AR2415 0xb0 /* Talon */
302 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
303 #define AR5K_SREV_AR5418 0xca /* PCI-E */
304 #define AR5K_SREV_AR2425 0xe0 /* Swan */
305 #define AR5K_SREV_AR2417 0xf0 /* Nala */
306 
307 #define AR5K_SREV_RAD_5110 0x00
308 #define AR5K_SREV_RAD_5111 0x10
309 #define AR5K_SREV_RAD_5111A 0x15
310 #define AR5K_SREV_RAD_2111 0x20
311 #define AR5K_SREV_RAD_5112 0x30
312 #define AR5K_SREV_RAD_5112A 0x35
313 #define AR5K_SREV_RAD_5112B 0x36
314 #define AR5K_SREV_RAD_2112 0x40
315 #define AR5K_SREV_RAD_2112A 0x45
316 #define AR5K_SREV_RAD_2112B 0x46
317 #define AR5K_SREV_RAD_2413 0x50
318 #define AR5K_SREV_RAD_5413 0x60
319 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
320 #define AR5K_SREV_RAD_2317 0x80
321 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
322 #define AR5K_SREV_RAD_2425 0xa2
323 #define AR5K_SREV_RAD_5133 0xc0
324 
325 #define AR5K_SREV_PHY_5211 0x30
326 #define AR5K_SREV_PHY_5212 0x41
327 #define AR5K_SREV_PHY_5212A 0x42
328 #define AR5K_SREV_PHY_5212B 0x43
329 #define AR5K_SREV_PHY_2413 0x45
330 #define AR5K_SREV_PHY_5413 0x61
331 #define AR5K_SREV_PHY_2425 0x70
332 
333 /*
334  * Some of this information is based on Documentation from:
335  *
336  * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
337  *
338  * Modulation for Atheros' eXtended Range - range enhancing extension that is
339  * supposed to double the distance an Atheros client device can keep a
340  * connection with an Atheros access point. This is achieved by increasing
341  * the receiver sensitivity up to, -105dBm, which is about 20dB above what
342  * the 802.11 specifications demand. In addition, new (proprietary) data rates
343  * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
344  *
345  * Please note that can you either use XR or TURBO but you cannot use both,
346  * they are exclusive.
347  *
348  */
349 #define MODULATION_XR 0x00000200
350 
351 /*
352  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
353  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
354  * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
355  * channels. To use this feature your Access Point must also suport it.
356  * There is also a distinction between "static" and "dynamic" turbo modes:
357  *
358  * - Static: is the dumb version: devices set to this mode stick to it until
359  * the mode is turned off.
360  * - Dynamic: is the intelligent version, the network decides itself if it
361  * is ok to use turbo. As soon as traffic is detected on adjacent channels
362  * (which would get used in turbo mode), or when a non-turbo station joins
363  * the network, turbo mode won't be used until the situation changes again.
364  * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
365  * monitors the used radio band in order to decide whether turbo mode may
366  * be used or not.
367  *
368  * This article claims Super G sticks to bonding of channels 5 and 6 for
369  * USA:
370  *
371  * http://www.pcworld.com/article/id,113428-page,1/article.html
372  *
373  * The channel bonding seems to be driver specific though. In addition to
374  * deciding what channels will be used, these "Turbo" modes are accomplished
375  * by also enabling the following features:
376  *
377  * - Bursting: allows multiple frames to be sent at once, rather than pausing
378  * after each frame. Bursting is a standards-compliant feature that can be
379  * used with any Access Point.
380  * - Fast frames: increases the amount of information that can be sent per
381  * frame, also resulting in a reduction of transmission overhead. It is a
382  * proprietary feature that needs to be supported by the Access Point.
383  * - Compression: data frames are compressed in real time using a Lempel Ziv
384  * algorithm. This is done transparently. Once this feature is enabled,
385  * compression and decompression takes place inside the chipset, without
386  * putting additional load on the host CPU.
387  *
388  */
389 #define MODULATION_TURBO 0x00000080
390 
398 };
399 
400 enum {
407 };
408 
409 /****************\
410  TX DEFINITIONS
411 \****************/
412 
413 /*
414  * TX Status descriptor
415  */
428 } __attribute__ ((packed));
429 
430 #define AR5K_TXSTAT_ALTRATE 0x80
431 #define AR5K_TXERR_XRETRY 0x01
432 #define AR5K_TXERR_FILT 0x02
433 #define AR5K_TXERR_FIFO 0x04
434 
435 /**
436  * enum ath5k_tx_queue - Queue types used to classify tx queues.
437  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
438  * @AR5K_TX_QUEUE_DATA: A normal data queue
439  * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
440  * @AR5K_TX_QUEUE_BEACON: The beacon queue
441  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
442  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
443  */
451 };
452 
453 /*
454  * Queue syb-types to classify normal data queues.
455  * These are the 4 Access Categories as defined in
456  * WME spec. 0 is the lowest priority and 4 is the
457  * highest. Normal data that hasn't been classified
458  * goes to the Best Effort AC.
459  */
461  AR5K_WME_AC_BK = 0, /*Background traffic*/
462  AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
463  AR5K_WME_AC_VI, /*Video traffic*/
464  AR5K_WME_AC_VO, /*Voice traffic*/
465 };
466 
467 /*
468  * Queue ID numbers as returned by the hw functions, each number
469  * represents a hw queue. If hw does not support hw queues
470  * (eg 5210) all data goes in one queue. These match
471  * d80211 definitions (net80211/MadWiFi don't use them).
472  */
476  AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
477  AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
478  AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
479  AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
480  AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
483 };
484 
485 /*
486  * Flags to set hw queue's parameters...
487  */
488 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
489 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
490 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
491 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
492 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
493 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
494 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
495 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
496 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
497 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
498 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
499 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
500 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
501 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
502 
503 /*
504  * A struct to hold tx queue's parameters
505  */
509  u16 tqi_flags; /* Tx queue flags (see above) */
510  u32 tqi_aifs; /* Arbitrated Interframe Space */
511  s32 tqi_cw_min; /* Minimum Contention Window */
512  s32 tqi_cw_max; /* Maximum Contention Window */
513  u32 tqi_cbr_period; /* Constant bit rate period */
516  u32 tqi_ready_time; /* Not used */
517 };
518 
519 /*
520  * Transmit packet types.
521  * used on tx control descriptor
522  * TODO: Use them inside base.c corectly
523  */
531 };
532 
533 /*
534  * TX power and TPC settings
535  */
536 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
537  ((0 & 1) << ((_v) + 6)) | \
538  (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
539 )
540 
541 #define AR5K_TXPOWER_CCK(_r, _v) ( \
542  (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
543 )
544 
545 /*
546  * DMA size definitions (2^n+2)
547  */
557 };
558 
559 
560 /****************\
561  RX DEFINITIONS
562 \****************/
563 
564 /*
565  * RX Status descriptor
566  */
577 };
578 
579 #define AR5K_RXERR_CRC 0x01
580 #define AR5K_RXERR_PHY 0x02
581 #define AR5K_RXERR_FIFO 0x04
582 #define AR5K_RXERR_DECRYPT 0x08
583 #define AR5K_RXERR_MIC 0x10
584 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
585 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
586 
587 
588 /*
589  * TSF to TU conversion:
590  *
591  * TSF is a 64bit value in usec (microseconds).
592  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
593  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
594  */
595 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
596 
597 
598 /*******************************\
599  GAIN OPTIMIZATION DEFINITIONS
600 \*******************************/
601 
607 };
608 
609 struct ath5k_gain {
617 };
618 
619 /********************\
620  COMMON DEFINITIONS
621 \********************/
622 
623 #define AR5K_SLOT_TIME_9 396
624 #define AR5K_SLOT_TIME_20 880
625 #define AR5K_SLOT_TIME_MAX 0xffff
626 
627 /* channel_flags */
628 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
629 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
630 #define CHANNEL_CCK 0x0020 /* CCK channel */
631 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
632 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
633 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
634 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
635 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
636 #define CHANNEL_XR 0x0800 /* XR channel */
637 
638 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
639 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
640 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
641 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
642 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
643 #define CHANNEL_108A CHANNEL_T
644 #define CHANNEL_108G CHANNEL_TG
645 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
646 
647 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
648  CHANNEL_TURBO)
649 
650 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
651 #define CHANNEL_MODES CHANNEL_ALL
652 
653 /*
654  * Used internaly for reset_tx_queue).
655  * Also see struct struct net80211_channel.
656  */
657 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
658 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
659 
660 /*
661  * The following structure is used to map 2GHz channels to
662  * 5GHz Atheros channels.
663  * TODO: Clean up
664  */
668 };
669 
670 
671 /******************\
672  RATE DEFINITIONS
673 \******************/
674 
675 /**
676  * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
677  *
678  * The rate code is used to get the RX rate or set the TX rate on the
679  * hardware descriptors. It is also used for internal modulation control
680  * and settings.
681  *
682  * This is the hardware rate map we are aware of:
683  *
684  * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
685  * rate_kbps 3000 1000 ? ? ? 2000 500 48000
686  *
687  * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
688  * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
689  *
690  * rate_code 17 18 19 20 21 22 23 24
691  * rate_kbps ? ? ? ? ? ? ? 11000
692  *
693  * rate_code 25 26 27 28 29 30 31 32
694  * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
695  *
696  * "S" indicates CCK rates with short preamble.
697  *
698  * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
699  * lowest 4 bits, so they are the same as below with a 0xF mask.
700  * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
701  * We handle this in ath5k_setup_bands().
702  */
703 #define AR5K_MAX_RATES 32
704 
705 /* B */
706 #define ATH5K_RATE_CODE_1M 0x1B
707 #define ATH5K_RATE_CODE_2M 0x1A
708 #define ATH5K_RATE_CODE_5_5M 0x19
709 #define ATH5K_RATE_CODE_11M 0x18
710 /* A and G */
711 #define ATH5K_RATE_CODE_6M 0x0B
712 #define ATH5K_RATE_CODE_9M 0x0F
713 #define ATH5K_RATE_CODE_12M 0x0A
714 #define ATH5K_RATE_CODE_18M 0x0E
715 #define ATH5K_RATE_CODE_24M 0x09
716 #define ATH5K_RATE_CODE_36M 0x0D
717 #define ATH5K_RATE_CODE_48M 0x08
718 #define ATH5K_RATE_CODE_54M 0x0C
719 /* XR */
720 #define ATH5K_RATE_CODE_XR_500K 0x07
721 #define ATH5K_RATE_CODE_XR_1M 0x02
722 #define ATH5K_RATE_CODE_XR_2M 0x06
723 #define ATH5K_RATE_CODE_XR_3M 0x01
724 
725 /* adding this flag to rate_code enables short preamble */
726 #define AR5K_SET_SHORT_PREAMBLE 0x04
727 
728 /*
729  * Crypto definitions
730  */
731 
732 #define AR5K_KEYCACHE_SIZE 8
733 
734 /***********************\
735  HW RELATED DEFINITIONS
736 \***********************/
737 
738 /*
739  * Misc definitions
740  */
741 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
742 
743 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
744  if (_e >= _s) \
745  return 0; \
746 } while (0)
747 
748 /*
749  * Hardware interrupt abstraction
750  */
751 
752 /**
753  * enum ath5k_int - Hardware interrupt masks helpers
754  *
755  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
756  * AR5K_ISR_RXOK or AR5K_ISR_RXERR
757  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
758  * @AR5K_INT_RXNOFRM: No frame received (?)
759  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
760  * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
761  * LinkPtr is NULL. For more details, refer to:
762  * http://www.freepatentsonline.com/20030225739.html
763  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
764  * Note that Rx overrun is not always fatal, on some chips we can continue
765  * operation without reseting the card, that's why int_fatal is not
766  * common for all chips.
767  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
768  * AR5K_ISR_TXOK or AR5K_ISR_TXERR
769  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
770  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
771  * We currently do increments on interrupt by
772  * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
773  * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
774  * checked. We should do this with ath5k_hw_update_mib_counters() but
775  * it seems we should also then do some noise immunity work.
776  * @AR5K_INT_RXPHY: RX PHY Error
777  * @AR5K_INT_RXKCM: RX Key cache miss
778  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
779  * beacon that must be handled in software. The alternative is if you
780  * have VEOL support, in that case you let the hardware deal with things.
781  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
782  * beacons from the AP have associated with, we should probably try to
783  * reassociate. When in IBSS mode this might mean we have not received
784  * any beacons from any local stations. Note that every station in an
785  * IBSS schedules to send beacons at the Target Beacon Transmission Time
786  * (TBTT) with a random backoff.
787  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
788  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
789  * until properly handled
790  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
791  * errors. These types of errors we can enable seem to be of type
792  * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
793  * @AR5K_INT_GLOBAL: Used to clear and set the IER
794  * @AR5K_INT_NOCARD: signals the card has been removed
795  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
796  * bit value
797  *
798  * These are mapped to take advantage of some common bits
799  * between the MACs, to be able to set intr properties
800  * easier. Some of them are not used yet inside hw.c. Most map
801  * to the respective hw interrupt value as they are common amogst different
802  * MACs.
803  */
804 enum ath5k_int {
805  AR5K_INT_RXOK = 0x00000001,
806  AR5K_INT_RXDESC = 0x00000002,
807  AR5K_INT_RXERR = 0x00000004,
808  AR5K_INT_RXNOFRM = 0x00000008,
809  AR5K_INT_RXEOL = 0x00000010,
810  AR5K_INT_RXORN = 0x00000020,
811  AR5K_INT_TXOK = 0x00000040,
812  AR5K_INT_TXDESC = 0x00000080,
813  AR5K_INT_TXERR = 0x00000100,
814  AR5K_INT_TXNOFRM = 0x00000200,
815  AR5K_INT_TXEOL = 0x00000400,
816  AR5K_INT_TXURN = 0x00000800,
817  AR5K_INT_MIB = 0x00001000,
818  AR5K_INT_SWI = 0x00002000,
819  AR5K_INT_RXPHY = 0x00004000,
820  AR5K_INT_RXKCM = 0x00008000,
821  AR5K_INT_SWBA = 0x00010000,
822  AR5K_INT_BRSSI = 0x00020000,
823  AR5K_INT_BMISS = 0x00040000,
824  AR5K_INT_FATAL = 0x00080000, /* Non common */
825  AR5K_INT_BNR = 0x00100000, /* Non common */
826  AR5K_INT_TIM = 0x00200000, /* Non common */
827  AR5K_INT_DTIM = 0x00400000, /* Non common */
828  AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
829  AR5K_INT_GPIO = 0x01000000,
830  AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
831  AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
832  AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
833  AR5K_INT_QCBRORN = 0x10000000, /* Non common */
834  AR5K_INT_QCBRURN = 0x20000000, /* Non common */
835  AR5K_INT_QTRIG = 0x40000000, /* Non common */
836  AR5K_INT_GLOBAL = 0x80000000,
837 
844  | AR5K_INT_TXOK
850  | AR5K_INT_MIB
851  | AR5K_INT_SWI
854  | AR5K_INT_SWBA
857  | AR5K_INT_GPIO
858  | AR5K_INT_GLOBAL,
859 
860  AR5K_INT_NOCARD = 0xffffffff
861 };
862 
863 /*
864  * Power management
865  */
872 };
873 
874 /* GPIO-controlled software LED */
875 #define AR5K_SOFTLED_PIN 0
876 #define AR5K_SOFTLED_ON 0
877 #define AR5K_SOFTLED_OFF 1
878 
879 /*
880  * Chipset capabilities -see ath5k_hw_get_capability-
881  * get_capability function is not yet fully implemented
882  * in ath5k so most of these don't work yet...
883  * TODO: Implement these & merge with _TUNE_ stuff above
884  */
886  AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
887  AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
888  AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
889  AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
890  AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
891  AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
892  AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
893  AR5K_CAP_COMPRESSION = 8, /* Supports compression */
894  AR5K_CAP_BURST = 9, /* Supports packet bursting */
895  AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
896  AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
897  AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
898  AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
899  AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
900  AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
901  AR5K_CAP_XR = 16, /* Supports XR mode */
902  AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
903  AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
904  AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
905  AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
906 };
907 
908 
909 /* XXX: we *may* move cap_range stuff to struct wiphy */
911  /*
912  * Supported PHY modes
913  * (ie. CHANNEL_A, CHANNEL_B, ...)
914  */
916 
917  /*
918  * Frequency range (without regulation restrictions)
919  */
920  struct {
925  } cap_range;
926 
927  /*
928  * Values stored in the EEPROM (some of them...)
929  */
931 
932  /*
933  * Queue information
934  */
935  struct {
937  } cap_queues;
938 };
939 
940 
941 /***************************************\
942  HARDWARE ABSTRACTION LAYER STRUCTURE
943 \***************************************/
944 
945 /*
946  * Misc defines
947  */
948 
949 #define AR5K_MAX_GPIO 10
950 #define AR5K_MAX_RF_BANKS 8
951 
952 /* TODO: Clean up and merge with ath5k_softc */
953 struct ath5k_hw {
955  void *ah_iobase;
956 
958  int ah_ier;
959 
961  int ah_turbo;
966 
973 
977 
978  int ah_5ghz;
979  int ah_2ghz;
980 
981 #define ah_regdomain ah_capabilities.cap_regdomain.reg_current
982 #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
983 #define ah_modes ah_capabilities.cap_mode
984 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
985 
992 
995 
997 
998  /* Current BSSID we are trying to assoc to / create.
999  * This is passed by mac80211 on config_interface() and cached here for
1000  * use in resets */
1003 
1006 
1008 
1026 
1027 
1028  struct {
1029  /* Temporary tables used for interpolation */
1037  int txp_tpc;
1038  /* Values in 0.25dB units */
1043  /* Values in dB units */
1046  } ah_txpower;
1047 
1048  /* noise floor from last periodic calibration */
1050 
1051  /*
1052  * Function pointers
1053  */
1054  int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1055  u32 size, unsigned int flags);
1056  int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1057  unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1058  unsigned int, unsigned int, unsigned int, unsigned int,
1059  unsigned int, unsigned int, unsigned int);
1060  int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1061  struct ath5k_tx_status *);
1062  int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1063  struct ath5k_rx_status *);
1064 };
1065 
1066 /*
1067  * Prototypes
1068  */
1069 
1070 extern int ath5k_bitrate_to_hw_rix(int bitrate);
1071 
1072 /* Attach/Detach Functions */
1073 extern int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah);
1074 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1075 
1076 /* LED functions */
1077 extern int ath5k_init_leds(struct ath5k_softc *sc);
1078 extern void ath5k_led_enable(struct ath5k_softc *sc);
1079 extern void ath5k_led_off(struct ath5k_softc *sc);
1080 extern void ath5k_unregister_leds(struct ath5k_softc *sc);
1081 
1082 /* Reset Functions */
1083 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial);
1084 extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel);
1085 /* Power management functions */
1086 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration);
1087 
1088 /* DMA Related Functions */
1089 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1090 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1091 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1092 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1093 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1094 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1095 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1096 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1097  u32 phys_addr);
1098 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase);
1099 /* Interrupt handling */
1100 extern int ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1101 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1102 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1103 
1104 /* EEPROM access functions */
1105 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1106 extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
1107 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1108 extern int ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
1109 
1110 /* Protocol Control Unit Functions */
1111 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1112 /* BSSID Functions */
1113 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1114 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1115 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1116 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1117 /* Receive start/stop functions */
1118 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1119 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1120 /* RX Filter functions */
1121 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1122 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1123 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1124 /* ACK bit rate */
1125 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high);
1126 /* ACK/CTS Timeouts */
1127 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1128 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1129 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1130 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1131 /* Key table (WEP) functions */
1132 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1133 
1134 /* Queue Control Unit, DFS Control Unit Functions */
1135 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info);
1136 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1137  enum ath5k_tx_queue queue_type,
1138  struct ath5k_txq_info *queue_info);
1139 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah);
1140 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah);
1141 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah);
1142 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1143 
1144 /* Hardware Descriptor Functions */
1145 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1146 
1147 /* GPIO Functions */
1148 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1149 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1150 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1151 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1152 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1153 
1154 /* rfkill Functions */
1155 extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1156 extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1157 
1158 /* Misc functions */
1160 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1161 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1162 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1163 
1164 /* Initial register settings functions */
1165 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel);
1166 
1167 /* Initialize RF */
1168 extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1169  struct net80211_channel *channel,
1170  unsigned int mode);
1171 extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1172 extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1173 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1174 /* PHY/RF channel functions */
1175 extern int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1176 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel);
1177 /* PHY calibration */
1178 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel);
1179 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1180 /* Misc PHY functions */
1181 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1182 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1183 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1184 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1185 /* TX power setup */
1186 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower);
1187 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
1188 
1189 /*
1190  * Functions used internaly
1191  */
1192 
1193 /*
1194  * Translate usec to hw clock units
1195  * TODO: Half/quarter rate
1196  */
1197 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
1198 {
1199  return turbo ? (usec * 80) : (usec * 40);
1200 }
1201 
1202 /*
1203  * Translate hw clock units to usec
1204  * TODO: Half/quarter rate
1205  */
1206 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo)
1207 {
1208  return turbo ? (clock / 80) : (clock / 40);
1209 }
1210 
1211 /*
1212  * Read from a register
1213  */
1214 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1215 {
1216  return readl(ah->ah_iobase + reg);
1217 }
1218 
1219 /*
1220  * Write to a register
1221  */
1222 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1223 {
1224  writel(val, ah->ah_iobase + reg);
1225 }
1226 
1227 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1228 /*
1229  * Check if a register write has been completed
1230  */
1231 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1232  u32 val, int is_set)
1233 {
1234  int i;
1235  u32 data;
1236 
1237  for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1239  if (is_set && (data & flag))
1240  break;
1241  else if ((data & flag) == val)
1242  break;
1243  udelay(15);
1244  }
1245 
1246  return (i <= 0) ? -EAGAIN : 0;
1247 }
1248 
1249 /*
1250  * Convert channel frequency to channel number
1251  */
1252 static inline int ath5k_freq_to_channel(int freq)
1253 {
1254  if (freq == 2484)
1255  return 14;
1256 
1257  if (freq < 2484)
1258  return (freq - 2407) / 5;
1259 
1260  return freq/5 - 1000;
1261 }
1262 
1263 #endif
1264 
1265 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1266 {
1267  u32 retval = 0, bit, i;
1268 
1269  for (i = 0; i < bits; i++) {
1270  bit = (val >> i) & 1;
1271  retval = (retval << 1) | bit;
1272  }
1273 
1274  return retval;
1275 }
1276 
1277 #endif
int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id)
u16 range_5ghz_max
Definition: ath5k.h:924
uint16_t u16
Definition: stdint.h:21
int8_t s8
Definition: stdint.h:18
#define __attribute__(x)
Definition: compiler.h:10
u32 ah_txq_status
Definition: ath5k.h:1010
struct ath5k_capabilities ah_capabilities
Definition: ath5k.h:1007
void ath5k_unregister_leds(struct ath5k_softc *sc)
u32 * ah_rf_banks
Definition: ath5k.h:1021
iPXE I/O API
u8 g_low
Definition: ath5k.h:613
int16_t s16
Definition: stdint.h:20
void ath5k_led_enable(struct ath5k_softc *sc)
int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
Definition: ath5k_pcu.c:130
void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
ath5k_hw_get_lladdr - Get station id
Definition: ath5k_pcu.c:187
int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
ath5k_hw_stop_rx_dma - Stop DMA receive
Definition: ath5k_dma.c:65
u32 ah_txq_isr
Definition: ath5k.h:1020
int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
int(* ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)
Definition: ath5k.h:1056
int(* ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, struct ath5k_tx_status *)
Definition: ath5k.h:1060
int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
Definition: ath5k_pcu.c:496
u16 range_2ghz_max
Definition: ath5k.h:922
static unsigned int unsigned int bit
Definition: bigint.h:205
unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
Definition: ath5k_pcu.c:118
u16 ah_mac_version
Definition: ath5k.h:968
u8 g_high
Definition: ath5k.h:614
int ath5k_bitrate_to_hw_rix(int bitrate)
Definition: ath5k.c:718
const char * sr_name
Definition: ath5k.h:281
int32_t s32
Definition: stdint.h:22
u32 ah_txq_imr_qtrig
Definition: ath5k.h:1018
UINT8_t filter
Receive packet filter.
Definition: pxe_api.h:68
Error codes.
u16 txp_rates_power_table[AR5K_MAX_RATES]
Definition: ath5k.h:1035
u8 ts_retry[4]
Definition: ath5k.h:421
int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
ath5k_hw_set_lladdr - Set station id
Definition: ath5k_pcu.c:200
int ath5k_hw_phy_disable(struct ath5k_hw *ah)
Definition: ath5k_phy.c:1358
unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
Definition: ath5k_pcu.c:147
u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
Definition: ath5k_phy.c:1372
u32 ah_txq_imr_txeol
Definition: ath5k.h:1015
static u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
Definition: ath5k.h:1265
ath5k_version
Definition: ath5k.h:253
void ath5k_rfkill_hw_stop(struct ath5k_hw *ah)
Definition: ath5k_rfkill.c:97
int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
Definition: ath5k_gpio.c:49
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower)
Definition: ath5k_phy.c:2572
ath5k_capability_type
Definition: ath5k.h:885
u32 ah_cw_min
Definition: ath5k.h:988
u16 rs_tstamp
Definition: ath5k.h:569
#define AR5K_MAX_RF_BANKS
Definition: ath5k.h:950
int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
Definition: ath5k_dma.c:292
u8 ah_offset[AR5K_MAX_RF_BANKS]
Definition: ath5k.h:1025
unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
Definition: ath5k_phy.c:1422
u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
Definition: ath5k_dma.c:261
int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
Definition: ath5k_qcu.c:34
struct ath5k_capabilities::@11 cap_queues
enum ath5k_int ah_imr
Definition: ath5k.h:957
u8 g_target
Definition: ath5k.h:612
struct ath5k_softc * ah_sc
Definition: ath5k.h:954
void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level)
Definition: ath5k_gpio.c:98
int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
Definition: ath5k_phy.c:452
void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high)
ath5k_hw_set_ack_bitrate - set bitrate for ACKs
Definition: ath5k_pcu.c:95
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
u16 ts_tstamp
Definition: ath5k.h:418
u16 ah_phy_revision
Definition: ath5k.h:970
enum ath5k_radio ah_radio
Definition: ath5k.h:975
int ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
u32 ah_phy
Definition: ath5k.h:976
u8 txp_min_idx
Definition: ath5k.h:1036
u32 ah_cw_max
Definition: ath5k.h:989
int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:97
void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
ath5k_hw_set_associd - Set BSSID for association
Definition: ath5k_pcu.c:228
u16 ah_radio_5ghz_revision
Definition: ath5k.h:971
void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
ath5k_hw_start_rx_dma - Start DMA receive
Definition: ath5k_dma.c:54
int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
Definition: ath5k_desc.c:522
u32 ah_txq_imr_txurn
Definition: ath5k.h:1013
int(* ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc, u32 size, unsigned int flags)
Definition: ath5k.h:1054
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
size_t ah_rf_regs_count
Definition: ath5k.h:1023
void ath5k_rfkill_hw_start(struct ath5k_hw *ah)
Definition: ath5k_rfkill.c:80
struct ath5k_eeprom_info cap_eeprom
Definition: ath5k.h:930
u32 tqi_burst_time
Definition: ath5k.h:515
void ath5k_led_off(struct ath5k_softc *sc)
#define AR5K_EEPROM_N_PD_GAINS
Definition: eeprom.h:207
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR5K_EEPROM_POWER_TABLE_SIZE
Definition: eeprom.h:215
int ah_5ghz
Definition: ath5k.h:978
u16 range_2ghz_min
Definition: ath5k.h:921
s16 txp_max_pwr
Definition: ath5k.h:1040
int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
Definition: ath5k_phy.c:1127
int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
Definition: ath5k_dma.c:127
int ah_ant_diversity
Definition: ath5k.h:994
int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
Definition: ath5k_phy.c:830
int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode)
Definition: ath5k_phy.c:514
int result
Definition: bigint.h:148
u32 ah_limit_tx_retries
Definition: ath5k.h:991
ath5k_power_mode
Definition: ath5k.h:866
u32 tqi_cbr_period
Definition: ath5k.h:513
void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
ath5k_hw_set_rx_filter - Set rx filter
Definition: ath5k_pcu.c:453
u16 capability
Capability flags.
Definition: ieee80211.h:1036
u32 ah_txq_imr_txerr
Definition: ath5k.h:1012
int ah_calibration
Definition: ath5k.h:962
u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
ath5k_hw_get_rx_filter - Get current rx filter
Definition: ath5k_pcu.c:424
unsigned sr_val
Definition: ath5k.h:283
struct ath5k_gain ah_gain
Definition: ath5k.h:1024
int ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
ath5k_hw_is_intr_pending - Check if we have pending interrupts
Definition: ath5k_dma.c:391
static unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
Definition: ath5k.h:1197
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
ath5k_tx_queue_id
Definition: ath5k.h:473
void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
ath5k_hw_set_rxdp - Set RX Descriptor's address
Definition: ath5k_dma.c:102
ath5k_tx_queue
enum ath5k_tx_queue - Queue types used to classify tx queues.
Definition: ath5k.h:444
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
u8 ts_rate[4]
Definition: ath5k.h:420
int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
Definition: ath5k_caps.c:36
int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel)
Definition: ath5k_reset.c:690
u8 g_f_corr
Definition: ath5k.h:615
int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
Definition: ath5k_phy.c:1048
s16 txp_cck_ofdm_gainf_delta
Definition: ath5k.h:1045
u8 ah_bssid[ETH_ALEN]
Definition: ath5k.h:1001
u32 ah_txq_imr_cbrorn
Definition: ath5k.h:1016
#define AR5K_EEPROM_N_MODES
Definition: eeprom.h:179
void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
ath5k_hw_start_rx_pcu - Start RX engine
Definition: ath5k_pcu.c:384
struct ath5k_capabilities::@10 cap_range
s16 txp_cck_ofdm_pwr_delta
Definition: ath5k.h:1044
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
ath5k_rfgain
Definition: ath5k.h:602
u32 ah_atim_window
Definition: ath5k.h:986
int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
Definition: ath5k_phy.c:158
int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
Definition: ath5k_gpio.c:34
enum ath5k_tx_queue tqi_type
Definition: ath5k.h:507
u32 tqi_cbr_overflow_limit
Definition: ath5k.h:514
int ah_combined_mic
Definition: ath5k.h:965
enum ath5k_tx_queue_subtype tqi_subtype
Definition: ath5k.h:508
#define AR5K_TUNE_REGISTER_TIMEOUT
Definition: ath5k.h:169
FILE_LICENCE(MIT)
enum ath5k_version ah_version
Definition: ath5k.h:974
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
The iPXE 802.11 MAC layer.
static unsigned int unsigned int reg
Definition: intel.h:245
void ath5k_hw_release_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:86
u32 tqi_aifs
Definition: ath5k.h:510
ath5k_srev_type
Definition: ath5k.h:275
s32 tqi_cw_max
Definition: ath5k.h:512
An 802.11 RF channel.
Definition: net80211.h:385
int ah_ier
Definition: ath5k.h:958
s16 txp_min_pwr
Definition: ath5k.h:1039
int ah_single_chip
Definition: ath5k.h:964
enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
ath5k_hw_set_imr - Set interrupt mask
Definition: ath5k_dma.c:548
u32 ah_txq_imr_txdesc
Definition: ath5k.h:1014
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
u8 ts_longretry
Definition: ath5k.h:425
u16 ah_mac_revision
Definition: ath5k.h:969
u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah)
void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
at5k_hw_stop_rx_pcu - Stop RX engine
Definition: ath5k_pcu.c:398
#define ETH_ALEN
Definition: if_ether.h:8
void ath5k_eeprom_detach(struct ath5k_hw *ah)
int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial)
Definition: ath5k_reset.c:282
u16 ah_radio_2ghz_revision
Definition: ath5k.h:972
struct ath5k_txq_info ah_txq
Definition: ath5k.h:1009
int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
Definition: ath5k_pcu.c:159
#define EAGAIN
Resource temporarily unavailable.
Definition: errno.h:318
int ah_running
Definition: ath5k.h:963
int ah_turbo
Definition: ath5k.h:961
u32 ah_txq_imr_txok
Definition: ath5k.h:1011
u8 ah_sta_id[ETH_ALEN]
Definition: ath5k.h:996
static unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo)
Definition: ath5k.h:1206
void __asmcall int val
Definition: setjmp.h:28
int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
Definition: ath5k_dma.c:412
ath5k_dmasize
Definition: ath5k.h:548
int(* ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, struct ath5k_rx_status *)
Definition: ath5k.h:1062
int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah)
ath5k_hw_attach - Check if hw is supported and init the needed structs
Definition: ath5k_attach.c:112
unsigned long retval
Definition: xen.h:45
u16 bitrate
Definition: ath5k.c:93
Network device management.
size_t ah_rf_banks_size
Definition: ath5k.h:1022
u8 g_current
Definition: ath5k.h:611
int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
Definition: ath5k_qcu.c:377
int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
Definition: ath5k_gpio.c:77
s16 txp_ofdm
Definition: ath5k.h:1042
int ath5k_hw_set_opmode(struct ath5k_hw *ah)
ath5k_hw_set_opmode - Set PCU operating mode
Definition: ath5k_pcu.c:48
static volatile void * bits
Definition: bitops.h:27
u8 tmpR[AR5K_EEPROM_N_PD_GAINS][AR5K_EEPROM_POWER_TABLE_SIZE]
Definition: ath5k.h:1033
int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
ath5k_hw_set_bssid_mask - filter out bssids we listen
Definition: ath5k_pcu.c:348
u16 ts_seqnum
Definition: ath5k.h:417
u8 g_step_idx
Definition: ath5k.h:610
struct ath5k_hw::@12 ah_txpower
void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
Definition: ath5k_pcu.c:406
struct net80211_channel * ah_current_channel
Definition: ath5k.h:960
void * ah_iobase
Definition: ath5k.h:955
int ah_2ghz
Definition: ath5k.h:979
u32 ah_txq_imr_nofrm
Definition: ath5k.h:1019
u16 tqi_flags
Definition: ath5k.h:509
u8 ah_bssid_mask[ETH_ALEN]
Definition: ath5k.h:1002
int txp_tpc
Definition: ath5k.h:1037
s32 tqi_cw_min
Definition: ath5k.h:511
u32 ah_gpio[AR5K_MAX_GPIO]
Definition: ath5k.h:1004
int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase)
ath5k_hw_update_tx_triglevel - Update tx trigger level
Definition: ath5k_dma.c:339
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
ath5k_radio
Definition: ath5k.h:260
u32 tqi_ready_time
Definition: ath5k.h:516
u16 range_5ghz_min
Definition: ath5k.h:923
int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
int ah_gpio_npins
Definition: ath5k.h:1005
enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
Definition: ath5k_phy.c:389
ath5k_tx_queue_subtype
Definition: ath5k.h:460
void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
Definition: ath5k_phy.c:1416
ath5k_pkt_type
Definition: ath5k.h:524
uint8_t ah
Definition: registers.h:85
s16 txp_offset
Definition: ath5k.h:1041
void timeout(int)
s32 ah_noise_floor
Definition: ath5k.h:1049
u32 ah_aifs
Definition: ath5k.h:987
uint32_t high
High 32 bits of address.
Definition: intel.h:22
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
enum ath5k_srev_type sr_type
Definition: ath5k.h:282
u32 ah_mac_srev
Definition: ath5k.h:967
#define AR5K_MAX_RATES
Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
Definition: ath5k.h:703
u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE *2]
Definition: ath5k.h:1034
int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower)
Definition: ath5k_phy.c:2474
uint16_t queue
Queue ID.
Definition: ena.h:22
ath5k_driver_mode
Definition: ath5k.h:391
u16 rs_datalen
Definition: ath5k.h:568
int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
Definition: ath5k_dma.c:167
int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result)
Definition: ath5k_caps.c:115
#define AR5K_MAX_GPIO
Definition: ath5k.h:949
int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
int ath5k_eeprom_init(struct ath5k_hw *ah)
u8 ts_shortretry
Definition: ath5k.h:424
int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel)
Definition: ath5k_phy.c:1345
u8 g_state
Definition: ath5k.h:616
void ath5k_hw_detach(struct ath5k_hw *ah)
ath5k_hw_detach - Free the ath5k_hw struct
Definition: ath5k_attach.c:335
u8 ts_final_idx
Definition: ath5k.h:422
u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
Definition: ath5k_gpio.c:64
uint8_t u8
Definition: stdint.h:19
u8 tmpL[AR5K_EEPROM_N_PD_GAINS][AR5K_EEPROM_POWER_TABLE_SIZE]
Definition: ath5k.h:1031
ath5k_int
enum ath5k_int - Hardware interrupt masks helpers
Definition: ath5k.h:804
u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]
Definition: ath5k.h:993
uint32_t u32
Definition: stdint.h:23
int ath5k_init_leds(struct ath5k_softc *sc)
int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
Definition: ath5k_qcu.c:55
uint16_t flag
Flag number.
Definition: hyperv.h:14
u32 ah_txq_imr_cbrurn
Definition: ath5k.h:1017
int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration)
uint8_t flags
Flags.
Definition: ena.h:18
u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
ath5k_hw_get_rxdp - Get RX Descriptor's address
Definition: ath5k_dma.c:89
int ah_software_retry
Definition: ath5k.h:990