iPXE
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#include <stddef.h>
#include <byteswap.h>
#include <ipxe/io.h>
#include <ipxe/netdevice.h>
#include <ipxe/net80211.h>
#include <errno.h>
#include "desc.h"
#include "eeprom.h"
Go to the source code of this file.
Data Structures | |
struct | ath5k_srev_name |
struct | ath5k_tx_status |
struct | ath5k_txq_info |
struct | ath5k_rx_status |
struct | ath5k_gain |
struct | ath5k_athchan_2ghz |
struct | ath5k_capabilities |
struct | ath5k_hw |
ath5k_hw_get_isr - Get interrupt status More... | |
Macros | |
#define | ERRFILE ERRFILE_ath5k |
#define | PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ |
#define | PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ |
#define | PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ |
#define | PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ |
#define | PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ |
#define | AR5K_REG_SM(_val, _flags) (((_val) << _flags##_S) & (_flags)) |
#define | AR5K_REG_MS(_val, _flags) (((_val) & (_flags)) >> _flags##_S) |
#define | AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) |
#define | AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) |
#define | AR5K_REG_ENABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) |
#define | AR5K_REG_DISABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) |
#define | AR5K_PHY_READ(ah, _reg) ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) |
#define | AR5K_PHY_WRITE(ah, _reg, _val) ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) |
#define | AR5K_REG_READ_Q(ah, _reg, _queue) (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ |
#define | AR5K_REG_WRITE_Q(ah, _reg, _queue) ath5k_hw_reg_write(ah, (1 << _queue), _reg) |
#define | AR5K_Q_ENABLE_BITS(_reg, _queue) |
#define | AR5K_Q_DISABLE_BITS(_reg, _queue) |
#define | AR5K_REG_WAIT(_i) |
#define | AR5K_INI_RFGAIN_5GHZ 0 |
#define | AR5K_INI_RFGAIN_2GHZ 1 |
#define | AR5K_INI_VAL_11A 0 |
#define | AR5K_INI_VAL_11A_TURBO 1 |
#define | AR5K_INI_VAL_11B 2 |
#define | AR5K_INI_VAL_11G 3 |
#define | AR5K_INI_VAL_11G_TURBO 4 |
#define | AR5K_INI_VAL_XR 0 |
#define | AR5K_INI_VAL_MAX 5 |
#define | AR5K_LOW_ID(_a) |
#define | AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) |
#define | IEEE80211_MAX_LEN 2352 |
#define | AR5K_TUNE_DMA_BEACON_RESP 2 |
#define | AR5K_TUNE_SW_BEACON_RESP 10 |
#define | AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 |
#define | AR5K_TUNE_RADAR_ALERT 0 |
#define | AR5K_TUNE_MIN_TX_FIFO_THRES 1 |
#define | AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) |
#define | AR5K_TUNE_REGISTER_TIMEOUT 20000 |
#define | AR5K_TUNE_RSSI_THRES 129 |
#define | AR5K_TUNE_BMISS_THRES 7 |
#define | AR5K_TUNE_REGISTER_DWELL_TIME 20000 |
#define | AR5K_TUNE_BEACON_INTERVAL 100 |
#define | AR5K_TUNE_AIFS 2 |
#define | AR5K_TUNE_AIFS_11B 2 |
#define | AR5K_TUNE_AIFS_XR 0 |
#define | AR5K_TUNE_CWMIN 15 |
#define | AR5K_TUNE_CWMIN_11B 31 |
#define | AR5K_TUNE_CWMIN_XR 3 |
#define | AR5K_TUNE_CWMAX 1023 |
#define | AR5K_TUNE_CWMAX_11B 1023 |
#define | AR5K_TUNE_CWMAX_XR 7 |
#define | AR5K_TUNE_NOISE_FLOOR -72 |
#define | AR5K_TUNE_MAX_TXPOWER 63 |
#define | AR5K_TUNE_DEFAULT_TXPOWER 25 |
#define | AR5K_TUNE_TPC_TXPOWER 0 |
#define | AR5K_TUNE_ANT_DIVERSITY 1 |
#define | AR5K_TUNE_HWTXTRIES 4 |
#define | AR5K_INIT_CARR_SENSE_EN 1 |
#define | AR5K_INIT_CFG 0x00000000 |
#define | AR5K_INIT_CYCRSSI_THR1 2 |
#define | AR5K_INIT_TX_LATENCY 502 |
#define | AR5K_INIT_USEC 39 |
#define | AR5K_INIT_USEC_TURBO 79 |
#define | AR5K_INIT_USEC_32 31 |
#define | AR5K_INIT_SLOT_TIME 396 |
#define | AR5K_INIT_SLOT_TIME_TURBO 480 |
#define | AR5K_INIT_ACK_CTS_TIMEOUT 1024 |
#define | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 |
#define | AR5K_INIT_PROG_IFS 920 |
#define | AR5K_INIT_PROG_IFS_TURBO 960 |
#define | AR5K_INIT_EIFS 3440 |
#define | AR5K_INIT_EIFS_TURBO 6880 |
#define | AR5K_INIT_SIFS 560 |
#define | AR5K_INIT_SIFS_TURBO 480 |
#define | AR5K_INIT_SH_RETRY 10 |
#define | AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY |
#define | AR5K_INIT_SSH_RETRY 32 |
#define | AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY |
#define | AR5K_INIT_TX_RETRY 10 |
#define | AR5K_INIT_TRANSMIT_LATENCY |
#define | AR5K_INIT_TRANSMIT_LATENCY_TURBO |
#define | AR5K_INIT_PROTO_TIME_CNTRL |
#define | AR5K_INIT_PROTO_TIME_CNTRL_TURBO |
#define | AR5K_TXQ_USEDEFAULT ((u32) -1) |
#define | AR5K_SREV_UNKNOWN 0xffff |
#define | AR5K_SREV_AR5210 0x00 /* Crete */ |
#define | AR5K_SREV_AR5311 0x10 /* Maui 1 */ |
#define | AR5K_SREV_AR5311A 0x20 /* Maui 2 */ |
#define | AR5K_SREV_AR5311B 0x30 /* Spirit */ |
#define | AR5K_SREV_AR5211 0x40 /* Oahu */ |
#define | AR5K_SREV_AR5212 0x50 /* Venice */ |
#define | AR5K_SREV_AR5213 0x55 /* ??? */ |
#define | AR5K_SREV_AR5213A 0x59 /* Hainan */ |
#define | AR5K_SREV_AR2413 0x78 /* Griffin lite */ |
#define | AR5K_SREV_AR2414 0x70 /* Griffin */ |
#define | AR5K_SREV_AR5424 0x90 /* Condor */ |
#define | AR5K_SREV_AR5413 0xa4 /* Eagle lite */ |
#define | AR5K_SREV_AR5414 0xa0 /* Eagle */ |
#define | AR5K_SREV_AR2415 0xb0 /* Talon */ |
#define | AR5K_SREV_AR5416 0xc0 /* PCI-E */ |
#define | AR5K_SREV_AR5418 0xca /* PCI-E */ |
#define | AR5K_SREV_AR2425 0xe0 /* Swan */ |
#define | AR5K_SREV_AR2417 0xf0 /* Nala */ |
#define | AR5K_SREV_RAD_5110 0x00 |
#define | AR5K_SREV_RAD_5111 0x10 |
#define | AR5K_SREV_RAD_5111A 0x15 |
#define | AR5K_SREV_RAD_2111 0x20 |
#define | AR5K_SREV_RAD_5112 0x30 |
#define | AR5K_SREV_RAD_5112A 0x35 |
#define | AR5K_SREV_RAD_5112B 0x36 |
#define | AR5K_SREV_RAD_2112 0x40 |
#define | AR5K_SREV_RAD_2112A 0x45 |
#define | AR5K_SREV_RAD_2112B 0x46 |
#define | AR5K_SREV_RAD_2413 0x50 |
#define | AR5K_SREV_RAD_5413 0x60 |
#define | AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ |
#define | AR5K_SREV_RAD_2317 0x80 |
#define | AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ |
#define | AR5K_SREV_RAD_2425 0xa2 |
#define | AR5K_SREV_RAD_5133 0xc0 |
#define | AR5K_SREV_PHY_5211 0x30 |
#define | AR5K_SREV_PHY_5212 0x41 |
#define | AR5K_SREV_PHY_5212A 0x42 |
#define | AR5K_SREV_PHY_5212B 0x43 |
#define | AR5K_SREV_PHY_2413 0x45 |
#define | AR5K_SREV_PHY_5413 0x61 |
#define | AR5K_SREV_PHY_2425 0x70 |
#define | MODULATION_XR 0x00000200 |
#define | MODULATION_TURBO 0x00000080 |
#define | AR5K_TXSTAT_ALTRATE 0x80 |
#define | AR5K_TXERR_XRETRY 0x01 |
#define | AR5K_TXERR_FILT 0x02 |
#define | AR5K_TXERR_FIFO 0x04 |
#define | AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ |
#define | AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ |
#define | AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ |
#define | AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ |
#define | AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ |
#define | AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ |
#define | AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ |
#define | AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ |
#define | AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ |
#define | AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ |
#define | AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ |
#define | AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ |
#define | AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ |
#define | AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ |
#define | AR5K_TXPOWER_OFDM(_r, _v) |
#define | AR5K_TXPOWER_CCK(_r, _v) |
#define | AR5K_RXERR_CRC 0x01 |
#define | AR5K_RXERR_PHY 0x02 |
#define | AR5K_RXERR_FIFO 0x04 |
#define | AR5K_RXERR_DECRYPT 0x08 |
#define | AR5K_RXERR_MIC 0x10 |
#define | AR5K_RXKEYIX_INVALID ((u8) - 1) |
#define | AR5K_TXKEYIX_INVALID ((u32) - 1) |
#define | TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) |
#define | AR5K_SLOT_TIME_9 396 |
#define | AR5K_SLOT_TIME_20 880 |
#define | AR5K_SLOT_TIME_MAX 0xffff |
#define | CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ |
#define | CHANNEL_TURBO 0x0010 /* Turbo Channel */ |
#define | CHANNEL_CCK 0x0020 /* CCK channel */ |
#define | CHANNEL_OFDM 0x0040 /* OFDM channel */ |
#define | CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ |
#define | CHANNEL_5GHZ 0x0100 /* 5GHz channel */ |
#define | CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ |
#define | CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ |
#define | CHANNEL_XR 0x0800 /* XR channel */ |
#define | CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
#define | CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
#define | CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
#define | CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
#define | CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
#define | CHANNEL_108A CHANNEL_T |
#define | CHANNEL_108G CHANNEL_TG |
#define | CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) |
#define | CHANNEL_ALL |
#define | CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) |
#define | CHANNEL_MODES CHANNEL_ALL |
#define | IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) |
#define | IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) |
#define | AR5K_MAX_RATES 32 |
Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. More... | |
#define | ATH5K_RATE_CODE_1M 0x1B |
#define | ATH5K_RATE_CODE_2M 0x1A |
#define | ATH5K_RATE_CODE_5_5M 0x19 |
#define | ATH5K_RATE_CODE_11M 0x18 |
#define | ATH5K_RATE_CODE_6M 0x0B |
#define | ATH5K_RATE_CODE_9M 0x0F |
#define | ATH5K_RATE_CODE_12M 0x0A |
#define | ATH5K_RATE_CODE_18M 0x0E |
#define | ATH5K_RATE_CODE_24M 0x09 |
#define | ATH5K_RATE_CODE_36M 0x0D |
#define | ATH5K_RATE_CODE_48M 0x08 |
#define | ATH5K_RATE_CODE_54M 0x0C |
#define | ATH5K_RATE_CODE_XR_500K 0x07 |
#define | ATH5K_RATE_CODE_XR_1M 0x02 |
#define | ATH5K_RATE_CODE_XR_2M 0x06 |
#define | ATH5K_RATE_CODE_XR_3M 0x01 |
#define | AR5K_SET_SHORT_PREAMBLE 0x04 |
#define | AR5K_KEYCACHE_SIZE 8 |
#define | AR5K_RSSI_EP_MULTIPLIER (1<<7) |
#define | AR5K_ASSERT_ENTRY(_e, _s) |
#define | AR5K_SOFTLED_PIN 0 |
#define | AR5K_SOFTLED_ON 0 |
#define | AR5K_SOFTLED_OFF 1 |
#define | AR5K_MAX_GPIO 10 |
#define | AR5K_MAX_RF_BANKS 8 |
#define | ah_regdomain ah_capabilities.cap_regdomain.reg_current |
#define | ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw |
#define | ah_modes ah_capabilities.cap_mode |
#define | ah_ee_version ah_capabilities.cap_eeprom.ee_version |
Functions | |
FILE_LICENCE (MIT) | |
int | ath5k_bitrate_to_hw_rix (int bitrate) |
int | ath5k_hw_attach (struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah) |
ath5k_hw_attach - Check if hw is supported and init the needed structs More... | |
void | ath5k_hw_detach (struct ath5k_hw *ah) |
ath5k_hw_detach - Free the ath5k_hw struct More... | |
int | ath5k_init_leds (struct ath5k_softc *sc) |
void | ath5k_led_enable (struct ath5k_softc *sc) |
void | ath5k_led_off (struct ath5k_softc *sc) |
void | ath5k_unregister_leds (struct ath5k_softc *sc) |
int | ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, int initial) |
int | ath5k_hw_reset (struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel) |
int | ath5k_hw_set_power (struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration) |
void | ath5k_hw_start_rx_dma (struct ath5k_hw *ah) |
ath5k_hw_start_rx_dma - Start DMA receive More... | |
int | ath5k_hw_stop_rx_dma (struct ath5k_hw *ah) |
ath5k_hw_stop_rx_dma - Stop DMA receive More... | |
u32 | ath5k_hw_get_rxdp (struct ath5k_hw *ah) |
ath5k_hw_get_rxdp - Get RX Descriptor's address More... | |
void | ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr) |
ath5k_hw_set_rxdp - Set RX Descriptor's address More... | |
int | ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue More... | |
int | ath5k_hw_stop_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue More... | |
u32 | ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue More... | |
int | ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) |
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue More... | |
int | ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, int increase) |
ath5k_hw_update_tx_triglevel - Update tx trigger level More... | |
int | ath5k_hw_is_intr_pending (struct ath5k_hw *ah) |
ath5k_hw_is_intr_pending - Check if we have pending interrupts More... | |
int | ath5k_hw_get_isr (struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) |
enum ath5k_int | ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask) |
ath5k_hw_set_imr - Set interrupt mask More... | |
int | ath5k_eeprom_init (struct ath5k_hw *ah) |
void | ath5k_eeprom_detach (struct ath5k_hw *ah) |
int | ath5k_eeprom_read_mac (struct ath5k_hw *ah, u8 *mac) |
int | ath5k_eeprom_is_hb63 (struct ath5k_hw *ah) |
int | ath5k_hw_set_opmode (struct ath5k_hw *ah) |
ath5k_hw_set_opmode - Set PCU operating mode More... | |
void | ath5k_hw_get_lladdr (struct ath5k_hw *ah, u8 *mac) |
ath5k_hw_get_lladdr - Get station id More... | |
int | ath5k_hw_set_lladdr (struct ath5k_hw *ah, const u8 *mac) |
ath5k_hw_set_lladdr - Set station id More... | |
void | ath5k_hw_set_associd (struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) |
ath5k_hw_set_associd - Set BSSID for association More... | |
int | ath5k_hw_set_bssid_mask (struct ath5k_hw *ah, const u8 *mask) |
ath5k_hw_set_bssid_mask - filter out bssids we listen More... | |
void | ath5k_hw_start_rx_pcu (struct ath5k_hw *ah) |
ath5k_hw_start_rx_pcu - Start RX engine More... | |
void | ath5k_hw_stop_rx_pcu (struct ath5k_hw *ah) |
at5k_hw_stop_rx_pcu - Stop RX engine More... | |
void | ath5k_hw_set_mcast_filter (struct ath5k_hw *ah, u32 filter0, u32 filter1) |
u32 | ath5k_hw_get_rx_filter (struct ath5k_hw *ah) |
ath5k_hw_get_rx_filter - Get current rx filter More... | |
void | ath5k_hw_set_rx_filter (struct ath5k_hw *ah, u32 filter) |
ath5k_hw_set_rx_filter - Set rx filter More... | |
void | ath5k_hw_set_ack_bitrate_high (struct ath5k_hw *ah, int high) |
ath5k_hw_set_ack_bitrate - set bitrate for ACKs More... | |
int | ath5k_hw_set_ack_timeout (struct ath5k_hw *ah, unsigned int timeout) |
ath5k_hw_set_ack_timeout - Set ACK timeout on PCU More... | |
unsigned int | ath5k_hw_get_ack_timeout (struct ath5k_hw *ah) |
ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec More... | |
int | ath5k_hw_set_cts_timeout (struct ath5k_hw *ah, unsigned int timeout) |
ath5k_hw_set_cts_timeout - Set CTS timeout on PCU More... | |
unsigned int | ath5k_hw_get_cts_timeout (struct ath5k_hw *ah) |
ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec More... | |
int | ath5k_hw_reset_key (struct ath5k_hw *ah, u16 entry) |
int | ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info) |
int | ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) |
u32 | ath5k_hw_num_tx_pending (struct ath5k_hw *ah) |
void | ath5k_hw_release_tx_queue (struct ath5k_hw *ah) |
int | ath5k_hw_reset_tx_queue (struct ath5k_hw *ah) |
int | ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time) |
int | ath5k_hw_init_desc_functions (struct ath5k_hw *ah) |
int | ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio) |
int | ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio) |
u32 | ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio) |
int | ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val) |
void | ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level) |
void | ath5k_rfkill_hw_start (struct ath5k_hw *ah) |
void | ath5k_rfkill_hw_stop (struct ath5k_hw *ah) |
int | ath5k_hw_set_capabilities (struct ath5k_hw *ah) |
int | ath5k_hw_get_capability (struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result) |
int | ath5k_hw_enable_pspoll (struct ath5k_hw *ah, u8 *bssid, u16 assoc_id) |
int | ath5k_hw_disable_pspoll (struct ath5k_hw *ah) |
int | ath5k_hw_write_initvals (struct ath5k_hw *ah, u8 mode, int change_channel) |
int | ath5k_hw_rfregs_init (struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode) |
int | ath5k_hw_rfgain_init (struct ath5k_hw *ah, unsigned int freq) |
enum ath5k_rfgain | ath5k_hw_gainf_calibrate (struct ath5k_hw *ah) |
int | ath5k_hw_rfgain_opt_init (struct ath5k_hw *ah) |
int | ath5k_channel_ok (struct ath5k_hw *ah, u16 freq, unsigned int flags) |
int | ath5k_hw_channel (struct ath5k_hw *ah, struct net80211_channel *channel) |
int | ath5k_hw_phy_calibrate (struct ath5k_hw *ah, struct net80211_channel *channel) |
int | ath5k_hw_noise_floor_calibration (struct ath5k_hw *ah, short freq) |
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration More... | |
u16 | ath5k_hw_radio_revision (struct ath5k_hw *ah, unsigned int chan) |
void | ath5k_hw_set_def_antenna (struct ath5k_hw *ah, unsigned int ant) |
unsigned int | ath5k_hw_get_def_antenna (struct ath5k_hw *ah) |
int | ath5k_hw_phy_disable (struct ath5k_hw *ah) |
int | ath5k_hw_txpower (struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower) |
int | ath5k_hw_set_txpower_limit (struct ath5k_hw *ah, u8 ee_mode, u8 txpower) |
static unsigned int | ath5k_hw_htoclock (unsigned int usec, int turbo) |
static unsigned int | ath5k_hw_clocktoh (unsigned int clock, int turbo) |
static u32 | ath5k_hw_reg_read (struct ath5k_hw *ah, u16 reg) |
static void | ath5k_hw_reg_write (struct ath5k_hw *ah, u32 val, u16 reg) |
static u32 | ath5k_hw_bitswap (u32 val, unsigned int bits) |
#define ERRFILE ERRFILE_ath5k |
#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ |
#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ |
#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ |
#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ |
#define AR5K_REG_SM | ( | _val, | |
_flags | |||
) | (((_val) << _flags##_S) & (_flags)) |
#define AR5K_REG_MS | ( | _val, | |
_flags | |||
) | (((_val) & (_flags)) >> _flags##_S) |
#define AR5K_REG_WRITE_BITS | ( | ah, | |
_reg, | |||
_flags, | |||
_val | |||
) |
#define AR5K_REG_MASKED_BITS | ( | ah, | |
_reg, | |||
_flags, | |||
_mask | |||
) |
#define AR5K_REG_ENABLE_BITS | ( | ah, | |
_reg, | |||
_flags | |||
) | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) |
#define AR5K_REG_DISABLE_BITS | ( | ah, | |
_reg, | |||
_flags | |||
) | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) |
#define AR5K_PHY_READ | ( | ah, | |
_reg | |||
) | ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) |
#define AR5K_PHY_WRITE | ( | ah, | |
_reg, | |||
_val | |||
) | ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) |
#define AR5K_REG_READ_Q | ( | ah, | |
_reg, | |||
_queue | |||
) | (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ |
#define AR5K_REG_WRITE_Q | ( | ah, | |
_reg, | |||
_queue | |||
) | ath5k_hw_reg_write(ah, (1 << _queue), _reg) |
#define AR5K_Q_ENABLE_BITS | ( | _reg, | |
_queue | |||
) |
#define AR5K_Q_DISABLE_BITS | ( | _reg, | |
_queue | |||
) |
#define AR5K_REG_WAIT | ( | _i | ) |
#define AR5K_LOW_ID | ( | _a | ) |
#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) |
#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY |
#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY |
#define AR5K_INIT_TRANSMIT_LATENCY |
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO |
#define AR5K_INIT_PROTO_TIME_CNTRL |
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO |
#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ |
#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ |
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ |
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ |
#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ |
#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ |
#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ |
#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ |
#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ |
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ |
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ |
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ |
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ |
#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ |
#define AR5K_TXPOWER_OFDM | ( | _r, | |
_v | |||
) |
#define AR5K_TXPOWER_CCK | ( | _r, | |
_v | |||
) |
#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ |
#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ |
#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ |
#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
#define CHANNEL_108G CHANNEL_TG |
#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) |
#define CHANNEL_ALL |
#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) |
#define CHANNEL_MODES CHANNEL_ALL |
#define IS_CHAN_XR | ( | _c | ) | ((_c->hw_value & CHANNEL_XR) != 0) |
#define AR5K_MAX_RATES 32 |
Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
The rate code is used to get the RX rate or set the TX rate on the hardware descriptors. It is also used for internal modulation control and settings.
This is the hardware rate map we are aware of:
rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 rate_kbps 3000 1000 ? ? ? 2000 500 48000
rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
rate_code 17 18 19 20 21 22 23 24 rate_kbps ? ? ? ? ? ? ? 11000
rate_code 25 26 27 28 29 30 31 32 rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
"S" indicates CCK rates with short preamble.
AR5211 has different rate codes for CCK (802.11B) rates. It only uses the lowest 4 bits, so they are the same as below with a 0xF mask. (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). We handle this in ath5k_setup_bands().
#define AR5K_ASSERT_ENTRY | ( | _e, | |
_s | |||
) |
#define ah_regdomain ah_capabilities.cap_regdomain.reg_current |
#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw |
enum ath5k_version |
Enumerator | |
---|---|
AR5K_AR5210 | |
AR5K_AR5211 | |
AR5K_AR5212 |
enum ath5k_radio |
Enumerator | |
---|---|
AR5K_RF5110 | |
AR5K_RF5111 | |
AR5K_RF5112 | |
AR5K_RF2413 | |
AR5K_RF5413 | |
AR5K_RF2316 | |
AR5K_RF2317 | |
AR5K_RF2425 |
Definition at line 260 of file ath5k.h.
enum ath5k_srev_type |
Enumerator | |
---|---|
AR5K_VERSION_MAC | |
AR5K_VERSION_RAD |
Definition at line 275 of file ath5k.h.
enum ath5k_driver_mode |
Enumerator | |
---|---|
AR5K_MODE_11A | |
AR5K_MODE_11A_TURBO | |
AR5K_MODE_11B | |
AR5K_MODE_11G | |
AR5K_MODE_11G_TURBO | |
AR5K_MODE_XR |
Definition at line 391 of file ath5k.h.
anonymous enum |
Enumerator | |
---|---|
AR5K_MODE_BIT_11A | |
AR5K_MODE_BIT_11A_TURBO | |
AR5K_MODE_BIT_11B | |
AR5K_MODE_BIT_11G | |
AR5K_MODE_BIT_11G_TURBO | |
AR5K_MODE_BIT_XR |
Definition at line 400 of file ath5k.h.
enum ath5k_tx_queue |
enum ath5k_tx_queue - Queue types used to classify tx queues.
@AR5K_TX_QUEUE_INACTIVE: q is unused – see ath5k_hw_release_tx_queue @AR5K_TX_QUEUE_DATA: A normal data queue @AR5K_TX_QUEUE_XR_DATA: An XR-data queue @AR5K_TX_QUEUE_BEACON: The beacon queue @AR5K_TX_QUEUE_CAB: The after-beacon queue @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
Enumerator | |
---|---|
AR5K_TX_QUEUE_INACTIVE | |
AR5K_TX_QUEUE_DATA | |
AR5K_TX_QUEUE_XR_DATA | |
AR5K_TX_QUEUE_BEACON | |
AR5K_TX_QUEUE_CAB | |
AR5K_TX_QUEUE_UAPSD |
Definition at line 444 of file ath5k.h.
Enumerator | |
---|---|
AR5K_WME_AC_BK | |
AR5K_WME_AC_BE | |
AR5K_WME_AC_VI | |
AR5K_WME_AC_VO |
enum ath5k_tx_queue_id |
Definition at line 473 of file ath5k.h.
enum ath5k_pkt_type |
Enumerator | |
---|---|
AR5K_PKT_TYPE_NORMAL | |
AR5K_PKT_TYPE_ATIM | |
AR5K_PKT_TYPE_PSPOLL | |
AR5K_PKT_TYPE_BEACON | |
AR5K_PKT_TYPE_PROBE_RESP | |
AR5K_PKT_TYPE_PIFS |
Definition at line 524 of file ath5k.h.
enum ath5k_dmasize |
Enumerator | |
---|---|
AR5K_DMASIZE_4B | |
AR5K_DMASIZE_8B | |
AR5K_DMASIZE_16B | |
AR5K_DMASIZE_32B | |
AR5K_DMASIZE_64B | |
AR5K_DMASIZE_128B | |
AR5K_DMASIZE_256B | |
AR5K_DMASIZE_512B |
Definition at line 548 of file ath5k.h.
enum ath5k_rfgain |
Enumerator | |
---|---|
AR5K_RFGAIN_INACTIVE | |
AR5K_RFGAIN_ACTIVE | |
AR5K_RFGAIN_READ_REQUESTED | |
AR5K_RFGAIN_NEED_CHANGE |
enum ath5k_int |
enum ath5k_int - Hardware interrupt masks helpers
@AR5K_INT_RX: mask to identify received frame interrupts, of type AR5K_ISR_RXOK or AR5K_ISR_RXERR @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) @AR5K_INT_RXNOFRM: No frame received (?) @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's LinkPtr is NULL. For more details, refer to: http://www.freepatentsonline.com/20030225739.html @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). Note that Rx overrun is not always fatal, on some chips we can continue operation without reseting the card, that's why int_fatal is not common for all chips. @AR5K_INT_TX: mask to identify received frame interrupts, of type AR5K_ISR_TXOK or AR5K_ISR_TXERR @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) @AR5K_INT_TXURN: received when we should increase the TX trigger threshold We currently do increments on interrupt by (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 @AR5K_INT_MIB: Indicates the Management Information Base counters should be checked. We should do this with ath5k_hw_update_mib_counters() but it seems we should also then do some noise immunity work. @AR5K_INT_RXPHY: RX PHY Error @AR5K_INT_RXKCM: RX Key cache miss @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a beacon that must be handled in software. The alternative is if you have VEOL support, in that case you let the hardware deal with things. @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing beacons from the AP have associated with, we should probably try to reassociate. When in IBSS mode this might mean we have not received any beacons from any local stations. Note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now until properly handled @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA errors. These types of errors we can enable seem to be of type AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. @AR5K_INT_GLOBAL: Used to clear and set the IER @AR5K_INT_NOCARD: signals the card has been removed @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same bit value
These are mapped to take advantage of some common bits between the MACs, to be able to set intr properties easier. Some of them are not used yet inside hw.c. Most map to the respective hw interrupt value as they are common amogst different MACs.
Definition at line 804 of file ath5k.h.
enum ath5k_power_mode |
Enumerator | |
---|---|
AR5K_PM_UNDEFINED | |
AR5K_PM_AUTO | |
AR5K_PM_AWAKE | |
AR5K_PM_FULL_SLEEP | |
AR5K_PM_NETWORK_SLEEP |
Definition at line 866 of file ath5k.h.
Definition at line 885 of file ath5k.h.
FILE_LICENCE | ( | MIT | ) |
int ath5k_bitrate_to_hw_rix | ( | int | bitrate | ) |
Definition at line 718 of file ath5k.c.
References ATH5K_NR_RATES, ATH5K_RATE_CODE_1M, ath5k_rates, bitrate, and DBG.
Referenced by ath5k_hw_write_rate_duration().
int ath5k_hw_attach | ( | struct ath5k_softc * | sc, |
u8 | mac_version, | ||
struct ath5k_hw ** | hw | ||
) |
ath5k_hw_attach - Check if hw is supported and init the needed structs
@sc: The &struct ath5k_softc we got from the driver's attach function @mac_version: The mac version id (check out ath5k.h) based on pci id @hw: Returned newly allocated hardware structure, on success
Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.
Definition at line 112 of file ath5k_attach.c.
References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_INIT_TX_RETRY, AR5K_MISC_MODE, AR5K_MISC_MODE_COMBINED_MIC, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX, AR5K_PCIE_SERDES, AR5K_PCIE_SERDES_RESET, AR5K_PHY, AR5K_PHY_CHIP_ID, AR5K_REG_ENABLE_BITS, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_SREV, AR5K_SREV_AR2414, AR5K_SREV_AR2415, AR5K_SREV_AR2417, AR5K_SREV_AR2425, AR5K_SREV_AR5213A, AR5K_SREV_AR5414, AR5K_SREV_AR5416, AR5K_SREV_PHY_2413, AR5K_SREV_PHY_2425, AR5K_SREV_PHY_5212B, AR5K_SREV_PHY_5413, AR5K_SREV_RAD_2112, AR5K_SREV_RAD_2316, AR5K_SREV_RAD_2317, AR5K_SREV_RAD_2413, AR5K_SREV_RAD_2425, AR5K_SREV_RAD_5111, AR5K_SREV_RAD_5112, AR5K_SREV_RAD_5112B, AR5K_SREV_RAD_5413, AR5K_SREV_RAD_5424, AR5K_SREV_REV, AR5K_SREV_VER, AR5K_TUNE_AIFS, AR5K_TUNE_ANT_DIVERSITY, AR5K_TUNE_CWMIN, ath5k_eeprom_init(), ath5k_hw_init_desc_functions(), ath5k_hw_nic_wakeup(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_rfgain_opt_init(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_opmode(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_B, DBG, pci_device::device, ENOMEM, ENOTSUP, ETH_ALEN, free, ath5k_softc::iobase, mdelay(), memset(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, and zalloc().
Referenced by ath5k_probe().
void ath5k_hw_detach | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_detach - Free the ath5k_hw struct
@ah: The &struct ath5k_hw
Definition at line 335 of file ath5k_attach.c.
References ah, ath5k_eeprom_detach(), and free.
Referenced by ath5k_probe(), and ath5k_remove().
int ath5k_init_leds | ( | struct ath5k_softc * | sc | ) |
void ath5k_led_enable | ( | struct ath5k_softc * | sc | ) |
void ath5k_led_off | ( | struct ath5k_softc * | sc | ) |
void ath5k_unregister_leds | ( | struct ath5k_softc * | sc | ) |
int ath5k_hw_nic_wakeup | ( | struct ath5k_hw * | ah, |
int | flags, | ||
int | initial | ||
) |
Definition at line 282 of file ath5k_reset.c.
References ah, AR5K_AR5210, AR5K_AR5211, AR5K_PHY_MODE, AR5K_PHY_MODE_FREQ_2GHZ, AR5K_PHY_MODE_FREQ_5GHZ, AR5K_PHY_MODE_MOD_CCK, AR5K_PHY_MODE_MOD_DYN, AR5K_PHY_MODE_MOD_OFDM, AR5K_PHY_MODE_RAD_RF5111, AR5K_PHY_MODE_RAD_RF5112, AR5K_PHY_PLL, AR5K_PHY_PLL_40MHZ, AR5K_PHY_PLL_40MHZ_5413, AR5K_PHY_PLL_44MHZ, AR5K_PHY_PLL_RF5111, AR5K_PHY_PLL_RF5112, AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCI, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RF5112, AR5K_RF5413, ath5k_hw_nic_reset(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_wake(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EINVAL, EIO, flags, mdelay(), PCI_CAP_ID_EXP, pci_find_capability(), and udelay().
Referenced by ath5k_hw_attach(), and ath5k_hw_reset().
int ath5k_hw_reset | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel, | ||
int | change_channel | ||
) |
Definition at line 690 of file ath5k_reset.c.
References ah, AR5K_ANT_FIXED_A, AR5K_ANT_FIXED_B, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_BEACON, AR5K_BEACON_ENABLE, AR5K_BEACON_RESET_TSF, AR5K_DEFAULT_ANTENNA, AR5K_DMASIZE_128B, AR5K_EEPROM_HDR_RFKILL, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_GPIOCR, AR5K_GPIODO, AR5K_HIGH_ID, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_LOW_ID, AR5K_MIC_QOS_CTL, AR5K_MIC_QOS_SEL, AR5K_MODE_11A, AR5K_MODE_11A_TURBO, AR5K_MODE_11B, AR5K_MODE_11G, AR5K_MODE_11G_TURBO, AR5K_MODE_XR, AR5K_PCICFG, AR5K_PCICFG_LEDSTATE, AR5K_PHY, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ADC_TEST, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, AR5K_PHY_IQ_RUN, AR5K_PHY_RX_DELAY, AR5K_PHY_RX_DELAY_M, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY_TST1, AR5K_PHY_TST1_TXHOLD, AR5K_PISR, AR5K_QOS_NOACK, AR5K_QOS_NOACK_2BIT_VALUES, AR5K_QOS_NOACK_BIT_OFFSET, AR5K_QOS_NOACK_BYTE_OFFSET, AR5K_QUEUE_DCU_SEQNUM, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5111, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS_S, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_SREV_AR2413, AR5K_SREV_AR5211, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, AR5K_STA_ID1_DEFAULT_ANTENNA, AR5K_STA_ID1_DESC_ANTENNA, AR5K_STA_ID1_RTS_DEF_ANTENNA, AR5K_STA_ID1_SELFGEN_DEF_ANT, AR5K_TUNE_BMISS_THRES, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_RSSI_THRES, AR5K_TXCFG, AR5K_TXCFG_B_MODE, AR5K_TXCFG_SDMAMR, ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_gpio(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_tx_queue(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_imr(), ath5k_hw_set_opmode(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_write_initvals(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), channel, CHANNEL_A, CHANNEL_B, CHANNEL_CCK, CHANNEL_G, CHANNEL_MODES, CHANNEL_OFDM, CHANNEL_T, CHANNEL_TG, CHANNEL_XR, DBG, delay, EINVAL, mdelay(), NULL, and udelay().
Referenced by ath5k_reset().
int ath5k_hw_set_power | ( | struct ath5k_hw * | ah, |
enum ath5k_power_mode | mode, | ||
int | set_chip, | ||
u16 | sleep_duration | ||
) |
void ath5k_hw_start_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_start_rx_dma - Start DMA receive
@ah: The &struct ath5k_hw
Definition at line 54 of file ath5k_dma.c.
References ah, AR5K_CR, AR5K_CR_RXE, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
int ath5k_hw_stop_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_stop_rx_dma - Stop DMA receive
@ah: The &struct ath5k_hw
Definition at line 65 of file ath5k_dma.c.
References ah, AR5K_CR, AR5K_CR_RXD, AR5K_CR_RXE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, and udelay().
Referenced by ath5k_rx_stop().
ath5k_hw_get_rxdp - Get RX Descriptor's address
@ah: The &struct ath5k_hw
XXX: Is RXDP read and clear ?
Definition at line 89 of file ath5k_dma.c.
References ah, AR5K_RXDP, and ath5k_hw_reg_read().
ath5k_hw_set_rxdp - Set RX Descriptor's address
@ah: The &struct ath5k_hw @phys_addr: RX descriptor address
XXX: Should we check if rx is enabled before setting rxdp ?
Definition at line 102 of file ath5k_dma.c.
References ah, AR5K_RXDP, and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
int ath5k_hw_start_tx_dma | ( | struct ath5k_hw * | ah, |
unsigned int | queue | ||
) |
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.
NOTE: Must be called after setting up tx control descriptor for that queue (see below).
Definition at line 127 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_QCU_TXD, AR5K_QCU_TXE, AR5K_REG_READ_Q, AR5K_REG_WRITE_Q, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EIO, and queue.
Referenced by ath5k_txbuf_setup().
int ath5k_hw_stop_tx_dma | ( | struct ath5k_hw * | ah, |
unsigned int | queue | ||
) |
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Stop DMA transmit on a specific hw queue and drain queue so we don't have any pending frames. Returns -EBUSY if we still have pending frames, -EINVAL if queue number is out of range.
Definition at line 167 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_CHANEL_IDLE_HIGH, AR5K_QCU_STS_FRMPENDCNT, AR5K_QCU_TXD, AR5K_QUEUE_STATUS, AR5K_QUIET_CTL1, AR5K_QUIET_CTL1_NEXT_QT_TSF, AR5K_QUIET_CTL1_QT_EN, AR5K_QUIET_CTL2, AR5K_QUIET_CTL2_QT_DUR, AR5K_QUIET_CTL2_QT_PER, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SREV_AR2414, AR5K_TSF_L32_5211, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, EIO, pending, queue, and udelay().
Referenced by ath5k_txq_cleanup().
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.
XXX: Is TXDP read and clear ?
Definition at line 261 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QUEUE_TXDP, ath5k_hw_reg_read(), and queue.
Referenced by ath5k_txq_cleanup().
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.
Definition at line 292 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QCU_TXE, AR5K_QUEUE_TXDP, AR5K_REG_READ_Q, ath5k_hw_reg_write(), EIO, and queue.
Referenced by ath5k_txbuf_setup().
int ath5k_hw_update_tx_triglevel | ( | struct ath5k_hw * | ah, |
int | increase | ||
) |
ath5k_hw_update_tx_triglevel - Update tx trigger level
@ah: The &struct ath5k_hw @increase: Flag to force increase of trigger level
This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits it's data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems (i think bmiss is related). Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have have reached maximum/minimum.
XXX: Link this with tx DMA size ? XXX: Use it to save interrupts ? TODO: Needs testing, i think it's related to bmiss...
Definition at line 339 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_INT_GLOBAL, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TRIG_LVL, AR5K_TUNE_MAX_TX_FIFO_THRES, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_TXCFG, AR5K_TXCFG_TXFULL, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_set_imr(), done, EIO, and imr.
Referenced by ath5k_poll().
int ath5k_hw_is_intr_pending | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_is_intr_pending - Check if we have pending interrupts
@ah: The &struct ath5k_hw
Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.
Definition at line 391 of file ath5k_dma.c.
References ah, AR5K_INTPEND, and ath5k_hw_reg_read().
Referenced by ath5k_poll().
Definition at line 412 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_NOCARD, AR5K_INT_QCBRORN, AR5K_INT_QCBRURN, AR5K_INT_QTRIG, AR5K_INT_RX_DOPPLER, AR5K_INT_TIM, AR5K_ISR, AR5K_ISR_BCNMISC, AR5K_ISR_BNR, AR5K_ISR_DPERR, AR5K_ISR_HIUERR, AR5K_ISR_MCABT, AR5K_ISR_QCBRORN, AR5K_ISR_QCBRURN, AR5K_ISR_QTRIG, AR5K_ISR_RXDOPPLER, AR5K_ISR_SSERR, AR5K_ISR_TIM, AR5K_ISR_TXDESC, AR5K_ISR_TXEOL, AR5K_ISR_TXERR, AR5K_ISR_TXOK, AR5K_ISR_TXURN, AR5K_RAC_PISR, AR5K_RAC_SISR0, AR5K_RAC_SISR1, AR5K_RAC_SISR2, AR5K_RAC_SISR3, AR5K_RAC_SISR4, AR5K_REG_MS, AR5K_SISR0_QCU_TXDESC, AR5K_SISR0_QCU_TXOK, AR5K_SISR1_QCU_TXEOL, AR5K_SISR1_QCU_TXERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DPERR, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_MCABT, AR5K_SISR2_QCU_TXURN, AR5K_SISR2_SSERR, AR5K_SISR2_TIM, AR5K_SISR3_QCBRORN, AR5K_SISR3_QCBRURN, AR5K_SISR4_QTRIG, ath5k_hw_reg_read(), data, ENODEV, and if().
Referenced by ath5k_poll().
ath5k_hw_set_imr - Set interrupt mask
@ah: The &struct ath5k_hw @new_mask: The new interrupt mask to be set
Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.
Definition at line 548 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_IER, AR5K_IER_DISABLE, AR5K_IMR, AR5K_IMR_DPERR, AR5K_IMR_HIUERR, AR5K_IMR_MCABT, AR5K_IMR_RXDOPPLER, AR5K_IMR_SSERR, AR5K_IMR_TIM, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_GLOBAL, AR5K_INT_RX_DOPPLER, AR5K_INT_RXNOFRM, AR5K_INT_TIM, AR5K_PIMR, AR5K_RXNOFRM, AR5K_SIMR2, AR5K_SIMR2_DPERR, AR5K_SIMR2_MCABT, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR2_SSERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_TIM, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_hw_reset(), ath5k_hw_update_tx_triglevel(), ath5k_irq(), ath5k_reset(), and ath5k_stop_hw().
int ath5k_eeprom_init | ( | struct ath5k_hw * | ah | ) |
Definition at line 1697 of file ath5k_eeprom.c.
References ah, ath5k_eeprom_init_header(), ath5k_eeprom_init_modes(), ath5k_eeprom_read_ctl_info(), and ath5k_eeprom_read_pcal_info().
Referenced by ath5k_hw_attach().
void ath5k_eeprom_detach | ( | struct ath5k_hw * | ah | ) |
Definition at line 1576 of file ath5k_eeprom.c.
References ah, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11G, and ath5k_eeprom_free_pcal_info().
Referenced by ath5k_hw_detach().
Definition at line 1723 of file ath5k_eeprom.c.
References ah, ath5k_hw_eeprom_read(), data, EINVAL, ETH_ALEN, mac, memcpy(), and offset.
Referenced by ath5k_attach().
int ath5k_eeprom_is_hb63 | ( | struct ath5k_hw * | ah | ) |
Definition at line 1753 of file ath5k_eeprom.c.
References ah, AR5K_EEPROM_IS_HB63, AR5K_SREV_AR2425, ath5k_hw_eeprom_read(), and data.
Referenced by ath5k_hw_tweak_initval_settings().
int ath5k_hw_set_opmode | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_set_opmode - Set PCU operating mode
@ah: The &struct ath5k_hw
Initialize PCU for the various operating modes (AP/STA etc)
For iPXE we always assume STA mode.
Definition at line 48 of file ath5k_pcu.c.
References ah, AR5K_AR5210, AR5K_BCR, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ADHOC, AR5K_STA_ID1_AP, AR5K_STA_ID1_KEYSRCH_MODE, AR5K_STA_ID1_NO_PSPOLL, AR5K_STA_ID1_PWR_SV, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_hw_attach(), ath5k_hw_reset(), and ath5k_mode_setup().
ath5k_hw_get_lladdr - Get station id
@ah: The &struct ath5k_hw @mac: The card's mac address
Initialize ah->ah_sta_id using the mac address provided (just a memcpy).
TODO: Remove it once we merge ath5k_softc and ath5k_hw
Definition at line 187 of file ath5k_pcu.c.
ath5k_hw_set_lladdr - Set station id
@ah: The &struct ath5k_hw @mac: The card's mac address
Set station id on hw using the provided mac address
Definition at line 200 of file ath5k_pcu.c.
References ah, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ETH_ALEN, mac, and memcpy().
Referenced by ath5k_start(), and ath5k_stop().
ath5k_hw_set_associd - Set BSSID for association
@ah: The &struct ath5k_hw @bssid: BSSID @assoc_id: Assoc id
Sets the BSSID which trigers the "SME Join" operation
Definition at line 228 of file ath5k_pcu.c.
References ah, AR5K_AR5212, AR5K_BSS_ID0, AR5K_BSS_ID1, AR5K_BSS_ID1_AID_S, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, and ath5k_hw_reg_write().
Referenced by ath5k_config(), ath5k_hw_attach(), and ath5k_hw_reset().
ath5k_hw_set_bssid_mask - filter out bssids we listen
@ah: the &struct ath5k_hw @mask: the bssid_mask, a u8 array of size ETH_ALEN
BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.
NOTE: This is a simple filter and does not filter out all relevant frames. Some frames that are not for us might get ACKed from us by PCU because they just match the mask.
When handling multiple BSSes you can get the BSSID mask by computing the set of ~ ( MAC XOR BSSID ) for all bssids we handle.
When you do this you are essentially computing the common bits of all your BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with the MAC address to obtain the relevant bits and compare the result with (frame's BSSID & mask) to see if they match.
Definition at line 348 of file ath5k_pcu.c.
References ah, AR5K_AR5212, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, ath5k_hw_reg_write(), EIO, ETH_ALEN, and memcpy().
Referenced by ath5k_attach(), and ath5k_mode_setup().
void ath5k_hw_start_rx_pcu | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_start_rx_pcu - Start RX engine
@ah: The &struct ath5k_hw
Starts RX engine on PCU so that hw can process RXed frames (ACK etc).
NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma TODO: Init ANI here
Definition at line 384 of file ath5k_pcu.c.
References ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_DISABLE_BITS.
Referenced by ath5k_rx_start().
void ath5k_hw_stop_rx_pcu | ( | struct ath5k_hw * | ah | ) |
at5k_hw_stop_rx_pcu - Stop RX engine
@ah: The &struct ath5k_hw
Stops RX engine on PCU
TODO: Detach ANI here
Definition at line 398 of file ath5k_pcu.c.
References ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_ENABLE_BITS.
Referenced by ath5k_rx_stop().
Definition at line 406 of file ath5k_pcu.c.
References ah, AR5K_MCAST_FILTER0, AR5K_MCAST_FILTER1, and ath5k_hw_reg_write().
Referenced by ath5k_configure_filter(), and ath5k_mode_setup().
ath5k_hw_get_rx_filter - Get current rx filter
@ah: The &struct ath5k_hw
Returns the RX filter by reading rx filter and phy error filter registers. RX filter is used to set the allowed frame types that PCU will accept and pass to the driver. For a list of frame types check out reg.h.
Definition at line 424 of file ath5k_pcu.c.
References ah, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_RADARERR, ath5k_hw_reg_read(), data, and filter.
ath5k_hw_set_rx_filter - Set rx filter
@ah: The &struct ath5k_hw @filter: RX filter mask (see reg.h)
Sets RX filter register and also handles PHY error filter register on 5212 and newer chips so that we have proper PHY error reporting.
Definition at line 453 of file ath5k_pcu.c.
References ah, AR5K_AR5210, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_PROM, AR5K_RX_FILTER_RADARERR, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA, ath5k_hw_reg_write(), data, and filter.
Referenced by ath5k_configure_filter(), ath5k_mode_setup(), and ath5k_rx_stop().
void ath5k_hw_set_ack_bitrate_high | ( | struct ath5k_hw * | ah, |
int | high | ||
) |
ath5k_hw_set_ack_bitrate - set bitrate for ACKs
@ah: The &struct ath5k_hw @high: Flag to determine if we want to use high transmition rate for ACKs or not
If high flag is set, we tell hw to use a set of control rates based on the current transmition rate (check out control_rates array inside reset.c). If not hw just uses the lowest rate available for the current modulation scheme being used (1Mbit for CCK and 6Mbits for OFDM).
Definition at line 95 of file ath5k_pcu.c.
References ah, AR5K_AR5212, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, high, and val.
Referenced by ath5k_init().
int ath5k_hw_set_ack_timeout | ( | struct ath5k_hw * | ah, |
unsigned int | timeout | ||
) |
ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
@ah: The &struct ath5k_hw @timeout: Timeout in usec
Definition at line 130 of file ath5k_pcu.c.
References ah, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), EINVAL, and timeout().
unsigned int ath5k_hw_get_ack_timeout | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
@ah: The &struct ath5k_hw
Definition at line 118 of file ath5k_pcu.c.
References ah, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().
int ath5k_hw_set_cts_timeout | ( | struct ath5k_hw * | ah, |
unsigned int | timeout | ||
) |
ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
@ah: The &struct ath5k_hw @timeout: Timeout in usec
Definition at line 159 of file ath5k_pcu.c.
References ah, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), EINVAL, and timeout().
unsigned int ath5k_hw_get_cts_timeout | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
@ah: The &struct ath5k_hw
Definition at line 147 of file ath5k_pcu.c.
References ah, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().
Definition at line 496 of file ath5k_pcu.c.
References ah, AR5K_AR5211, AR5K_KEYCACHE_SIZE, AR5K_KEYTABLE_MIC_OFFSET, AR5K_KEYTABLE_OFF, AR5K_KEYTABLE_TYPE, AR5K_KEYTABLE_TYPE_NULL, AR5K_KEYTABLE_TYPE_TKIP, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and type.
Referenced by ath5k_init().
int ath5k_hw_set_tx_queueprops | ( | struct ath5k_hw * | ah, |
const struct ath5k_txq_info * | queue_info | ||
) |
Definition at line 34 of file ath5k_qcu.c.
References ah, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TX_QUEUE_UAPSD, AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS, AR5K_WME_AC_VI, AR5K_WME_AC_VO, EIO, memcpy(), ath5k_txq_info::tqi_subtype, and ath5k_txq_info::tqi_type.
Referenced by ath5k_hw_setup_tx_queue().
int ath5k_hw_setup_tx_queue | ( | struct ath5k_hw * | ah, |
enum ath5k_tx_queue | queue_type, | ||
struct ath5k_txq_info * | queue_info | ||
) |
Definition at line 55 of file ath5k_qcu.c.
References ah, AR5K_Q_ENABLE_BITS, ath5k_hw_set_tx_queueprops(), memset(), NULL, and ath5k_txq_info::tqi_type.
Referenced by ath5k_txq_setup().
void ath5k_hw_release_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 86 of file ath5k_qcu.c.
References ah, AR5K_Q_DISABLE_BITS, and AR5K_TX_QUEUE_INACTIVE.
Referenced by ath5k_txq_release().
int ath5k_hw_reset_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 97 of file ath5k_qcu.c.
References ah, AR5K_AR5210, AR5K_AR5212, AR5K_DCU_CHAN_TIME_DUR, AR5K_DCU_CHAN_TIME_ENABLE, AR5K_DCU_LCL_IFS_AIFS, AR5K_DCU_LCL_IFS_CW_MAX, AR5K_DCU_LCL_IFS_CW_MIN, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_DCU_MISC_FRAG_WAIT, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_DCU_MISC_SEQNUM_CTL, AR5K_DCU_RETRY_LMT_LG_RETRY, AR5K_DCU_RETRY_LMT_SH_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY, AR5K_IFS0, AR5K_IFS0_DIFS_S, AR5K_IFS1, AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_INIT_ACK_CTS_TIMEOUT_TURBO, AR5K_INIT_LG_RETRY, AR5K_INIT_PROTO_TIME_CNTRL, AR5K_INIT_PROTO_TIME_CNTRL_TURBO, AR5K_INIT_SH_RETRY, AR5K_INIT_SIFS, AR5K_INIT_SIFS_TURBO, AR5K_INIT_SLG_RETRY, AR5K_INIT_SLOT_TIME, AR5K_INIT_SLOT_TIME_TURBO, AR5K_INIT_SSH_RETRY, AR5K_INIT_TRANSMIT_LATENCY, AR5K_INIT_TRANSMIT_LATENCY_TURBO, AR5K_NODCU_RETRY_LMT, AR5K_NODCU_RETRY_LMT_CW_MIN_S, AR5K_NODCU_RETRY_LMT_LG_RETRY, AR5K_NODCU_RETRY_LMT_SH_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY, AR5K_PHY_FRAME_CTL_5210, AR5K_PHY_FRAME_CTL_INI, AR5K_PHY_SETTLING, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_Q_ENABLE_BITS, AR5K_QCU_CBRCFG_INTVAL, AR5K_QCU_CBRCFG_ORN_THRES, AR5K_QCU_MISC_CBR_THRES_ENABLE, AR5K_QCU_MISC_DCU_EARLY, AR5K_QCU_MISC_FRSHED_CBR, AR5K_QCU_MISC_RDY_VEOL_POLICY, AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QCU_RDYTIMECFG_INTVAL, AR5K_QUEUE_CBRCFG, AR5K_QUEUE_DFS_CHANNEL_TIME, AR5K_QUEUE_DFS_LOCAL_IFS, AR5K_QUEUE_DFS_MISC, AR5K_QUEUE_DFS_RETRY_LIMIT, AR5K_QUEUE_MISC, AR5K_QUEUE_QCUMASK, AR5K_QUEUE_RDYTIMECFG, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SIMR0, AR5K_SIMR0_QCU_TXDESC, AR5K_SIMR0_QCU_TXOK, AR5K_SIMR1, AR5K_SIMR1_QCU_TXEOL, AR5K_SIMR1_QCU_TXERR, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR3, AR5K_SIMR3_QCBRORN, AR5K_SIMR3_QCBRURN, AR5K_SIMR4, AR5K_SIMR4_QTRIG, AR5K_SLOT_TIME, AR5K_SREV_AR5211, AR5K_TUNE_AIFS, AR5K_TUNE_AIFS_11B, AR5K_TUNE_AIFS_XR, AR5K_TUNE_CWMAX, AR5K_TUNE_CWMAX_11B, AR5K_TUNE_CWMAX_XR, AR5K_TUNE_CWMIN, AR5K_TUNE_CWMIN_11B, AR5K_TUNE_CWMIN_XR, AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TXNOFRM, AR5K_TXNOFRM_QCU, AR5K_TXQ_FLAG_BACKOFF_DISABLE, AR5K_TXQ_FLAG_CBRORNINT_ENABLE, AR5K_TXQ_FLAG_CBRURNINT_ENABLE, AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, AR5K_TXQ_FLAG_QTRIGINT_ENABLE, AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, AR5K_TXQ_FLAG_TXDESCINT_ENABLE, AR5K_TXQ_FLAG_TXEOLINT_ENABLE, AR5K_TXQ_FLAG_TXERRINT_ENABLE, AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE, AR5K_TXQ_FLAG_TXOKINT_ENABLE, AR5K_TXQ_FLAG_TXURNINT_ENABLE, AR5K_USEC_5210, ath5k_hw_reg_read(), ath5k_hw_reg_write(), IS_CHAN_B, IS_CHAN_XR, queue, ath5k_txq_info::tqi_aifs, ath5k_txq_info::tqi_burst_time, ath5k_txq_info::tqi_cbr_overflow_limit, ath5k_txq_info::tqi_cbr_period, ath5k_txq_info::tqi_cw_max, ath5k_txq_info::tqi_cw_min, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_ready_time, and ath5k_txq_info::tqi_type.
Referenced by ath5k_hw_reset().
int ath5k_hw_set_slot_time | ( | struct ath5k_hw * | ah, |
unsigned int | slot_time | ||
) |
Definition at line 377 of file ath5k_qcu.c.
References ah, AR5K_AR5210, AR5K_DCU_GBL_IFS_SLOT, AR5K_SLOT_TIME, AR5K_SLOT_TIME_MAX, ath5k_hw_htoclock(), ath5k_hw_reg_write(), and EINVAL.
int ath5k_hw_init_desc_functions | ( | struct ath5k_hw * | ah | ) |
Definition at line 522 of file ath5k_desc.c.
References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, ath5k_hw_proc_2word_tx_status(), ath5k_hw_proc_4word_tx_status(), ath5k_hw_proc_5210_rx_status(), ath5k_hw_proc_5212_rx_status(), ath5k_hw_setup_2word_tx_desc(), ath5k_hw_setup_4word_tx_desc(), ath5k_hw_setup_rx_desc(), and ENOTSUP.
Referenced by ath5k_hw_attach().
Definition at line 34 of file ath5k_gpio.c.
References ah, AR5K_GPIOCR, AR5K_GPIOCR_IN, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EINVAL, and gpio.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
Definition at line 49 of file ath5k_gpio.c.
References ah, AR5K_GPIOCR, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EINVAL, and gpio.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
Definition at line 64 of file ath5k_gpio.c.
References ah, AR5K_GPIODI, AR5K_GPIODI_M, AR5K_NUM_GPIO, ath5k_hw_reg_read(), and gpio.
Referenced by ath5k_hw_reset(), ath5k_is_rfkill_set(), and ath5k_rfkill_set_intr().
Definition at line 77 of file ath5k_gpio.c.
References ah, AR5K_GPIODO, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), data, EINVAL, gpio, and val.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
Definition at line 98 of file ath5k_gpio.c.
References ah, AR5K_GPIOCR, AR5K_GPIOCR_INT_ENA, AR5K_GPIOCR_INT_SEL, AR5K_GPIOCR_INT_SELH, AR5K_GPIOCR_OUT, AR5K_IMR_GPIO, AR5K_NUM_GPIO, AR5K_PIMR, AR5K_REG_ENABLE_BITS, ath5k_hw_reg_read(), ath5k_hw_reg_write(), data, and gpio.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
void ath5k_rfkill_hw_start | ( | struct ath5k_hw * | ah | ) |
Definition at line 80 of file ath5k_rfkill.c.
References ah, AR5K_EEPROM_HDR_RFKILL, ath5k_rfkill_disable(), ath5k_rfkill_set_intr(), ath5k_softc::gpio, ath5k_softc::polarity, and ath5k_softc::rf_kill.
Referenced by ath5k_init().
void ath5k_rfkill_hw_stop | ( | struct ath5k_hw * | ah | ) |
Definition at line 97 of file ath5k_rfkill.c.
References ah, AR5K_EEPROM_HDR_RFKILL, ath5k_rfkill_enable(), and ath5k_rfkill_set_intr().
Referenced by ath5k_stop_hw().
int ath5k_hw_set_capabilities | ( | struct ath5k_hw * | ah | ) |
Definition at line 36 of file ath5k_caps.c.
References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_EEPROM_HDR_11A, AR5K_EEPROM_HDR_11B, AR5K_EEPROM_HDR_11G, AR5K_MODE_BIT_11A, AR5K_MODE_BIT_11A_TURBO, AR5K_MODE_BIT_11B, AR5K_MODE_BIT_11G, AR5K_MODE_BIT_11G_TURBO, and AR5K_NUM_GPIO.
Referenced by ath5k_hw_attach().
int ath5k_hw_get_capability | ( | struct ath5k_hw * | ah, |
enum ath5k_capability_type | cap_type, | ||
u32 | capability, | ||
u32 * | result | ||
) |
Definition at line 115 of file ath5k_caps.c.
References ah, AR5K_AR5212, AR5K_CAP_BSSIDMASK, AR5K_CAP_BURST, AR5K_CAP_COMPRESSION, AR5K_CAP_NUM_TXQUEUES, AR5K_CAP_TPC, AR5K_CAP_VEOL, AR5K_CAP_XR, EINVAL, and result.
int ath5k_hw_disable_pspoll | ( | struct ath5k_hw * | ah | ) |
Definition at line 1418 of file ath5k_initvals.c.
References ah, ar5210_ini, ar5211_ini, ar5211_ini_mode, ar5212_ini_common_start, ar5212_ini_mode_start, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_PHY_AGC, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_reg_write(), DBG, EINVAL, rf2413_ini_common_end, rf2413_ini_mode_end, rf2425_ini_common_end, rf2425_ini_mode_end, rf5111_ini_bbgain, rf5111_ini_common_end, rf5111_ini_mode_end, rf5112_ini_bbgain, rf5112_ini_common_end, rf5112_ini_mode_end, rf5413_ini_common_end, and rf5413_ini_mode_end.
Referenced by ath5k_hw_reset().
int ath5k_hw_rfregs_init | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel, | ||
unsigned int | mode | ||
) |
Definition at line 514 of file ath5k_phy.c.
References ah, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_MAX_RF_BANKS, AR5K_PHY_FRAME_CTL, AR5K_PHY_FRAME_CTL_TX_CLIP, AR5K_REG_WAIT, AR5K_REG_WRITE_BITS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_RF_DB_2GHZ, AR5K_RF_DB_5GHZ, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF_GAIN_I, AR5K_RF_HIGH_VC_CP, AR5K_RF_LOW_VC_CP, AR5K_RF_MID_VC_CP, AR5K_RF_MIXGAIN_OVR, AR5K_RF_OB_2GHZ, AR5K_RF_OB_5GHZ, AR5K_RF_PAD2GND, AR5K_RF_PD_GAIN_HI, AR5K_RF_PD_GAIN_LO, AR5K_RF_PLO_SEL, AR5K_RF_PUSH_UP, AR5K_RF_PWD_130, AR5K_RF_PWD_131, AR5K_RF_PWD_132, AR5K_RF_PWD_136, AR5K_RF_PWD_137, AR5K_RF_PWD_138, AR5K_RF_PWD_166, AR5K_RF_PWD_167, AR5K_RF_PWD_84, AR5K_RF_PWD_90, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF_PWD_XPD, AR5K_RF_RFGAIN_SEL, AR5K_RF_XB2_LVL, AR5K_RF_XB5_LVL, AR5K_RF_XPD_GAIN, AR5K_RF_XPD_SEL, AR5K_RFGAIN_ACTIVE, AR5K_SREV_AR2417, AR5K_SREV_AR5413, AR5K_SREV_AR5424, AR5K_SREV_PHY_5212A, AR5K_SREV_RAD_5112A, ARRAY_SIZE, ath5k_hw_bitswap(), ath5k_hw_reg_write(), ath5k_hw_rfb_op(), channel, CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, DBG, ath5k_eeprom_info::ee_db, ath5k_eeprom_info::ee_i_gain, ath5k_eeprom_info::ee_ob, ath5k_eeprom_info::ee_x_gain, ath5k_eeprom_info::ee_xpd, EINVAL, ENOMEM, ath5k_gain_opt::go_step, ath5k_gain_opt_step::gos_param, malloc(), NULL, rf_regs_2316, rf_regs_2413, rf_regs_2425, rf_regs_5111, rf_regs_5112, rf_regs_5112a, rf_regs_5413, rfb_2316, rfb_2317, rfb_2413, rfb_2417, rfb_2425, rfb_5111, rfb_5112, rfb_5112a, rfb_5413, ath5k_ini_rfbuffer::rfb_bank, ath5k_ini_rfbuffer::rfb_mode_data, rfgain_opt_5111, and rfgain_opt_5112.
Referenced by ath5k_hw_reset().
int ath5k_hw_rfgain_init | ( | struct ath5k_hw * | ah, |
unsigned int | freq | ||
) |
Definition at line 452 of file ath5k_phy.c.
References ah, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_REG_WAIT, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_reg_write(), EINVAL, ath5k_ini_rfgain::rfg_register, ath5k_ini_rfgain::rfg_value, rfgain_2316, rfgain_2413, rfgain_2425, rfgain_5111, rfgain_5112, rfgain_5413, and size.
Referenced by ath5k_hw_reset().
enum ath5k_rfgain ath5k_hw_gainf_calibrate | ( | struct ath5k_hw * | ah | ) |
Definition at line 389 of file ath5k_phy.c.
References ah, AR5K_GAIN_CCK_PROBE_CORR, AR5K_GAIN_CHECK_ADJUST, AR5K_PHY_PAPD_PROBE, AR5K_PHY_PAPD_PROBE_GAINF_S, AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE_TYPE, AR5K_PHY_PAPD_PROBE_TYPE_CCK, AR5K_REG_MS, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_INACTIVE, AR5K_RFGAIN_NEED_CHANGE, AR5K_RFGAIN_READ_REQUESTED, AR5K_SREV_RAD_5112A, ath5k_hw_reg_read(), ath5k_hw_rf_check_gainf_readback(), ath5k_hw_rf_gainf_adjust(), ath5k_hw_rf_gainf_corr(), data, done, ath5k_eeprom_info::ee_cck_ofdm_gain_delta, NULL, and type.
Referenced by ath5k_calibrate(), and ath5k_hw_reset().
int ath5k_hw_rfgain_opt_init | ( | struct ath5k_hw * | ah | ) |
Definition at line 158 of file ath5k_phy.c.
References ah, AR5K_RF5111, AR5K_RF5112, AR5K_RFGAIN_ACTIVE, EINVAL, ath5k_gain_opt::go_default, rfgain_opt_5111, and rfgain_opt_5112.
Referenced by ath5k_hw_attach().
Definition at line 830 of file ath5k_phy.c.
References ah, CHANNEL_2GHZ, CHANNEL_5GHZ, and flags.
Referenced by ath5k_copy_channels(), and ath5k_hw_channel().
int ath5k_hw_channel | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel | ||
) |
Definition at line 1048 of file ath5k_phy.c.
References ah, AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_JAPAN, AR5K_PHY_CCKTXCTL_WORLD, AR5K_REG_ENABLE_BITS, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, ath5k_channel_ok(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), channel, CHANNEL_T, DBG, EINVAL, and strerror().
Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().
int ath5k_hw_phy_calibrate | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel | ||
) |
Definition at line 1345 of file ath5k_phy.c.
References ah, AR5K_RF5110, ath5k_hw_rf5110_calibrate(), ath5k_hw_rf511x_calibrate(), and channel.
Referenced by ath5k_calibrate().
int ath5k_hw_noise_floor_calibration | ( | struct ath5k_hw * | ah, |
short | freq | ||
) |
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
@ah: struct ath5k_hw pointer we are operating on @freq: the channel frequency, just used for error logging
This function performs a noise floor calibration of the PHY and waits for it to complete. Then the noise floor value is compared to some maximum noise floor we consider valid.
Note that this is different from what the madwifi HAL does: it reads the noise floor and afterwards initiates the calibration. Since the noise floor calibration can take some time to finish, depending on the current channel use, that avoids the occasional timeout warnings we are seeing now.
See the following link for an Atheros patent on noise floor calibration: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
XXX: Since during noise floor calibration antennas are detached according to the patent, we should stop tx queues here.
Definition at line 1127 of file ath5k_phy.c.
References ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, AR5K_PHY_NF, AR5K_PHY_NF_ACTIVE, AR5K_PHY_NF_AVAL, AR5K_PHY_NF_RVAL, AR5K_REG_ENABLE_BITS, AR5K_TUNE_NOISE_FLOOR, ath5k_hw_reg_read(), DBG, DBG2, EAGAIN, and mdelay().
Referenced by ath5k_hw_reset(), ath5k_hw_rf5110_calibrate(), and ath5k_hw_rf511x_calibrate().
Definition at line 1372 of file ath5k_phy.c.
References ah, AR5K_AR5210, AR5K_PHY, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY_SHIFT_5GHZ, ath5k_hw_bitswap(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), CHANNEL_2GHZ, CHANNEL_5GHZ, mdelay(), and u16.
Referenced by ath5k_hw_attach().
void ath5k_hw_set_def_antenna | ( | struct ath5k_hw * | ah, |
unsigned int | ant | ||
) |
Definition at line 1416 of file ath5k_phy.c.
References ah, AR5K_AR5210, AR5K_DEFAULT_ANTENNA, and ath5k_hw_reg_write().
unsigned int ath5k_hw_get_def_antenna | ( | struct ath5k_hw * | ah | ) |
Definition at line 1422 of file ath5k_phy.c.
References ah, AR5K_AR5210, AR5K_DEFAULT_ANTENNA, and ath5k_hw_reg_read().
int ath5k_hw_phy_disable | ( | struct ath5k_hw * | ah | ) |
Definition at line 1358 of file ath5k_phy.c.
References ah, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, and ath5k_hw_reg_write().
Referenced by ath5k_stop_hw().
int ath5k_hw_txpower | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel, | ||
u8 | ee_mode, | ||
u8 | txpower | ||
) |
Definition at line 2474 of file ath5k_phy.c.
References ah, AR5K_PHY_TXPOWER_RATE1, AR5K_PHY_TXPOWER_RATE2, AR5K_PHY_TXPOWER_RATE3, AR5K_PHY_TXPOWER_RATE4, AR5K_PHY_TXPOWER_RATE_MAX, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE, AR5K_PWRTABLE_LINEAR_PCDAC, AR5K_PWRTABLE_PWR_TO_PCDAC, AR5K_PWRTABLE_PWR_TO_PDADC, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_TPC, AR5K_TPC_ACK, AR5K_TPC_CHIRP, AR5K_TPC_CTS, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_MAX_TXPOWER, AR5K_TUNE_TPC_TXPOWER, AR5K_TXPOWER_CCK, AR5K_TXPOWER_OFDM, ath5k_get_max_ctl_power(), ath5k_get_rate_pcal_data(), ath5k_hw_reg_write(), ath5k_setup_channel_powertable(), ath5k_setup_rate_powertable(), channel, DBG, EINVAL, memset(), and type.
Referenced by ath5k_hw_reset(), and ath5k_hw_set_txpower_limit().
Definition at line 2572 of file ath5k_phy.c.
References ah, ath5k_hw_txpower(), channel, and DBG2.
|
inlinestatic |
Definition at line 1197 of file ath5k.h.
Referenced by ath5k_hw_set_ack_timeout(), ath5k_hw_set_cts_timeout(), ath5k_hw_set_slot_time(), and ath5k_hw_write_ofdm_timings().
|
inlinestatic |
Definition at line 1206 of file ath5k.h.
Referenced by ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_set_ack_timeout(), and ath5k_hw_set_cts_timeout().
Definition at line 1214 of file ath5k.h.
References ah, readl(), and reg.
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_attach(), ath5k_hw_eeprom_read(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_get_def_antenna(), ath5k_hw_get_gpio(), ath5k_hw_get_isr(), ath5k_hw_get_rx_filter(), ath5k_hw_get_rxdp(), ath5k_hw_get_txdp(), ath5k_hw_ini_registers(), ath5k_hw_is_intr_pending(), ath5k_hw_nic_reset(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reset(), ath5k_hw_reset_key(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf511x_calibrate(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_gpio_output(), ath5k_hw_set_imr(), ath5k_hw_set_lladdr(), ath5k_hw_set_opmode(), ath5k_hw_start_rx_dma(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_rx_dma(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), ath5k_hw_update_tx_triglevel(), ath5k_hw_wake(), and ath5k_setup_pwr_to_pdadc_table().
Definition at line 1222 of file ath5k.h.
References ah, reg, val, and writel().
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_attach(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_eeprom_read(), ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_nic_reset(), ath5k_hw_nic_wakeup(), ath5k_hw_phy_disable(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_request_rfgain_probe(), ath5k_hw_reset(), ath5k_hw_reset_key(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_def_antenna(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_gpio_output(), ath5k_hw_set_imr(), ath5k_hw_set_lladdr(), ath5k_hw_set_mcast_filter(), ath5k_hw_set_opmode(), ath5k_hw_set_rx_filter(), ath5k_hw_set_rxdp(), ath5k_hw_set_slot_time(), ath5k_hw_set_txdp(), ath5k_hw_start_rx_dma(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_rx_dma(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_update_tx_triglevel(), ath5k_hw_wake(), ath5k_hw_write_initvals(), ath5k_hw_write_rate_duration(), ath5k_irq(), ath5k_setup_pcdac_table(), and ath5k_setup_pwr_to_pdadc_table().
Definition at line 1265 of file ath5k.h.
References bit, bits, retval, and val.
Referenced by ath5k_hw_radio_revision(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_chan2athchan(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfb_op(), and ath5k_hw_rfregs_init().