iPXE
Data Structures | Macros | Enumerations | Functions
ath5k.h File Reference
#include <stddef.h>
#include <byteswap.h>
#include <ipxe/io.h>
#include <ipxe/netdevice.h>
#include <ipxe/net80211.h>
#include <errno.h>
#include "desc.h"
#include "eeprom.h"

Go to the source code of this file.

Data Structures

struct  ath5k_srev_name
 
struct  ath5k_tx_status
 
struct  ath5k_txq_info
 
struct  ath5k_rx_status
 
struct  ath5k_gain
 
struct  ath5k_athchan_2ghz
 
struct  ath5k_capabilities
 
struct  ath5k_hw
 ath5k_hw_get_isr - Get interrupt status More...
 

Macros

#define ERRFILE   ERRFILE_ath5k
 
#define PCI_DEVICE_ID_ATHEROS_AR5210   0x0007 /* AR5210 */
 
#define PCI_DEVICE_ID_ATHEROS_AR5311   0x0011 /* AR5311 */
 
#define PCI_DEVICE_ID_ATHEROS_AR5211   0x0012 /* AR5211 */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212   0x0013 /* AR5212 */
 
#define PCI_DEVICE_ID_3COM_3CRDAG675   0x0013 /* 3CRDAG675 (Atheros AR5212) */
 
#define PCI_DEVICE_ID_3COM_2_3CRPAG175   0x0013 /* 3CRPAG175 (Atheros AR5212) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5210_AP   0x0207 /* AR5210 (Early) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM   0x1014 /* AR5212 (IBM MiniPCI) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA   0xf013 /* AR5212 (emulation board) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY   0xff12 /* AR5211 (emulation board) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2   0x0052 /* AR5312 WMAC (AP31) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7   0x0057 /* AR5312 WMAC (AP30-040) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8   0x0058 /* AR5312 WMAC (AP43-030) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0014   0x0014 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0015   0x0015 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0016   0x0016 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0017   0x0017 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0018   0x0018 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR5212_0019   0x0019 /* AR5212 compatible */
 
#define PCI_DEVICE_ID_ATHEROS_AR2413   0x001a /* AR2413 (Griffin-lite) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5413   0x001b /* AR5413 (Eagle) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5424   0x001c /* AR5424 (Condor PCI-E) */
 
#define PCI_DEVICE_ID_ATHEROS_AR5416   0x0023 /* AR5416 */
 
#define PCI_DEVICE_ID_ATHEROS_AR5418   0x0024 /* AR5418 */
 
#define AR5K_REG_SM(_val, _flags)   (((_val) << _flags##_S) & (_flags))
 
#define AR5K_REG_MS(_val, _flags)   (((_val) & (_flags)) >> _flags##_S)
 
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
 
#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)
 
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)   ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
 
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)   ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
 
#define AR5K_PHY_READ(ah, _reg)   ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
 
#define AR5K_PHY_WRITE(ah, _reg, _val)   ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
 
#define AR5K_REG_READ_Q(ah, _reg, _queue)   (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
 
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)   ath5k_hw_reg_write(ah, (1 << _queue), _reg)
 
#define AR5K_Q_ENABLE_BITS(_reg, _queue)
 
#define AR5K_Q_DISABLE_BITS(_reg, _queue)
 
#define AR5K_REG_WAIT(_i)
 
#define AR5K_INI_RFGAIN_5GHZ   0
 
#define AR5K_INI_RFGAIN_2GHZ   1
 
#define AR5K_INI_VAL_11A   0
 
#define AR5K_INI_VAL_11A_TURBO   1
 
#define AR5K_INI_VAL_11B   2
 
#define AR5K_INI_VAL_11G   3
 
#define AR5K_INI_VAL_11G_TURBO   4
 
#define AR5K_INI_VAL_XR   0
 
#define AR5K_INI_VAL_MAX   5
 
#define AR5K_LOW_ID(_a)
 
#define AR5K_HIGH_ID(_a)   ((_a)[4] | (_a)[5] << 8)
 
#define IEEE80211_MAX_LEN   2352
 
#define AR5K_TUNE_DMA_BEACON_RESP   2
 
#define AR5K_TUNE_SW_BEACON_RESP   10
 
#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF   0
 
#define AR5K_TUNE_RADAR_ALERT   0
 
#define AR5K_TUNE_MIN_TX_FIFO_THRES   1
 
#define AR5K_TUNE_MAX_TX_FIFO_THRES   ((IEEE80211_MAX_LEN / 64) + 1)
 
#define AR5K_TUNE_REGISTER_TIMEOUT   20000
 
#define AR5K_TUNE_RSSI_THRES   129
 
#define AR5K_TUNE_BMISS_THRES   7
 
#define AR5K_TUNE_REGISTER_DWELL_TIME   20000
 
#define AR5K_TUNE_BEACON_INTERVAL   100
 
#define AR5K_TUNE_AIFS   2
 
#define AR5K_TUNE_AIFS_11B   2
 
#define AR5K_TUNE_AIFS_XR   0
 
#define AR5K_TUNE_CWMIN   15
 
#define AR5K_TUNE_CWMIN_11B   31
 
#define AR5K_TUNE_CWMIN_XR   3
 
#define AR5K_TUNE_CWMAX   1023
 
#define AR5K_TUNE_CWMAX_11B   1023
 
#define AR5K_TUNE_CWMAX_XR   7
 
#define AR5K_TUNE_NOISE_FLOOR   -72
 
#define AR5K_TUNE_MAX_TXPOWER   63
 
#define AR5K_TUNE_DEFAULT_TXPOWER   25
 
#define AR5K_TUNE_TPC_TXPOWER   0
 
#define AR5K_TUNE_ANT_DIVERSITY   1
 
#define AR5K_TUNE_HWTXTRIES   4
 
#define AR5K_INIT_CARR_SENSE_EN   1
 
#define AR5K_INIT_CFG   0x00000000
 
#define AR5K_INIT_CYCRSSI_THR1   2
 
#define AR5K_INIT_TX_LATENCY   502
 
#define AR5K_INIT_USEC   39
 
#define AR5K_INIT_USEC_TURBO   79
 
#define AR5K_INIT_USEC_32   31
 
#define AR5K_INIT_SLOT_TIME   396
 
#define AR5K_INIT_SLOT_TIME_TURBO   480
 
#define AR5K_INIT_ACK_CTS_TIMEOUT   1024
 
#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO   0x08000800
 
#define AR5K_INIT_PROG_IFS   920
 
#define AR5K_INIT_PROG_IFS_TURBO   960
 
#define AR5K_INIT_EIFS   3440
 
#define AR5K_INIT_EIFS_TURBO   6880
 
#define AR5K_INIT_SIFS   560
 
#define AR5K_INIT_SIFS_TURBO   480
 
#define AR5K_INIT_SH_RETRY   10
 
#define AR5K_INIT_LG_RETRY   AR5K_INIT_SH_RETRY
 
#define AR5K_INIT_SSH_RETRY   32
 
#define AR5K_INIT_SLG_RETRY   AR5K_INIT_SSH_RETRY
 
#define AR5K_INIT_TX_RETRY   10
 
#define AR5K_INIT_TRANSMIT_LATENCY
 
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO
 
#define AR5K_INIT_PROTO_TIME_CNTRL
 
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO
 
#define AR5K_TXQ_USEDEFAULT   ((u32) -1)
 
#define AR5K_SREV_UNKNOWN   0xffff
 
#define AR5K_SREV_AR5210   0x00 /* Crete */
 
#define AR5K_SREV_AR5311   0x10 /* Maui 1 */
 
#define AR5K_SREV_AR5311A   0x20 /* Maui 2 */
 
#define AR5K_SREV_AR5311B   0x30 /* Spirit */
 
#define AR5K_SREV_AR5211   0x40 /* Oahu */
 
#define AR5K_SREV_AR5212   0x50 /* Venice */
 
#define AR5K_SREV_AR5213   0x55 /* ??? */
 
#define AR5K_SREV_AR5213A   0x59 /* Hainan */
 
#define AR5K_SREV_AR2413   0x78 /* Griffin lite */
 
#define AR5K_SREV_AR2414   0x70 /* Griffin */
 
#define AR5K_SREV_AR5424   0x90 /* Condor */
 
#define AR5K_SREV_AR5413   0xa4 /* Eagle lite */
 
#define AR5K_SREV_AR5414   0xa0 /* Eagle */
 
#define AR5K_SREV_AR2415   0xb0 /* Talon */
 
#define AR5K_SREV_AR5416   0xc0 /* PCI-E */
 
#define AR5K_SREV_AR5418   0xca /* PCI-E */
 
#define AR5K_SREV_AR2425   0xe0 /* Swan */
 
#define AR5K_SREV_AR2417   0xf0 /* Nala */
 
#define AR5K_SREV_RAD_5110   0x00
 
#define AR5K_SREV_RAD_5111   0x10
 
#define AR5K_SREV_RAD_5111A   0x15
 
#define AR5K_SREV_RAD_2111   0x20
 
#define AR5K_SREV_RAD_5112   0x30
 
#define AR5K_SREV_RAD_5112A   0x35
 
#define AR5K_SREV_RAD_5112B   0x36
 
#define AR5K_SREV_RAD_2112   0x40
 
#define AR5K_SREV_RAD_2112A   0x45
 
#define AR5K_SREV_RAD_2112B   0x46
 
#define AR5K_SREV_RAD_2413   0x50
 
#define AR5K_SREV_RAD_5413   0x60
 
#define AR5K_SREV_RAD_2316   0x70 /* Cobra SoC */
 
#define AR5K_SREV_RAD_2317   0x80
 
#define AR5K_SREV_RAD_5424   0xa0 /* Mostly same as 5413 */
 
#define AR5K_SREV_RAD_2425   0xa2
 
#define AR5K_SREV_RAD_5133   0xc0
 
#define AR5K_SREV_PHY_5211   0x30
 
#define AR5K_SREV_PHY_5212   0x41
 
#define AR5K_SREV_PHY_5212A   0x42
 
#define AR5K_SREV_PHY_5212B   0x43
 
#define AR5K_SREV_PHY_2413   0x45
 
#define AR5K_SREV_PHY_5413   0x61
 
#define AR5K_SREV_PHY_2425   0x70
 
#define MODULATION_XR   0x00000200
 
#define MODULATION_TURBO   0x00000080
 
#define AR5K_TXSTAT_ALTRATE   0x80
 
#define AR5K_TXERR_XRETRY   0x01
 
#define AR5K_TXERR_FILT   0x02
 
#define AR5K_TXERR_FIFO   0x04
 
#define AR5K_TXQ_FLAG_TXOKINT_ENABLE   0x0001 /* Enable TXOK interrupt */
 
#define AR5K_TXQ_FLAG_TXERRINT_ENABLE   0x0002 /* Enable TXERR interrupt */
 
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE   0x0004 /* Enable TXEOL interrupt -not used- */
 
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE   0x0008 /* Enable TXDESC interrupt -not used- */
 
#define AR5K_TXQ_FLAG_TXURNINT_ENABLE   0x0010 /* Enable TXURN interrupt */
 
#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE   0x0020 /* Enable CBRORN interrupt */
 
#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE   0x0040 /* Enable CBRURN interrupt */
 
#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE   0x0080 /* Enable QTRIG interrupt */
 
#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE   0x0100 /* Enable TXNOFRM interrupt */
 
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE   0x0200 /* Disable random post-backoff */
 
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE   0x0300 /* Enable ready time expiry policy (?)*/
 
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE   0x0800 /* Enable backoff while bursting */
 
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS   0x1000 /* Disable backoff while bursting */
 
#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE   0x2000 /* Enable hw compression -not implemented-*/
 
#define AR5K_TXPOWER_OFDM(_r, _v)
 
#define AR5K_TXPOWER_CCK(_r, _v)
 
#define AR5K_RXERR_CRC   0x01
 
#define AR5K_RXERR_PHY   0x02
 
#define AR5K_RXERR_FIFO   0x04
 
#define AR5K_RXERR_DECRYPT   0x08
 
#define AR5K_RXERR_MIC   0x10
 
#define AR5K_RXKEYIX_INVALID   ((u8) - 1)
 
#define AR5K_TXKEYIX_INVALID   ((u32) - 1)
 
#define TSF_TO_TU(_tsf)   (u32)((_tsf) >> 10)
 
#define AR5K_SLOT_TIME_9   396
 
#define AR5K_SLOT_TIME_20   880
 
#define AR5K_SLOT_TIME_MAX   0xffff
 
#define CHANNEL_CW_INT   0x0008 /* Contention Window interference detected */
 
#define CHANNEL_TURBO   0x0010 /* Turbo Channel */
 
#define CHANNEL_CCK   0x0020 /* CCK channel */
 
#define CHANNEL_OFDM   0x0040 /* OFDM channel */
 
#define CHANNEL_2GHZ   0x0080 /* 2GHz channel. */
 
#define CHANNEL_5GHZ   0x0100 /* 5GHz channel */
 
#define CHANNEL_PASSIVE   0x0200 /* Only passive scan allowed */
 
#define CHANNEL_DYN   0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
 
#define CHANNEL_XR   0x0800 /* XR channel */
 
#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)
 
#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)
 
#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)
 
#define CHANNEL_T   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 
#define CHANNEL_TG   (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 
#define CHANNEL_108A   CHANNEL_T
 
#define CHANNEL_108G   CHANNEL_TG
 
#define CHANNEL_X   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 
#define CHANNEL_ALL
 
#define CHANNEL_ALL_NOTURBO   (CHANNEL_ALL & ~CHANNEL_TURBO)
 
#define CHANNEL_MODES   CHANNEL_ALL
 
#define IS_CHAN_XR(_c)   ((_c->hw_value & CHANNEL_XR) != 0)
 
#define IS_CHAN_B(_c)   ((_c->hw_value & CHANNEL_B) != 0)
 
#define AR5K_MAX_RATES   32
 Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. More...
 
#define ATH5K_RATE_CODE_1M   0x1B
 
#define ATH5K_RATE_CODE_2M   0x1A
 
#define ATH5K_RATE_CODE_5_5M   0x19
 
#define ATH5K_RATE_CODE_11M   0x18
 
#define ATH5K_RATE_CODE_6M   0x0B
 
#define ATH5K_RATE_CODE_9M   0x0F
 
#define ATH5K_RATE_CODE_12M   0x0A
 
#define ATH5K_RATE_CODE_18M   0x0E
 
#define ATH5K_RATE_CODE_24M   0x09
 
#define ATH5K_RATE_CODE_36M   0x0D
 
#define ATH5K_RATE_CODE_48M   0x08
 
#define ATH5K_RATE_CODE_54M   0x0C
 
#define ATH5K_RATE_CODE_XR_500K   0x07
 
#define ATH5K_RATE_CODE_XR_1M   0x02
 
#define ATH5K_RATE_CODE_XR_2M   0x06
 
#define ATH5K_RATE_CODE_XR_3M   0x01
 
#define AR5K_SET_SHORT_PREAMBLE   0x04
 
#define AR5K_KEYCACHE_SIZE   8
 
#define AR5K_RSSI_EP_MULTIPLIER   (1<<7)
 
#define AR5K_ASSERT_ENTRY(_e, _s)
 
#define AR5K_SOFTLED_PIN   0
 
#define AR5K_SOFTLED_ON   0
 
#define AR5K_SOFTLED_OFF   1
 
#define AR5K_MAX_GPIO   10
 
#define AR5K_MAX_RF_BANKS   8
 
#define ah_regdomain   ah_capabilities.cap_regdomain.reg_current
 
#define ah_regdomain_hw   ah_capabilities.cap_regdomain.reg_hw
 
#define ah_modes   ah_capabilities.cap_mode
 
#define ah_ee_version   ah_capabilities.cap_eeprom.ee_version
 

Enumerations

enum  ath5k_version { AR5K_AR5210 = 0, AR5K_AR5211 = 1, AR5K_AR5212 = 2 }
 
enum  ath5k_radio {
  AR5K_RF5110 = 0, AR5K_RF5111 = 1, AR5K_RF5112 = 2, AR5K_RF2413 = 3,
  AR5K_RF5413 = 4, AR5K_RF2316 = 5, AR5K_RF2317 = 6, AR5K_RF2425 = 7
}
 
enum  ath5k_srev_type { AR5K_VERSION_MAC, AR5K_VERSION_RAD }
 
enum  ath5k_driver_mode {
  AR5K_MODE_11A = 0, AR5K_MODE_11A_TURBO = 1, AR5K_MODE_11B = 2, AR5K_MODE_11G = 3,
  AR5K_MODE_11G_TURBO = 4, AR5K_MODE_XR = 5
}
 
enum  {
  AR5K_MODE_BIT_11A = (1 << AR5K_MODE_11A), AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO), AR5K_MODE_BIT_11B = (1 << AR5K_MODE_11B), AR5K_MODE_BIT_11G = (1 << AR5K_MODE_11G),
  AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO), AR5K_MODE_BIT_XR = (1 << AR5K_MODE_XR)
}
 
enum  ath5k_tx_queue {
  AR5K_TX_QUEUE_INACTIVE = 0, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_XR_DATA, AR5K_TX_QUEUE_BEACON,
  AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_UAPSD
}
 enum ath5k_tx_queue - Queue types used to classify tx queues. More...
 
enum  ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, AR5K_WME_AC_BE, AR5K_WME_AC_VI, AR5K_WME_AC_VO }
 
enum  ath5k_tx_queue_id {
  AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, AR5K_TX_QUEUE_ID_DATA_MAX = 4,
  AR5K_TX_QUEUE_ID_DATA_SVP = 5, AR5K_TX_QUEUE_ID_CAB = 6, AR5K_TX_QUEUE_ID_BEACON = 7, AR5K_TX_QUEUE_ID_UAPSD = 8,
  AR5K_TX_QUEUE_ID_XR_DATA = 9
}
 
enum  ath5k_pkt_type {
  AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3,
  AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5
}
 
enum  ath5k_dmasize {
  AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, AR5K_DMASIZE_32B,
  AR5K_DMASIZE_64B, AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B
}
 
enum  ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE }
 
enum  ath5k_int {
  AR5K_INT_RXOK = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXERR = 0x00000004, AR5K_INT_RXNOFRM = 0x00000008,
  AR5K_INT_RXEOL = 0x00000010, AR5K_INT_RXORN = 0x00000020, AR5K_INT_TXOK = 0x00000040, AR5K_INT_TXDESC = 0x00000080,
  AR5K_INT_TXERR = 0x00000100, AR5K_INT_TXNOFRM = 0x00000200, AR5K_INT_TXEOL = 0x00000400, AR5K_INT_TXURN = 0x00000800,
  AR5K_INT_MIB = 0x00001000, AR5K_INT_SWI = 0x00002000, AR5K_INT_RXPHY = 0x00004000, AR5K_INT_RXKCM = 0x00008000,
  AR5K_INT_SWBA = 0x00010000, AR5K_INT_BRSSI = 0x00020000, AR5K_INT_BMISS = 0x00040000, AR5K_INT_FATAL = 0x00080000,
  AR5K_INT_BNR = 0x00100000, AR5K_INT_TIM = 0x00200000, AR5K_INT_DTIM = 0x00400000, AR5K_INT_DTIM_SYNC = 0x00800000,
  AR5K_INT_GPIO = 0x01000000, AR5K_INT_BCN_TIMEOUT = 0x02000000, AR5K_INT_CAB_TIMEOUT = 0x04000000, AR5K_INT_RX_DOPPLER = 0x08000000,
  AR5K_INT_QCBRORN = 0x10000000, AR5K_INT_QCBRURN = 0x20000000, AR5K_INT_QTRIG = 0x40000000, AR5K_INT_GLOBAL = 0x80000000,
  AR5K_INT_COMMON, AR5K_INT_NOCARD = 0xffffffff
}
 enum ath5k_int - Hardware interrupt masks helpers More...
 
enum  ath5k_power_mode {
  AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP,
  AR5K_PM_NETWORK_SLEEP
}
 
enum  ath5k_capability_type {
  AR5K_CAP_REG_DMN = 0, AR5K_CAP_TKIP_MIC = 2, AR5K_CAP_TKIP_SPLIT = 3, AR5K_CAP_PHYCOUNTERS = 4,
  AR5K_CAP_DIVERSITY = 5, AR5K_CAP_NUM_TXQUEUES = 6, AR5K_CAP_VEOL = 7, AR5K_CAP_COMPRESSION = 8,
  AR5K_CAP_BURST = 9, AR5K_CAP_FASTFRAME = 10, AR5K_CAP_TXPOW = 11, AR5K_CAP_TPC = 12,
  AR5K_CAP_BSSIDMASK = 13, AR5K_CAP_MCAST_KEYSRCH = 14, AR5K_CAP_TSF_ADJUST = 15, AR5K_CAP_XR = 16,
  AR5K_CAP_WME_TKIPMIC = 17, AR5K_CAP_CHAN_HALFRATE = 18, AR5K_CAP_CHAN_QUARTERRATE = 19, AR5K_CAP_RFSILENT = 20
}
 

Functions

 FILE_LICENCE (MIT)
 
int ath5k_bitrate_to_hw_rix (int bitrate)
 
int ath5k_hw_attach (struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah)
 ath5k_hw_attach - Check if hw is supported and init the needed structs More...
 
void ath5k_hw_detach (struct ath5k_hw *ah)
 ath5k_hw_detach - Free the ath5k_hw struct More...
 
int ath5k_init_leds (struct ath5k_softc *sc)
 
void ath5k_led_enable (struct ath5k_softc *sc)
 
void ath5k_led_off (struct ath5k_softc *sc)
 
void ath5k_unregister_leds (struct ath5k_softc *sc)
 
int ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, int initial)
 
int ath5k_hw_reset (struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel)
 
int ath5k_hw_set_power (struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration)
 
void ath5k_hw_start_rx_dma (struct ath5k_hw *ah)
 ath5k_hw_start_rx_dma - Start DMA receive More...
 
int ath5k_hw_stop_rx_dma (struct ath5k_hw *ah)
 ath5k_hw_stop_rx_dma - Stop DMA receive More...
 
u32 ath5k_hw_get_rxdp (struct ath5k_hw *ah)
 ath5k_hw_get_rxdp - Get RX Descriptor's address More...
 
void ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr)
 ath5k_hw_set_rxdp - Set RX Descriptor's address More...
 
int ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue More...
 
int ath5k_hw_stop_tx_dma (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue More...
 
u32 ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue More...
 
int ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
 ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue More...
 
int ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, int increase)
 ath5k_hw_update_tx_triglevel - Update tx trigger level More...
 
int ath5k_hw_is_intr_pending (struct ath5k_hw *ah)
 ath5k_hw_is_intr_pending - Check if we have pending interrupts More...
 
int ath5k_hw_get_isr (struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
 
enum ath5k_int ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask)
 ath5k_hw_set_imr - Set interrupt mask More...
 
int ath5k_eeprom_init (struct ath5k_hw *ah)
 
void ath5k_eeprom_detach (struct ath5k_hw *ah)
 
int ath5k_eeprom_read_mac (struct ath5k_hw *ah, u8 *mac)
 
int ath5k_eeprom_is_hb63 (struct ath5k_hw *ah)
 
int ath5k_hw_set_opmode (struct ath5k_hw *ah)
 ath5k_hw_set_opmode - Set PCU operating mode More...
 
void ath5k_hw_get_lladdr (struct ath5k_hw *ah, u8 *mac)
 ath5k_hw_get_lladdr - Get station id More...
 
int ath5k_hw_set_lladdr (struct ath5k_hw *ah, const u8 *mac)
 ath5k_hw_set_lladdr - Set station id More...
 
void ath5k_hw_set_associd (struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
 ath5k_hw_set_associd - Set BSSID for association More...
 
int ath5k_hw_set_bssid_mask (struct ath5k_hw *ah, const u8 *mask)
 ath5k_hw_set_bssid_mask - filter out bssids we listen More...
 
void ath5k_hw_start_rx_pcu (struct ath5k_hw *ah)
 ath5k_hw_start_rx_pcu - Start RX engine More...
 
void ath5k_hw_stop_rx_pcu (struct ath5k_hw *ah)
 at5k_hw_stop_rx_pcu - Stop RX engine More...
 
void ath5k_hw_set_mcast_filter (struct ath5k_hw *ah, u32 filter0, u32 filter1)
 
u32 ath5k_hw_get_rx_filter (struct ath5k_hw *ah)
 ath5k_hw_get_rx_filter - Get current rx filter More...
 
void ath5k_hw_set_rx_filter (struct ath5k_hw *ah, u32 filter)
 ath5k_hw_set_rx_filter - Set rx filter More...
 
void ath5k_hw_set_ack_bitrate_high (struct ath5k_hw *ah, int high)
 ath5k_hw_set_ack_bitrate - set bitrate for ACKs More...
 
int ath5k_hw_set_ack_timeout (struct ath5k_hw *ah, unsigned int timeout)
 ath5k_hw_set_ack_timeout - Set ACK timeout on PCU More...
 
unsigned int ath5k_hw_get_ack_timeout (struct ath5k_hw *ah)
 ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec More...
 
int ath5k_hw_set_cts_timeout (struct ath5k_hw *ah, unsigned int timeout)
 ath5k_hw_set_cts_timeout - Set CTS timeout on PCU More...
 
unsigned int ath5k_hw_get_cts_timeout (struct ath5k_hw *ah)
 ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec More...
 
int ath5k_hw_reset_key (struct ath5k_hw *ah, u16 entry)
 
int ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
 
int ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
 
u32 ath5k_hw_num_tx_pending (struct ath5k_hw *ah)
 
void ath5k_hw_release_tx_queue (struct ath5k_hw *ah)
 
int ath5k_hw_reset_tx_queue (struct ath5k_hw *ah)
 
int ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time)
 
int ath5k_hw_init_desc_functions (struct ath5k_hw *ah)
 
int ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio)
 
int ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio)
 
u32 ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio)
 
int ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val)
 
void ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level)
 
void ath5k_rfkill_hw_start (struct ath5k_hw *ah)
 
void ath5k_rfkill_hw_stop (struct ath5k_hw *ah)
 
int ath5k_hw_set_capabilities (struct ath5k_hw *ah)
 
int ath5k_hw_get_capability (struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result)
 
int ath5k_hw_enable_pspoll (struct ath5k_hw *ah, u8 *bssid, u16 assoc_id)
 
int ath5k_hw_disable_pspoll (struct ath5k_hw *ah)
 
int ath5k_hw_write_initvals (struct ath5k_hw *ah, u8 mode, int change_channel)
 
int ath5k_hw_rfregs_init (struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode)
 
int ath5k_hw_rfgain_init (struct ath5k_hw *ah, unsigned int freq)
 
enum ath5k_rfgain ath5k_hw_gainf_calibrate (struct ath5k_hw *ah)
 
int ath5k_hw_rfgain_opt_init (struct ath5k_hw *ah)
 
int ath5k_channel_ok (struct ath5k_hw *ah, u16 freq, unsigned int flags)
 
int ath5k_hw_channel (struct ath5k_hw *ah, struct net80211_channel *channel)
 
int ath5k_hw_phy_calibrate (struct ath5k_hw *ah, struct net80211_channel *channel)
 
int ath5k_hw_noise_floor_calibration (struct ath5k_hw *ah, short freq)
 ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration More...
 
u16 ath5k_hw_radio_revision (struct ath5k_hw *ah, unsigned int chan)
 
void ath5k_hw_set_def_antenna (struct ath5k_hw *ah, unsigned int ant)
 
unsigned int ath5k_hw_get_def_antenna (struct ath5k_hw *ah)
 
int ath5k_hw_phy_disable (struct ath5k_hw *ah)
 
int ath5k_hw_txpower (struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower)
 
int ath5k_hw_set_txpower_limit (struct ath5k_hw *ah, u8 ee_mode, u8 txpower)
 
static unsigned int ath5k_hw_htoclock (unsigned int usec, int turbo)
 
static unsigned int ath5k_hw_clocktoh (unsigned int clock, int turbo)
 
static u32 ath5k_hw_reg_read (struct ath5k_hw *ah, u16 reg)
 
static void ath5k_hw_reg_write (struct ath5k_hw *ah, u32 val, u16 reg)
 
static u32 ath5k_hw_bitswap (u32 val, unsigned int bits)
 

Macro Definition Documentation

◆ ERRFILE

#define ERRFILE   ERRFILE_ath5k

Definition at line 35 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5210

#define PCI_DEVICE_ID_ATHEROS_AR5210   0x0007 /* AR5210 */

Definition at line 44 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5311

#define PCI_DEVICE_ID_ATHEROS_AR5311   0x0011 /* AR5311 */

Definition at line 45 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5211

#define PCI_DEVICE_ID_ATHEROS_AR5211   0x0012 /* AR5211 */

Definition at line 46 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212

#define PCI_DEVICE_ID_ATHEROS_AR5212   0x0013 /* AR5212 */

Definition at line 47 of file ath5k.h.

◆ PCI_DEVICE_ID_3COM_3CRDAG675

#define PCI_DEVICE_ID_3COM_3CRDAG675   0x0013 /* 3CRDAG675 (Atheros AR5212) */

Definition at line 48 of file ath5k.h.

◆ PCI_DEVICE_ID_3COM_2_3CRPAG175

#define PCI_DEVICE_ID_3COM_2_3CRPAG175   0x0013 /* 3CRPAG175 (Atheros AR5212) */

Definition at line 49 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5210_AP

#define PCI_DEVICE_ID_ATHEROS_AR5210_AP   0x0207 /* AR5210 (Early) */

Definition at line 50 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_IBM

#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM   0x1014 /* AR5212 (IBM MiniPCI) */

Definition at line 51 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT

#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */

Definition at line 52 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT

#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */

Definition at line 53 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT

#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */

Definition at line 54 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_FPGA

#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA   0xf013 /* AR5212 (emulation board) */

Definition at line 55 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY

#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY   0xff12 /* AR5211 (emulation board) */

Definition at line 56 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B

#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */

Definition at line 57 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5312_REV2

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2   0x0052 /* AR5312 WMAC (AP31) */

Definition at line 58 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5312_REV7

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7   0x0057 /* AR5312 WMAC (AP30-040) */

Definition at line 59 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5312_REV8

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8   0x0058 /* AR5312 WMAC (AP43-030) */

Definition at line 60 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0014

#define PCI_DEVICE_ID_ATHEROS_AR5212_0014   0x0014 /* AR5212 compatible */

Definition at line 61 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0015

#define PCI_DEVICE_ID_ATHEROS_AR5212_0015   0x0015 /* AR5212 compatible */

Definition at line 62 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0016

#define PCI_DEVICE_ID_ATHEROS_AR5212_0016   0x0016 /* AR5212 compatible */

Definition at line 63 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0017

#define PCI_DEVICE_ID_ATHEROS_AR5212_0017   0x0017 /* AR5212 compatible */

Definition at line 64 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0018

#define PCI_DEVICE_ID_ATHEROS_AR5212_0018   0x0018 /* AR5212 compatible */

Definition at line 65 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5212_0019

#define PCI_DEVICE_ID_ATHEROS_AR5212_0019   0x0019 /* AR5212 compatible */

Definition at line 66 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR2413

#define PCI_DEVICE_ID_ATHEROS_AR2413   0x001a /* AR2413 (Griffin-lite) */

Definition at line 67 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5413

#define PCI_DEVICE_ID_ATHEROS_AR5413   0x001b /* AR5413 (Eagle) */

Definition at line 68 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5424

#define PCI_DEVICE_ID_ATHEROS_AR5424   0x001c /* AR5424 (Condor PCI-E) */

Definition at line 69 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5416

#define PCI_DEVICE_ID_ATHEROS_AR5416   0x0023 /* AR5416 */

Definition at line 70 of file ath5k.h.

◆ PCI_DEVICE_ID_ATHEROS_AR5418

#define PCI_DEVICE_ID_ATHEROS_AR5418   0x0024 /* AR5418 */

Definition at line 71 of file ath5k.h.

◆ AR5K_REG_SM

#define AR5K_REG_SM (   _val,
  _flags 
)    (((_val) << _flags##_S) & (_flags))

Definition at line 84 of file ath5k.h.

◆ AR5K_REG_MS

#define AR5K_REG_MS (   _val,
  _flags 
)    (((_val) & (_flags)) >> _flags##_S)

Definition at line 88 of file ath5k.h.

◆ AR5K_REG_WRITE_BITS

#define AR5K_REG_WRITE_BITS (   ah,
  _reg,
  _flags,
  _val 
)
Value:
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
(((_val) << _flags##_S) & (_flags)), _reg)
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

Definition at line 96 of file ath5k.h.

◆ AR5K_REG_MASKED_BITS

#define AR5K_REG_MASKED_BITS (   ah,
  _reg,
  _flags,
  _mask 
)
Value:
(_mask)) | (_flags), _reg)
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

Definition at line 100 of file ath5k.h.

◆ AR5K_REG_ENABLE_BITS

#define AR5K_REG_ENABLE_BITS (   ah,
  _reg,
  _flags 
)    ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)

Definition at line 104 of file ath5k.h.

◆ AR5K_REG_DISABLE_BITS

#define AR5K_REG_DISABLE_BITS (   ah,
  _reg,
  _flags 
)    ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)

Definition at line 107 of file ath5k.h.

◆ AR5K_PHY_READ

#define AR5K_PHY_READ (   ah,
  _reg 
)    ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))

Definition at line 111 of file ath5k.h.

◆ AR5K_PHY_WRITE

#define AR5K_PHY_WRITE (   ah,
  _reg,
  _val 
)    ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))

Definition at line 114 of file ath5k.h.

◆ AR5K_REG_READ_Q

#define AR5K_REG_READ_Q (   ah,
  _reg,
  _queue 
)    (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \

Definition at line 118 of file ath5k.h.

◆ AR5K_REG_WRITE_Q

#define AR5K_REG_WRITE_Q (   ah,
  _reg,
  _queue 
)    ath5k_hw_reg_write(ah, (1 << _queue), _reg)

Definition at line 121 of file ath5k.h.

◆ AR5K_Q_ENABLE_BITS

#define AR5K_Q_ENABLE_BITS (   _reg,
  _queue 
)
Value:
do { \
_reg |= 1 << _queue; \
} while (0)

Definition at line 124 of file ath5k.h.

◆ AR5K_Q_DISABLE_BITS

#define AR5K_Q_DISABLE_BITS (   _reg,
  _queue 
)
Value:
do { \
_reg &= ~(1 << _queue); \
} while (0)

Definition at line 128 of file ath5k.h.

◆ AR5K_REG_WAIT

#define AR5K_REG_WAIT (   _i)
Value:
do { \
if (_i % 64) \
udelay(1); \
} while (0)

Definition at line 133 of file ath5k.h.

◆ AR5K_INI_RFGAIN_5GHZ

#define AR5K_INI_RFGAIN_5GHZ   0

Definition at line 139 of file ath5k.h.

◆ AR5K_INI_RFGAIN_2GHZ

#define AR5K_INI_RFGAIN_2GHZ   1

Definition at line 140 of file ath5k.h.

◆ AR5K_INI_VAL_11A

#define AR5K_INI_VAL_11A   0

Definition at line 143 of file ath5k.h.

◆ AR5K_INI_VAL_11A_TURBO

#define AR5K_INI_VAL_11A_TURBO   1

Definition at line 144 of file ath5k.h.

◆ AR5K_INI_VAL_11B

#define AR5K_INI_VAL_11B   2

Definition at line 145 of file ath5k.h.

◆ AR5K_INI_VAL_11G

#define AR5K_INI_VAL_11G   3

Definition at line 146 of file ath5k.h.

◆ AR5K_INI_VAL_11G_TURBO

#define AR5K_INI_VAL_11G_TURBO   4

Definition at line 147 of file ath5k.h.

◆ AR5K_INI_VAL_XR

#define AR5K_INI_VAL_XR   0

Definition at line 148 of file ath5k.h.

◆ AR5K_INI_VAL_MAX

#define AR5K_INI_VAL_MAX   5

Definition at line 149 of file ath5k.h.

◆ AR5K_LOW_ID

#define AR5K_LOW_ID (   _a)
Value:
( \
(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
)

Definition at line 152 of file ath5k.h.

◆ AR5K_HIGH_ID

#define AR5K_HIGH_ID (   _a)    ((_a)[4] | (_a)[5] << 8)

Definition at line 156 of file ath5k.h.

◆ IEEE80211_MAX_LEN

#define IEEE80211_MAX_LEN   2352

Definition at line 158 of file ath5k.h.

◆ AR5K_TUNE_DMA_BEACON_RESP

#define AR5K_TUNE_DMA_BEACON_RESP   2

Definition at line 163 of file ath5k.h.

◆ AR5K_TUNE_SW_BEACON_RESP

#define AR5K_TUNE_SW_BEACON_RESP   10

Definition at line 164 of file ath5k.h.

◆ AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF

#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF   0

Definition at line 165 of file ath5k.h.

◆ AR5K_TUNE_RADAR_ALERT

#define AR5K_TUNE_RADAR_ALERT   0

Definition at line 166 of file ath5k.h.

◆ AR5K_TUNE_MIN_TX_FIFO_THRES

#define AR5K_TUNE_MIN_TX_FIFO_THRES   1

Definition at line 167 of file ath5k.h.

◆ AR5K_TUNE_MAX_TX_FIFO_THRES

#define AR5K_TUNE_MAX_TX_FIFO_THRES   ((IEEE80211_MAX_LEN / 64) + 1)

Definition at line 168 of file ath5k.h.

◆ AR5K_TUNE_REGISTER_TIMEOUT

#define AR5K_TUNE_REGISTER_TIMEOUT   20000

Definition at line 169 of file ath5k.h.

◆ AR5K_TUNE_RSSI_THRES

#define AR5K_TUNE_RSSI_THRES   129

Definition at line 172 of file ath5k.h.

◆ AR5K_TUNE_BMISS_THRES

#define AR5K_TUNE_BMISS_THRES   7

Definition at line 178 of file ath5k.h.

◆ AR5K_TUNE_REGISTER_DWELL_TIME

#define AR5K_TUNE_REGISTER_DWELL_TIME   20000

Definition at line 179 of file ath5k.h.

◆ AR5K_TUNE_BEACON_INTERVAL

#define AR5K_TUNE_BEACON_INTERVAL   100

Definition at line 180 of file ath5k.h.

◆ AR5K_TUNE_AIFS

#define AR5K_TUNE_AIFS   2

Definition at line 181 of file ath5k.h.

◆ AR5K_TUNE_AIFS_11B

#define AR5K_TUNE_AIFS_11B   2

Definition at line 182 of file ath5k.h.

◆ AR5K_TUNE_AIFS_XR

#define AR5K_TUNE_AIFS_XR   0

Definition at line 183 of file ath5k.h.

◆ AR5K_TUNE_CWMIN

#define AR5K_TUNE_CWMIN   15

Definition at line 184 of file ath5k.h.

◆ AR5K_TUNE_CWMIN_11B

#define AR5K_TUNE_CWMIN_11B   31

Definition at line 185 of file ath5k.h.

◆ AR5K_TUNE_CWMIN_XR

#define AR5K_TUNE_CWMIN_XR   3

Definition at line 186 of file ath5k.h.

◆ AR5K_TUNE_CWMAX

#define AR5K_TUNE_CWMAX   1023

Definition at line 187 of file ath5k.h.

◆ AR5K_TUNE_CWMAX_11B

#define AR5K_TUNE_CWMAX_11B   1023

Definition at line 188 of file ath5k.h.

◆ AR5K_TUNE_CWMAX_XR

#define AR5K_TUNE_CWMAX_XR   7

Definition at line 189 of file ath5k.h.

◆ AR5K_TUNE_NOISE_FLOOR

#define AR5K_TUNE_NOISE_FLOOR   -72

Definition at line 190 of file ath5k.h.

◆ AR5K_TUNE_MAX_TXPOWER

#define AR5K_TUNE_MAX_TXPOWER   63

Definition at line 191 of file ath5k.h.

◆ AR5K_TUNE_DEFAULT_TXPOWER

#define AR5K_TUNE_DEFAULT_TXPOWER   25

Definition at line 192 of file ath5k.h.

◆ AR5K_TUNE_TPC_TXPOWER

#define AR5K_TUNE_TPC_TXPOWER   0

Definition at line 193 of file ath5k.h.

◆ AR5K_TUNE_ANT_DIVERSITY

#define AR5K_TUNE_ANT_DIVERSITY   1

Definition at line 194 of file ath5k.h.

◆ AR5K_TUNE_HWTXTRIES

#define AR5K_TUNE_HWTXTRIES   4

Definition at line 195 of file ath5k.h.

◆ AR5K_INIT_CARR_SENSE_EN

#define AR5K_INIT_CARR_SENSE_EN   1

Definition at line 197 of file ath5k.h.

◆ AR5K_INIT_CFG

#define AR5K_INIT_CFG   0x00000000

Definition at line 205 of file ath5k.h.

◆ AR5K_INIT_CYCRSSI_THR1

#define AR5K_INIT_CYCRSSI_THR1   2

Definition at line 209 of file ath5k.h.

◆ AR5K_INIT_TX_LATENCY

#define AR5K_INIT_TX_LATENCY   502

Definition at line 210 of file ath5k.h.

◆ AR5K_INIT_USEC

#define AR5K_INIT_USEC   39

Definition at line 211 of file ath5k.h.

◆ AR5K_INIT_USEC_TURBO

#define AR5K_INIT_USEC_TURBO   79

Definition at line 212 of file ath5k.h.

◆ AR5K_INIT_USEC_32

#define AR5K_INIT_USEC_32   31

Definition at line 213 of file ath5k.h.

◆ AR5K_INIT_SLOT_TIME

#define AR5K_INIT_SLOT_TIME   396

Definition at line 214 of file ath5k.h.

◆ AR5K_INIT_SLOT_TIME_TURBO

#define AR5K_INIT_SLOT_TIME_TURBO   480

Definition at line 215 of file ath5k.h.

◆ AR5K_INIT_ACK_CTS_TIMEOUT

#define AR5K_INIT_ACK_CTS_TIMEOUT   1024

Definition at line 216 of file ath5k.h.

◆ AR5K_INIT_ACK_CTS_TIMEOUT_TURBO

#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO   0x08000800

Definition at line 217 of file ath5k.h.

◆ AR5K_INIT_PROG_IFS

#define AR5K_INIT_PROG_IFS   920

Definition at line 218 of file ath5k.h.

◆ AR5K_INIT_PROG_IFS_TURBO

#define AR5K_INIT_PROG_IFS_TURBO   960

Definition at line 219 of file ath5k.h.

◆ AR5K_INIT_EIFS

#define AR5K_INIT_EIFS   3440

Definition at line 220 of file ath5k.h.

◆ AR5K_INIT_EIFS_TURBO

#define AR5K_INIT_EIFS_TURBO   6880

Definition at line 221 of file ath5k.h.

◆ AR5K_INIT_SIFS

#define AR5K_INIT_SIFS   560

Definition at line 222 of file ath5k.h.

◆ AR5K_INIT_SIFS_TURBO

#define AR5K_INIT_SIFS_TURBO   480

Definition at line 223 of file ath5k.h.

◆ AR5K_INIT_SH_RETRY

#define AR5K_INIT_SH_RETRY   10

Definition at line 224 of file ath5k.h.

◆ AR5K_INIT_LG_RETRY

#define AR5K_INIT_LG_RETRY   AR5K_INIT_SH_RETRY

Definition at line 225 of file ath5k.h.

◆ AR5K_INIT_SSH_RETRY

#define AR5K_INIT_SSH_RETRY   32

Definition at line 226 of file ath5k.h.

◆ AR5K_INIT_SLG_RETRY

#define AR5K_INIT_SLG_RETRY   AR5K_INIT_SSH_RETRY

Definition at line 227 of file ath5k.h.

◆ AR5K_INIT_TX_RETRY

#define AR5K_INIT_TX_RETRY   10

Definition at line 228 of file ath5k.h.

◆ AR5K_INIT_TRANSMIT_LATENCY

#define AR5K_INIT_TRANSMIT_LATENCY
Value:
( \
)
#define AR5K_INIT_USEC
Definition: ath5k.h:211
#define AR5K_INIT_TX_LATENCY
Definition: ath5k.h:210
#define AR5K_INIT_USEC_32
Definition: ath5k.h:213

Definition at line 230 of file ath5k.h.

◆ AR5K_INIT_TRANSMIT_LATENCY_TURBO

#define AR5K_INIT_TRANSMIT_LATENCY_TURBO
Value:
( \
)
#define AR5K_INIT_USEC_TURBO
Definition: ath5k.h:212
#define AR5K_INIT_TX_LATENCY
Definition: ath5k.h:210
#define AR5K_INIT_USEC_32
Definition: ath5k.h:213

Definition at line 234 of file ath5k.h.

◆ AR5K_INIT_PROTO_TIME_CNTRL

#define AR5K_INIT_PROTO_TIME_CNTRL
Value:
( \
)
#define AR5K_INIT_CARR_SENSE_EN
Definition: ath5k.h:197
#define AR5K_INIT_EIFS
Definition: ath5k.h:220
#define AR5K_INIT_PROG_IFS
Definition: ath5k.h:218

Definition at line 238 of file ath5k.h.

◆ AR5K_INIT_PROTO_TIME_CNTRL_TURBO

#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO
Value:
( \
)
#define AR5K_INIT_PROG_IFS_TURBO
Definition: ath5k.h:219
#define AR5K_INIT_EIFS_TURBO
Definition: ath5k.h:221
#define AR5K_INIT_CARR_SENSE_EN
Definition: ath5k.h:197

Definition at line 242 of file ath5k.h.

◆ AR5K_TXQ_USEDEFAULT

#define AR5K_TXQ_USEDEFAULT   ((u32) -1)

Definition at line 248 of file ath5k.h.

◆ AR5K_SREV_UNKNOWN

#define AR5K_SREV_UNKNOWN   0xffff

Definition at line 286 of file ath5k.h.

◆ AR5K_SREV_AR5210

#define AR5K_SREV_AR5210   0x00 /* Crete */

Definition at line 288 of file ath5k.h.

◆ AR5K_SREV_AR5311

#define AR5K_SREV_AR5311   0x10 /* Maui 1 */

Definition at line 289 of file ath5k.h.

◆ AR5K_SREV_AR5311A

#define AR5K_SREV_AR5311A   0x20 /* Maui 2 */

Definition at line 290 of file ath5k.h.

◆ AR5K_SREV_AR5311B

#define AR5K_SREV_AR5311B   0x30 /* Spirit */

Definition at line 291 of file ath5k.h.

◆ AR5K_SREV_AR5211

#define AR5K_SREV_AR5211   0x40 /* Oahu */

Definition at line 292 of file ath5k.h.

◆ AR5K_SREV_AR5212

#define AR5K_SREV_AR5212   0x50 /* Venice */

Definition at line 293 of file ath5k.h.

◆ AR5K_SREV_AR5213

#define AR5K_SREV_AR5213   0x55 /* ??? */

Definition at line 294 of file ath5k.h.

◆ AR5K_SREV_AR5213A

#define AR5K_SREV_AR5213A   0x59 /* Hainan */

Definition at line 295 of file ath5k.h.

◆ AR5K_SREV_AR2413

#define AR5K_SREV_AR2413   0x78 /* Griffin lite */

Definition at line 296 of file ath5k.h.

◆ AR5K_SREV_AR2414

#define AR5K_SREV_AR2414   0x70 /* Griffin */

Definition at line 297 of file ath5k.h.

◆ AR5K_SREV_AR5424

#define AR5K_SREV_AR5424   0x90 /* Condor */

Definition at line 298 of file ath5k.h.

◆ AR5K_SREV_AR5413

#define AR5K_SREV_AR5413   0xa4 /* Eagle lite */

Definition at line 299 of file ath5k.h.

◆ AR5K_SREV_AR5414

#define AR5K_SREV_AR5414   0xa0 /* Eagle */

Definition at line 300 of file ath5k.h.

◆ AR5K_SREV_AR2415

#define AR5K_SREV_AR2415   0xb0 /* Talon */

Definition at line 301 of file ath5k.h.

◆ AR5K_SREV_AR5416

#define AR5K_SREV_AR5416   0xc0 /* PCI-E */

Definition at line 302 of file ath5k.h.

◆ AR5K_SREV_AR5418

#define AR5K_SREV_AR5418   0xca /* PCI-E */

Definition at line 303 of file ath5k.h.

◆ AR5K_SREV_AR2425

#define AR5K_SREV_AR2425   0xe0 /* Swan */

Definition at line 304 of file ath5k.h.

◆ AR5K_SREV_AR2417

#define AR5K_SREV_AR2417   0xf0 /* Nala */

Definition at line 305 of file ath5k.h.

◆ AR5K_SREV_RAD_5110

#define AR5K_SREV_RAD_5110   0x00

Definition at line 307 of file ath5k.h.

◆ AR5K_SREV_RAD_5111

#define AR5K_SREV_RAD_5111   0x10

Definition at line 308 of file ath5k.h.

◆ AR5K_SREV_RAD_5111A

#define AR5K_SREV_RAD_5111A   0x15

Definition at line 309 of file ath5k.h.

◆ AR5K_SREV_RAD_2111

#define AR5K_SREV_RAD_2111   0x20

Definition at line 310 of file ath5k.h.

◆ AR5K_SREV_RAD_5112

#define AR5K_SREV_RAD_5112   0x30

Definition at line 311 of file ath5k.h.

◆ AR5K_SREV_RAD_5112A

#define AR5K_SREV_RAD_5112A   0x35

Definition at line 312 of file ath5k.h.

◆ AR5K_SREV_RAD_5112B

#define AR5K_SREV_RAD_5112B   0x36

Definition at line 313 of file ath5k.h.

◆ AR5K_SREV_RAD_2112

#define AR5K_SREV_RAD_2112   0x40

Definition at line 314 of file ath5k.h.

◆ AR5K_SREV_RAD_2112A

#define AR5K_SREV_RAD_2112A   0x45

Definition at line 315 of file ath5k.h.

◆ AR5K_SREV_RAD_2112B

#define AR5K_SREV_RAD_2112B   0x46

Definition at line 316 of file ath5k.h.

◆ AR5K_SREV_RAD_2413

#define AR5K_SREV_RAD_2413   0x50

Definition at line 317 of file ath5k.h.

◆ AR5K_SREV_RAD_5413

#define AR5K_SREV_RAD_5413   0x60

Definition at line 318 of file ath5k.h.

◆ AR5K_SREV_RAD_2316

#define AR5K_SREV_RAD_2316   0x70 /* Cobra SoC */

Definition at line 319 of file ath5k.h.

◆ AR5K_SREV_RAD_2317

#define AR5K_SREV_RAD_2317   0x80

Definition at line 320 of file ath5k.h.

◆ AR5K_SREV_RAD_5424

#define AR5K_SREV_RAD_5424   0xa0 /* Mostly same as 5413 */

Definition at line 321 of file ath5k.h.

◆ AR5K_SREV_RAD_2425

#define AR5K_SREV_RAD_2425   0xa2

Definition at line 322 of file ath5k.h.

◆ AR5K_SREV_RAD_5133

#define AR5K_SREV_RAD_5133   0xc0

Definition at line 323 of file ath5k.h.

◆ AR5K_SREV_PHY_5211

#define AR5K_SREV_PHY_5211   0x30

Definition at line 325 of file ath5k.h.

◆ AR5K_SREV_PHY_5212

#define AR5K_SREV_PHY_5212   0x41

Definition at line 326 of file ath5k.h.

◆ AR5K_SREV_PHY_5212A

#define AR5K_SREV_PHY_5212A   0x42

Definition at line 327 of file ath5k.h.

◆ AR5K_SREV_PHY_5212B

#define AR5K_SREV_PHY_5212B   0x43

Definition at line 328 of file ath5k.h.

◆ AR5K_SREV_PHY_2413

#define AR5K_SREV_PHY_2413   0x45

Definition at line 329 of file ath5k.h.

◆ AR5K_SREV_PHY_5413

#define AR5K_SREV_PHY_5413   0x61

Definition at line 330 of file ath5k.h.

◆ AR5K_SREV_PHY_2425

#define AR5K_SREV_PHY_2425   0x70

Definition at line 331 of file ath5k.h.

◆ MODULATION_XR

#define MODULATION_XR   0x00000200

Definition at line 349 of file ath5k.h.

◆ MODULATION_TURBO

#define MODULATION_TURBO   0x00000080

Definition at line 389 of file ath5k.h.

◆ AR5K_TXSTAT_ALTRATE

#define AR5K_TXSTAT_ALTRATE   0x80

Definition at line 430 of file ath5k.h.

◆ AR5K_TXERR_XRETRY

#define AR5K_TXERR_XRETRY   0x01

Definition at line 431 of file ath5k.h.

◆ AR5K_TXERR_FILT

#define AR5K_TXERR_FILT   0x02

Definition at line 432 of file ath5k.h.

◆ AR5K_TXERR_FIFO

#define AR5K_TXERR_FIFO   0x04

Definition at line 433 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXOKINT_ENABLE

#define AR5K_TXQ_FLAG_TXOKINT_ENABLE   0x0001 /* Enable TXOK interrupt */

Definition at line 488 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXERRINT_ENABLE

#define AR5K_TXQ_FLAG_TXERRINT_ENABLE   0x0002 /* Enable TXERR interrupt */

Definition at line 489 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXEOLINT_ENABLE

#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE   0x0004 /* Enable TXEOL interrupt -not used- */

Definition at line 490 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXDESCINT_ENABLE

#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE   0x0008 /* Enable TXDESC interrupt -not used- */

Definition at line 491 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXURNINT_ENABLE

#define AR5K_TXQ_FLAG_TXURNINT_ENABLE   0x0010 /* Enable TXURN interrupt */

Definition at line 492 of file ath5k.h.

◆ AR5K_TXQ_FLAG_CBRORNINT_ENABLE

#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE   0x0020 /* Enable CBRORN interrupt */

Definition at line 493 of file ath5k.h.

◆ AR5K_TXQ_FLAG_CBRURNINT_ENABLE

#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE   0x0040 /* Enable CBRURN interrupt */

Definition at line 494 of file ath5k.h.

◆ AR5K_TXQ_FLAG_QTRIGINT_ENABLE

#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE   0x0080 /* Enable QTRIG interrupt */

Definition at line 495 of file ath5k.h.

◆ AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE

#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE   0x0100 /* Enable TXNOFRM interrupt */

Definition at line 496 of file ath5k.h.

◆ AR5K_TXQ_FLAG_BACKOFF_DISABLE

#define AR5K_TXQ_FLAG_BACKOFF_DISABLE   0x0200 /* Disable random post-backoff */

Definition at line 497 of file ath5k.h.

◆ AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE

#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE   0x0300 /* Enable ready time expiry policy (?)*/

Definition at line 498 of file ath5k.h.

◆ AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE

#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE   0x0800 /* Enable backoff while bursting */

Definition at line 499 of file ath5k.h.

◆ AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS

#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS   0x1000 /* Disable backoff while bursting */

Definition at line 500 of file ath5k.h.

◆ AR5K_TXQ_FLAG_COMPRESSION_ENABLE

#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE   0x2000 /* Enable hw compression -not implemented-*/

Definition at line 501 of file ath5k.h.

◆ AR5K_TXPOWER_OFDM

#define AR5K_TXPOWER_OFDM (   _r,
  _v 
)
Value:
( \
((0 & 1) << ((_v) + 6)) | \
(((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
)
uint8_t ah
Definition: registers.h:85

Definition at line 536 of file ath5k.h.

◆ AR5K_TXPOWER_CCK

#define AR5K_TXPOWER_CCK (   _r,
  _v 
)
Value:
( \
(ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
)
uint8_t ah
Definition: registers.h:85

Definition at line 541 of file ath5k.h.

◆ AR5K_RXERR_CRC

#define AR5K_RXERR_CRC   0x01

Definition at line 579 of file ath5k.h.

◆ AR5K_RXERR_PHY

#define AR5K_RXERR_PHY   0x02

Definition at line 580 of file ath5k.h.

◆ AR5K_RXERR_FIFO

#define AR5K_RXERR_FIFO   0x04

Definition at line 581 of file ath5k.h.

◆ AR5K_RXERR_DECRYPT

#define AR5K_RXERR_DECRYPT   0x08

Definition at line 582 of file ath5k.h.

◆ AR5K_RXERR_MIC

#define AR5K_RXERR_MIC   0x10

Definition at line 583 of file ath5k.h.

◆ AR5K_RXKEYIX_INVALID

#define AR5K_RXKEYIX_INVALID   ((u8) - 1)

Definition at line 584 of file ath5k.h.

◆ AR5K_TXKEYIX_INVALID

#define AR5K_TXKEYIX_INVALID   ((u32) - 1)

Definition at line 585 of file ath5k.h.

◆ TSF_TO_TU

#define TSF_TO_TU (   _tsf)    (u32)((_tsf) >> 10)

Definition at line 595 of file ath5k.h.

◆ AR5K_SLOT_TIME_9

#define AR5K_SLOT_TIME_9   396

Definition at line 623 of file ath5k.h.

◆ AR5K_SLOT_TIME_20

#define AR5K_SLOT_TIME_20   880

Definition at line 624 of file ath5k.h.

◆ AR5K_SLOT_TIME_MAX

#define AR5K_SLOT_TIME_MAX   0xffff

Definition at line 625 of file ath5k.h.

◆ CHANNEL_CW_INT

#define CHANNEL_CW_INT   0x0008 /* Contention Window interference detected */

Definition at line 628 of file ath5k.h.

◆ CHANNEL_TURBO

#define CHANNEL_TURBO   0x0010 /* Turbo Channel */

Definition at line 629 of file ath5k.h.

◆ CHANNEL_CCK

#define CHANNEL_CCK   0x0020 /* CCK channel */

Definition at line 630 of file ath5k.h.

◆ CHANNEL_OFDM

#define CHANNEL_OFDM   0x0040 /* OFDM channel */

Definition at line 631 of file ath5k.h.

◆ CHANNEL_2GHZ

#define CHANNEL_2GHZ   0x0080 /* 2GHz channel. */

Definition at line 632 of file ath5k.h.

◆ CHANNEL_5GHZ

#define CHANNEL_5GHZ   0x0100 /* 5GHz channel */

Definition at line 633 of file ath5k.h.

◆ CHANNEL_PASSIVE

#define CHANNEL_PASSIVE   0x0200 /* Only passive scan allowed */

Definition at line 634 of file ath5k.h.

◆ CHANNEL_DYN

#define CHANNEL_DYN   0x0400 /* Dynamic CCK-OFDM channel (for g operation) */

Definition at line 635 of file ath5k.h.

◆ CHANNEL_XR

#define CHANNEL_XR   0x0800 /* XR channel */

Definition at line 636 of file ath5k.h.

◆ CHANNEL_A

#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)

Definition at line 638 of file ath5k.h.

◆ CHANNEL_B

#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)

Definition at line 639 of file ath5k.h.

◆ CHANNEL_G

#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)

Definition at line 640 of file ath5k.h.

◆ CHANNEL_T

#define CHANNEL_T   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)

Definition at line 641 of file ath5k.h.

◆ CHANNEL_TG

#define CHANNEL_TG   (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)

Definition at line 642 of file ath5k.h.

◆ CHANNEL_108A

#define CHANNEL_108A   CHANNEL_T

Definition at line 643 of file ath5k.h.

◆ CHANNEL_108G

#define CHANNEL_108G   CHANNEL_TG

Definition at line 644 of file ath5k.h.

◆ CHANNEL_X

#define CHANNEL_X   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)

Definition at line 645 of file ath5k.h.

◆ CHANNEL_ALL

#define CHANNEL_ALL
Value:
CHANNEL_TURBO)
#define CHANNEL_CCK
Definition: ath5k.h:630
#define CHANNEL_OFDM
Definition: ath5k.h:631
#define CHANNEL_5GHZ
Definition: ath5k.h:633
#define CHANNEL_2GHZ
Definition: ath5k.h:632

Definition at line 647 of file ath5k.h.

◆ CHANNEL_ALL_NOTURBO

#define CHANNEL_ALL_NOTURBO   (CHANNEL_ALL & ~CHANNEL_TURBO)

Definition at line 650 of file ath5k.h.

◆ CHANNEL_MODES

#define CHANNEL_MODES   CHANNEL_ALL

Definition at line 651 of file ath5k.h.

◆ IS_CHAN_XR

#define IS_CHAN_XR (   _c)    ((_c->hw_value & CHANNEL_XR) != 0)

Definition at line 657 of file ath5k.h.

◆ IS_CHAN_B

#define IS_CHAN_B (   _c)    ((_c->hw_value & CHANNEL_B) != 0)

Definition at line 658 of file ath5k.h.

◆ AR5K_MAX_RATES

#define AR5K_MAX_RATES   32

Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.

The rate code is used to get the RX rate or set the TX rate on the hardware descriptors. It is also used for internal modulation control and settings.

This is the hardware rate map we are aware of:

rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 rate_kbps 3000 1000 ? ? ? 2000 500 48000

rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?

rate_code 17 18 19 20 21 22 23 24 rate_kbps ? ? ? ? ? ? ? 11000

rate_code 25 26 27 28 29 30 31 32 rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?

"S" indicates CCK rates with short preamble.

AR5211 has different rate codes for CCK (802.11B) rates. It only uses the lowest 4 bits, so they are the same as below with a 0xF mask. (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). We handle this in ath5k_setup_bands().

Definition at line 703 of file ath5k.h.

◆ ATH5K_RATE_CODE_1M

#define ATH5K_RATE_CODE_1M   0x1B

Definition at line 706 of file ath5k.h.

◆ ATH5K_RATE_CODE_2M

#define ATH5K_RATE_CODE_2M   0x1A

Definition at line 707 of file ath5k.h.

◆ ATH5K_RATE_CODE_5_5M

#define ATH5K_RATE_CODE_5_5M   0x19

Definition at line 708 of file ath5k.h.

◆ ATH5K_RATE_CODE_11M

#define ATH5K_RATE_CODE_11M   0x18

Definition at line 709 of file ath5k.h.

◆ ATH5K_RATE_CODE_6M

#define ATH5K_RATE_CODE_6M   0x0B

Definition at line 711 of file ath5k.h.

◆ ATH5K_RATE_CODE_9M

#define ATH5K_RATE_CODE_9M   0x0F

Definition at line 712 of file ath5k.h.

◆ ATH5K_RATE_CODE_12M

#define ATH5K_RATE_CODE_12M   0x0A

Definition at line 713 of file ath5k.h.

◆ ATH5K_RATE_CODE_18M

#define ATH5K_RATE_CODE_18M   0x0E

Definition at line 714 of file ath5k.h.

◆ ATH5K_RATE_CODE_24M

#define ATH5K_RATE_CODE_24M   0x09

Definition at line 715 of file ath5k.h.

◆ ATH5K_RATE_CODE_36M

#define ATH5K_RATE_CODE_36M   0x0D

Definition at line 716 of file ath5k.h.

◆ ATH5K_RATE_CODE_48M

#define ATH5K_RATE_CODE_48M   0x08

Definition at line 717 of file ath5k.h.

◆ ATH5K_RATE_CODE_54M

#define ATH5K_RATE_CODE_54M   0x0C

Definition at line 718 of file ath5k.h.

◆ ATH5K_RATE_CODE_XR_500K

#define ATH5K_RATE_CODE_XR_500K   0x07

Definition at line 720 of file ath5k.h.

◆ ATH5K_RATE_CODE_XR_1M

#define ATH5K_RATE_CODE_XR_1M   0x02

Definition at line 721 of file ath5k.h.

◆ ATH5K_RATE_CODE_XR_2M

#define ATH5K_RATE_CODE_XR_2M   0x06

Definition at line 722 of file ath5k.h.

◆ ATH5K_RATE_CODE_XR_3M

#define ATH5K_RATE_CODE_XR_3M   0x01

Definition at line 723 of file ath5k.h.

◆ AR5K_SET_SHORT_PREAMBLE

#define AR5K_SET_SHORT_PREAMBLE   0x04

Definition at line 726 of file ath5k.h.

◆ AR5K_KEYCACHE_SIZE

#define AR5K_KEYCACHE_SIZE   8

Definition at line 732 of file ath5k.h.

◆ AR5K_RSSI_EP_MULTIPLIER

#define AR5K_RSSI_EP_MULTIPLIER   (1<<7)

Definition at line 741 of file ath5k.h.

◆ AR5K_ASSERT_ENTRY

#define AR5K_ASSERT_ENTRY (   _e,
  _s 
)
Value:
do { \
if (_e >= _s) \
return 0; \
} while (0)

Definition at line 743 of file ath5k.h.

◆ AR5K_SOFTLED_PIN

#define AR5K_SOFTLED_PIN   0

Definition at line 875 of file ath5k.h.

◆ AR5K_SOFTLED_ON

#define AR5K_SOFTLED_ON   0

Definition at line 876 of file ath5k.h.

◆ AR5K_SOFTLED_OFF

#define AR5K_SOFTLED_OFF   1

Definition at line 877 of file ath5k.h.

◆ AR5K_MAX_GPIO

#define AR5K_MAX_GPIO   10

Definition at line 949 of file ath5k.h.

◆ AR5K_MAX_RF_BANKS

#define AR5K_MAX_RF_BANKS   8

Definition at line 950 of file ath5k.h.

◆ ah_regdomain

#define ah_regdomain   ah_capabilities.cap_regdomain.reg_current

Definition at line 981 of file ath5k.h.

◆ ah_regdomain_hw

#define ah_regdomain_hw   ah_capabilities.cap_regdomain.reg_hw

Definition at line 982 of file ath5k.h.

◆ ah_modes

#define ah_modes   ah_capabilities.cap_mode

Definition at line 983 of file ath5k.h.

◆ ah_ee_version

#define ah_ee_version   ah_capabilities.cap_eeprom.ee_version

Definition at line 984 of file ath5k.h.

Enumeration Type Documentation

◆ ath5k_version

Enumerator
AR5K_AR5210 
AR5K_AR5211 
AR5K_AR5212 

Definition at line 253 of file ath5k.h.

253  {
254  AR5K_AR5210 = 0,
255  AR5K_AR5211 = 1,
256  AR5K_AR5212 = 2,
257 };

◆ ath5k_radio

Enumerator
AR5K_RF5110 
AR5K_RF5111 
AR5K_RF5112 
AR5K_RF2413 
AR5K_RF5413 
AR5K_RF2316 
AR5K_RF2317 
AR5K_RF2425 

Definition at line 260 of file ath5k.h.

260  {
261  AR5K_RF5110 = 0,
262  AR5K_RF5111 = 1,
263  AR5K_RF5112 = 2,
264  AR5K_RF2413 = 3,
265  AR5K_RF5413 = 4,
266  AR5K_RF2316 = 5,
267  AR5K_RF2317 = 6,
268  AR5K_RF2425 = 7,
269 };

◆ ath5k_srev_type

Enumerator
AR5K_VERSION_MAC 
AR5K_VERSION_RAD 

Definition at line 275 of file ath5k.h.

275  {
278 };

◆ ath5k_driver_mode

Enumerator
AR5K_MODE_11A 
AR5K_MODE_11A_TURBO 
AR5K_MODE_11B 
AR5K_MODE_11G 
AR5K_MODE_11G_TURBO 
AR5K_MODE_XR 

Definition at line 391 of file ath5k.h.

391  {
392  AR5K_MODE_11A = 0,
394  AR5K_MODE_11B = 2,
395  AR5K_MODE_11G = 3,
397  AR5K_MODE_XR = 5,
398 };

◆ anonymous enum

anonymous enum
Enumerator
AR5K_MODE_BIT_11A 
AR5K_MODE_BIT_11A_TURBO 
AR5K_MODE_BIT_11B 
AR5K_MODE_BIT_11G 
AR5K_MODE_BIT_11G_TURBO 
AR5K_MODE_BIT_XR 

Definition at line 400 of file ath5k.h.

◆ ath5k_tx_queue

enum ath5k_tx_queue - Queue types used to classify tx queues.

@AR5K_TX_QUEUE_INACTIVE: q is unused – see ath5k_hw_release_tx_queue @AR5K_TX_QUEUE_DATA: A normal data queue @AR5K_TX_QUEUE_XR_DATA: An XR-data queue @AR5K_TX_QUEUE_BEACON: The beacon queue @AR5K_TX_QUEUE_CAB: The after-beacon queue @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue

Enumerator
AR5K_TX_QUEUE_INACTIVE 
AR5K_TX_QUEUE_DATA 
AR5K_TX_QUEUE_XR_DATA 
AR5K_TX_QUEUE_BEACON 
AR5K_TX_QUEUE_CAB 
AR5K_TX_QUEUE_UAPSD 

Definition at line 444 of file ath5k.h.

◆ ath5k_tx_queue_subtype

Enumerator
AR5K_WME_AC_BK 
AR5K_WME_AC_BE 
AR5K_WME_AC_VI 
AR5K_WME_AC_VO 

Definition at line 460 of file ath5k.h.

460  {
461  AR5K_WME_AC_BK = 0, /*Background traffic*/
462  AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
463  AR5K_WME_AC_VI, /*Video traffic*/
464  AR5K_WME_AC_VO, /*Voice traffic*/
465 };

◆ ath5k_tx_queue_id

Enumerator
AR5K_TX_QUEUE_ID_NOQCU_DATA 
AR5K_TX_QUEUE_ID_NOQCU_BEACON 
AR5K_TX_QUEUE_ID_DATA_MIN 
AR5K_TX_QUEUE_ID_DATA_MAX 
AR5K_TX_QUEUE_ID_DATA_SVP 
AR5K_TX_QUEUE_ID_CAB 
AR5K_TX_QUEUE_ID_BEACON 
AR5K_TX_QUEUE_ID_UAPSD 
AR5K_TX_QUEUE_ID_XR_DATA 

Definition at line 473 of file ath5k.h.

473  {
476  AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
477  AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
478  AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
479  AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
480  AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
483 };

◆ ath5k_pkt_type

Enumerator
AR5K_PKT_TYPE_NORMAL 
AR5K_PKT_TYPE_ATIM 
AR5K_PKT_TYPE_PSPOLL 
AR5K_PKT_TYPE_BEACON 
AR5K_PKT_TYPE_PROBE_RESP 
AR5K_PKT_TYPE_PIFS 

Definition at line 524 of file ath5k.h.

◆ ath5k_dmasize

Enumerator
AR5K_DMASIZE_4B 
AR5K_DMASIZE_8B 
AR5K_DMASIZE_16B 
AR5K_DMASIZE_32B 
AR5K_DMASIZE_64B 
AR5K_DMASIZE_128B 
AR5K_DMASIZE_256B 
AR5K_DMASIZE_512B 

Definition at line 548 of file ath5k.h.

◆ ath5k_rfgain

Enumerator
AR5K_RFGAIN_INACTIVE 
AR5K_RFGAIN_ACTIVE 
AR5K_RFGAIN_READ_REQUESTED 
AR5K_RFGAIN_NEED_CHANGE 

Definition at line 602 of file ath5k.h.

◆ ath5k_int

enum ath5k_int

enum ath5k_int - Hardware interrupt masks helpers

@AR5K_INT_RX: mask to identify received frame interrupts, of type AR5K_ISR_RXOK or AR5K_ISR_RXERR @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) @AR5K_INT_RXNOFRM: No frame received (?) @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's LinkPtr is NULL. For more details, refer to: http://www.freepatentsonline.com/20030225739.html @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). Note that Rx overrun is not always fatal, on some chips we can continue operation without reseting the card, that's why int_fatal is not common for all chips. @AR5K_INT_TX: mask to identify received frame interrupts, of type AR5K_ISR_TXOK or AR5K_ISR_TXERR @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) @AR5K_INT_TXURN: received when we should increase the TX trigger threshold We currently do increments on interrupt by (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 @AR5K_INT_MIB: Indicates the Management Information Base counters should be checked. We should do this with ath5k_hw_update_mib_counters() but it seems we should also then do some noise immunity work. @AR5K_INT_RXPHY: RX PHY Error @AR5K_INT_RXKCM: RX Key cache miss @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a beacon that must be handled in software. The alternative is if you have VEOL support, in that case you let the hardware deal with things. @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing beacons from the AP have associated with, we should probably try to reassociate. When in IBSS mode this might mean we have not received any beacons from any local stations. Note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now until properly handled @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA errors. These types of errors we can enable seem to be of type AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. @AR5K_INT_GLOBAL: Used to clear and set the IER @AR5K_INT_NOCARD: signals the card has been removed @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same bit value

These are mapped to take advantage of some common bits between the MACs, to be able to set intr properties easier. Some of them are not used yet inside hw.c. Most map to the respective hw interrupt value as they are common amogst different MACs.

Enumerator
AR5K_INT_RXOK 
AR5K_INT_RXDESC 
AR5K_INT_RXERR 
AR5K_INT_RXNOFRM 
AR5K_INT_RXEOL 
AR5K_INT_RXORN 
AR5K_INT_TXOK 
AR5K_INT_TXDESC 
AR5K_INT_TXERR 
AR5K_INT_TXNOFRM 
AR5K_INT_TXEOL 
AR5K_INT_TXURN 
AR5K_INT_MIB 
AR5K_INT_SWI 
AR5K_INT_RXPHY 
AR5K_INT_RXKCM 
AR5K_INT_SWBA 
AR5K_INT_BRSSI 
AR5K_INT_BMISS 
AR5K_INT_FATAL 
AR5K_INT_BNR 
AR5K_INT_TIM 
AR5K_INT_DTIM 
AR5K_INT_DTIM_SYNC 
AR5K_INT_GPIO 
AR5K_INT_BCN_TIMEOUT 
AR5K_INT_CAB_TIMEOUT 
AR5K_INT_RX_DOPPLER 
AR5K_INT_QCBRORN 
AR5K_INT_QCBRURN 
AR5K_INT_QTRIG 
AR5K_INT_GLOBAL 
AR5K_INT_COMMON 
AR5K_INT_NOCARD 

Definition at line 804 of file ath5k.h.

804  {
805  AR5K_INT_RXOK = 0x00000001,
806  AR5K_INT_RXDESC = 0x00000002,
807  AR5K_INT_RXERR = 0x00000004,
808  AR5K_INT_RXNOFRM = 0x00000008,
809  AR5K_INT_RXEOL = 0x00000010,
810  AR5K_INT_RXORN = 0x00000020,
811  AR5K_INT_TXOK = 0x00000040,
812  AR5K_INT_TXDESC = 0x00000080,
813  AR5K_INT_TXERR = 0x00000100,
814  AR5K_INT_TXNOFRM = 0x00000200,
815  AR5K_INT_TXEOL = 0x00000400,
816  AR5K_INT_TXURN = 0x00000800,
817  AR5K_INT_MIB = 0x00001000,
818  AR5K_INT_SWI = 0x00002000,
819  AR5K_INT_RXPHY = 0x00004000,
820  AR5K_INT_RXKCM = 0x00008000,
821  AR5K_INT_SWBA = 0x00010000,
822  AR5K_INT_BRSSI = 0x00020000,
823  AR5K_INT_BMISS = 0x00040000,
824  AR5K_INT_FATAL = 0x00080000, /* Non common */
825  AR5K_INT_BNR = 0x00100000, /* Non common */
826  AR5K_INT_TIM = 0x00200000, /* Non common */
827  AR5K_INT_DTIM = 0x00400000, /* Non common */
828  AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
829  AR5K_INT_GPIO = 0x01000000,
830  AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
831  AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
832  AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
833  AR5K_INT_QCBRORN = 0x10000000, /* Non common */
834  AR5K_INT_QCBRURN = 0x20000000, /* Non common */
835  AR5K_INT_QTRIG = 0x40000000, /* Non common */
836  AR5K_INT_GLOBAL = 0x80000000,
837 
844  | AR5K_INT_TXOK
850  | AR5K_INT_MIB
851  | AR5K_INT_SWI
854  | AR5K_INT_SWBA
857  | AR5K_INT_GPIO
858  | AR5K_INT_GLOBAL,
859 
860  AR5K_INT_NOCARD = 0xffffffff
861 };

◆ ath5k_power_mode

Enumerator
AR5K_PM_UNDEFINED 
AR5K_PM_AUTO 
AR5K_PM_AWAKE 
AR5K_PM_FULL_SLEEP 
AR5K_PM_NETWORK_SLEEP 

Definition at line 866 of file ath5k.h.

◆ ath5k_capability_type

Enumerator
AR5K_CAP_REG_DMN 
AR5K_CAP_TKIP_MIC 
AR5K_CAP_TKIP_SPLIT 
AR5K_CAP_PHYCOUNTERS 
AR5K_CAP_DIVERSITY 
AR5K_CAP_NUM_TXQUEUES 
AR5K_CAP_VEOL 
AR5K_CAP_COMPRESSION 
AR5K_CAP_BURST 
AR5K_CAP_FASTFRAME 
AR5K_CAP_TXPOW 
AR5K_CAP_TPC 
AR5K_CAP_BSSIDMASK 
AR5K_CAP_MCAST_KEYSRCH 
AR5K_CAP_TSF_ADJUST 
AR5K_CAP_XR 
AR5K_CAP_WME_TKIPMIC 
AR5K_CAP_CHAN_HALFRATE 
AR5K_CAP_CHAN_QUARTERRATE 
AR5K_CAP_RFSILENT 

Definition at line 885 of file ath5k.h.

885  {
886  AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
887  AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
888  AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
889  AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
890  AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
891  AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
892  AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
893  AR5K_CAP_COMPRESSION = 8, /* Supports compression */
894  AR5K_CAP_BURST = 9, /* Supports packet bursting */
895  AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
896  AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
897  AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
898  AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
899  AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
900  AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
901  AR5K_CAP_XR = 16, /* Supports XR mode */
902  AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
903  AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
904  AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
905  AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
906 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( MIT  )

◆ ath5k_bitrate_to_hw_rix()

int ath5k_bitrate_to_hw_rix ( int  bitrate)

Definition at line 718 of file ath5k.c.

719 {
720  int i;
721 
722  for (i = 0; i < ATH5K_NR_RATES; i++) {
723  if (ath5k_rates[i].bitrate == bitrate)
724  return ath5k_rates[i].hw_code;
725  }
726 
727  DBG("ath5k: invalid bitrate %d\n", bitrate);
728  return ATH5K_RATE_CODE_1M; /* use lowest rate */
729 }
#define ATH5K_NR_RATES
Definition: ath5k.c:115
u16 bitrate
Definition: ath5k.c:93
static const struct @8 ath5k_rates[]
#define ATH5K_RATE_CODE_1M
Definition: ath5k.h:706
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ATH5K_NR_RATES, ATH5K_RATE_CODE_1M, ath5k_rates, bitrate, and DBG.

Referenced by ath5k_hw_write_rate_duration().

◆ ath5k_hw_attach()

int ath5k_hw_attach ( struct ath5k_softc sc,
u8  mac_version,
struct ath5k_hw **  hw 
)

ath5k_hw_attach - Check if hw is supported and init the needed structs

@sc: The &struct ath5k_softc we got from the driver's attach function @mac_version: The mac version id (check out ath5k.h) based on pci id @hw: Returned newly allocated hardware structure, on success

Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.

Definition at line 112 of file ath5k_attach.c.

114 {
115  struct ath5k_hw *ah;
116  struct pci_device *pdev = sc->pdev;
117  int ret;
118  u32 srev;
119 
120  ah = zalloc(sizeof(struct ath5k_hw));
121  if (ah == NULL) {
122  ret = -ENOMEM;
123  DBG("ath5k: out of memory\n");
124  goto err;
125  }
126 
127  ah->ah_sc = sc;
128  ah->ah_iobase = sc->iobase;
129 
130  /*
131  * HW information
132  */
133  ah->ah_turbo = 0;
134  ah->ah_txpower.txp_tpc = 0;
135  ah->ah_imr = 0;
136  ah->ah_atim_window = 0;
137  ah->ah_aifs = AR5K_TUNE_AIFS;
138  ah->ah_cw_min = AR5K_TUNE_CWMIN;
139  ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
140  ah->ah_software_retry = 0;
141  ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
142 
143  /*
144  * Set the mac version based on the pci id
145  */
146  ah->ah_version = mac_version;
147 
148  /*Fill the ath5k_hw struct with the needed functions*/
150  if (ret)
151  goto err_free;
152 
153  /* Bring device out of sleep and reset it's units */
154  ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1);
155  if (ret)
156  goto err_free;
157 
158  /* Get MAC, PHY and RADIO revisions */
159  srev = ath5k_hw_reg_read(ah, AR5K_SREV);
160  ah->ah_mac_srev = srev;
161  ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
162  ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
163  ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID);
164  ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ);
165  ah->ah_phy = AR5K_PHY(0);
166 
167  /* Try to identify radio chip based on it's srev */
168  switch (ah->ah_radio_5ghz_revision & 0xf0) {
169  case AR5K_SREV_RAD_5111:
170  ah->ah_radio = AR5K_RF5111;
171  ah->ah_single_chip = 0;
172  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
173  CHANNEL_2GHZ);
174  break;
175  case AR5K_SREV_RAD_5112:
176  case AR5K_SREV_RAD_2112:
177  ah->ah_radio = AR5K_RF5112;
178  ah->ah_single_chip = 0;
179  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
180  CHANNEL_2GHZ);
181  break;
182  case AR5K_SREV_RAD_2413:
183  ah->ah_radio = AR5K_RF2413;
184  ah->ah_single_chip = 1;
185  break;
186  case AR5K_SREV_RAD_5413:
187  ah->ah_radio = AR5K_RF5413;
188  ah->ah_single_chip = 1;
189  break;
190  case AR5K_SREV_RAD_2316:
191  ah->ah_radio = AR5K_RF2316;
192  ah->ah_single_chip = 1;
193  break;
194  case AR5K_SREV_RAD_2317:
195  ah->ah_radio = AR5K_RF2317;
196  ah->ah_single_chip = 1;
197  break;
198  case AR5K_SREV_RAD_5424:
199  if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
200  ah->ah_mac_version == AR5K_SREV_AR2417) {
201  ah->ah_radio = AR5K_RF2425;
202  } else {
203  ah->ah_radio = AR5K_RF5413;
204  }
205  ah->ah_single_chip = 1;
206  break;
207  default:
208  /* Identify radio based on mac/phy srev */
209  if (ah->ah_version == AR5K_AR5210) {
210  ah->ah_radio = AR5K_RF5110;
211  ah->ah_single_chip = 0;
212  } else if (ah->ah_version == AR5K_AR5211) {
213  ah->ah_radio = AR5K_RF5111;
214  ah->ah_single_chip = 0;
215  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
216  CHANNEL_2GHZ);
217  } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
218  ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
219  ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
220  ah->ah_radio = AR5K_RF2425;
221  ah->ah_single_chip = 1;
222  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
223  } else if (srev == AR5K_SREV_AR5213A &&
224  ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
225  ah->ah_radio = AR5K_RF5112;
226  ah->ah_single_chip = 0;
227  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
228  } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
229  ah->ah_radio = AR5K_RF2316;
230  ah->ah_single_chip = 1;
231  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
232  } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
233  ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
234  ah->ah_radio = AR5K_RF5413;
235  ah->ah_single_chip = 1;
236  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
237  } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
238  ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
239  ah->ah_radio = AR5K_RF2413;
240  ah->ah_single_chip = 1;
241  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
242  } else {
243  DBG("ath5k: Couldn't identify radio revision.\n");
244  ret = -ENOTSUP;
245  goto err_free;
246  }
247  }
248 
249  /* Return on unsuported chips (unsupported eeprom etc) */
250  if ((srev >= AR5K_SREV_AR5416) &&
251  (srev < AR5K_SREV_AR2425)) {
252  DBG("ath5k: Device not yet supported.\n");
253  ret = -ENOTSUP;
254  goto err_free;
255  }
256 
257  /*
258  * Write PCI-E power save settings
259  */
260  if ((ah->ah_version == AR5K_AR5212) &&
262  ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
263  ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
264  /* Shut off RX when elecidle is asserted */
265  ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
266  ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
267  /* TODO: EEPROM work */
268  ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
269  /* Shut off PLL and CLKREQ active in L1 */
270  ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
271  /* Preserce other settings */
272  ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
273  ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
274  ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
275  /* Reset SERDES to load new settings */
277  mdelay(1);
278  }
279 
280  /*
281  * POST
282  */
283  ret = ath5k_hw_post(ah);
284  if (ret)
285  goto err_free;
286 
287  /* Enable pci core retry fix on Hainan (5213A) and later chips */
288  if (srev >= AR5K_SREV_AR5213A)
290 
291  /*
292  * Get card capabilities, calibration values etc
293  * TODO: EEPROM work
294  */
295  ret = ath5k_eeprom_init(ah);
296  if (ret) {
297  DBG("ath5k: unable to init EEPROM\n");
298  goto err_free;
299  }
300 
301  /* Get misc capabilities */
303  if (ret) {
304  DBG("ath5k: unable to get device capabilities: 0x%04x\n",
305  sc->pdev->device);
306  goto err_free;
307  }
308 
309  if (srev >= AR5K_SREV_AR2414) {
310  ah->ah_combined_mic = 1;
313  }
314 
315  /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
316  memset(ah->ah_bssid, 0xff, ETH_ALEN);
317  ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
319 
321 
322  *hw = ah;
323  return 0;
324 err_free:
325  free(ah);
326 err:
327  return ret;
328 }
#define AR5K_SREV
Definition: reg.h:957
static int ath5k_hw_post(struct ath5k_hw *ah)
ath5k_hw_post - Power On Self Test helper function
Definition: ath5k_attach.c:40
#define AR5K_SREV_RAD_5413
Definition: ath5k.h:318
#define AR5K_SREV_RAD_2112
Definition: ath5k.h:314
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:36
#define AR5K_PHY_CHIP_ID
Definition: reg.h:1927
#define AR5K_SREV_PHY_2413
Definition: ath5k.h:329
u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
Definition: ath5k_phy.c:1372
#define AR5K_SREV_REV
Definition: reg.h:958
#define AR5K_PCIE_SERDES
Definition: reg.h:1014
#define AR5K_SREV_AR5414
Definition: ath5k.h:300
#define AR5K_TUNE_ANT_DIVERSITY
Definition: ath5k.h:194
#define AR5K_SREV_PHY_5212B
Definition: ath5k.h:328
#define AR5K_INIT_TX_RETRY
Definition: ath5k.h:228
#define AR5K_PCICFG
Definition: reg.h:880
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_SREV_RAD_5112
Definition: ath5k.h:311
#define AR5K_SREV_AR2417
Definition: ath5k.h:305
#define AR5K_TUNE_CWMIN
Definition: ath5k.h:184
void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
ath5k_hw_set_associd - Set BSSID for association
Definition: ath5k_pcu.c:228
Definition: hw.c:16
#define AR5K_SREV_RAD_2413
Definition: ath5k.h:317
#define AR5K_SREV_RAD_5424
Definition: ath5k.h:321
int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
Definition: ath5k_desc.c:522
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define AR5K_SREV_RAD_2317
Definition: ath5k.h:320
#define AR5K_PCICFG_RETRY_FIX
Definition: reg.h:898
uint16_t device
Device ID.
Definition: pci.h:204
#define AR5K_SREV_RAD_2425
Definition: ath5k.h:322
#define AR5K_PCIE_SERDES_RESET
Definition: reg.h:1015
int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
Definition: ath5k_caps.c:36
int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
Definition: ath5k_phy.c:158
#define AR5K_SREV_PHY_2425
Definition: ath5k.h:331
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
#define AR5K_SREV_RAD_5112B
Definition: ath5k.h:313
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
#define AR5K_SREV_RAD_2316
Definition: ath5k.h:319
A PCI device.
Definition: pci.h:187
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define ETH_ALEN
Definition: if_ether.h:8
int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial)
Definition: ath5k_reset.c:282
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:96
#define AR5K_SREV_AR5213A
Definition: ath5k.h:295
struct pci_device * pdev
Definition: base.h:89
#define AR5K_SREV_AR2425
Definition: ath5k.h:304
#define AR5K_TUNE_AIFS
Definition: ath5k.h:181
#define AR5K_SREV_AR5416
Definition: ath5k.h:302
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define AR5K_SREV_AR2415
Definition: ath5k.h:301
int ath5k_hw_set_opmode(struct ath5k_hw *ah)
ath5k_hw_set_opmode - Set PCU operating mode
Definition: ath5k_pcu.c:48
#define AR5K_PHY(_n)
Definition: reg.h:1861
#define AR5K_SREV_PHY_5413
Definition: ath5k.h:330
void * iobase
Definition: base.h:90
#define AR5K_SREV_VER
Definition: reg.h:960
#define CHANNEL_5GHZ
Definition: ath5k.h:633
#define AR5K_SREV_RAD_5111
Definition: ath5k.h:308
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
#define CHANNEL_2GHZ
Definition: ath5k.h:632
#define AR5K_MISC_MODE
Definition: reg.h:1745
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
int ath5k_eeprom_init(struct ath5k_hw *ah)
uint32_t u32
Definition: stdint.h:23
#define AR5K_SREV_AR2414
Definition: ath5k.h:297
#define AR5K_MISC_MODE_COMBINED_MIC
Definition: reg.h:1748
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104
void * memset(void *dest, int character, size_t len) __nonnull

References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_INIT_TX_RETRY, AR5K_MISC_MODE, AR5K_MISC_MODE_COMBINED_MIC, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX, AR5K_PCIE_SERDES, AR5K_PCIE_SERDES_RESET, AR5K_PHY, AR5K_PHY_CHIP_ID, AR5K_REG_ENABLE_BITS, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_SREV, AR5K_SREV_AR2414, AR5K_SREV_AR2415, AR5K_SREV_AR2417, AR5K_SREV_AR2425, AR5K_SREV_AR5213A, AR5K_SREV_AR5414, AR5K_SREV_AR5416, AR5K_SREV_PHY_2413, AR5K_SREV_PHY_2425, AR5K_SREV_PHY_5212B, AR5K_SREV_PHY_5413, AR5K_SREV_RAD_2112, AR5K_SREV_RAD_2316, AR5K_SREV_RAD_2317, AR5K_SREV_RAD_2413, AR5K_SREV_RAD_2425, AR5K_SREV_RAD_5111, AR5K_SREV_RAD_5112, AR5K_SREV_RAD_5112B, AR5K_SREV_RAD_5413, AR5K_SREV_RAD_5424, AR5K_SREV_REV, AR5K_SREV_VER, AR5K_TUNE_AIFS, AR5K_TUNE_ANT_DIVERSITY, AR5K_TUNE_CWMIN, ath5k_eeprom_init(), ath5k_hw_init_desc_functions(), ath5k_hw_nic_wakeup(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_rfgain_opt_init(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_opmode(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_B, DBG, pci_device::device, ENOMEM, ENOTSUP, ETH_ALEN, free, ath5k_softc::iobase, mdelay(), memset(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, and zalloc().

Referenced by ath5k_probe().

◆ ath5k_hw_detach()

void ath5k_hw_detach ( struct ath5k_hw ah)

ath5k_hw_detach - Free the ath5k_hw struct

@ah: The &struct ath5k_hw

Definition at line 335 of file ath5k_attach.c.

336 {
337  free(ah->ah_rf_banks);
339  free(ah);
340 }
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
void ath5k_eeprom_detach(struct ath5k_hw *ah)
uint8_t ah
Definition: registers.h:85

References ah, ath5k_eeprom_detach(), and free.

Referenced by ath5k_probe(), and ath5k_remove().

◆ ath5k_init_leds()

int ath5k_init_leds ( struct ath5k_softc sc)

◆ ath5k_led_enable()

void ath5k_led_enable ( struct ath5k_softc sc)

◆ ath5k_led_off()

void ath5k_led_off ( struct ath5k_softc sc)

◆ ath5k_unregister_leds()

void ath5k_unregister_leds ( struct ath5k_softc sc)

◆ ath5k_hw_nic_wakeup()

int ath5k_hw_nic_wakeup ( struct ath5k_hw ah,
int  flags,
int  initial 
)

Definition at line 282 of file ath5k_reset.c.

283 {
284  struct pci_device *pdev = ah->ah_sc->pdev;
285  u32 turbo, mode, clock, bus_flags;
286  int ret;
287 
288  turbo = 0;
289  mode = 0;
290  clock = 0;
291 
292  /* Wakeup the device */
293  ret = ath5k_hw_wake(ah);
294  if (ret) {
295  DBG("ath5k: failed to wake up the MAC chip\n");
296  return ret;
297  }
298 
299  if (ah->ah_version != AR5K_AR5210) {
300  /*
301  * Get channel mode flags
302  */
303 
304  if (ah->ah_radio >= AR5K_RF5112) {
306  clock = AR5K_PHY_PLL_RF5112;
307  } else {
308  mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
309  clock = AR5K_PHY_PLL_RF5111; /*Zero*/
310  }
311 
312  if (flags & CHANNEL_2GHZ) {
313  mode |= AR5K_PHY_MODE_FREQ_2GHZ;
314  clock |= AR5K_PHY_PLL_44MHZ;
315 
316  if (flags & CHANNEL_CCK) {
317  mode |= AR5K_PHY_MODE_MOD_CCK;
318  } else if (flags & CHANNEL_OFDM) {
319  /* XXX Dynamic OFDM/CCK is not supported by the
320  * AR5211 so we set MOD_OFDM for plain g (no
321  * CCK headers) operation. We need to test
322  * this, 5211 might support ofdm-only g after
323  * all, there are also initial register values
324  * in the code for g mode (see initvals.c). */
325  if (ah->ah_version == AR5K_AR5211)
326  mode |= AR5K_PHY_MODE_MOD_OFDM;
327  else
328  mode |= AR5K_PHY_MODE_MOD_DYN;
329  } else {
330  DBG("ath5k: invalid radio modulation mode\n");
331  return -EINVAL;
332  }
333  } else if (flags & CHANNEL_5GHZ) {
334  mode |= AR5K_PHY_MODE_FREQ_5GHZ;
335 
336  if (ah->ah_radio == AR5K_RF5413)
337  clock = AR5K_PHY_PLL_40MHZ_5413;
338  else
339  clock |= AR5K_PHY_PLL_40MHZ;
340 
341  if (flags & CHANNEL_OFDM)
342  mode |= AR5K_PHY_MODE_MOD_OFDM;
343  else {
344  DBG("ath5k: invalid radio modulation mode\n");
345  return -EINVAL;
346  }
347  } else {
348  DBG("ath5k: invalid radio frequency mode\n");
349  return -EINVAL;
350  }
351 
352  if (flags & CHANNEL_TURBO)
354  } else { /* Reset the device */
355 
356  /* ...enable Atheros turbo mode if requested */
357  if (flags & CHANNEL_TURBO)
360  }
361 
362  /* reseting PCI on PCI-E cards results card to hang
363  * and always return 0xffff... so we ingore that flag
364  * for PCI-E cards */
366  bus_flags = 0;
367  else
368  bus_flags = AR5K_RESET_CTL_PCI;
369 
370  /* Reset chipset */
371  if (ah->ah_version == AR5K_AR5210) {
375  mdelay(2);
376  } else {
378  AR5K_RESET_CTL_BASEBAND | bus_flags);
379  }
380  if (ret) {
381  DBG("ath5k: failed to reset the MAC chip\n");
382  return -EIO;
383  }
384 
385  /* ...wakeup again!*/
386  ret = ath5k_hw_wake(ah);
387  if (ret) {
388  DBG("ath5k: failed to resume the MAC chip\n");
389  return ret;
390  }
391 
392  /* ...final warm reset */
393  if (ath5k_hw_nic_reset(ah, 0)) {
394  DBG("ath5k: failed to warm reset the MAC chip\n");
395  return -EIO;
396  }
397 
398  if (ah->ah_version != AR5K_AR5210) {
399 
400  /* ...update PLL if needed */
401  if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
403  udelay(300);
404  }
405 
406  /* ...set the PHY operating mode */
409  }
410 
411  return 0;
412 }
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_PHY_MODE_RAD_RF5112
Definition: reg.h:2513
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:36
#define AR5K_PHY_PLL_40MHZ
Definition: reg.h:2103
int ath5k_hw_wake(struct ath5k_hw *ah)
Definition: ath5k_reset.c:240
#define AR5K_PHY_PLL_44MHZ
Definition: reg.h:2108
#define AR5K_PHY_MODE_MOD_DYN
Definition: reg.h:2510
#define AR5K_PHY_PLL
Definition: reg.h:2097
#define CHANNEL_CCK
Definition: ath5k.h:630
#define AR5K_RESET_CTL_PCI
Definition: reg.h:846
#define AR5K_PHY_PLL_RF5112
Definition: reg.h:2112
#define AR5K_RESET_CTL_MAC
Definition: reg.h:844
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR5K_PHY_TURBO_MODE
Definition: reg.h:1897
#define AR5K_PHY_TURBO
Definition: reg.h:1896
static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
Definition: ath5k_reset.c:198
#define AR5K_RESET_CTL_PCU
Definition: reg.h:841
#define AR5K_PHY_MODE_MOD_CCK
Definition: reg.h:2506
#define AR5K_PHY_MODE_FREQ_5GHZ
Definition: reg.h:2508
#define AR5K_PHY_MODE
Definition: reg.h:2503
A PCI device.
Definition: pci.h:187
#define AR5K_PHY_MODE_RAD_RF5111
Definition: reg.h:2512
#define CHANNEL_TURBO
Definition: ath5k.h:629
#define AR5K_PHY_MODE_MOD_OFDM
Definition: reg.h:2505
#define CHANNEL_OFDM
Definition: ath5k.h:631
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:96
#define AR5K_PHY_TURBO_SHORT
Definition: reg.h:1898
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define AR5K_PHY_PLL_RF5111
Definition: reg.h:2111
#define CHANNEL_5GHZ
Definition: ath5k.h:633
#define EIO
Input/output error.
Definition: errno.h:433
#define AR5K_PHY_PLL_40MHZ_5413
Definition: reg.h:2102
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_RESET_CTL_PHY
Definition: reg.h:845
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_2GHZ
Definition: ath5k.h:632
#define AR5K_RESET_CTL_DMA
Definition: reg.h:842
#define AR5K_PHY_MODE_FREQ_2GHZ
Definition: reg.h:2509
uint32_t u32
Definition: stdint.h:23
#define AR5K_RESET_CTL_BASEBAND
Definition: reg.h:843
uint8_t flags
Flags.
Definition: ena.h:18

References ah, AR5K_AR5210, AR5K_AR5211, AR5K_PHY_MODE, AR5K_PHY_MODE_FREQ_2GHZ, AR5K_PHY_MODE_FREQ_5GHZ, AR5K_PHY_MODE_MOD_CCK, AR5K_PHY_MODE_MOD_DYN, AR5K_PHY_MODE_MOD_OFDM, AR5K_PHY_MODE_RAD_RF5111, AR5K_PHY_MODE_RAD_RF5112, AR5K_PHY_PLL, AR5K_PHY_PLL_40MHZ, AR5K_PHY_PLL_40MHZ_5413, AR5K_PHY_PLL_44MHZ, AR5K_PHY_PLL_RF5111, AR5K_PHY_PLL_RF5112, AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCI, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RF5112, AR5K_RF5413, ath5k_hw_nic_reset(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_wake(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EINVAL, EIO, flags, mdelay(), PCI_CAP_ID_EXP, pci_find_capability(), and udelay().

Referenced by ath5k_hw_attach(), and ath5k_hw_reset().

◆ ath5k_hw_reset()

int ath5k_hw_reset ( struct ath5k_hw ah,
struct net80211_channel channel,
int  change_channel 
)

Definition at line 690 of file ath5k_reset.c.

692 {
693  u32 s_seq[10], s_ant, s_led[3], staid1_flags;
694  u32 phy_tst1;
695  u8 mode, freq, ee_mode, ant[2];
696  int i, ret;
697 
698  s_ant = 0;
699  ee_mode = 0;
700  staid1_flags = 0;
701  freq = 0;
702  mode = 0;
703 
704  /*
705  * Save some registers before a reset
706  */
707  /*DCU/Antenna selection not available on 5210*/
708  if (ah->ah_version != AR5K_AR5210) {
709 
710  switch (channel->hw_value & CHANNEL_MODES) {
711  case CHANNEL_A:
712  mode = AR5K_MODE_11A;
713  freq = AR5K_INI_RFGAIN_5GHZ;
714  ee_mode = AR5K_EEPROM_MODE_11A;
715  break;
716  case CHANNEL_G:
717  mode = AR5K_MODE_11G;
718  freq = AR5K_INI_RFGAIN_2GHZ;
719  ee_mode = AR5K_EEPROM_MODE_11G;
720  break;
721  case CHANNEL_B:
722  mode = AR5K_MODE_11B;
723  freq = AR5K_INI_RFGAIN_2GHZ;
724  ee_mode = AR5K_EEPROM_MODE_11B;
725  break;
726  case CHANNEL_T:
727  mode = AR5K_MODE_11A_TURBO;
728  freq = AR5K_INI_RFGAIN_5GHZ;
729  ee_mode = AR5K_EEPROM_MODE_11A;
730  break;
731  case CHANNEL_TG:
732  if (ah->ah_version == AR5K_AR5211) {
733  DBG("ath5k: TurboG not available on 5211\n");
734  return -EINVAL;
735  }
736  mode = AR5K_MODE_11G_TURBO;
737  freq = AR5K_INI_RFGAIN_2GHZ;
738  ee_mode = AR5K_EEPROM_MODE_11G;
739  break;
740  case CHANNEL_XR:
741  if (ah->ah_version == AR5K_AR5211) {
742  DBG("ath5k: XR mode not available on 5211\n");
743  return -EINVAL;
744  }
745  mode = AR5K_MODE_XR;
746  freq = AR5K_INI_RFGAIN_5GHZ;
747  ee_mode = AR5K_EEPROM_MODE_11A;
748  break;
749  default:
750  DBG("ath5k: invalid channel (%d MHz)\n",
751  channel->center_freq);
752  return -EINVAL;
753  }
754 
755  if (change_channel) {
756  /*
757  * Save frame sequence count
758  * For revs. after Oahu, only save
759  * seq num for DCU 0 (Global seq num)
760  */
761  if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
762 
763  for (i = 0; i < 10; i++)
764  s_seq[i] = ath5k_hw_reg_read(ah,
766 
767  } else {
768  s_seq[0] = ath5k_hw_reg_read(ah,
770  }
771  }
772 
773  /* Save default antenna */
775 
776  if (ah->ah_version == AR5K_AR5212) {
777  /* Since we are going to write rf buffer
778  * check if we have any pending gain_F
779  * optimization settings */
780  if (change_channel && ah->ah_rf_banks != NULL)
782  }
783  }
784 
785  /*GPIOs*/
786  s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
788  s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
789  s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
790 
791  /* AR5K_STA_ID1 flags, only preserve antenna
792  * settings and ack/cts rate mode */
793  staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
800 
801  /* Wakeup the device */
802  ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0);
803  if (ret)
804  return ret;
805 
806  /* PHY access enable */
807  if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
809  else
811  AR5K_PHY(0));
812 
813  /* Write initial settings */
814  ret = ath5k_hw_write_initvals(ah, mode, change_channel);
815  if (ret)
816  return ret;
817 
818  /*
819  * 5211/5212 Specific
820  */
821  if (ah->ah_version != AR5K_AR5210) {
822 
823  /*
824  * Write initial RF gain settings
825  * This should work for both 5111/5112
826  */
827  ret = ath5k_hw_rfgain_init(ah, freq);
828  if (ret)
829  return ret;
830 
831  mdelay(1);
832 
833  /*
834  * Tweak initval settings for revised
835  * chipsets and add some more config
836  * bits
837  */
839 
840  /*
841  * Set TX power (FIXME)
842  */
843  ret = ath5k_hw_txpower(ah, channel, ee_mode,
845  if (ret)
846  return ret;
847 
848  /* Write rate duration table only on AR5212 */
849  if (ah->ah_version == AR5K_AR5212)
851 
852  /*
853  * Write RF buffer
854  */
855  ret = ath5k_hw_rfregs_init(ah, channel, mode);
856  if (ret)
857  return ret;
858 
859 
860  /* Write OFDM timings on 5212*/
861  if (ah->ah_version == AR5K_AR5212 &&
862  channel->hw_value & CHANNEL_OFDM) {
864  if (ret)
865  return ret;
866  }
867 
868  /*Enable/disable 802.11b mode on 5111
869  (enable 2111 frequency converter + CCK)*/
870  if (ah->ah_radio == AR5K_RF5111) {
871  if (mode == AR5K_MODE_11B)
874  else
877  }
878 
879  /*
880  * In case a fixed antenna was set as default
881  * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
882  * registers.
883  */
884  if (s_ant != 0) {
885  if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
886  ant[0] = ant[1] = AR5K_ANT_FIXED_A;
887  else /* 2 - Aux */
888  ant[0] = ant[1] = AR5K_ANT_FIXED_B;
889  } else {
890  ant[0] = AR5K_ANT_FIXED_A;
891  ant[1] = AR5K_ANT_FIXED_B;
892  }
893 
894  /* Commit values from EEPROM */
896 
897  } else {
898  /*
899  * For 5210 we do all initialization using
900  * initvals, so we don't have to modify
901  * any settings (5210 also only supports
902  * a/aturbo modes)
903  */
904  mdelay(1);
905  /* Disable phy and wait */
907  mdelay(1);
908  }
909 
910  /*
911  * Restore saved values
912  */
913 
914  /*DCU/Antenna selection not available on 5210*/
915  if (ah->ah_version != AR5K_AR5210) {
916 
917  if (change_channel) {
918  if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
919  for (i = 0; i < 10; i++)
920  ath5k_hw_reg_write(ah, s_seq[i],
922  } else {
923  ath5k_hw_reg_write(ah, s_seq[0],
925  }
926  }
927 
929  }
930 
931  /* Ledstate */
932  AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
933 
934  /* Gpio settings */
935  ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
936  ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
937 
938  /* Restore sta_id flags and preserve our mac address*/
939  ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
940  AR5K_STA_ID0);
941  ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
942  AR5K_STA_ID1);
943 
944 
945  /*
946  * Configure PCU
947  */
948 
949  /* Restore bssid and bssid mask */
950  /* XXX: add ah->aid once mac80211 gives this to us */
951  ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
952 
953  /* Set PCU config */
955 
956  /* Clear any pending interrupts
957  * PISR/SISR Not available on 5210 */
958  if (ah->ah_version != AR5K_AR5210)
959  ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
960 
961  /* Set RSSI/BRSSI thresholds
962  *
963  * Note: If we decide to set this value
964  * dynamicaly, have in mind that when AR5K_RSSI_THR
965  * register is read it might return 0x40 if we haven't
966  * wrote anything to it plus BMISS RSSI threshold is zeroed.
967  * So doing a save/restore procedure here isn't the right
968  * choice. Instead store it on ath5k_hw */
972  AR5K_RSSI_THR);
973 
974  /* MIC QoS support */
975  if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
976  ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
977  ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
978  }
979 
980  /* QoS NOACK Policy */
981  if (ah->ah_version == AR5K_AR5212) {
987  }
988 
989 
990  /*
991  * Configure PHY
992  */
993 
994  /* Set channel on PHY */
995  ret = ath5k_hw_channel(ah, channel);
996  if (ret)
997  return ret;
998 
999  /*
1000  * Enable the PHY and wait until completion
1001  * This includes BaseBand and Synthesizer
1002  * activation.
1003  */
1005 
1006  /*
1007  * On 5211+ read activation -> rx delay
1008  * and use it.
1009  *
1010  * TODO: Half/quarter rate support
1011  */
1012  if (ah->ah_version != AR5K_AR5210) {
1013  u32 delay;
1016  delay = (channel->hw_value & CHANNEL_CCK) ?
1017  ((delay << 2) / 22) : (delay / 10);
1018 
1019  udelay(100 + (2 * delay));
1020  } else {
1021  mdelay(1);
1022  }
1023 
1024  /*
1025  * Perform ADC test to see if baseband is ready
1026  * Set tx hold and check adc test register
1027  */
1028  phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1030  for (i = 0; i <= 20; i++) {
1031  if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1032  break;
1033  udelay(200);
1034  }
1035  ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1036 
1037  /*
1038  * Start automatic gain control calibration
1039  *
1040  * During AGC calibration RX path is re-routed to
1041  * a power detector so we don't receive anything.
1042  *
1043  * This method is used to calibrate some static offsets
1044  * used together with on-the fly I/Q calibration (the
1045  * one performed via ath5k_hw_phy_calibrate), that doesn't
1046  * interrupt rx path.
1047  *
1048  * While rx path is re-routed to the power detector we also
1049  * start a noise floor calibration, to measure the
1050  * card's noise floor (the noise we measure when we are not
1051  * transmiting or receiving anything).
1052  *
1053  * If we are in a noisy environment AGC calibration may time
1054  * out and/or noise floor calibration might timeout.
1055  */
1058 
1059  /* At the same time start I/Q calibration for QAM constellation
1060  * -no need for CCK- */
1061  ah->ah_calibration = 0;
1062  if (!(mode == AR5K_MODE_11B)) {
1063  ah->ah_calibration = 1;
1067  AR5K_PHY_IQ_RUN);
1068  }
1069 
1070  /* Wait for gain calibration to finish (we check for I/Q calibration
1071  * during ath5k_phy_calibrate) */
1072  if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1073  AR5K_PHY_AGCCTL_CAL, 0, 0)) {
1074  DBG("ath5k: gain calibration timeout (%d MHz)\n",
1075  channel->center_freq);
1076  }
1077 
1078  /*
1079  * If we run NF calibration before AGC, it always times out.
1080  * Binary HAL starts NF and AGC calibration at the same time
1081  * and only waits for AGC to finish. Also if AGC or NF cal.
1082  * times out, reset doesn't fail on binary HAL. I believe
1083  * that's wrong because since rx path is routed to a detector,
1084  * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211
1085  * enables noise floor calibration after offset calibration and if noise
1086  * floor calibration fails, reset fails. I believe that's
1087  * a better approach, we just need to find a polling interval
1088  * that suits best, even if reset continues we need to make
1089  * sure that rx path is ready.
1090  */
1092 
1093 
1094  /*
1095  * Configure QCUs/DCUs
1096  */
1097 
1098  /* TODO: HW Compression support for data queues */
1099  /* TODO: Burst prefetch for data queues */
1100 
1101  /*
1102  * Reset queues and start beacon timers at the end of the reset routine
1103  * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1104  * Note: If we want we can assign multiple qcus on one dcu.
1105  */
1106  ret = ath5k_hw_reset_tx_queue(ah);
1107  if (ret) {
1108  DBG("ath5k: failed to reset TX queue\n");
1109  return ret;
1110  }
1111 
1112  /*
1113  * Configure DMA/Interrupts
1114  */
1115 
1116  /*
1117  * Set Rx/Tx DMA Configuration
1118  *
1119  * Set standard DMA size (128). Note that
1120  * a DMA size of 512 causes rx overruns and tx errors
1121  * on pci-e cards (tested on 5424 but since rx overruns
1122  * also occur on 5416/5418 with madwifi we set 128
1123  * for all PCI-E cards to be safe).
1124  *
1125  * XXX: need to check 5210 for this
1126  * TODO: Check out tx triger level, it's always 64 on dumps but I
1127  * guess we can tweak it and see how it goes ;-)
1128  */
1129  if (ah->ah_version != AR5K_AR5210) {
1134  }
1135 
1136  /* Pre-enable interrupts on 5211/5212*/
1137  if (ah->ah_version != AR5K_AR5210)
1138  ath5k_hw_set_imr(ah, ah->ah_imr);
1139 
1140  /*
1141  * Setup RFKill interrupt if rfkill flag is set on eeprom.
1142  * TODO: Use gpio pin and polarity infos from eeprom
1143  * TODO: Handle this in ath5k_intr because it'll result
1144  * a nasty interrupt storm.
1145  */
1146 #if 0
1147  if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1149  ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1150  if (ah->ah_gpio[0] == 0)
1151  ath5k_hw_set_gpio_intr(ah, 0, 1);
1152  else
1153  ath5k_hw_set_gpio_intr(ah, 0, 0);
1154  }
1155 #endif
1156 
1157  /*
1158  * Disable beacons and reset the register
1159  */
1162 
1163  return 0;
1164 }
#define AR5K_PHY_SHIFT_5GHZ
Definition: reg.h:1884
#define AR5K_QOS_NOACK_BYTE_OFFSET
Definition: reg.h:1707
#define AR5K_TXCFG_SDMAMR
Definition: reg.h:170
#define AR5K_PHY_RX_DELAY_M
Definition: reg.h:2179
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_TUNE_RSSI_THRES
Definition: ath5k.h:172
#define AR5K_MIC_QOS_CTL
Definition: reg.h:1732
#define AR5K_EEPROM_MODE_11G
Definition: eeprom.h:64
#define AR5K_PHY_TST1_TXHOLD
Definition: reg.h:1908
#define AR5K_EEPROM_MODE_11A
Definition: eeprom.h:62
#define AR5K_BEACON_ENABLE
Definition: reg.h:1248
#define AR5K_BEACON_RESET_TSF
Definition: reg.h:1249
#define AR5K_BEACON
Definition: reg.h:1242
#define AR5K_INI_RFGAIN_5GHZ
Definition: ath5k.h:139
int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial __unused)
Definition: ath5k_reset.c:282
#define AR5K_PCICFG_LEDSTATE
Definition: reg.h:909
#define AR5K_PHY_AGCCTL_CAL
Definition: reg.h:2029
#define AR5K_GPIODO
Definition: reg.h:946
#define AR5K_PCICFG
Definition: reg.h:880
#define AR5K_PHY_IQ
Definition: reg.h:2190
#define AR5K_TXCFG
Definition: reg.h:169
void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level)
Definition: ath5k_gpio.c:98
int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
Definition: ath5k_phy.c:452
#define AR5K_STA_ID0
Definition: reg.h:1122
int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:97
void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
ath5k_hw_set_associd - Set BSSID for association
Definition: ath5k_pcu.c:228
#define CHANNEL_A
Definition: ath5k.h:638
#define AR5K_QOS_NOACK_BIT_OFFSET
Definition: reg.h:1705
#define AR5K_LOW_ID(_a)
Definition: ath5k.h:152
#define CHANNEL_CCK
Definition: ath5k.h:630
#define AR5K_TUNE_DEFAULT_TXPOWER
Definition: ath5k.h:192
int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
Definition: ath5k_phy.c:1127
int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode)
Definition: ath5k_phy.c:514
#define AR5K_STA_ID1_BASE_RATE_11B
Definition: reg.h:1143
#define AR5K_HIGH_ID(_a)
Definition: ath5k.h:156
#define AR5K_PHY_AGCCTL
Definition: reg.h:2028
#define CHANNEL_G
Definition: ath5k.h:640
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
Definition: ath5k.h:96
#define AR5K_STA_ID1
Definition: reg.h:1128
#define AR5K_STA_ID1_SELFGEN_DEF_ANT
Definition: reg.h:1144
#define AR5K_GPIOCR
Definition: reg.h:933
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define CHANNEL_XR
Definition: ath5k.h:636
#define AR5K_PISR
Definition: reg.h:286
int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
Definition: ath5k_phy.c:1048
#define AR5K_MIC_QOS_SEL
Definition: reg.h:1739
static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, struct net80211_channel *channel)
Definition: ath5k_reset.c:435
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
#define AR5K_QOS_NOACK_2BIT_VALUES
Definition: reg.h:1703
int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
Definition: ath5k_gpio.c:34
#define AR5K_STA_ID1_RTS_DEF_ANTENNA
Definition: reg.h:1141
#define AR5K_RSSI_THR_BMISS_S
Definition: reg.h:1190
#define AR5K_QUEUE_DCU_SEQNUM(_q)
Definition: reg.h:757
#define AR5K_SREV_AR2413
Definition: ath5k.h:296
#define AR5K_DEFAULT_ANTENNA
Definition: reg.h:1476
#define AR5K_EEPROM_MODE_11B
Definition: eeprom.h:63
enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
ath5k_hw_set_imr - Set interrupt mask
Definition: ath5k_dma.c:548
#define CHANNEL_OFDM
Definition: ath5k.h:631
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_QOS_NOACK
Definition: reg.h:1702
#define AR5K_PHY_ADC_TEST
Definition: reg.h:2434
#define AR5K_PHY_ACT_DISABLE
Definition: reg.h:1934
#define AR5K_TXCFG_B_MODE
Definition: reg.h:172
#define AR5K_RSSI_THR
Definition: reg.h:1182
#define AR5K_EEPROM_HDR_RFKILL(_v)
Definition: eeprom.h:73
#define AR5K_TUNE_BMISS_THRES
Definition: ath5k.h:178
#define AR5K_PHY_TST1
Definition: reg.h:1906
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:107
#define CHANNEL_T
Definition: ath5k.h:641
#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX
Definition: reg.h:2195
int ath5k_hw_set_opmode(struct ath5k_hw *ah)
ath5k_hw_set_opmode - Set PCU operating mode
Definition: ath5k_pcu.c:48
#define AR5K_PHY(_n)
Definition: reg.h:1861
#define AR5K_STA_ID1_DESC_ANTENNA
Definition: reg.h:1140
#define AR5K_INI_RFGAIN_2GHZ
Definition: ath5k.h:140
uint16_t delay
Forward delay.
Definition: stp.h:40
#define AR5K_STA_ID1_DEFAULT_ANTENNA
Definition: reg.h:1139
static int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, struct net80211_channel *channel)
ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
Definition: ath5k_reset.c:85
enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
Definition: ath5k_phy.c:389
#define CHANNEL_MODES
Definition: ath5k.h:651
uint8_t ah
Definition: registers.h:85
#define AR5K_RXCFG
Definition: reg.h:196
static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, struct net80211_channel *channel, u8 *ant, u8 ee_mode)
Definition: ath5k_reset.c:537
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_SREV_AR5211
Definition: ath5k.h:292
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower)
Definition: ath5k_phy.c:2474
#define AR5K_PHY_IQ_RUN
Definition: reg.h:2197
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR5K_PHY_RX_DELAY
Definition: reg.h:2178
int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
#define CHANNEL_TG
Definition: ath5k.h:642
static void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, unsigned int mode __unused)
ath5k_hw_write_rate_duration - fill rate code to duration table
Definition: ath5k_reset.c:156
#define AR5K_STA_ID1_ACKCTS_6MB
Definition: reg.h:1142
u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
Definition: ath5k_gpio.c:64
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
#define AR5K_PHY_ACT_ENABLE
Definition: reg.h:1933
#define AR5K_RXCFG_SDMAMW
Definition: reg.h:197
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104
#define AR5K_PHY_ACT
Definition: reg.h:1932
#define AR5K_REG_SM(_val, _flags)
Definition: ath5k.h:84

References ah, AR5K_ANT_FIXED_A, AR5K_ANT_FIXED_B, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_BEACON, AR5K_BEACON_ENABLE, AR5K_BEACON_RESET_TSF, AR5K_DEFAULT_ANTENNA, AR5K_DMASIZE_128B, AR5K_EEPROM_HDR_RFKILL, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_GPIOCR, AR5K_GPIODO, AR5K_HIGH_ID, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_LOW_ID, AR5K_MIC_QOS_CTL, AR5K_MIC_QOS_SEL, AR5K_MODE_11A, AR5K_MODE_11A_TURBO, AR5K_MODE_11B, AR5K_MODE_11G, AR5K_MODE_11G_TURBO, AR5K_MODE_XR, AR5K_PCICFG, AR5K_PCICFG_LEDSTATE, AR5K_PHY, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ADC_TEST, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, AR5K_PHY_IQ_RUN, AR5K_PHY_RX_DELAY, AR5K_PHY_RX_DELAY_M, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY_TST1, AR5K_PHY_TST1_TXHOLD, AR5K_PISR, AR5K_QOS_NOACK, AR5K_QOS_NOACK_2BIT_VALUES, AR5K_QOS_NOACK_BIT_OFFSET, AR5K_QOS_NOACK_BYTE_OFFSET, AR5K_QUEUE_DCU_SEQNUM, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5111, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS_S, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_SREV_AR2413, AR5K_SREV_AR5211, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, AR5K_STA_ID1_DEFAULT_ANTENNA, AR5K_STA_ID1_DESC_ANTENNA, AR5K_STA_ID1_RTS_DEF_ANTENNA, AR5K_STA_ID1_SELFGEN_DEF_ANT, AR5K_TUNE_BMISS_THRES, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_RSSI_THRES, AR5K_TXCFG, AR5K_TXCFG_B_MODE, AR5K_TXCFG_SDMAMR, ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_gpio(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_tx_queue(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_imr(), ath5k_hw_set_opmode(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_write_initvals(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), channel, CHANNEL_A, CHANNEL_B, CHANNEL_CCK, CHANNEL_G, CHANNEL_MODES, CHANNEL_OFDM, CHANNEL_T, CHANNEL_TG, CHANNEL_XR, DBG, delay, EINVAL, mdelay(), NULL, and udelay().

Referenced by ath5k_reset().

◆ ath5k_hw_set_power()

int ath5k_hw_set_power ( struct ath5k_hw ah,
enum ath5k_power_mode  mode,
int  set_chip,
u16  sleep_duration 
)

◆ ath5k_hw_start_rx_dma()

void ath5k_hw_start_rx_dma ( struct ath5k_hw ah)

ath5k_hw_start_rx_dma - Start DMA receive

@ah: The &struct ath5k_hw

Definition at line 54 of file ath5k_dma.c.

55 {
58 }
#define AR5K_CR_RXE
Definition: reg.h:56
#define AR5K_CR
Definition: reg.h:53
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

References ah, AR5K_CR, AR5K_CR_RXE, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_rx_start().

◆ ath5k_hw_stop_rx_dma()

int ath5k_hw_stop_rx_dma ( struct ath5k_hw ah)

ath5k_hw_stop_rx_dma - Stop DMA receive

@ah: The &struct ath5k_hw

Definition at line 65 of file ath5k_dma.c.

66 {
67  unsigned int i;
68 
70 
71  /*
72  * It may take some time to disable the DMA receive unit
73  */
74  for (i = 1000; i > 0 &&
76  i--)
77  udelay(10);
78 
79  return i ? 0 : -EBUSY;
80 }
#define AR5K_CR_RXE
Definition: reg.h:56
#define EBUSY
Device or resource busy.
Definition: errno.h:338
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR5K_CR
Definition: reg.h:53
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
uint8_t ah
Definition: registers.h:85
#define AR5K_CR_RXD
Definition: reg.h:59
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

References ah, AR5K_CR, AR5K_CR_RXD, AR5K_CR_RXE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, and udelay().

Referenced by ath5k_rx_stop().

◆ ath5k_hw_get_rxdp()

u32 ath5k_hw_get_rxdp ( struct ath5k_hw ah)

ath5k_hw_get_rxdp - Get RX Descriptor's address

@ah: The &struct ath5k_hw

XXX: Is RXDP read and clear ?

Definition at line 89 of file ath5k_dma.c.

90 {
92 }
#define AR5K_RXDP
Definition: reg.h:65
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

References ah, AR5K_RXDP, and ath5k_hw_reg_read().

◆ ath5k_hw_set_rxdp()

void ath5k_hw_set_rxdp ( struct ath5k_hw ah,
u32  phys_addr 
)

ath5k_hw_set_rxdp - Set RX Descriptor's address

@ah: The &struct ath5k_hw @phys_addr: RX descriptor address

XXX: Should we check if rx is enabled before setting rxdp ?

Definition at line 102 of file ath5k_dma.c.

103 {
104  ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
105 }
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_RXDP
Definition: reg.h:65
uint8_t ah
Definition: registers.h:85

References ah, AR5K_RXDP, and ath5k_hw_reg_write().

Referenced by ath5k_rx_start().

◆ ath5k_hw_start_tx_dma()

int ath5k_hw_start_tx_dma ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue

@ah: The &struct ath5k_hw @queue: The hw queue number

Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.

NOTE: Must be called after setting up tx control descriptor for that queue (see below).

Definition at line 127 of file ath5k_dma.c.

128 {
129  u32 tx_queue;
130 
131  /* Return if queue is declared inactive */
132  if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
133  return -EIO;
134 
135  if (ah->ah_version == AR5K_AR5210) {
136  tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
137 
138  /* Assume always a data queue */
139  tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
140 
141  /* Start queue */
142  ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
144  } else {
145  /* Return if queue is disabled */
147  return -EIO;
148 
149  /* Start queue */
151  }
152 
153  return 0;
154 }
#define AR5K_QCU_TXE
Definition: reg.h:559
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)
Definition: ath5k.h:121
#define AR5K_CR_TXD0
Definition: reg.h:57
#define AR5K_QCU_TXD
Definition: reg.h:566
#define AR5K_CR
Definition: reg.h:53
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_REG_READ_Q(ah, _reg, _queue)
Definition: ath5k.h:118
#define EIO
Input/output error.
Definition: errno.h:433
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
uint16_t queue
Queue ID.
Definition: ena.h:22
uint32_t u32
Definition: stdint.h:23
#define AR5K_CR_TXE0
Definition: reg.h:54

References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_QCU_TXD, AR5K_QCU_TXE, AR5K_REG_READ_Q, AR5K_REG_WRITE_Q, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EIO, and queue.

Referenced by ath5k_txbuf_setup().

◆ ath5k_hw_stop_tx_dma()

int ath5k_hw_stop_tx_dma ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue

@ah: The &struct ath5k_hw @queue: The hw queue number

Stop DMA transmit on a specific hw queue and drain queue so we don't have any pending frames. Returns -EBUSY if we still have pending frames, -EINVAL if queue number is out of range.

Definition at line 167 of file ath5k_dma.c.

168 {
169  unsigned int i = 40;
170  u32 tx_queue, pending;
171 
172  /* Return if queue is declared inactive */
173  if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
174  return -EIO;
175 
176  if (ah->ah_version == AR5K_AR5210) {
177  tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
178 
179  /* Assume a data queue */
180  tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
181 
182  /* Stop queue */
183  ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
185  } else {
186  /*
187  * Schedule TX disable and wait until queue is empty
188  */
190 
191  /*Check for pending frames*/
192  do {
196  udelay(100);
197  } while (--i && pending);
198 
199  /* For 2413+ order PCU to drop packets using
200  * QUIET mechanism */
201  if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && pending) {
202  /* Set periodicity and duration */
207 
208  /* Enable quiet period for current TSF */
212  AR5K_TSF_L32_5211) >> 10,
215 
216  /* Force channel idle high */
219 
220  /* Wait a while and disable mechanism */
221  udelay(200);
224 
225  /* Re-check for pending frames */
226  i = 40;
227  do {
231  udelay(100);
232  } while (--i && pending);
233 
236  }
237 
238  /* Clear register */
240  if (pending)
241  return -EBUSY;
242  }
243 
244  /* TODO: Check for success on 5210 else return error */
245  return 0;
246 }
#define AR5K_QUIET_CTL1
Definition: reg.h:1680
#define EBUSY
Device or resource busy.
Definition: errno.h:338
#define AR5K_QUIET_CTL2_QT_DUR
Definition: reg.h:1689
uint32_t pending
Pending events.
Definition: hyperv.h:12
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)
Definition: ath5k.h:121
#define AR5K_QCU_STS_FRMPENDCNT
Definition: reg.h:627
#define AR5K_CR_TXD0
Definition: reg.h:57
#define AR5K_QUIET_CTL2_QT_PER
Definition: reg.h:1687
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH
Definition: reg.h:1433
#define AR5K_QCU_TXD
Definition: reg.h:566
#define AR5K_CR
Definition: reg.h:53
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_QUIET_CTL1_QT_EN
Definition: reg.h:1683
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:107
#define AR5K_QUEUE_STATUS(_q)
Definition: reg.h:629
#define AR5K_DIAG_SW_5211
Definition: reg.h:1391
#define EIO
Input/output error.
Definition: errno.h:433
#define AR5K_QUIET_CTL2
Definition: reg.h:1686
uint8_t ah
Definition: registers.h:85
#define AR5K_QUIET_CTL1_NEXT_QT_TSF
Definition: reg.h:1681
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
uint16_t queue
Queue ID.
Definition: ena.h:22
#define AR5K_TSF_L32_5211
Definition: reg.h:1440
uint32_t u32
Definition: stdint.h:23
#define AR5K_SREV_AR2414
Definition: ath5k.h:297
#define AR5K_CR_TXE0
Definition: reg.h:54
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104
#define AR5K_REG_SM(_val, _flags)
Definition: ath5k.h:84

References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_CHANEL_IDLE_HIGH, AR5K_QCU_STS_FRMPENDCNT, AR5K_QCU_TXD, AR5K_QUEUE_STATUS, AR5K_QUIET_CTL1, AR5K_QUIET_CTL1_NEXT_QT_TSF, AR5K_QUIET_CTL1_QT_EN, AR5K_QUIET_CTL2, AR5K_QUIET_CTL2_QT_DUR, AR5K_QUIET_CTL2_QT_PER, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SREV_AR2414, AR5K_TSF_L32_5211, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, EIO, pending, queue, and udelay().

Referenced by ath5k_txq_cleanup().

◆ ath5k_hw_get_txdp()

u32 ath5k_hw_get_txdp ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue

@ah: The &struct ath5k_hw @queue: The hw queue number

Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.

XXX: Is TXDP read and clear ?

Definition at line 261 of file ath5k_dma.c.

262 {
263  u16 tx_reg;
264 
265  /*
266  * Get the transmit queue descriptor pointer from the selected queue
267  */
268  /*5210 doesn't have QCU*/
269  if (ah->ah_version == AR5K_AR5210) {
270  /* Assume a data queue */
271  tx_reg = AR5K_NOQCU_TXDP0;
272  } else {
273  tx_reg = AR5K_QUEUE_TXDP(queue);
274  }
275 
276  return ath5k_hw_reg_read(ah, tx_reg);
277 }
uint16_t u16
Definition: stdint.h:21
#define AR5K_NOQCU_TXDP0
Definition: reg.h:47
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_QUEUE_TXDP(_q)
Definition: reg.h:554
uint16_t queue
Queue ID.
Definition: ena.h:22

References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QUEUE_TXDP, ath5k_hw_reg_read(), and queue.

Referenced by ath5k_txq_cleanup().

◆ ath5k_hw_set_txdp()

int ath5k_hw_set_txdp ( struct ath5k_hw ah,
unsigned int  queue,
u32  phys_addr 
)

ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue

@ah: The &struct ath5k_hw @queue: The hw queue number

Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.

Definition at line 292 of file ath5k_dma.c.

293 {
294  u16 tx_reg;
295 
296  /*
297  * Set the transmit queue descriptor pointer register by type
298  * on 5210
299  */
300  if (ah->ah_version == AR5K_AR5210) {
301  /* Assume a data queue */
302  tx_reg = AR5K_NOQCU_TXDP0;
303  } else {
304  /*
305  * Set the transmit queue descriptor pointer for
306  * the selected queue on QCU for 5211+
307  * (this won't work if the queue is still active)
308  */
310  return -EIO;
311 
312  tx_reg = AR5K_QUEUE_TXDP(queue);
313  }
314 
315  /* Set descriptor pointer */
316  ath5k_hw_reg_write(ah, phys_addr, tx_reg);
317 
318  return 0;
319 }
uint16_t u16
Definition: stdint.h:21
#define AR5K_QCU_TXE
Definition: reg.h:559
#define AR5K_NOQCU_TXDP0
Definition: reg.h:47
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_REG_READ_Q(ah, _reg, _queue)
Definition: ath5k.h:118
#define EIO
Input/output error.
Definition: errno.h:433
uint8_t ah
Definition: registers.h:85
#define AR5K_QUEUE_TXDP(_q)
Definition: reg.h:554
uint16_t queue
Queue ID.
Definition: ena.h:22

References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QCU_TXE, AR5K_QUEUE_TXDP, AR5K_REG_READ_Q, ath5k_hw_reg_write(), EIO, and queue.

Referenced by ath5k_txbuf_setup().

◆ ath5k_hw_update_tx_triglevel()

int ath5k_hw_update_tx_triglevel ( struct ath5k_hw ah,
int  increase 
)

ath5k_hw_update_tx_triglevel - Update tx trigger level

@ah: The &struct ath5k_hw @increase: Flag to force increase of trigger level

This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits it's data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems (i think bmiss is related). Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have have reached maximum/minimum.

XXX: Link this with tx DMA size ? XXX: Use it to save interrupts ? TODO: Needs testing, i think it's related to bmiss...

Definition at line 339 of file ath5k_dma.c.

340 {
341  u32 trigger_level, imr;
342  int ret = -EIO;
343 
344  /*
345  * Disable interrupts by setting the mask
346  */
347  imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
348 
349  trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
351 
352  if (!increase) {
353  if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
354  goto done;
355  } else
356  trigger_level +=
357  ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
358 
359  /*
360  * Update trigger level on success
361  */
362  if (ah->ah_version == AR5K_AR5210)
363  ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
364  else
366  AR5K_TXCFG_TXFULL, trigger_level);
367 
368  ret = 0;
369 
370 done:
371  /*
372  * Restore interrupt mask
373  */
375 
376  return ret;
377 }
Definition: sis900.h:27
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_TXCFG
Definition: reg.h:169
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
Definition: ath5k.h:96
#define AR5K_TUNE_MIN_TX_FIFO_THRES
Definition: ath5k.h:167
#define AR5K_TRIG_LVL
Definition: reg.h:1381
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_TXCFG_TXFULL
Definition: reg.h:174
#define EIO
Input/output error.
Definition: errno.h:433
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_TUNE_MAX_TX_FIFO_THRES
Definition: ath5k.h:168
enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
ath5k_hw_set_imr - Set interrupt mask
Definition: ath5k_dma.c:548
struct bofm_section_header done
Definition: bofm_test.c:46
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_AR5210, AR5K_INT_GLOBAL, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TRIG_LVL, AR5K_TUNE_MAX_TX_FIFO_THRES, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_TXCFG, AR5K_TXCFG_TXFULL, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_set_imr(), done, EIO, and imr.

Referenced by ath5k_poll().

◆ ath5k_hw_is_intr_pending()

int ath5k_hw_is_intr_pending ( struct ath5k_hw ah)

ath5k_hw_is_intr_pending - Check if we have pending interrupts

@ah: The &struct ath5k_hw

Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.

Definition at line 391 of file ath5k_dma.c.

392 {
393  return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
394 }
#define AR5K_INTPEND
Definition: reg.h:867
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214

References ah, AR5K_INTPEND, and ath5k_hw_reg_read().

Referenced by ath5k_poll().

◆ ath5k_hw_get_isr()

int ath5k_hw_get_isr ( struct ath5k_hw ah,
enum ath5k_int interrupt_mask 
)

Definition at line 412 of file ath5k_dma.c.

413 {
414  u32 data;
415 
416  /*
417  * Read interrupt status from the Interrupt Status register
418  * on 5210
419  */
420  if (ah->ah_version == AR5K_AR5210) {
422  if (data == AR5K_INT_NOCARD) {
423  *interrupt_mask = data;
424  return -ENODEV;
425  }
426  } else {
427  /*
428  * Read interrupt status from Interrupt
429  * Status Register shadow copy (Read And Clear)
430  *
431  * Note: PISR/SISR Not available on 5210
432  */
434  if (data == AR5K_INT_NOCARD) {
435  *interrupt_mask = data;
436  return -ENODEV;
437  }
438  }
439 
440  /*
441  * Get abstract interrupt mask (driver-compatible)
442  */
443  *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
444 
445  if (ah->ah_version != AR5K_AR5210) {
447 
448  /*HIU = Host Interface Unit (PCI etc)*/
449  if (data & (AR5K_ISR_HIUERR))
450  *interrupt_mask |= AR5K_INT_FATAL;
451 
452  /*Beacon Not Ready*/
453  if (data & (AR5K_ISR_BNR))
454  *interrupt_mask |= AR5K_INT_BNR;
455 
456  if (sisr2 & (AR5K_SISR2_SSERR | AR5K_SISR2_DPERR |
458  *interrupt_mask |= AR5K_INT_FATAL;
459 
460  if (data & AR5K_ISR_TIM)
461  *interrupt_mask |= AR5K_INT_TIM;
462 
463  if (data & AR5K_ISR_BCNMISC) {
464  if (sisr2 & AR5K_SISR2_TIM)
465  *interrupt_mask |= AR5K_INT_TIM;
466  if (sisr2 & AR5K_SISR2_DTIM)
467  *interrupt_mask |= AR5K_INT_DTIM;
468  if (sisr2 & AR5K_SISR2_DTIM_SYNC)
469  *interrupt_mask |= AR5K_INT_DTIM_SYNC;
470  if (sisr2 & AR5K_SISR2_BCN_TIMEOUT)
471  *interrupt_mask |= AR5K_INT_BCN_TIMEOUT;
472  if (sisr2 & AR5K_SISR2_CAB_TIMEOUT)
473  *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
474  }
475 
476  if (data & AR5K_ISR_RXDOPPLER)
477  *interrupt_mask |= AR5K_INT_RX_DOPPLER;
478  if (data & AR5K_ISR_QCBRORN) {
479  *interrupt_mask |= AR5K_INT_QCBRORN;
480  ah->ah_txq_isr |= AR5K_REG_MS(
483  }
484  if (data & AR5K_ISR_QCBRURN) {
485  *interrupt_mask |= AR5K_INT_QCBRURN;
486  ah->ah_txq_isr |= AR5K_REG_MS(
489  }
490  if (data & AR5K_ISR_QTRIG) {
491  *interrupt_mask |= AR5K_INT_QTRIG;
492  ah->ah_txq_isr |= AR5K_REG_MS(
495  }
496 
497  if (data & AR5K_ISR_TXOK)
498  ah->ah_txq_isr |= AR5K_REG_MS(
501 
502  if (data & AR5K_ISR_TXDESC)
503  ah->ah_txq_isr |= AR5K_REG_MS(
506 
507  if (data & AR5K_ISR_TXERR)
508  ah->ah_txq_isr |= AR5K_REG_MS(
511 
512  if (data & AR5K_ISR_TXEOL)
513  ah->ah_txq_isr |= AR5K_REG_MS(
516 
517  if (data & AR5K_ISR_TXURN)
518  ah->ah_txq_isr |= AR5K_REG_MS(
521  } else {
524  *interrupt_mask |= AR5K_INT_FATAL;
525 
526  /*
527  * XXX: BMISS interrupts may occur after association.
528  * I found this on 5210 code but it needs testing. If this is
529  * true we should disable them before assoc and re-enable them
530  * after a successful assoc + some jiffies.
531  interrupt_mask &= ~AR5K_INT_BMISS;
532  */
533  }
534 
535  return 0;
536 }
#define AR5K_SISR2_TIM
Definition: reg.h:345
#define AR5K_ISR_QCBRURN
Definition: reg.h:318
#define AR5K_RAC_SISR3
Definition: reg.h:370
#define AR5K_ISR_HIUERR
Definition: reg.h:306
#define AR5K_SISR2_CAB_TIMEOUT
Definition: reg.h:349
#define AR5K_SISR2_DPERR
Definition: reg.h:344
#define AR5K_ISR_MCABT
Definition: reg.h:308
#define AR5K_ISR_TIM
Definition: reg.h:313
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_RAC_PISR
Definition: reg.h:366
#define AR5K_ISR_TXDESC
Definition: reg.h:294
#define AR5K_SISR3_QCBRURN
Definition: reg.h:356
#define AR5K_SISR1_QCU_TXEOL
Definition: reg.h:336
#define AR5K_ISR_RXDOPPLER
Definition: reg.h:312
#define AR5K_SISR2_DTIM_SYNC
Definition: reg.h:347
#define AR5K_SISR1_QCU_TXERR
Definition: reg.h:334
#define AR5K_ISR_QTRIG
Definition: reg.h:319
#define AR5K_RAC_SISR4
Definition: reg.h:371
#define AR5K_ISR_TXEOL
Definition: reg.h:297
#define AR5K_ISR_QCBRORN
Definition: reg.h:317
#define AR5K_ISR_SSERR
Definition: reg.h:310
#define AR5K_ISR_BCNMISC
Definition: reg.h:314
#define ENODEV
No such device.
Definition: errno.h:509
#define AR5K_ISR_TXURN
Definition: reg.h:298
#define AR5K_ISR_TXOK
Definition: reg.h:293
#define AR5K_ISR
Definition: reg.h:285
#define AR5K_RAC_SISR1
Definition: reg.h:368
#define AR5K_SISR2_QCU_TXURN
Definition: reg.h:340
#define AR5K_ISR_TXERR
Definition: reg.h:295
#define AR5K_ISR_DPERR
Definition: reg.h:311
#define AR5K_SISR4_QTRIG
Definition: reg.h:360
uint8_t ah
Definition: registers.h:85
#define AR5K_SISR2_BCN_TIMEOUT
Definition: reg.h:348
#define AR5K_SISR0_QCU_TXDESC
Definition: reg.h:330
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
#define AR5K_RAC_SISR0
Definition: reg.h:367
#define AR5K_SISR3_QCBRORN
Definition: reg.h:354
#define AR5K_SISR2_SSERR
Definition: reg.h:343
#define AR5K_ISR_BNR
Definition: reg.h:307
#define AR5K_SISR2_DTIM
Definition: reg.h:350
#define AR5K_SISR0_QCU_TXOK
Definition: reg.h:328
uint32_t u32
Definition: stdint.h:23
#define AR5K_SISR2_MCABT
Definition: reg.h:342
if(natsemi->flags &NATSEMI_64BIT) return 1
#define AR5K_RAC_SISR2
Definition: reg.h:369

References ah, AR5K_AR5210, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_NOCARD, AR5K_INT_QCBRORN, AR5K_INT_QCBRURN, AR5K_INT_QTRIG, AR5K_INT_RX_DOPPLER, AR5K_INT_TIM, AR5K_ISR, AR5K_ISR_BCNMISC, AR5K_ISR_BNR, AR5K_ISR_DPERR, AR5K_ISR_HIUERR, AR5K_ISR_MCABT, AR5K_ISR_QCBRORN, AR5K_ISR_QCBRURN, AR5K_ISR_QTRIG, AR5K_ISR_RXDOPPLER, AR5K_ISR_SSERR, AR5K_ISR_TIM, AR5K_ISR_TXDESC, AR5K_ISR_TXEOL, AR5K_ISR_TXERR, AR5K_ISR_TXOK, AR5K_ISR_TXURN, AR5K_RAC_PISR, AR5K_RAC_SISR0, AR5K_RAC_SISR1, AR5K_RAC_SISR2, AR5K_RAC_SISR3, AR5K_RAC_SISR4, AR5K_REG_MS, AR5K_SISR0_QCU_TXDESC, AR5K_SISR0_QCU_TXOK, AR5K_SISR1_QCU_TXEOL, AR5K_SISR1_QCU_TXERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DPERR, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_MCABT, AR5K_SISR2_QCU_TXURN, AR5K_SISR2_SSERR, AR5K_SISR2_TIM, AR5K_SISR3_QCBRORN, AR5K_SISR3_QCBRURN, AR5K_SISR4_QTRIG, ath5k_hw_reg_read(), data, ENODEV, and if().

Referenced by ath5k_poll().

◆ ath5k_hw_set_imr()

enum ath5k_int ath5k_hw_set_imr ( struct ath5k_hw ah,
enum ath5k_int  new_mask 
)

ath5k_hw_set_imr - Set interrupt mask

@ah: The &struct ath5k_hw @new_mask: The new interrupt mask to be set

Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.

Definition at line 548 of file ath5k_dma.c.

549 {
550  enum ath5k_int old_mask, int_mask;
551 
552  old_mask = ah->ah_imr;
553 
554  /*
555  * Disable card interrupts to prevent any race conditions
556  * (they will be re-enabled afterwards if AR5K_INT GLOBAL
557  * is set again on the new mask).
558  */
559  if (old_mask & AR5K_INT_GLOBAL) {
562  }
563 
564  /*
565  * Add additional, chipset-dependent interrupt mask flags
566  * and write them to the IMR (interrupt mask register).
567  */
568  int_mask = new_mask & AR5K_INT_COMMON;
569 
570  if (ah->ah_version != AR5K_AR5210) {
571  /* Preserve per queue TXURN interrupt mask */
574 
575  if (new_mask & AR5K_INT_FATAL) {
576  int_mask |= AR5K_IMR_HIUERR;
578  | AR5K_SIMR2_DPERR);
579  }
580 
581  /*Beacon Not Ready*/
582  if (new_mask & AR5K_INT_BNR)
583  int_mask |= AR5K_INT_BNR;
584 
585  if (new_mask & AR5K_INT_TIM)
586  int_mask |= AR5K_IMR_TIM;
587 
588  if (new_mask & AR5K_INT_TIM)
589  simr2 |= AR5K_SISR2_TIM;
590  if (new_mask & AR5K_INT_DTIM)
591  simr2 |= AR5K_SISR2_DTIM;
592  if (new_mask & AR5K_INT_DTIM_SYNC)
593  simr2 |= AR5K_SISR2_DTIM_SYNC;
594  if (new_mask & AR5K_INT_BCN_TIMEOUT)
595  simr2 |= AR5K_SISR2_BCN_TIMEOUT;
596  if (new_mask & AR5K_INT_CAB_TIMEOUT)
597  simr2 |= AR5K_SISR2_CAB_TIMEOUT;
598 
599  if (new_mask & AR5K_INT_RX_DOPPLER)
600  int_mask |= AR5K_IMR_RXDOPPLER;
601 
602  /* Note: Per queue interrupt masks
603  * are set via reset_tx_queue (qcu.c) */
604  ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
606 
607  } else {
608  if (new_mask & AR5K_INT_FATAL)
609  int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
611 
612  ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
613  }
614 
615  /* If RXNOFRM interrupt is masked disable it
616  * by setting AR5K_RXNOFRM to zero */
617  if (!(new_mask & AR5K_INT_RXNOFRM))
619 
620  /* Store new interrupt mask */
621  ah->ah_imr = new_mask;
622 
623  /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */
624  if (new_mask & AR5K_INT_GLOBAL) {
625  ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
627  }
628 
629  return old_mask;
630 }
#define AR5K_SISR2_TIM
Definition: reg.h:345
#define AR5K_SIMR2_MCABT
Definition: reg.h:433
#define AR5K_SISR2_CAB_TIMEOUT
Definition: reg.h:349
#define AR5K_IMR_SSERR
Definition: reg.h:404
#define AR5K_IMR_MCABT
Definition: reg.h:402
#define AR5K_IMR_TIM
Definition: reg.h:407
#define AR5K_SISR2_DTIM_SYNC
Definition: reg.h:347
#define AR5K_PIMR
Definition: reg.h:380
#define AR5K_SIMR2
Definition: reg.h:430
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_SIMR2_SSERR
Definition: reg.h:434
#define AR5K_IMR_RXDOPPLER
Definition: reg.h:406
#define AR5K_IER_DISABLE
Definition: reg.h:91
#define AR5K_RXNOFRM
Definition: reg.h:229
#define AR5K_IMR
Definition: reg.h:379
uint8_t ah
Definition: registers.h:85
#define AR5K_IER
Definition: reg.h:90
#define AR5K_SISR2_BCN_TIMEOUT
Definition: reg.h:348
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_IMR_HIUERR
Definition: reg.h:400
#define AR5K_IMR_DPERR
Definition: reg.h:405
#define AR5K_SISR2_DTIM
Definition: reg.h:350
#define AR5K_SIMR2_DPERR
Definition: reg.h:435
#define AR5K_SIMR2_QCU_TXURN
Definition: reg.h:431
ath5k_int
enum ath5k_int - Hardware interrupt masks helpers
Definition: ath5k.h:804
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_AR5210, AR5K_IER, AR5K_IER_DISABLE, AR5K_IMR, AR5K_IMR_DPERR, AR5K_IMR_HIUERR, AR5K_IMR_MCABT, AR5K_IMR_RXDOPPLER, AR5K_IMR_SSERR, AR5K_IMR_TIM, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_GLOBAL, AR5K_INT_RX_DOPPLER, AR5K_INT_RXNOFRM, AR5K_INT_TIM, AR5K_PIMR, AR5K_RXNOFRM, AR5K_SIMR2, AR5K_SIMR2_DPERR, AR5K_SIMR2_MCABT, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR2_SSERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_TIM, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_hw_reset(), ath5k_hw_update_tx_triglevel(), ath5k_irq(), ath5k_reset(), and ath5k_stop_hw().

◆ ath5k_eeprom_init()

int ath5k_eeprom_init ( struct ath5k_hw ah)

Definition at line 1693 of file ath5k_eeprom.c.

1694 {
1695  int err;
1696 
1698  if (err < 0)
1699  return err;
1700 
1701  err = ath5k_eeprom_init_modes(ah);
1702  if (err < 0)
1703  return err;
1704 
1706  if (err < 0)
1707  return err;
1708 
1710  if (err < 0)
1711  return err;
1712 
1713  return 0;
1714 }
static int ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
static int ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
static int ath5k_eeprom_init_header(struct ath5k_hw *ah)
Definition: ath5k_eeprom.c:100
uint8_t ah
Definition: registers.h:85
static int ath5k_eeprom_init_modes(struct ath5k_hw *ah)
Definition: ath5k_eeprom.c:459

References ah, ath5k_eeprom_init_header(), ath5k_eeprom_init_modes(), ath5k_eeprom_read_ctl_info(), and ath5k_eeprom_read_pcal_info().

Referenced by ath5k_hw_attach().

◆ ath5k_eeprom_detach()

void ath5k_eeprom_detach ( struct ath5k_hw ah)

Definition at line 1572 of file ath5k_eeprom.c.

1573 {
1574  u8 mode;
1575 
1576  for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1578 }
#define AR5K_EEPROM_MODE_11G
Definition: eeprom.h:64
#define AR5K_EEPROM_MODE_11A
Definition: eeprom.h:62
static int ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19

References ah, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11G, and ath5k_eeprom_free_pcal_info().

Referenced by ath5k_hw_detach().

◆ ath5k_eeprom_read_mac()

int ath5k_eeprom_read_mac ( struct ath5k_hw ah,
u8 mac 
)

Definition at line 1719 of file ath5k_eeprom.c.

1720 {
1721  u8 mac_d[ETH_ALEN] = {};
1722  u32 total, offset;
1723  u16 data;
1724  int octet, ret;
1725 
1726  ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1727  if (ret)
1728  return ret;
1729 
1730  for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1731  ret = ath5k_hw_eeprom_read(ah, offset, &data);
1732  if (ret)
1733  return ret;
1734 
1735  total += data;
1736  mac_d[octet + 1] = data & 0xff;
1737  mac_d[octet] = data >> 8;
1738  octet += 2;
1739  }
1740 
1741  if (!total || total == 3 * 0xffff)
1742  return -EINVAL;
1743 
1744  memcpy(mac, mac_d, ETH_ALEN);
1745 
1746  return 0;
1747 }
uint16_t u16
Definition: stdint.h:21
#define EINVAL
Invalid argument.
Definition: errno.h:428
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
Definition: ath5k_eeprom.c:38
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
#define ETH_ALEN
Definition: if_ether.h:8
uint8_t ah
Definition: registers.h:85
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23

References ah, ath5k_hw_eeprom_read(), data, EINVAL, ETH_ALEN, mac, memcpy(), and offset.

Referenced by ath5k_attach().

◆ ath5k_eeprom_is_hb63()

int ath5k_eeprom_is_hb63 ( struct ath5k_hw ah)

Definition at line 1749 of file ath5k_eeprom.c.

1750 {
1751  u16 data;
1752 
1754 
1755  if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
1756  return 1;
1757  else
1758  return 0;
1759 }
uint16_t u16
Definition: stdint.h:21
#define AR5K_EEPROM_IS_HB63
Definition: eeprom.h:28
static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
Definition: ath5k_eeprom.c:38
#define AR5K_SREV_AR2425
Definition: ath5k.h:304
uint8_t ah
Definition: registers.h:85
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12

References ah, AR5K_EEPROM_IS_HB63, AR5K_SREV_AR2425, ath5k_hw_eeprom_read(), and data.

Referenced by ath5k_hw_tweak_initval_settings().

◆ ath5k_hw_set_opmode()

int ath5k_hw_set_opmode ( struct ath5k_hw ah)

ath5k_hw_set_opmode - Set PCU operating mode

@ah: The &struct ath5k_hw

Initialize PCU for the various operating modes (AP/STA etc)

For iPXE we always assume STA mode.

Definition at line 48 of file ath5k_pcu.c.

49 {
50  u32 pcu_reg, beacon_reg, low_id, high_id;
51 
52 
53  /* Preserve rest settings */
54  pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55  pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
57  | (ah->ah_version == AR5K_AR5210 ?
59 
60  beacon_reg = 0;
61 
62  pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
63  | (ah->ah_version == AR5K_AR5210 ?
65 
66  /*
67  * Set PCU registers
68  */
69  low_id = AR5K_LOW_ID(ah->ah_sta_id);
70  high_id = AR5K_HIGH_ID(ah->ah_sta_id);
72  ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
73 
74  /*
75  * Set Beacon Control Register on 5210
76  */
77  if (ah->ah_version == AR5K_AR5210)
78  ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
79 
80  return 0;
81 }
#define AR5K_STA_ID1_KEYSRCH_MODE
Definition: reg.h:1146
#define AR5K_BCR
Definition: reg.h:103
#define AR5K_STA_ID0
Definition: reg.h:1122
#define AR5K_STA_ID1_ADHOC
Definition: reg.h:1131
#define AR5K_LOW_ID(_a)
Definition: ath5k.h:152
#define AR5K_HIGH_ID(_a)
Definition: ath5k.h:156
#define AR5K_STA_ID1
Definition: reg.h:1128
#define AR5K_STA_ID1_PWR_SV
Definition: reg.h:1132
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_STA_ID1_AP
Definition: reg.h:1130
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
uint32_t u32
Definition: stdint.h:23
#define AR5K_STA_ID1_NO_PSPOLL
Definition: reg.h:1134

References ah, AR5K_AR5210, AR5K_BCR, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ADHOC, AR5K_STA_ID1_AP, AR5K_STA_ID1_KEYSRCH_MODE, AR5K_STA_ID1_NO_PSPOLL, AR5K_STA_ID1_PWR_SV, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_hw_attach(), ath5k_hw_reset(), and ath5k_mode_setup().

◆ ath5k_hw_get_lladdr()

void ath5k_hw_get_lladdr ( struct ath5k_hw ah,
u8 mac 
)

ath5k_hw_get_lladdr - Get station id

@ah: The &struct ath5k_hw @mac: The card's mac address

Initialize ah->ah_sta_id using the mac address provided (just a memcpy).

TODO: Remove it once we merge ath5k_softc and ath5k_hw

Definition at line 187 of file ath5k_pcu.c.

188 {
189  memcpy(mac, ah->ah_sta_id, ETH_ALEN);
190 }
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define ETH_ALEN
Definition: if_ether.h:8
uint8_t ah
Definition: registers.h:85

References ah, ETH_ALEN, mac, and memcpy().

◆ ath5k_hw_set_lladdr()

int ath5k_hw_set_lladdr ( struct ath5k_hw ah,
const u8 mac 
)

ath5k_hw_set_lladdr - Set station id

@ah: The &struct ath5k_hw @mac: The card's mac address

Set station id on hw using the provided mac address

Definition at line 200 of file ath5k_pcu.c.

201 {
202  u32 low_id, high_id;
203  u32 pcu_reg;
204 
205  /* Set new station ID */
206  memcpy(ah->ah_sta_id, mac, ETH_ALEN);
207 
208  pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
209 
210  low_id = AR5K_LOW_ID(mac);
211  high_id = AR5K_HIGH_ID(mac);
212 
214  ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
215 
216  return 0;
217 }
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define AR5K_STA_ID0
Definition: reg.h:1122
#define AR5K_LOW_ID(_a)
Definition: ath5k.h:152
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define AR5K_HIGH_ID(_a)
Definition: ath5k.h:156
#define AR5K_STA_ID1
Definition: reg.h:1128
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define ETH_ALEN
Definition: if_ether.h:8
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ETH_ALEN, mac, and memcpy().

Referenced by ath5k_start(), and ath5k_stop().

◆ ath5k_hw_set_associd()

void ath5k_hw_set_associd ( struct ath5k_hw ah,
const u8 bssid,
u16  assoc_id 
)

ath5k_hw_set_associd - Set BSSID for association

@ah: The &struct ath5k_hw @bssid: BSSID @assoc_id: Assoc id

Sets the BSSID which trigers the "SME Join" operation

Definition at line 228 of file ath5k_pcu.c.

229 {
230  u32 low_id, high_id;
231 
232  /*
233  * Set simple BSSID mask on 5212
234  */
235  if (ah->ah_version == AR5K_AR5212) {
236  ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask),
237  AR5K_BSS_IDM0);
238  ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask),
239  AR5K_BSS_IDM1);
240  }
241 
242  /*
243  * Set BSSID which triggers the "SME Join" operation
244  */
245  low_id = AR5K_LOW_ID(bssid);
246  high_id = AR5K_HIGH_ID(bssid);
248  ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
250 }
#define AR5K_BSS_ID0
Definition: reg.h:1154
#define AR5K_BSS_ID1_AID_S
Definition: reg.h:1163
#define AR5K_BSS_IDM0
Definition: reg.h:1650
#define AR5K_LOW_ID(_a)
Definition: ath5k.h:152
#define AR5K_HIGH_ID(_a)
Definition: ath5k.h:156
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_BSS_IDM1
Definition: reg.h:1651
#define AR5K_BSS_ID1
Definition: reg.h:1161
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_AR5212, AR5K_BSS_ID0, AR5K_BSS_ID1, AR5K_BSS_ID1_AID_S, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, and ath5k_hw_reg_write().

Referenced by ath5k_config(), ath5k_hw_attach(), and ath5k_hw_reset().

◆ ath5k_hw_set_bssid_mask()

int ath5k_hw_set_bssid_mask ( struct ath5k_hw ah,
const u8 mask 
)

ath5k_hw_set_bssid_mask - filter out bssids we listen

@ah: the &struct ath5k_hw @mask: the bssid_mask, a u8 array of size ETH_ALEN

BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.

NOTE: This is a simple filter and does not filter out all relevant frames. Some frames that are not for us might get ACKed from us by PCU because they just match the mask.

When handling multiple BSSes you can get the BSSID mask by computing the set of ~ ( MAC XOR BSSID ) for all bssids we handle.

When you do this you are essentially computing the common bits of all your BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with the MAC address to obtain the relevant bits and compare the result with (frame's BSSID & mask) to see if they match.

Definition at line 348 of file ath5k_pcu.c.

349 {
350  u32 low_id, high_id;
351 
352  /* Cache bssid mask so that we can restore it
353  * on reset */
354  memcpy(ah->ah_bssid_mask, mask, ETH_ALEN);
355  if (ah->ah_version == AR5K_AR5212) {
356  low_id = AR5K_LOW_ID(mask);
357  high_id = AR5K_HIGH_ID(mask);
358 
361 
362  return 0;
363  }
364 
365  return -EIO;
366 }
#define AR5K_BSS_IDM0
Definition: reg.h:1650
#define AR5K_LOW_ID(_a)
Definition: ath5k.h:152
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define AR5K_HIGH_ID(_a)
Definition: ath5k.h:156
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define ETH_ALEN
Definition: if_ether.h:8
#define AR5K_BSS_IDM1
Definition: reg.h:1651
#define EIO
Input/output error.
Definition: errno.h:433
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_AR5212, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, ath5k_hw_reg_write(), EIO, ETH_ALEN, and memcpy().

Referenced by ath5k_attach(), and ath5k_mode_setup().

◆ ath5k_hw_start_rx_pcu()

void ath5k_hw_start_rx_pcu ( struct ath5k_hw ah)

ath5k_hw_start_rx_pcu - Start RX engine

@ah: The &struct ath5k_hw

Starts RX engine on PCU so that hw can process RXed frames (ACK etc).

NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma TODO: Init ANI here

Definition at line 384 of file ath5k_pcu.c.

385 {
387 }
#define AR5K_DIAG_SW_DIS_RX
Definition: reg.h:1402
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:107
#define AR5K_DIAG_SW
Definition: reg.h:1392
uint8_t ah
Definition: registers.h:85

References ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_DISABLE_BITS.

Referenced by ath5k_rx_start().

◆ ath5k_hw_stop_rx_pcu()

void ath5k_hw_stop_rx_pcu ( struct ath5k_hw ah)

at5k_hw_stop_rx_pcu - Stop RX engine

@ah: The &struct ath5k_hw

Stops RX engine on PCU

TODO: Detach ANI here

Definition at line 398 of file ath5k_pcu.c.

399 {
401 }
#define AR5K_DIAG_SW_DIS_RX
Definition: reg.h:1402
#define AR5K_DIAG_SW
Definition: reg.h:1392
uint8_t ah
Definition: registers.h:85
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104

References ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_ENABLE_BITS.

Referenced by ath5k_rx_stop().

◆ ath5k_hw_set_mcast_filter()

void ath5k_hw_set_mcast_filter ( struct ath5k_hw ah,
u32  filter0,
u32  filter1 
)

Definition at line 406 of file ath5k_pcu.c.

407 {
408  /* Set the multicat filter */
411 }
#define AR5K_MCAST_FILTER0
Definition: reg.h:1351
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_MCAST_FILTER1
Definition: reg.h:1359
uint8_t ah
Definition: registers.h:85

References ah, AR5K_MCAST_FILTER0, AR5K_MCAST_FILTER1, and ath5k_hw_reg_write().

Referenced by ath5k_configure_filter(), and ath5k_mode_setup().

◆ ath5k_hw_get_rx_filter()

u32 ath5k_hw_get_rx_filter ( struct ath5k_hw ah)

ath5k_hw_get_rx_filter - Get current rx filter

@ah: The &struct ath5k_hw

Returns the RX filter by reading rx filter and phy error filter registers. RX filter is used to set the allowed frame types that PCU will accept and pass to the driver. For a list of frame types check out reg.h.

Definition at line 424 of file ath5k_pcu.c.

425 {
426  u32 data, filter = 0;
427 
429 
430  /*Radar detection for 5212*/
431  if (ah->ah_version == AR5K_AR5212) {
433 
438  }
439 
440  return filter;
441 }
#define AR5K_PHY_ERR_FIL_RADAR
Definition: reg.h:1714
#define AR5K_PHY_ERR_FIL_OFDM
Definition: reg.h:1715
#define AR5K_RX_FILTER_RADARERR
Definition: reg.h:1342
UINT8_t filter
Receive packet filter.
Definition: pxe_api.h:68
#define AR5K_PHY_ERR_FIL
Definition: reg.h:1713
#define AR5K_RX_FILTER
Definition: reg.h:1325
#define AR5K_RX_FILTER_PHYERR
Definition: reg.h:1339
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
#define AR5K_PHY_ERR_FIL_CCK
Definition: reg.h:1716
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_RADARERR, ath5k_hw_reg_read(), data, and filter.

◆ ath5k_hw_set_rx_filter()

void ath5k_hw_set_rx_filter ( struct ath5k_hw ah,
u32  filter 
)

ath5k_hw_set_rx_filter - Set rx filter

@ah: The &struct ath5k_hw @filter: RX filter mask (see reg.h)

Sets RX filter register and also handles PHY error filter register on 5212 and newer chips so that we have proper PHY error reporting.

Definition at line 453 of file ath5k_pcu.c.

454 {
455  u32 data = 0;
456 
457  /* Set PHY error filter register on 5212*/
458  if (ah->ah_version == AR5K_AR5212) {
46