iPXE
atl1e.h
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1 /*
2  * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3  * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
4  *
5  * Derived from Intel e1000 driver
6  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7  *
8  * Modified for iPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License as published by the Free
12  * Software Foundation; either version 2 of the License, or (at your option)
13  * any later version.
14  *
15  * This program is distributed in the hope that it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License along with
21  * this program; if not, write to the Free Software Foundation, Inc., 51
22  * Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
23  */
24 
25 FILE_LICENCE ( GPL2_OR_LATER );
26 
27 #ifndef _ATL1E_H_
28 #define _ATL1E_H_
29 
30 #include <mii.h>
31 #include <stdlib.h>
32 #include <string.h>
33 #include <unistd.h>
34 #include <byteswap.h>
35 #include <errno.h>
36 #include <ipxe/malloc.h>
37 #include <ipxe/pci.h>
38 #include <ipxe/pci_io.h>
39 #include <ipxe/iobuf.h>
40 #include <ipxe/netdevice.h>
41 #include <ipxe/ethernet.h>
42 #include <ipxe/if_ether.h>
43 #include <ipxe/io.h>
44 
45 #define ETH_FCS_LEN 4
46 #define VLAN_HLEN 4
47 #define NET_IP_ALIGN 2
48 
49 #define SPEED_0 0xffff
50 #define SPEED_10 10
51 #define SPEED_100 100
52 #define SPEED_1000 1000
53 #define HALF_DUPLEX 1
54 #define FULL_DUPLEX 2
55 
56 /* Error Codes */
57 #define AT_ERR_EEPROM 1
58 #define AT_ERR_PHY 2
59 #define AT_ERR_CONFIG 3
60 #define AT_ERR_PARAM 4
61 #define AT_ERR_MAC_TYPE 5
62 #define AT_ERR_PHY_TYPE 6
63 #define AT_ERR_PHY_SPEED 7
64 #define AT_ERR_PHY_RES 8
65 #define AT_ERR_TIMEOUT 9
66 
67 #define AT_MAX_RECEIVE_QUEUE 4
68 #define AT_PAGE_NUM_PER_QUEUE 2
69 
70 #define AT_TWSI_EEPROM_TIMEOUT 100
71 #define AT_HW_MAX_IDLE_DELAY 10
72 
73 #define AT_REGS_LEN 75
74 #define AT_EEPROM_LEN 512
75 
76 /* tpd word 2 */
77 #define TPD_BUFLEN_MASK 0x3FFF
78 #define TPD_BUFLEN_SHIFT 0
79 
80 /* tpd word 3 bits 0:4 */
81 #define TPD_EOP_MASK 0x0001
82 #define TPD_EOP_SHIFT 0
83 
88 };
89 
90 #define MAX_TX_BUF_LEN 0x2000
91 #define MAX_TX_BUF_SHIFT 13
92 
93 /* rrs word 1 bit 0:31 */
94 #define RRS_RX_CSUM_MASK 0xFFFF
95 #define RRS_RX_CSUM_SHIFT 0
96 #define RRS_PKT_SIZE_MASK 0x3FFF
97 #define RRS_PKT_SIZE_SHIFT 16
98 #define RRS_CPU_NUM_MASK 0x0003
99 #define RRS_CPU_NUM_SHIFT 30
100 
101 #define RRS_IS_RSS_IPV4 0x0001
102 #define RRS_IS_RSS_IPV4_TCP 0x0002
103 #define RRS_IS_RSS_IPV6 0x0004
104 #define RRS_IS_RSS_IPV6_TCP 0x0008
105 #define RRS_IS_IPV6 0x0010
106 #define RRS_IS_IP_FRAG 0x0020
107 #define RRS_IS_IP_DF 0x0040
108 #define RRS_IS_802_3 0x0080
109 #define RRS_IS_VLAN_TAG 0x0100
110 #define RRS_IS_ERR_FRAME 0x0200
111 #define RRS_IS_IPV4 0x0400
112 #define RRS_IS_UDP 0x0800
113 #define RRS_IS_TCP 0x1000
114 #define RRS_IS_BCAST 0x2000
115 #define RRS_IS_MCAST 0x4000
116 #define RRS_IS_PAUSE 0x8000
117 
118 #define RRS_ERR_BAD_CRC 0x0001
119 #define RRS_ERR_CODE 0x0002
120 #define RRS_ERR_DRIBBLE 0x0004
121 #define RRS_ERR_RUNT 0x0008
122 #define RRS_ERR_RX_OVERFLOW 0x0010
123 #define RRS_ERR_TRUNC 0x0020
124 #define RRS_ERR_IP_CSUM 0x0040
125 #define RRS_ERR_L4_CSUM 0x0080
126 #define RRS_ERR_LENGTH 0x0100
127 #define RRS_ERR_DES_ADDR 0x0200
128 
137 };
138 
146 };
147 
149  athr_l1e = 0,
152 };
153 
154 struct atl1e_hw {
155  u8 *hw_addr; /* inner register address */
160 
163 
166 
169  int emi_ca;
170 };
171 
172 /*
173  * wrapper around a pointer to a socket buffer,
174  * so a DMA handle can be stored along with the buffer
175  */
177  struct io_buffer *iob;
180 };
181 
183  u32 dma; /* receive rage DMA address */
184  u8 *addr; /* receive rage virtual address */
185  u32 write_offset_dma; /* the DMA address which contain the
186  receive data offset in the page */
187  u32 *write_offset_addr; /* the virtaul address which contain
188  the receive data offset in the page */
189  u32 read_offset; /* the offset where we have read */
190 };
191 
196 };
197 
198 /* transmit packet descriptor (tpd) ring */
200  struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */
201  u32 dma; /* descriptor ring physical address */
202  u16 count; /* the count of transmit rings */
208 };
209 
210 /* receive packet descriptor ring */
212  void *desc;
214  int size;
215  u32 page_size; /* bytes length of rxf page */
216  u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
218 };
219 
220 /* board specific private data structure */
223  struct pci_device *pdev;
224  struct mii_if_info mii; /* MII interface info */
225  struct atl1e_hw hw;
226 
229 
230  /* All Descriptor memory */
234 
237 
238  int bd_number; /* board number;*/
239 };
240 
241 #define AT_WRITE_REG(a, reg, value) \
242  writel((value), ((a)->hw_addr + reg))
243 
244 #define AT_WRITE_FLUSH(a) \
245  readl((a)->hw_addr)
246 
247 #define AT_READ_REG(a, reg) \
248  readl((a)->hw_addr + reg)
249 
250 #define AT_WRITE_REGB(a, reg, value) \
251  writeb((value), ((a)->hw_addr + reg))
252 
253 #define AT_READ_REGB(a, reg) \
254  readb((a)->hw_addr + reg)
255 
256 #define AT_WRITE_REGW(a, reg, value) \
257  writew((value), ((a)->hw_addr + reg))
258 
259 #define AT_READ_REGW(a, reg) \
260  readw((a)->hw_addr + reg)
261 
262 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) \
263  writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))
264 
265 #define AT_READ_REG_ARRAY(a, reg, offset) \
266  readl(((a)->hw_addr + reg) + ((offset) << 2))
267 
268 extern int atl1e_up(struct atl1e_adapter *adapter);
269 extern void atl1e_down(struct atl1e_adapter *adapter);
270 extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
271 
272 /********** Hardware-level functionality: **********/
273 
274 /* function prototype */
275 s32 atl1e_reset_hw(struct atl1e_hw *hw);
277 s32 atl1e_init_hw(struct atl1e_hw *hw);
280 u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
281 s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
282 s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
284 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
287 s32 atl1e_phy_init(struct atl1e_hw *hw);
289 void atl1e_force_ps(struct atl1e_hw *hw);
291 
292 /* register definition */
293 #define REG_PM_CTRLSTAT 0x44
294 
295 #define REG_PCIE_CAP_LIST 0x58
296 
297 #define REG_DEVICE_CAP 0x5C
298 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
299 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
300 
301 #define REG_DEVICE_CTRL 0x60
302 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
303 #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
304 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
305 #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
306 
307 #define REG_VPD_CAP 0x6C
308 #define VPD_CAP_ID_MASK 0xff
309 #define VPD_CAP_ID_SHIFT 0
310 #define VPD_CAP_NEXT_PTR_MASK 0xFF
311 #define VPD_CAP_NEXT_PTR_SHIFT 8
312 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
313 #define VPD_CAP_VPD_ADDR_SHIFT 16
314 #define VPD_CAP_VPD_FLAG 0x80000000
315 
316 #define REG_VPD_DATA 0x70
317 
318 #define REG_SPI_FLASH_CTRL 0x200
319 #define SPI_FLASH_CTRL_STS_NON_RDY 0x1
320 #define SPI_FLASH_CTRL_STS_WEN 0x2
321 #define SPI_FLASH_CTRL_STS_WPEN 0x80
322 #define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
323 #define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
324 #define SPI_FLASH_CTRL_INS_MASK 0x7
325 #define SPI_FLASH_CTRL_INS_SHIFT 8
326 #define SPI_FLASH_CTRL_START 0x800
327 #define SPI_FLASH_CTRL_EN_VPD 0x2000
328 #define SPI_FLASH_CTRL_LDSTART 0x8000
329 #define SPI_FLASH_CTRL_CS_HI_MASK 0x3
330 #define SPI_FLASH_CTRL_CS_HI_SHIFT 16
331 #define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
332 #define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
333 #define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
334 #define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
335 #define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
336 #define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
337 #define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
338 #define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
339 #define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
340 #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
341 #define SPI_FLASH_CTRL_WAIT_READY 0x10000000
342 
343 #define REG_SPI_ADDR 0x204
344 
345 #define REG_SPI_DATA 0x208
346 
347 #define REG_SPI_FLASH_CONFIG 0x20C
348 #define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
349 #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
350 #define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
351 #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
352 #define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
353 
354 
355 #define REG_SPI_FLASH_OP_PROGRAM 0x210
356 #define REG_SPI_FLASH_OP_SC_ERASE 0x211
357 #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
358 #define REG_SPI_FLASH_OP_RDID 0x213
359 #define REG_SPI_FLASH_OP_WREN 0x214
360 #define REG_SPI_FLASH_OP_RDSR 0x215
361 #define REG_SPI_FLASH_OP_WRSR 0x216
362 #define REG_SPI_FLASH_OP_READ 0x217
363 
364 #define REG_TWSI_CTRL 0x218
365 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
366 #define TWSI_CTRL_LD_OFFSET_SHIFT 0
367 #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
368 #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
369 #define TWSI_CTRL_SW_LDSTART 0x800
370 #define TWSI_CTRL_HW_LDSTART 0x1000
371 #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
372 #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
373 #define TWSI_CTRL_LD_EXIST 0x400000
374 #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
375 #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
376 #define TWSI_CTRL_FREQ_SEL_100K 0
377 #define TWSI_CTRL_FREQ_SEL_200K 1
378 #define TWSI_CTRL_FREQ_SEL_300K 2
379 #define TWSI_CTRL_FREQ_SEL_400K 3
380 #define TWSI_CTRL_SMB_SLV_ADDR
381 #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
382 #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
383 
384 
385 #define REG_PCIE_DEV_MISC_CTRL 0x21C
386 #define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
387 #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
388 #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
389 #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
390 #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
391 
392 #define REG_PCIE_PHYMISC 0x1000
393 #define PCIE_PHYMISC_FORCE_RCV_DET 0x4
394 
395 #define REG_LTSSM_TEST_MODE 0x12FC
396 #define LTSSM_TEST_MODE_DEF 0xE000
397 
398 /* Selene Master Control Register */
399 #define REG_MASTER_CTRL 0x1400
400 #define MASTER_CTRL_SOFT_RST 0x1
401 #define MASTER_CTRL_MTIMER_EN 0x2
402 #define MASTER_CTRL_ITIMER_EN 0x4
403 #define MASTER_CTRL_MANUAL_INT 0x8
404 #define MASTER_CTRL_ITIMER2_EN 0x20
405 #define MASTER_CTRL_INT_RDCLR 0x40
406 #define MASTER_CTRL_LED_MODE 0x200
407 #define MASTER_CTRL_REV_NUM_SHIFT 16
408 #define MASTER_CTRL_REV_NUM_MASK 0xff
409 #define MASTER_CTRL_DEV_ID_SHIFT 24
410 #define MASTER_CTRL_DEV_ID_MASK 0xff
411 
412 /* Timer Initial Value Register */
413 #define REG_MANUAL_TIMER_INIT 0x1404
414 
415 
416 /* IRQ ModeratorTimer Initial Value Register */
417 #define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
418 #define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
419 
420 
421 #define REG_GPHY_CTRL 0x140C
422 #define GPHY_CTRL_EXT_RESET 1
423 #define GPHY_CTRL_PIPE_MOD 2
424 #define GPHY_CTRL_TEST_MODE_MASK 3
425 #define GPHY_CTRL_TEST_MODE_SHIFT 2
426 #define GPHY_CTRL_BERT_START 0x10
427 #define GPHY_CTRL_GATE_25M_EN 0x20
428 #define GPHY_CTRL_LPW_EXIT 0x40
429 #define GPHY_CTRL_PHY_IDDQ 0x80
430 #define GPHY_CTRL_PHY_IDDQ_DIS 0x100
431 #define GPHY_CTRL_PCLK_SEL_DIS 0x200
432 #define GPHY_CTRL_HIB_EN 0x400
433 #define GPHY_CTRL_HIB_PULSE 0x800
434 #define GPHY_CTRL_SEL_ANA_RST 0x1000
435 #define GPHY_CTRL_PHY_PLL_ON 0x2000
436 #define GPHY_CTRL_PWDOWN_HW 0x4000
437 #define GPHY_CTRL_DEFAULT (\
438  GPHY_CTRL_PHY_PLL_ON |\
439  GPHY_CTRL_SEL_ANA_RST |\
440  GPHY_CTRL_HIB_PULSE |\
441  GPHY_CTRL_HIB_EN)
442 
443 #define GPHY_CTRL_PW_WOL_DIS (\
444  GPHY_CTRL_PHY_PLL_ON |\
445  GPHY_CTRL_SEL_ANA_RST |\
446  GPHY_CTRL_HIB_PULSE |\
447  GPHY_CTRL_HIB_EN |\
448  GPHY_CTRL_PWDOWN_HW |\
449  GPHY_CTRL_PCLK_SEL_DIS |\
450  GPHY_CTRL_PHY_IDDQ)
451 
452 /* IRQ Anti-Lost Timer Initial Value Register */
453 #define REG_CMBDISDMA_TIMER 0x140E
454 
455 
456 /* Block IDLE Status Register */
457 #define REG_IDLE_STATUS 0x1410
458 #define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
459 #define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
460 #define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
461 #define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
462 #define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
463 #define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
464 #define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
465 #define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
466 
467 /* MDIO Control Register */
468 #define REG_MDIO_CTRL 0x1414
469 #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
470 #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
471 #define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
472 #define MDIO_REG_ADDR_SHIFT 16
473 #define MDIO_RW 0x200000 /* 1: read, 0: write */
474 #define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
475 #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
476 #define MDIO_CLK_SEL_SHIFT 24
477 #define MDIO_CLK_25_4 0
478 #define MDIO_CLK_25_6 2
479 #define MDIO_CLK_25_8 3
480 #define MDIO_CLK_25_10 4
481 #define MDIO_CLK_25_14 5
482 #define MDIO_CLK_25_20 6
483 #define MDIO_CLK_25_28 7
484 #define MDIO_BUSY 0x8000000
485 #define MDIO_AP_EN 0x10000000
486 #define MDIO_WAIT_TIMES 10
487 
488 /* MII PHY Status Register */
489 #define REG_PHY_STATUS 0x1418
490 #define PHY_STATUS_100M 0x20000
491 #define PHY_STATUS_EMI_CA 0x40000
492 
493 /* BIST Control and Status Register0 (for the Packet Memory) */
494 #define REG_BIST0_CTRL 0x141c
495 #define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
496 /* BIST process and reset to zero when BIST is done */
497 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
498 /* decoder failure or more than 1 cell stuck-to-x failure */
499 #define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
500 
501 /* BIST Control and Status Register1(for the retry buffer of PCI Express) */
502 #define REG_BIST1_CTRL 0x1420
503 #define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
504 /* BIST process and reset to zero when BIST is done */
505 #define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
506 /* decoder failure or more than 1 cell stuck-to-x failure.*/
507 #define BIST1_FUSE_FLAG 0x4
508 
509 /* SerDes Lock Detect Control and Status Register */
510 #define REG_SERDES_LOCK 0x1424
511 #define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
512 #define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
513 
514 /* MAC Control Register */
515 #define REG_MAC_CTRL 0x1480
516 #define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
517 #define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
518 #define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
519 #define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
520 #define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
521 #define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
522 #define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
523 #define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
524 #define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
525 #define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
526 #define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
527 #define MAC_CTRL_PRMLEN_MASK 0xf
528 #define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
529 #define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
530 #define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
531 #define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
532 #define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
533 #define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
534 #define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
535 #define MAC_CTRL_SPEED_MASK 0x300000
536 #define MAC_CTRL_SPEED_1000 2
537 #define MAC_CTRL_SPEED_10_100 1
538 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
539 #define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
540 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
541 #define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
542 #define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
543 #define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
544 
545 /* MAC IPG/IFG Control Register */
546 #define REG_MAC_IPG_IFG 0x1484
547 #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
548 #define MAC_IPG_IFG_IPGT_MASK 0x7f
549 #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
550 #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
551 #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
552 #define MAC_IPG_IFG_IPGR1_MASK 0x7f
553 #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
554 #define MAC_IPG_IFG_IPGR2_MASK 0x7f
555 
556 /* MAC STATION ADDRESS */
557 #define REG_MAC_STA_ADDR 0x1488
558 
559 /* Hash table for multicast address */
560 #define REG_RX_HASH_TABLE 0x1490
561 
562 
563 /* MAC Half-Duplex Control Register */
564 #define REG_MAC_HALF_DUPLX_CTRL 0x1498
565 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
566 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
567 #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
568 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
569 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
570 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
571 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
572 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
573 #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
574 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
575 #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
576 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
577 
578 /* Maximum Frame Length Control Register */
579 #define REG_MTU 0x149c
580 
581 /* Wake-On-Lan control register */
582 #define REG_WOL_CTRL 0x14a0
583 #define WOL_PATTERN_EN 0x00000001
584 #define WOL_PATTERN_PME_EN 0x00000002
585 #define WOL_MAGIC_EN 0x00000004
586 #define WOL_MAGIC_PME_EN 0x00000008
587 #define WOL_LINK_CHG_EN 0x00000010
588 #define WOL_LINK_CHG_PME_EN 0x00000020
589 #define WOL_PATTERN_ST 0x00000100
590 #define WOL_MAGIC_ST 0x00000200
591 #define WOL_LINKCHG_ST 0x00000400
592 #define WOL_CLK_SWITCH_EN 0x00008000
593 #define WOL_PT0_EN 0x00010000
594 #define WOL_PT1_EN 0x00020000
595 #define WOL_PT2_EN 0x00040000
596 #define WOL_PT3_EN 0x00080000
597 #define WOL_PT4_EN 0x00100000
598 #define WOL_PT5_EN 0x00200000
599 #define WOL_PT6_EN 0x00400000
600 /* WOL Length ( 2 DWORD ) */
601 #define REG_WOL_PATTERN_LEN 0x14a4
602 #define WOL_PT_LEN_MASK 0x7f
603 #define WOL_PT0_LEN_SHIFT 0
604 #define WOL_PT1_LEN_SHIFT 8
605 #define WOL_PT2_LEN_SHIFT 16
606 #define WOL_PT3_LEN_SHIFT 24
607 #define WOL_PT4_LEN_SHIFT 0
608 #define WOL_PT5_LEN_SHIFT 8
609 #define WOL_PT6_LEN_SHIFT 16
610 
611 /* Internal SRAM Partition Register */
612 #define REG_SRAM_TRD_ADDR 0x1518
613 #define REG_SRAM_TRD_LEN 0x151C
614 #define REG_SRAM_RXF_ADDR 0x1520
615 #define REG_SRAM_RXF_LEN 0x1524
616 #define REG_SRAM_TXF_ADDR 0x1528
617 #define REG_SRAM_TXF_LEN 0x152C
618 #define REG_SRAM_TCPH_ADDR 0x1530
619 #define REG_SRAM_PKTH_ADDR 0x1532
620 
621 /* Load Ptr Register */
622 #define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
623 
624 /*
625  * addresses of all descriptors, as well as the following descriptor
626  * control register, which triggers each function block to load the head
627  * pointer to prepare for the operation. This bit is then self-cleared
628  * after one cycle.
629  */
630 
631 /* Descriptor Control register */
632 #define REG_RXF3_BASE_ADDR_HI 0x153C
633 #define REG_DESC_BASE_ADDR_HI 0x1540
634 #define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
635 #define REG_HOST_RXF0_PAGE0_LO 0x1544
636 #define REG_HOST_RXF0_PAGE1_LO 0x1548
637 #define REG_TPD_BASE_ADDR_LO 0x154C
638 #define REG_RXF1_BASE_ADDR_HI 0x1550
639 #define REG_RXF2_BASE_ADDR_HI 0x1554
640 #define REG_HOST_RXFPAGE_SIZE 0x1558
641 #define REG_TPD_RING_SIZE 0x155C
642 /* RSS about */
643 #define REG_RSS_KEY0 0x14B0
644 #define REG_RSS_KEY1 0x14B4
645 #define REG_RSS_KEY2 0x14B8
646 #define REG_RSS_KEY3 0x14BC
647 #define REG_RSS_KEY4 0x14C0
648 #define REG_RSS_KEY5 0x14C4
649 #define REG_RSS_KEY6 0x14C8
650 #define REG_RSS_KEY7 0x14CC
651 #define REG_RSS_KEY8 0x14D0
652 #define REG_RSS_KEY9 0x14D4
653 #define REG_IDT_TABLE4 0x14E0
654 #define REG_IDT_TABLE5 0x14E4
655 #define REG_IDT_TABLE6 0x14E8
656 #define REG_IDT_TABLE7 0x14EC
657 #define REG_IDT_TABLE0 0x1560
658 #define REG_IDT_TABLE1 0x1564
659 #define REG_IDT_TABLE2 0x1568
660 #define REG_IDT_TABLE3 0x156C
661 #define REG_IDT_TABLE REG_IDT_TABLE0
662 #define REG_RSS_HASH_VALUE 0x1570
663 #define REG_RSS_HASH_FLAG 0x1574
664 #define REG_BASE_CPU_NUMBER 0x157C
665 
666 
667 /* TXQ Control Register */
668 #define REG_TXQ_CTRL 0x1580
669 #define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
670 #define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
671 #define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
672 #define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
673 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
674 #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
675 
676 /* Jumbo packet Threshold for task offload */
677 #define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
678 /* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
679 #define TX_TX_EARLY_TH_MASK 0x7ff
680 #define TX_TX_EARLY_TH_SHIFT 0
681 
682 
683 /* RXQ Control Register */
684 #define REG_RXQ_CTRL 0x15A0
685 #define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
686 #define RXQ_CTRL_PBA_ALIGN_64 1
687 #define RXQ_CTRL_PBA_ALIGN_128 2
688 #define RXQ_CTRL_PBA_ALIGN_256 3
689 #define RXQ_CTRL_Q1_EN 0x10
690 #define RXQ_CTRL_Q2_EN 0x20
691 #define RXQ_CTRL_Q3_EN 0x40
692 #define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
693 #define RXQ_CTRL_HASH_TLEN_SHIFT 8
694 #define RXQ_CTRL_HASH_TLEN_MASK 0xFF
695 #define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
696 #define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
697 #define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
698 #define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
699 #define RXQ_CTRL_RSS_MODE_DISABLE 0
700 #define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
701 #define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
702 #define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
703 #define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
704 #define RXQ_CTRL_HASH_ENABLE 0x20000000
705 #define RXQ_CTRL_CUT_THRU_EN 0x40000000
706 #define RXQ_CTRL_EN 0x80000000
707 
708 /* Rx jumbo packet threshold and rrd retirement timer */
709 #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
710 /*
711  * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
712  * When the packet length greater than or equal to this value, RXQ
713  * shall start cut-through forwarding of the received packet.
714  */
715 #define RXQ_JMBOSZ_TH_MASK 0x7ff
716 #define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
717 #define RXQ_JMBO_LKAH_MASK 0xf
718 #define RXQ_JMBO_LKAH_SHIFT 11
719 
720 /* RXF flow control register */
721 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
722 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
723 #define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
724 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
725 #define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
726 
727 
728 /* DMA Engine Control Register */
729 #define REG_DMA_CTRL 0x15C0
730 #define DMA_CTRL_DMAR_IN_ORDER 0x1
731 #define DMA_CTRL_DMAR_ENH_ORDER 0x2
732 #define DMA_CTRL_DMAR_OUT_ORDER 0x4
733 #define DMA_CTRL_RCB_VALUE 0x8
734 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
735 #define DMA_CTRL_DMAR_BURST_LEN_MASK 7
736 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
737 #define DMA_CTRL_DMAW_BURST_LEN_MASK 7
738 #define DMA_CTRL_DMAR_REQ_PRI 0x400
739 #define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
740 #define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
741 #define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
742 #define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
743 #define DMA_CTRL_TXCMB_EN 0x100000
744 #define DMA_CTRL_RXCMB_EN 0x200000
745 
746 
747 /* CMB/SMB Control Register */
748 #define REG_SMB_STAT_TIMER 0x15C4
749 #define REG_TRIG_RRD_THRESH 0x15CA
750 #define REG_TRIG_TPD_THRESH 0x15C8
751 #define REG_TRIG_TXTIMER 0x15CC
752 #define REG_TRIG_RXTIMER 0x15CE
753 
754 /* HOST RXF Page 1,2,3 address */
755 #define REG_HOST_RXF1_PAGE0_LO 0x15D0
756 #define REG_HOST_RXF1_PAGE1_LO 0x15D4
757 #define REG_HOST_RXF2_PAGE0_LO 0x15D8
758 #define REG_HOST_RXF2_PAGE1_LO 0x15DC
759 #define REG_HOST_RXF3_PAGE0_LO 0x15E0
760 #define REG_HOST_RXF3_PAGE1_LO 0x15E4
761 
762 /* Mail box */
763 #define REG_MB_RXF1_RADDR 0x15B4
764 #define REG_MB_RXF2_RADDR 0x15B8
765 #define REG_MB_RXF3_RADDR 0x15BC
766 #define REG_MB_TPD_PROD_IDX 0x15F0
767 
768 /* RXF-Page 0-3 PageNo & Valid bit */
769 #define REG_HOST_RXF0_PAGE0_VLD 0x15F4
770 #define HOST_RXF_VALID 1
771 #define HOST_RXF_PAGENO_SHIFT 1
772 #define HOST_RXF_PAGENO_MASK 0x7F
773 #define REG_HOST_RXF0_PAGE1_VLD 0x15F5
774 #define REG_HOST_RXF1_PAGE0_VLD 0x15F6
775 #define REG_HOST_RXF1_PAGE1_VLD 0x15F7
776 #define REG_HOST_RXF2_PAGE0_VLD 0x15F8
777 #define REG_HOST_RXF2_PAGE1_VLD 0x15F9
778 #define REG_HOST_RXF3_PAGE0_VLD 0x15FA
779 #define REG_HOST_RXF3_PAGE1_VLD 0x15FB
780 
781 /* Interrupt Status Register */
782 #define REG_ISR 0x1600
783 #define ISR_SMB 1
784 #define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
785 /*
786  * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
787  * in Table 51 Selene Master Control Register (Offset 0x1400).
788  */
789 #define ISR_MANUAL 4
790 #define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
791 #define ISR_HOST_RXF0_OV 0x10
792 #define ISR_HOST_RXF1_OV 0x20
793 #define ISR_HOST_RXF2_OV 0x40
794 #define ISR_HOST_RXF3_OV 0x80
795 #define ISR_TXF_UN 0x100
796 #define ISR_RX0_PAGE_FULL 0x200
797 #define ISR_DMAR_TO_RST 0x400
798 #define ISR_DMAW_TO_RST 0x800
799 #define ISR_GPHY 0x1000
800 #define ISR_TX_CREDIT 0x2000
801 #define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
802 #define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
803 #define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
804 #define ISR_TX_DMA 0x40000
805 #define ISR_RX_PKT_1 0x80000
806 #define ISR_RX_PKT_2 0x100000
807 #define ISR_RX_PKT_3 0x200000
808 #define ISR_MAC_RX 0x400000
809 #define ISR_MAC_TX 0x800000
810 #define ISR_UR_DETECTED 0x1000000
811 #define ISR_FERR_DETECTED 0x2000000
812 #define ISR_NFERR_DETECTED 0x4000000
813 #define ISR_CERR_DETECTED 0x8000000
814 #define ISR_PHY_LINKDOWN 0x10000000
815 #define ISR_DIS_INT 0x80000000
816 
817 
818 /* Interrupt Mask Register */
819 #define REG_IMR 0x1604
820 
821 
822 #define IMR_NORMAL_MASK (\
823  ISR_SMB |\
824  ISR_TXF_UN |\
825  ISR_HW_RXF_OV |\
826  ISR_HOST_RXF0_OV|\
827  ISR_MANUAL |\
828  ISR_GPHY |\
829  ISR_GPHY_LPW |\
830  ISR_DMAR_TO_RST |\
831  ISR_DMAW_TO_RST |\
832  ISR_PHY_LINKDOWN|\
833  ISR_RX_PKT |\
834  ISR_TX_PKT)
835 
836 #define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
837 #define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
838 
839 #define REG_MAC_RX_STATUS_BIN 0x1700
840 #define REG_MAC_RX_STATUS_END 0x175c
841 #define REG_MAC_TX_STATUS_BIN 0x1760
842 #define REG_MAC_TX_STATUS_END 0x17c0
843 
844 /* Hardware Offset Register */
845 #define REG_HOST_RXF0_PAGEOFF 0x1800
846 #define REG_TPD_CONS_IDX 0x1804
847 #define REG_HOST_RXF1_PAGEOFF 0x1808
848 #define REG_HOST_RXF2_PAGEOFF 0x180C
849 #define REG_HOST_RXF3_PAGEOFF 0x1810
850 
851 /* RXF-Page 0-3 Offset DMA Address */
852 #define REG_HOST_RXF0_MB0_LO 0x1820
853 #define REG_HOST_RXF0_MB1_LO 0x1824
854 #define REG_HOST_RXF1_MB0_LO 0x1828
855 #define REG_HOST_RXF1_MB1_LO 0x182C
856 #define REG_HOST_RXF2_MB0_LO 0x1830
857 #define REG_HOST_RXF2_MB1_LO 0x1834
858 #define REG_HOST_RXF3_MB0_LO 0x1838
859 #define REG_HOST_RXF3_MB1_LO 0x183C
860 
861 /* Tpd CMB DMA Address */
862 #define REG_HOST_TX_CMB_LO 0x1840
863 #define REG_HOST_SMB_ADDR_LO 0x1844
864 
865 /* DEBUG ADDR */
866 #define REG_DEBUG_DATA0 0x1900
867 #define REG_DEBUG_DATA1 0x1904
868 
869 /***************************** MII definition ***************************************/
870 /* PHY Common Register */
871 #define MII_BMCR 0x00
872 #define MII_BMSR 0x01
873 #define MII_PHYSID1 0x02
874 #define MII_PHYSID2 0x03
875 #define MII_ADVERTISE 0x04
876 #define MII_LPA 0x05
877 #define MII_EXPANSION 0x06
878 #define MII_AT001_CR 0x09
879 #define MII_AT001_SR 0x0A
880 #define MII_AT001_ESR 0x0F
881 #define MII_AT001_PSCR 0x10
882 #define MII_AT001_PSSR 0x11
883 #define MII_INT_CTRL 0x12
884 #define MII_INT_STATUS 0x13
885 #define MII_SMARTSPEED 0x14
886 #define MII_RERRCOUNTER 0x15
887 #define MII_SREVISION 0x16
888 #define MII_RESV1 0x17
889 #define MII_LBRERROR 0x18
890 #define MII_PHYADDR 0x19
891 #define MII_RESV2 0x1a
892 #define MII_TPISTATUS 0x1b
893 #define MII_NCONFIG 0x1c
894 
895 #define MII_DBG_ADDR 0x1D
896 #define MII_DBG_DATA 0x1E
897 
898 
899 /* PHY Control Register */
900 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
901 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
902 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
903 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
904 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
905 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
906 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
907 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
908 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
909 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
910 #define MII_CR_SPEED_MASK 0x2040
911 #define MII_CR_SPEED_1000 0x0040
912 #define MII_CR_SPEED_100 0x2000
913 #define MII_CR_SPEED_10 0x0000
914 
915 
916 /* PHY Status Register */
917 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
918 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
919 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
920 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
921 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
922 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
923 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
924 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
925 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
926 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
927 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
928 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
929 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
930 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
931 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
932 
933 /* Link partner ability register. */
934 #define MII_LPA_SLCT 0x001f /* Same as advertise selector */
935 #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
936 #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
937 #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
938 #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
939 #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
940 #define MII_LPA_PAUSE 0x0400 /* PAUSE */
941 #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
942 #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
943 #define MII_LPA_LPACK 0x4000 /* Link partner acked us */
944 #define MII_LPA_NPAGE 0x8000 /* Next page bit */
945 
946 /* Autoneg Advertisement Register */
947 #define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
948 #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
949 #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
950 #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
951 #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
952 #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
953 #define MII_AR_PAUSE 0x0400 /* Pause operation desired */
954 #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
955 #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
956 #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
957 #define MII_AR_SPEED_MASK 0x01E0
958 #define MII_AR_DEFAULT_CAP_MASK 0x0DE0
959 
960 /* 1000BASE-T Control Register */
961 #define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
962 #define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
963 #define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
964 /* 0=DTE device */
965 #define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
966 /* 0=Configure PHY as Slave */
967 #define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
968 /* 0=Automatic Master/Slave config */
969 #define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
970 #define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
971 #define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
972 #define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
973 #define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
974 #define MII_AT001_CR_1000T_SPEED_MASK 0x0300
975 #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
976 
977 /* 1000BASE-T Status Register */
978 #define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
979 #define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
980 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
981 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
982 #define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
983 #define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
984 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
985 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
986 
987 /* Extended Status Register */
988 #define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
989 #define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
990 #define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
991 #define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
992 
993 /* AT001 PHY Specific Control Register */
994 #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
995 #define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
996 #define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
997 #define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
998 #define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
999  * 0=CLK125 toggling
1000  */
1001 #define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1002 /* Manual MDI configuration */
1003 #define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1004 #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1005  * 100BASE-TX/10BASE-T:
1006  * MDI Mode
1007  */
1008 #define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1009  * all speeds.
1010  */
1011 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1012 /* 1=Enable Extended 10BASE-T distance
1013  * (Lower 10BASE-T RX Threshold)
1014  * 0=Normal 10BASE-T RX Threshold */
1015 #define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
1016 /* 1=5-Bit interface in 100BASE-TX
1017  * 0=MII interface in 100BASE-TX */
1018 #define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1019 #define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1020 #define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1021 #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
1022 #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
1023 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1024 /* AT001 PHY Specific Status Register */
1025 #define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1026 #define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1027 #define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1028 #define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
1029 #define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
1030 #define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1031 
1032 
1033 #endif /* _ATL1_E_H_ */
struct atl1e_tpd_desc * desc
Definition: atl1e.h:200
uint16_t u16
Definition: stdint.h:21
u32 ring_size
Definition: atl1e.h:233
iPXE I/O API
u32 * cmb
Definition: atl1e.h:207
u8 mac_addr[ETH_ALEN]
Definition: atl1e.h:158
struct atl1e_rx_ring rx_ring
Definition: atl1e.h:236
u8 perm_mac_addr[ETH_ALEN]
Definition: atl1e.h:159
u16 count
Definition: atl1e.h:202
FILE_LICENCE(GPL2_OR_LATER)
int32_t s32
Definition: stdint.h:22
enum atl1e_dma_req_block dmar_block
Definition: atl1e.h:164
u16 mii_autoneg_adv_reg
Definition: atl1e.h:161
Error codes.
u32 ring_dma
Definition: atl1e.h:231
I/O buffers.
s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw)
void * desc
Definition: atl1e.h:212
void atl1e_down(struct atl1e_adapter *adapter)
Definition: atl1e.c:1024
enum atl1e_dma_req_block dmaw_block
Definition: atl1e.h:165
struct atl1e_rx_page_desc rx_page_desc
Definition: atl1e.h:217
void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
Definition: atl1e.c:1265
u16 next_to_clean
Definition: atl1e.h:204
u16 link_duplex
Definition: atl1e.h:228
Definition: hw.c:16
enum atl1e_nic_type nic_type
Definition: atl1e.h:157
Dynamic memory allocation.
u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex)
s32 atl1e_read_mac_addr(struct atl1e_hw *hw)
Definition: atl1e.c:1335
s32 atl1e_init_hw(struct atl1e_hw *hw)
Definition: atl1e.c:1670
u32 word2
Definition: atl1e.h:86
int size
Definition: atl1e.h:214
atl1e_nic_type
Definition: atl1e.h:148
Ethernet protocol.
u32 cmb_dma
Definition: atl1e.h:206
struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE]
Definition: atl1e.h:193
s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
Definition: atl1e.c:1351
uint64_t u64
Definition: stdint.h:25
s32 atl1e_reset_hw(struct atl1e_hw *hw)
Definition: atl1e.c:1614
int phy_configured
Definition: atl1e.h:167
s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
Definition: atl1e.c:1385
struct atl1e_tx_ring tx_ring
Definition: atl1e.h:235
u32 read_offset
Definition: atl1e.h:189
atl1e_dma_req_block
Definition: atl1e.h:139
struct atl1e_adapter * adapter
Definition: atl1e.h:156
struct atl1e_tx_buffer * tx_buffer
Definition: atl1e.h:205
int bd_number
Definition: atl1e.h:238
PCI bus.
A PCI device.
Definition: pci.h:187
A network device.
Definition: netdevice.h:348
struct mii_if_info mii
Definition: atl1e.h:224
int emi_ca
Definition: atl1e.h:169
#define ETH_ALEN
Definition: if_ether.h:8
struct pci_device * pdev
Definition: atl1e.h:223
u16 mii_1000t_ctrl_reg
Definition: atl1e.h:162
void atl1e_force_ps(struct atl1e_hw *hw)
Definition: atl1e.c:1324
void * ring_vir_addr
Definition: atl1e.h:232
int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
Definition: atl1e.c:1252
Network device management.
duplex
Definition: nic.h:40
struct net_device * netdev
Definition: atl1e.h:222
s32 atl1e_phy_init(struct atl1e_hw *hw)
Definition: atl1e.c:1522
s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
Definition: atl1e.c:1693
PCI I/O API.
Media Independent Interface constants.
u32 page_size
Definition: atl1e.h:215
u32 write_offset_dma
Definition: atl1e.h:185
int re_autoneg
Definition: atl1e.h:168
u64 buffer_addr
Definition: atl1e.h:85
s32 atl1e_phy_commit(struct atl1e_hw *hw)
Definition: atl1e.c:1491
struct io_buffer * iob
Definition: atl1e.h:177
#define AT_PAGE_NUM_PER_QUEUE
Definition: atl1e.h:68
int atl1e_up(struct atl1e_adapter *adapter)
Definition: atl1e.c:986
s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw)
u32 word3
Definition: atl1e.h:87
s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw)
u16 link_speed
Definition: atl1e.h:227
u32 real_page_size
Definition: atl1e.h:216
String functions.
uint8_t u8
Definition: stdint.h:19
u8 * addr
Definition: atl1e.h:184
uint32_t u32
Definition: stdint.h:23
u8 * hw_addr
Definition: atl1e.h:155
u32 * write_offset_addr
Definition: atl1e.h:187
s32 atl1e_restart_autoneg(struct atl1e_hw *hw)
Definition: atl1e.c:1729
u16 next_to_use
Definition: atl1e.h:203
A persistent I/O buffer.
Definition: iobuf.h:32