iPXE
Data Structures | Macros | Enumerations | Functions
atl1e.h File Reference
#include <mii.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <byteswap.h>
#include <errno.h>
#include <ipxe/malloc.h>
#include <ipxe/pci.h>
#include <ipxe/pci_io.h>
#include <ipxe/iobuf.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/io.h>

Go to the source code of this file.

Data Structures

struct  atl1e_tpd_desc
 
struct  atl1e_recv_ret_status
 
struct  atl1e_hw
 
struct  atl1e_tx_buffer
 
struct  atl1e_rx_page
 
struct  atl1e_rx_page_desc
 
struct  atl1e_tx_ring
 
struct  atl1e_rx_ring
 
struct  atl1e_adapter
 

Macros

#define _ATL1E_H_
 
#define ETH_FCS_LEN   4
 
#define VLAN_HLEN   4
 
#define NET_IP_ALIGN   2
 
#define SPEED_0   0xffff
 
#define SPEED_10   10
 
#define SPEED_100   100
 
#define SPEED_1000   1000
 
#define HALF_DUPLEX   1
 
#define FULL_DUPLEX   2
 
#define AT_ERR_EEPROM   1
 
#define AT_ERR_PHY   2
 
#define AT_ERR_CONFIG   3
 
#define AT_ERR_PARAM   4
 
#define AT_ERR_MAC_TYPE   5
 
#define AT_ERR_PHY_TYPE   6
 
#define AT_ERR_PHY_SPEED   7
 
#define AT_ERR_PHY_RES   8
 
#define AT_ERR_TIMEOUT   9
 
#define AT_MAX_RECEIVE_QUEUE   4
 
#define AT_PAGE_NUM_PER_QUEUE   2
 
#define AT_TWSI_EEPROM_TIMEOUT   100
 
#define AT_HW_MAX_IDLE_DELAY   10
 
#define AT_REGS_LEN   75
 
#define AT_EEPROM_LEN   512
 
#define TPD_BUFLEN_MASK   0x3FFF
 
#define TPD_BUFLEN_SHIFT   0
 
#define TPD_EOP_MASK   0x0001
 
#define TPD_EOP_SHIFT   0
 
#define MAX_TX_BUF_LEN   0x2000
 
#define MAX_TX_BUF_SHIFT   13
 
#define RRS_RX_CSUM_MASK   0xFFFF
 
#define RRS_RX_CSUM_SHIFT   0
 
#define RRS_PKT_SIZE_MASK   0x3FFF
 
#define RRS_PKT_SIZE_SHIFT   16
 
#define RRS_CPU_NUM_MASK   0x0003
 
#define RRS_CPU_NUM_SHIFT   30
 
#define RRS_IS_RSS_IPV4   0x0001
 
#define RRS_IS_RSS_IPV4_TCP   0x0002
 
#define RRS_IS_RSS_IPV6   0x0004
 
#define RRS_IS_RSS_IPV6_TCP   0x0008
 
#define RRS_IS_IPV6   0x0010
 
#define RRS_IS_IP_FRAG   0x0020
 
#define RRS_IS_IP_DF   0x0040
 
#define RRS_IS_802_3   0x0080
 
#define RRS_IS_VLAN_TAG   0x0100
 
#define RRS_IS_ERR_FRAME   0x0200
 
#define RRS_IS_IPV4   0x0400
 
#define RRS_IS_UDP   0x0800
 
#define RRS_IS_TCP   0x1000
 
#define RRS_IS_BCAST   0x2000
 
#define RRS_IS_MCAST   0x4000
 
#define RRS_IS_PAUSE   0x8000
 
#define RRS_ERR_BAD_CRC   0x0001
 
#define RRS_ERR_CODE   0x0002
 
#define RRS_ERR_DRIBBLE   0x0004
 
#define RRS_ERR_RUNT   0x0008
 
#define RRS_ERR_RX_OVERFLOW   0x0010
 
#define RRS_ERR_TRUNC   0x0020
 
#define RRS_ERR_IP_CSUM   0x0040
 
#define RRS_ERR_L4_CSUM   0x0080
 
#define RRS_ERR_LENGTH   0x0100
 
#define RRS_ERR_DES_ADDR   0x0200
 
#define AT_WRITE_REG(a, reg, value)   writel((value), ((a)->hw_addr + reg))
 
#define AT_WRITE_FLUSH(a)   readl((a)->hw_addr)
 
#define AT_READ_REG(a, reg)   readl((a)->hw_addr + reg)
 
#define AT_WRITE_REGB(a, reg, value)   writeb((value), ((a)->hw_addr + reg))
 
#define AT_READ_REGB(a, reg)   readb((a)->hw_addr + reg)
 
#define AT_WRITE_REGW(a, reg, value)   writew((value), ((a)->hw_addr + reg))
 
#define AT_READ_REGW(a, reg)   readw((a)->hw_addr + reg)
 
#define AT_WRITE_REG_ARRAY(a, reg, offset, value)   writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))
 
#define AT_READ_REG_ARRAY(a, reg, offset)   readl(((a)->hw_addr + reg) + ((offset) << 2))
 
#define REG_PM_CTRLSTAT   0x44
 
#define REG_PCIE_CAP_LIST   0x58
 
#define REG_DEVICE_CAP   0x5C
 
#define DEVICE_CAP_MAX_PAYLOAD_MASK   0x7
 
#define DEVICE_CAP_MAX_PAYLOAD_SHIFT   0
 
#define REG_DEVICE_CTRL   0x60
 
#define DEVICE_CTRL_MAX_PAYLOAD_MASK   0x7
 
#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT   5
 
#define DEVICE_CTRL_MAX_RREQ_SZ_MASK   0x7
 
#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT   12
 
#define REG_VPD_CAP   0x6C
 
#define VPD_CAP_ID_MASK   0xff
 
#define VPD_CAP_ID_SHIFT   0
 
#define VPD_CAP_NEXT_PTR_MASK   0xFF
 
#define VPD_CAP_NEXT_PTR_SHIFT   8
 
#define VPD_CAP_VPD_ADDR_MASK   0x7FFF
 
#define VPD_CAP_VPD_ADDR_SHIFT   16
 
#define VPD_CAP_VPD_FLAG   0x80000000
 
#define REG_VPD_DATA   0x70
 
#define REG_SPI_FLASH_CTRL   0x200
 
#define SPI_FLASH_CTRL_STS_NON_RDY   0x1
 
#define SPI_FLASH_CTRL_STS_WEN   0x2
 
#define SPI_FLASH_CTRL_STS_WPEN   0x80
 
#define SPI_FLASH_CTRL_DEV_STS_MASK   0xFF
 
#define SPI_FLASH_CTRL_DEV_STS_SHIFT   0
 
#define SPI_FLASH_CTRL_INS_MASK   0x7
 
#define SPI_FLASH_CTRL_INS_SHIFT   8
 
#define SPI_FLASH_CTRL_START   0x800
 
#define SPI_FLASH_CTRL_EN_VPD   0x2000
 
#define SPI_FLASH_CTRL_LDSTART   0x8000
 
#define SPI_FLASH_CTRL_CS_HI_MASK   0x3
 
#define SPI_FLASH_CTRL_CS_HI_SHIFT   16
 
#define SPI_FLASH_CTRL_CS_HOLD_MASK   0x3
 
#define SPI_FLASH_CTRL_CS_HOLD_SHIFT   18
 
#define SPI_FLASH_CTRL_CLK_LO_MASK   0x3
 
#define SPI_FLASH_CTRL_CLK_LO_SHIFT   20
 
#define SPI_FLASH_CTRL_CLK_HI_MASK   0x3
 
#define SPI_FLASH_CTRL_CLK_HI_SHIFT   22
 
#define SPI_FLASH_CTRL_CS_SETUP_MASK   0x3
 
#define SPI_FLASH_CTRL_CS_SETUP_SHIFT   24
 
#define SPI_FLASH_CTRL_EROM_PGSZ_MASK   0x3
 
#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT   26
 
#define SPI_FLASH_CTRL_WAIT_READY   0x10000000
 
#define REG_SPI_ADDR   0x204
 
#define REG_SPI_DATA   0x208
 
#define REG_SPI_FLASH_CONFIG   0x20C
 
#define SPI_FLASH_CONFIG_LD_ADDR_MASK   0xFFFFFF
 
#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT   0
 
#define SPI_FLASH_CONFIG_VPD_ADDR_MASK   0x3
 
#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT   24
 
#define SPI_FLASH_CONFIG_LD_EXIST   0x4000000
 
#define REG_SPI_FLASH_OP_PROGRAM   0x210
 
#define REG_SPI_FLASH_OP_SC_ERASE   0x211
 
#define REG_SPI_FLASH_OP_CHIP_ERASE   0x212
 
#define REG_SPI_FLASH_OP_RDID   0x213
 
#define REG_SPI_FLASH_OP_WREN   0x214
 
#define REG_SPI_FLASH_OP_RDSR   0x215
 
#define REG_SPI_FLASH_OP_WRSR   0x216
 
#define REG_SPI_FLASH_OP_READ   0x217
 
#define REG_TWSI_CTRL   0x218
 
#define TWSI_CTRL_LD_OFFSET_MASK   0xFF
 
#define TWSI_CTRL_LD_OFFSET_SHIFT   0
 
#define TWSI_CTRL_LD_SLV_ADDR_MASK   0x7
 
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT   8
 
#define TWSI_CTRL_SW_LDSTART   0x800
 
#define TWSI_CTRL_HW_LDSTART   0x1000
 
#define TWSI_CTRL_SMB_SLV_ADDR_MASK   0x0x7F
 
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT   15
 
#define TWSI_CTRL_LD_EXIST   0x400000
 
#define TWSI_CTRL_READ_FREQ_SEL_MASK   0x3
 
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT   23
 
#define TWSI_CTRL_FREQ_SEL_100K   0
 
#define TWSI_CTRL_FREQ_SEL_200K   1
 
#define TWSI_CTRL_FREQ_SEL_300K   2
 
#define TWSI_CTRL_FREQ_SEL_400K   3
 
#define TWSI_CTRL_SMB_SLV_ADDR
 
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3
 
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT   24
 
#define REG_PCIE_DEV_MISC_CTRL   0x21C
 
#define PCIE_DEV_MISC_CTRL_EXT_PIPE   0x2
 
#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS   0x1
 
#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST   0x4
 
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN   0x8
 
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN   0x10
 
#define REG_PCIE_PHYMISC   0x1000
 
#define PCIE_PHYMISC_FORCE_RCV_DET   0x4
 
#define REG_LTSSM_TEST_MODE   0x12FC
 
#define LTSSM_TEST_MODE_DEF   0xE000
 
#define REG_MASTER_CTRL   0x1400
 
#define MASTER_CTRL_SOFT_RST   0x1
 
#define MASTER_CTRL_MTIMER_EN   0x2
 
#define MASTER_CTRL_ITIMER_EN   0x4
 
#define MASTER_CTRL_MANUAL_INT   0x8
 
#define MASTER_CTRL_ITIMER2_EN   0x20
 
#define MASTER_CTRL_INT_RDCLR   0x40
 
#define MASTER_CTRL_LED_MODE   0x200
 
#define MASTER_CTRL_REV_NUM_SHIFT   16
 
#define MASTER_CTRL_REV_NUM_MASK   0xff
 
#define MASTER_CTRL_DEV_ID_SHIFT   24
 
#define MASTER_CTRL_DEV_ID_MASK   0xff
 
#define REG_MANUAL_TIMER_INIT   0x1404
 
#define REG_IRQ_MODU_TIMER_INIT   0x1408 /* w */
 
#define REG_IRQ_MODU_TIMER2_INIT   0x140A /* w */
 
#define REG_GPHY_CTRL   0x140C
 
#define GPHY_CTRL_EXT_RESET   1
 
#define GPHY_CTRL_PIPE_MOD   2
 
#define GPHY_CTRL_TEST_MODE_MASK   3
 
#define GPHY_CTRL_TEST_MODE_SHIFT   2
 
#define GPHY_CTRL_BERT_START   0x10
 
#define GPHY_CTRL_GATE_25M_EN   0x20
 
#define GPHY_CTRL_LPW_EXIT   0x40
 
#define GPHY_CTRL_PHY_IDDQ   0x80
 
#define GPHY_CTRL_PHY_IDDQ_DIS   0x100
 
#define GPHY_CTRL_PCLK_SEL_DIS   0x200
 
#define GPHY_CTRL_HIB_EN   0x400
 
#define GPHY_CTRL_HIB_PULSE   0x800
 
#define GPHY_CTRL_SEL_ANA_RST   0x1000
 
#define GPHY_CTRL_PHY_PLL_ON   0x2000
 
#define GPHY_CTRL_PWDOWN_HW   0x4000
 
#define GPHY_CTRL_DEFAULT
 
#define GPHY_CTRL_PW_WOL_DIS
 
#define REG_CMBDISDMA_TIMER   0x140E
 
#define REG_IDLE_STATUS   0x1410
 
#define IDLE_STATUS_RXMAC   1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
 
#define IDLE_STATUS_TXMAC   2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
 
#define IDLE_STATUS_RXQ   4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
 
#define IDLE_STATUS_TXQ   8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
 
#define IDLE_STATUS_DMAR   0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
 
#define IDLE_STATUS_DMAW   0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
 
#define IDLE_STATUS_SMB   0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
 
#define IDLE_STATUS_CMB   0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
 
#define REG_MDIO_CTRL   0x1414
 
#define MDIO_DATA_MASK   0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
 
#define MDIO_DATA_SHIFT   0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
 
#define MDIO_REG_ADDR_MASK   0x1f /* MDIO register address */
 
#define MDIO_REG_ADDR_SHIFT   16
 
#define MDIO_RW   0x200000 /* 1: read, 0: write */
 
#define MDIO_SUP_PREAMBLE   0x400000 /* Suppress preamble */
 
#define MDIO_START   0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
 
#define MDIO_CLK_SEL_SHIFT   24
 
#define MDIO_CLK_25_4   0
 
#define MDIO_CLK_25_6   2
 
#define MDIO_CLK_25_8   3
 
#define MDIO_CLK_25_10   4
 
#define MDIO_CLK_25_14   5
 
#define MDIO_CLK_25_20   6
 
#define MDIO_CLK_25_28   7
 
#define MDIO_BUSY   0x8000000
 
#define MDIO_AP_EN   0x10000000
 
#define MDIO_WAIT_TIMES   10
 
#define REG_PHY_STATUS   0x1418
 
#define PHY_STATUS_100M   0x20000
 
#define PHY_STATUS_EMI_CA   0x40000
 
#define REG_BIST0_CTRL   0x141c
 
#define BIST0_NOW   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
 
#define BIST0_SRAM_FAIL   0x2 /* 1: The SRAM failure is un-repairable because it has address */
 
#define BIST0_FUSE_FLAG   0x4 /* 1: Indicating one cell has been fixed */
 
#define REG_BIST1_CTRL   0x1420
 
#define BIST1_NOW   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
 
#define BIST1_SRAM_FAIL   0x2 /* 1: The SRAM failure is un-repairable because it has address */
 
#define BIST1_FUSE_FLAG   0x4
 
#define REG_SERDES_LOCK   0x1424
 
#define SERDES_LOCK_DETECT   1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
 
#define SERDES_LOCK_DETECT_EN   2 /* 1: Enable SerDes Lock detect function */
 
#define REG_MAC_CTRL   0x1480
 
#define MAC_CTRL_TX_EN   1 /* 1: Transmit Enable */
 
#define MAC_CTRL_RX_EN   2 /* 1: Receive Enable */
 
#define MAC_CTRL_TX_FLOW   4 /* 1: Transmit Flow Control Enable */
 
#define MAC_CTRL_RX_FLOW   8 /* 1: Receive Flow Control Enable */
 
#define MAC_CTRL_LOOPBACK   0x10 /* 1: Loop back at G/MII Interface */
 
#define MAC_CTRL_DUPLX   0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
 
#define MAC_CTRL_ADD_CRC   0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
 
#define MAC_CTRL_PAD   0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
 
#define MAC_CTRL_LENCHK   0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
 
#define MAC_CTRL_HUGE_EN   0x200 /* 1: receive Jumbo frame enable */
 
#define MAC_CTRL_PRMLEN_SHIFT   10 /* Preamble length */
 
#define MAC_CTRL_PRMLEN_MASK   0xf
 
#define MAC_CTRL_RMV_VLAN   0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
 
#define MAC_CTRL_PROMIS_EN   0x8000 /* 1: Promiscuous Mode Enable */
 
#define MAC_CTRL_TX_PAUSE   0x10000 /* 1: transmit test pause */
 
#define MAC_CTRL_SCNT   0x20000 /* 1: shortcut slot time counter */
 
#define MAC_CTRL_SRST_TX   0x40000 /* 1: synchronized reset Transmit MAC module */
 
#define MAC_CTRL_TX_SIMURST   0x80000 /* 1: transmit simulation reset */
 
#define MAC_CTRL_SPEED_SHIFT   20 /* 10: gigabit 01:10M/100M */
 
#define MAC_CTRL_SPEED_MASK   0x300000
 
#define MAC_CTRL_SPEED_1000   2
 
#define MAC_CTRL_SPEED_10_100   1
 
#define MAC_CTRL_DBG_TX_BKPRESURE   0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
 
#define MAC_CTRL_TX_HUGE   0x800000 /* 1: transmit huge enable */
 
#define MAC_CTRL_RX_CHKSUM_EN   0x1000000 /* 1: RX checksum enable */
 
#define MAC_CTRL_MC_ALL_EN   0x2000000 /* 1: upload all multicast frame without error to system */
 
#define MAC_CTRL_BC_EN   0x4000000 /* 1: upload all broadcast frame without error to system */
 
#define MAC_CTRL_DBG   0x8000000 /* 1: upload all received frame to system (Debug Mode) */
 
#define REG_MAC_IPG_IFG   0x1484
 
#define MAC_IPG_IFG_IPGT_SHIFT   0 /* Desired back to back inter-packet gap. The default is 96-bit time */
 
#define MAC_IPG_IFG_IPGT_MASK   0x7f
 
#define MAC_IPG_IFG_MIFG_SHIFT   8 /* Minimum number of IFG to enforce in between RX frames */
 
#define MAC_IPG_IFG_MIFG_MASK   0xff /* Frame gap below such IFP is dropped */
 
#define MAC_IPG_IFG_IPGR1_SHIFT   16 /* 64bit Carrier-Sense window */
 
#define MAC_IPG_IFG_IPGR1_MASK   0x7f
 
#define MAC_IPG_IFG_IPGR2_SHIFT   24 /* 96-bit IPG window */
 
#define MAC_IPG_IFG_IPGR2_MASK   0x7f
 
#define REG_MAC_STA_ADDR   0x1488
 
#define REG_RX_HASH_TABLE   0x1490
 
#define REG_MAC_HALF_DUPLX_CTRL   0x1498
 
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0 /* Collision Window */
 
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK   0x3ff
 
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT   12 /* Retransmission maximum, afterwards the packet will be discarded */
 
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf
 
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
 
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C   0x20000 /* 1: No back-off on collision, immediately start the retransmission */
 
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P   0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
 
#define MAC_HALF_DUPLX_CTRL_ABEBE   0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
 
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT   20 /* Maximum binary exponential number */
 
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf
 
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT   24 /* IPG to start JAM for collision based flow control in half-duplex */
 
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK   0xf /* mode. In unit of 8-bit time */
 
#define REG_MTU   0x149c
 
#define REG_WOL_CTRL   0x14a0
 
#define WOL_PATTERN_EN   0x00000001
 
#define WOL_PATTERN_PME_EN   0x00000002
 
#define WOL_MAGIC_EN   0x00000004
 
#define WOL_MAGIC_PME_EN   0x00000008
 
#define WOL_LINK_CHG_EN   0x00000010
 
#define WOL_LINK_CHG_PME_EN   0x00000020
 
#define WOL_PATTERN_ST   0x00000100
 
#define WOL_MAGIC_ST   0x00000200
 
#define WOL_LINKCHG_ST   0x00000400
 
#define WOL_CLK_SWITCH_EN   0x00008000
 
#define WOL_PT0_EN   0x00010000
 
#define WOL_PT1_EN   0x00020000
 
#define WOL_PT2_EN   0x00040000
 
#define WOL_PT3_EN   0x00080000
 
#define WOL_PT4_EN   0x00100000
 
#define WOL_PT5_EN   0x00200000
 
#define WOL_PT6_EN   0x00400000
 
#define REG_WOL_PATTERN_LEN   0x14a4
 
#define WOL_PT_LEN_MASK   0x7f
 
#define WOL_PT0_LEN_SHIFT   0
 
#define WOL_PT1_LEN_SHIFT   8
 
#define WOL_PT2_LEN_SHIFT   16
 
#define WOL_PT3_LEN_SHIFT   24
 
#define WOL_PT4_LEN_SHIFT   0
 
#define WOL_PT5_LEN_SHIFT   8
 
#define WOL_PT6_LEN_SHIFT   16
 
#define REG_SRAM_TRD_ADDR   0x1518
 
#define REG_SRAM_TRD_LEN   0x151C
 
#define REG_SRAM_RXF_ADDR   0x1520
 
#define REG_SRAM_RXF_LEN   0x1524
 
#define REG_SRAM_TXF_ADDR   0x1528
 
#define REG_SRAM_TXF_LEN   0x152C
 
#define REG_SRAM_TCPH_ADDR   0x1530
 
#define REG_SRAM_PKTH_ADDR   0x1532
 
#define REG_LOAD_PTR   0x1534 /* Software sets this bit after the initialization of the head and tail */
 
#define REG_RXF3_BASE_ADDR_HI   0x153C
 
#define REG_DESC_BASE_ADDR_HI   0x1540
 
#define REG_RXF0_BASE_ADDR_HI   0x1540 /* share with DESC BASE ADDR HI */
 
#define REG_HOST_RXF0_PAGE0_LO   0x1544
 
#define REG_HOST_RXF0_PAGE1_LO   0x1548
 
#define REG_TPD_BASE_ADDR_LO   0x154C
 
#define REG_RXF1_BASE_ADDR_HI   0x1550
 
#define REG_RXF2_BASE_ADDR_HI   0x1554
 
#define REG_HOST_RXFPAGE_SIZE   0x1558
 
#define REG_TPD_RING_SIZE   0x155C
 
#define REG_RSS_KEY0   0x14B0
 
#define REG_RSS_KEY1   0x14B4
 
#define REG_RSS_KEY2   0x14B8
 
#define REG_RSS_KEY3   0x14BC
 
#define REG_RSS_KEY4   0x14C0
 
#define REG_RSS_KEY5   0x14C4
 
#define REG_RSS_KEY6   0x14C8
 
#define REG_RSS_KEY7   0x14CC
 
#define REG_RSS_KEY8   0x14D0
 
#define REG_RSS_KEY9   0x14D4
 
#define REG_IDT_TABLE4   0x14E0
 
#define REG_IDT_TABLE5   0x14E4
 
#define REG_IDT_TABLE6   0x14E8
 
#define REG_IDT_TABLE7   0x14EC
 
#define REG_IDT_TABLE0   0x1560
 
#define REG_IDT_TABLE1   0x1564
 
#define REG_IDT_TABLE2   0x1568
 
#define REG_IDT_TABLE3   0x156C
 
#define REG_IDT_TABLE   REG_IDT_TABLE0
 
#define REG_RSS_HASH_VALUE   0x1570
 
#define REG_RSS_HASH_FLAG   0x1574
 
#define REG_BASE_CPU_NUMBER   0x157C
 
#define REG_TXQ_CTRL   0x1580
 
#define TXQ_CTRL_NUM_TPD_BURST_MASK   0xF
 
#define TXQ_CTRL_NUM_TPD_BURST_SHIFT   0
 
#define TXQ_CTRL_EN   0x20 /* 1: Enable TXQ */
 
#define TXQ_CTRL_ENH_MODE   0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
 
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT   16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
 
#define TXQ_CTRL_TXF_BURST_NUM_MASK   0xffff
 
#define REG_TX_EARLY_TH   0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
 
#define TX_TX_EARLY_TH_MASK   0x7ff
 
#define TX_TX_EARLY_TH_SHIFT   0
 
#define REG_RXQ_CTRL   0x15A0
 
#define RXQ_CTRL_PBA_ALIGN_32   0 /* rx-packet alignment */
 
#define RXQ_CTRL_PBA_ALIGN_64   1
 
#define RXQ_CTRL_PBA_ALIGN_128   2
 
#define RXQ_CTRL_PBA_ALIGN_256   3
 
#define RXQ_CTRL_Q1_EN   0x10
 
#define RXQ_CTRL_Q2_EN   0x20
 
#define RXQ_CTRL_Q3_EN   0x40
 
#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN   0x80
 
#define RXQ_CTRL_HASH_TLEN_SHIFT   8
 
#define RXQ_CTRL_HASH_TLEN_MASK   0xFF
 
#define RXQ_CTRL_HASH_TYPE_IPV4   0x10000
 
#define RXQ_CTRL_HASH_TYPE_IPV4_TCP   0x20000
 
#define RXQ_CTRL_HASH_TYPE_IPV6   0x40000
 
#define RXQ_CTRL_HASH_TYPE_IPV6_TCP   0x80000
 
#define RXQ_CTRL_RSS_MODE_DISABLE   0
 
#define RXQ_CTRL_RSS_MODE_SQSINT   0x4000000
 
#define RXQ_CTRL_RSS_MODE_MQUESINT   0x8000000
 
#define RXQ_CTRL_RSS_MODE_MQUEMINT   0xC000000
 
#define RXQ_CTRL_NIP_QUEUE_SEL_TBL   0x10000000
 
#define RXQ_CTRL_HASH_ENABLE   0x20000000
 
#define RXQ_CTRL_CUT_THRU_EN   0x40000000
 
#define RXQ_CTRL_EN   0x80000000
 
#define REG_RXQ_JMBOSZ_RRDTIM   0x15A4
 
#define RXQ_JMBOSZ_TH_MASK   0x7ff
 
#define RXQ_JMBOSZ_TH_SHIFT   0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
 
#define RXQ_JMBO_LKAH_MASK   0xf
 
#define RXQ_JMBO_LKAH_SHIFT   11
 
#define REG_RXQ_RXF_PAUSE_THRESH   0x15A8
 
#define RXQ_RXF_PAUSE_TH_HI_SHIFT   0
 
#define RXQ_RXF_PAUSE_TH_HI_MASK   0xfff
 
#define RXQ_RXF_PAUSE_TH_LO_SHIFT   16
 
#define RXQ_RXF_PAUSE_TH_LO_MASK   0xfff
 
#define REG_DMA_CTRL   0x15C0
 
#define DMA_CTRL_DMAR_IN_ORDER   0x1
 
#define DMA_CTRL_DMAR_ENH_ORDER   0x2
 
#define DMA_CTRL_DMAR_OUT_ORDER   0x4
 
#define DMA_CTRL_RCB_VALUE   0x8
 
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT   4
 
#define DMA_CTRL_DMAR_BURST_LEN_MASK   7
 
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT   7
 
#define DMA_CTRL_DMAW_BURST_LEN_MASK   7
 
#define DMA_CTRL_DMAR_REQ_PRI   0x400
 
#define DMA_CTRL_DMAR_DLY_CNT_MASK   0x1F
 
#define DMA_CTRL_DMAR_DLY_CNT_SHIFT   11
 
#define DMA_CTRL_DMAW_DLY_CNT_MASK   0xF
 
#define DMA_CTRL_DMAW_DLY_CNT_SHIFT   16
 
#define DMA_CTRL_TXCMB_EN   0x100000
 
#define DMA_CTRL_RXCMB_EN   0x200000
 
#define REG_SMB_STAT_TIMER   0x15C4
 
#define REG_TRIG_RRD_THRESH   0x15CA
 
#define REG_TRIG_TPD_THRESH   0x15C8
 
#define REG_TRIG_TXTIMER   0x15CC
 
#define REG_TRIG_RXTIMER   0x15CE
 
#define REG_HOST_RXF1_PAGE0_LO   0x15D0
 
#define REG_HOST_RXF1_PAGE1_LO   0x15D4
 
#define REG_HOST_RXF2_PAGE0_LO   0x15D8
 
#define REG_HOST_RXF2_PAGE1_LO   0x15DC
 
#define REG_HOST_RXF3_PAGE0_LO   0x15E0
 
#define REG_HOST_RXF3_PAGE1_LO   0x15E4
 
#define REG_MB_RXF1_RADDR   0x15B4
 
#define REG_MB_RXF2_RADDR   0x15B8
 
#define REG_MB_RXF3_RADDR   0x15BC
 
#define REG_MB_TPD_PROD_IDX   0x15F0
 
#define REG_HOST_RXF0_PAGE0_VLD   0x15F4
 
#define HOST_RXF_VALID   1
 
#define HOST_RXF_PAGENO_SHIFT   1
 
#define HOST_RXF_PAGENO_MASK   0x7F
 
#define REG_HOST_RXF0_PAGE1_VLD   0x15F5
 
#define REG_HOST_RXF1_PAGE0_VLD   0x15F6
 
#define REG_HOST_RXF1_PAGE1_VLD   0x15F7
 
#define REG_HOST_RXF2_PAGE0_VLD   0x15F8
 
#define REG_HOST_RXF2_PAGE1_VLD   0x15F9
 
#define REG_HOST_RXF3_PAGE0_VLD   0x15FA
 
#define REG_HOST_RXF3_PAGE1_VLD   0x15FB
 
#define REG_ISR   0x1600
 
#define ISR_SMB   1
 
#define ISR_TIMER   2 /* Interrupt when Timer is counted down to zero */
 
#define ISR_MANUAL   4
 
#define ISR_HW_RXF_OV   8 /* RXF overflow interrupt */
 
#define ISR_HOST_RXF0_OV   0x10
 
#define ISR_HOST_RXF1_OV   0x20
 
#define ISR_HOST_RXF2_OV   0x40
 
#define ISR_HOST_RXF3_OV   0x80
 
#define ISR_TXF_UN   0x100
 
#define ISR_RX0_PAGE_FULL   0x200
 
#define ISR_DMAR_TO_RST   0x400
 
#define ISR_DMAW_TO_RST   0x800
 
#define ISR_GPHY   0x1000
 
#define ISR_TX_CREDIT   0x2000
 
#define ISR_GPHY_LPW   0x4000 /* GPHY low power state interrupt */
 
#define ISR_RX_PKT   0x10000 /* One packet received, triggered by RFD */
 
#define ISR_TX_PKT   0x20000 /* One packet transmitted, triggered by TPD */
 
#define ISR_TX_DMA   0x40000
 
#define ISR_RX_PKT_1   0x80000
 
#define ISR_RX_PKT_2   0x100000
 
#define ISR_RX_PKT_3   0x200000
 
#define ISR_MAC_RX   0x400000
 
#define ISR_MAC_TX   0x800000
 
#define ISR_UR_DETECTED   0x1000000
 
#define ISR_FERR_DETECTED   0x2000000
 
#define ISR_NFERR_DETECTED   0x4000000
 
#define ISR_CERR_DETECTED   0x8000000
 
#define ISR_PHY_LINKDOWN   0x10000000
 
#define ISR_DIS_INT   0x80000000
 
#define REG_IMR   0x1604
 
#define IMR_NORMAL_MASK
 
#define ISR_TX_EVENT   (ISR_TXF_UN | ISR_TX_PKT)
 
#define ISR_RX_EVENT   (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
 
#define REG_MAC_RX_STATUS_BIN   0x1700
 
#define REG_MAC_RX_STATUS_END   0x175c
 
#define REG_MAC_TX_STATUS_BIN   0x1760
 
#define REG_MAC_TX_STATUS_END   0x17c0
 
#define REG_HOST_RXF0_PAGEOFF   0x1800
 
#define REG_TPD_CONS_IDX   0x1804
 
#define REG_HOST_RXF1_PAGEOFF   0x1808
 
#define REG_HOST_RXF2_PAGEOFF   0x180C
 
#define REG_HOST_RXF3_PAGEOFF   0x1810
 
#define REG_HOST_RXF0_MB0_LO   0x1820
 
#define REG_HOST_RXF0_MB1_LO   0x1824
 
#define REG_HOST_RXF1_MB0_LO   0x1828
 
#define REG_HOST_RXF1_MB1_LO   0x182C
 
#define REG_HOST_RXF2_MB0_LO   0x1830
 
#define REG_HOST_RXF2_MB1_LO   0x1834
 
#define REG_HOST_RXF3_MB0_LO   0x1838
 
#define REG_HOST_RXF3_MB1_LO   0x183C
 
#define REG_HOST_TX_CMB_LO   0x1840
 
#define REG_HOST_SMB_ADDR_LO   0x1844
 
#define REG_DEBUG_DATA0   0x1900
 
#define REG_DEBUG_DATA1   0x1904
 
#define MII_BMCR   0x00
 
#define MII_BMSR   0x01
 
#define MII_PHYSID1   0x02
 
#define MII_PHYSID2   0x03
 
#define MII_ADVERTISE   0x04
 
#define MII_LPA   0x05
 
#define MII_EXPANSION   0x06
 
#define MII_AT001_CR   0x09
 
#define MII_AT001_SR   0x0A
 
#define MII_AT001_ESR   0x0F
 
#define MII_AT001_PSCR   0x10
 
#define MII_AT001_PSSR   0x11
 
#define MII_INT_CTRL   0x12
 
#define MII_INT_STATUS   0x13
 
#define MII_SMARTSPEED   0x14
 
#define MII_RERRCOUNTER   0x15
 
#define MII_SREVISION   0x16
 
#define MII_RESV1   0x17
 
#define MII_LBRERROR   0x18
 
#define MII_PHYADDR   0x19
 
#define MII_RESV2   0x1a
 
#define MII_TPISTATUS   0x1b
 
#define MII_NCONFIG   0x1c
 
#define MII_DBG_ADDR   0x1D
 
#define MII_DBG_DATA   0x1E
 
#define MII_CR_SPEED_SELECT_MSB   0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
 
#define MII_CR_COLL_TEST_ENABLE   0x0080 /* Collision test enable */
 
#define MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */
 
#define MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */
 
#define MII_CR_ISOLATE   0x0400 /* Isolate PHY from MII */
 
#define MII_CR_POWER_DOWN   0x0800 /* Power down */
 
#define MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */
 
#define MII_CR_SPEED_SELECT_LSB   0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
 
#define MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */
 
#define MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */
 
#define MII_CR_SPEED_MASK   0x2040
 
#define MII_CR_SPEED_1000   0x0040
 
#define MII_CR_SPEED_100   0x2000
 
#define MII_CR_SPEED_10   0x0000
 
#define MII_SR_EXTENDED_CAPS   0x0001 /* Extended register capabilities */
 
#define MII_SR_JABBER_DETECT   0x0002 /* Jabber Detected */
 
#define MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */
 
#define MII_SR_AUTONEG_CAPS   0x0008 /* Auto Neg Capable */
 
#define MII_SR_REMOTE_FAULT   0x0010 /* Remote Fault Detect */
 
#define MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */
 
#define MII_SR_PREAMBLE_SUPPRESS   0x0040 /* Preamble may be suppressed */
 
#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
 
#define MII_SR_100T2_HD_CAPS   0x0200 /* 100T2 Half Duplex Capable */
 
#define MII_SR_100T2_FD_CAPS   0x0400 /* 100T2 Full Duplex Capable */
 
#define MII_SR_10T_HD_CAPS   0x0800 /* 10T Half Duplex Capable */
 
#define MII_SR_10T_FD_CAPS   0x1000 /* 10T Full Duplex Capable */
 
#define MII_SR_100X_HD_CAPS   0x2000 /* 100X Half Duplex Capable */
 
#define MII_SR_100X_FD_CAPS   0x4000 /* 100X Full Duplex Capable */
 
#define MII_SR_100T4_CAPS   0x8000 /* 100T4 Capable */
 
#define MII_LPA_SLCT   0x001f /* Same as advertise selector */
 
#define MII_LPA_10HALF   0x0020 /* Can do 10mbps half-duplex */
 
#define MII_LPA_10FULL   0x0040 /* Can do 10mbps full-duplex */
 
#define MII_LPA_100HALF   0x0080 /* Can do 100mbps half-duplex */
 
#define MII_LPA_100FULL   0x0100 /* Can do 100mbps full-duplex */
 
#define MII_LPA_100BASE4   0x0200 /* 100BASE-T4 */
 
#define MII_LPA_PAUSE   0x0400 /* PAUSE */
 
#define MII_LPA_ASYPAUSE   0x0800 /* Asymmetrical PAUSE */
 
#define MII_LPA_RFAULT   0x2000 /* Link partner faulted */
 
#define MII_LPA_LPACK   0x4000 /* Link partner acked us */
 
#define MII_LPA_NPAGE   0x8000 /* Next page bit */
 
#define MII_AR_SELECTOR_FIELD   0x0001 /* indicates IEEE 802.3 CSMA/CD */
 
#define MII_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */
 
#define MII_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */
 
#define MII_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */
 
#define MII_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */
 
#define MII_AR_100T4_CAPS   0x0200 /* 100T4 Capable */
 
#define MII_AR_PAUSE   0x0400 /* Pause operation desired */
 
#define MII_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */
 
#define MII_AR_REMOTE_FAULT   0x2000 /* Remote Fault detected */
 
#define MII_AR_NEXT_PAGE   0x8000 /* Next Page ability supported */
 
#define MII_AR_SPEED_MASK   0x01E0
 
#define MII_AR_DEFAULT_CAP_MASK   0x0DE0
 
#define MII_AT001_CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */
 
#define MII_AT001_CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */
 
#define MII_AT001_CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port */
 
#define MII_AT001_CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */
 
#define MII_AT001_CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */
 
#define MII_AT001_CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */
 
#define MII_AT001_CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */
 
#define MII_AT001_CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */
 
#define MII_AT001_CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */
 
#define MII_AT001_CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */
 
#define MII_AT001_CR_1000T_SPEED_MASK   0x0300
 
#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK   0x0300
 
#define MII_AT001_SR_1000T_LP_HD_CAPS   0x0400 /* LP is 1000T HD capable */
 
#define MII_AT001_SR_1000T_LP_FD_CAPS   0x0800 /* LP is 1000T FD capable */
 
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */
 
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */
 
#define MII_AT001_SR_1000T_MS_CONFIG_RES   0x4000 /* 1=Local TX is Master, 0=Slave */
 
#define MII_AT001_SR_1000T_MS_CONFIG_FAULT   0x8000 /* Master/Slave config fault */
 
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT   12
 
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT   13
 
#define MII_AT001_ESR_1000T_HD_CAPS   0x1000 /* 1000T HD capable */
 
#define MII_AT001_ESR_1000T_FD_CAPS   0x2000 /* 1000T FD capable */
 
#define MII_AT001_ESR_1000X_HD_CAPS   0x4000 /* 1000X HD capable */
 
#define MII_AT001_ESR_1000X_FD_CAPS   0x8000 /* 1000X FD capable */
 
#define MII_AT001_PSCR_JABBER_DISABLE   0x0001 /* 1=Jabber Function disabled */
 
#define MII_AT001_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */
 
#define MII_AT001_PSCR_SQE_TEST   0x0004 /* 1=SQE Test enabled */
 
#define MII_AT001_PSCR_MAC_POWERDOWN   0x0008
 
#define MII_AT001_PSCR_CLK125_DISABLE
 
#define MII_AT001_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */
 
#define MII_AT001_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */
 
#define MII_AT001_PSCR_AUTO_X_1000T
 
#define MII_AT001_PSCR_AUTO_X_MODE
 
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE   0x0080
 
#define MII_AT001_PSCR_MII_5BIT_ENABLE   0x0100
 
#define MII_AT001_PSCR_SCRAMBLER_DISABLE   0x0200 /* 1=Scrambler disable */
 
#define MII_AT001_PSCR_FORCE_LINK_GOOD   0x0400 /* 1=Force link good */
 
#define MII_AT001_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */
 
#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT   1
 
#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT   5
 
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT   7
 
#define MII_AT001_PSSR_SPD_DPLX_RESOLVED   0x0800 /* 1=Speed & Duplex resolved */
 
#define MII_AT001_PSSR_DPLX   0x2000 /* 1=Duplex 0=Half Duplex */
 
#define MII_AT001_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */
 
#define MII_AT001_PSSR_10MBS   0x0000 /* 00=10Mbs */
 
#define MII_AT001_PSSR_100MBS   0x4000 /* 01=100Mbs */
 
#define MII_AT001_PSSR_1000MBS   0x8000 /* 10=1000Mbs */
 

Enumerations

enum  atl1e_dma_req_block {
  atl1e_dma_req_128 = 0, atl1e_dma_req_256 = 1, atl1e_dma_req_512 = 2, atl1e_dma_req_1024 = 3,
  atl1e_dma_req_2048 = 4, atl1e_dma_req_4096 = 5
}
 
enum  atl1e_nic_type { athr_l1e = 0, athr_l2e_revA = 1, athr_l2e_revB = 2 }
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
int atl1e_up (struct atl1e_adapter *adapter)
 
void atl1e_down (struct atl1e_adapter *adapter)
 
s32 atl1e_reset_hw (struct atl1e_hw *hw)
 
s32 atl1e_read_mac_addr (struct atl1e_hw *hw)
 
s32 atl1e_init_hw (struct atl1e_hw *hw)
 
s32 atl1e_phy_commit (struct atl1e_hw *hw)
 
s32 atl1e_get_speed_and_duplex (struct atl1e_hw *hw, u16 *speed, u16 *duplex)
 
u32 atl1e_auto_get_fc (struct atl1e_adapter *adapter, u16 duplex)
 
s32 atl1e_read_phy_reg (struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
 
s32 atl1e_write_phy_reg (struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
 
s32 atl1e_validate_mdi_setting (struct atl1e_hw *hw)
 
void atl1e_hw_set_mac_addr (struct atl1e_hw *hw)
 
s32 atl1e_phy_enter_power_saving (struct atl1e_hw *hw)
 
s32 atl1e_phy_leave_power_saving (struct atl1e_hw *hw)
 
s32 atl1e_phy_init (struct atl1e_hw *hw)
 
int atl1e_check_eeprom_exist (struct atl1e_hw *hw)
 
void atl1e_force_ps (struct atl1e_hw *hw)
 
s32 atl1e_restart_autoneg (struct atl1e_hw *hw)
 

Macro Definition Documentation

◆ _ATL1E_H_

#define _ATL1E_H_

Definition at line 28 of file atl1e.h.

◆ ETH_FCS_LEN

#define ETH_FCS_LEN   4

Definition at line 45 of file atl1e.h.

◆ VLAN_HLEN

#define VLAN_HLEN   4

Definition at line 46 of file atl1e.h.

◆ NET_IP_ALIGN

#define NET_IP_ALIGN   2

Definition at line 47 of file atl1e.h.

◆ SPEED_0

#define SPEED_0   0xffff

Definition at line 49 of file atl1e.h.

◆ SPEED_10

#define SPEED_10   10

Definition at line 50 of file atl1e.h.

◆ SPEED_100

#define SPEED_100   100

Definition at line 51 of file atl1e.h.

◆ SPEED_1000

#define SPEED_1000   1000

Definition at line 52 of file atl1e.h.

◆ HALF_DUPLEX

#define HALF_DUPLEX   1

Definition at line 53 of file atl1e.h.

◆ FULL_DUPLEX

#define FULL_DUPLEX   2

Definition at line 54 of file atl1e.h.

◆ AT_ERR_EEPROM

#define AT_ERR_EEPROM   1

Definition at line 57 of file atl1e.h.

◆ AT_ERR_PHY

#define AT_ERR_PHY   2

Definition at line 58 of file atl1e.h.

◆ AT_ERR_CONFIG

#define AT_ERR_CONFIG   3

Definition at line 59 of file atl1e.h.

◆ AT_ERR_PARAM

#define AT_ERR_PARAM   4

Definition at line 60 of file atl1e.h.

◆ AT_ERR_MAC_TYPE

#define AT_ERR_MAC_TYPE   5

Definition at line 61 of file atl1e.h.

◆ AT_ERR_PHY_TYPE

#define AT_ERR_PHY_TYPE   6

Definition at line 62 of file atl1e.h.

◆ AT_ERR_PHY_SPEED

#define AT_ERR_PHY_SPEED   7

Definition at line 63 of file atl1e.h.

◆ AT_ERR_PHY_RES

#define AT_ERR_PHY_RES   8

Definition at line 64 of file atl1e.h.

◆ AT_ERR_TIMEOUT

#define AT_ERR_TIMEOUT   9

Definition at line 65 of file atl1e.h.

◆ AT_MAX_RECEIVE_QUEUE

#define AT_MAX_RECEIVE_QUEUE   4

Definition at line 67 of file atl1e.h.

◆ AT_PAGE_NUM_PER_QUEUE

#define AT_PAGE_NUM_PER_QUEUE   2

Definition at line 68 of file atl1e.h.

◆ AT_TWSI_EEPROM_TIMEOUT

#define AT_TWSI_EEPROM_TIMEOUT   100

Definition at line 70 of file atl1e.h.

◆ AT_HW_MAX_IDLE_DELAY

#define AT_HW_MAX_IDLE_DELAY   10

Definition at line 71 of file atl1e.h.

◆ AT_REGS_LEN

#define AT_REGS_LEN   75

Definition at line 73 of file atl1e.h.

◆ AT_EEPROM_LEN

#define AT_EEPROM_LEN   512

Definition at line 74 of file atl1e.h.

◆ TPD_BUFLEN_MASK

#define TPD_BUFLEN_MASK   0x3FFF

Definition at line 77 of file atl1e.h.

◆ TPD_BUFLEN_SHIFT

#define TPD_BUFLEN_SHIFT   0

Definition at line 78 of file atl1e.h.

◆ TPD_EOP_MASK

#define TPD_EOP_MASK   0x0001

Definition at line 81 of file atl1e.h.

◆ TPD_EOP_SHIFT

#define TPD_EOP_SHIFT   0

Definition at line 82 of file atl1e.h.

◆ MAX_TX_BUF_LEN

#define MAX_TX_BUF_LEN   0x2000

Definition at line 90 of file atl1e.h.

◆ MAX_TX_BUF_SHIFT

#define MAX_TX_BUF_SHIFT   13

Definition at line 91 of file atl1e.h.

◆ RRS_RX_CSUM_MASK

#define RRS_RX_CSUM_MASK   0xFFFF

Definition at line 94 of file atl1e.h.

◆ RRS_RX_CSUM_SHIFT

#define RRS_RX_CSUM_SHIFT   0

Definition at line 95 of file atl1e.h.

◆ RRS_PKT_SIZE_MASK

#define RRS_PKT_SIZE_MASK   0x3FFF

Definition at line 96 of file atl1e.h.

◆ RRS_PKT_SIZE_SHIFT

#define RRS_PKT_SIZE_SHIFT   16

Definition at line 97 of file atl1e.h.

◆ RRS_CPU_NUM_MASK

#define RRS_CPU_NUM_MASK   0x0003

Definition at line 98 of file atl1e.h.

◆ RRS_CPU_NUM_SHIFT

#define RRS_CPU_NUM_SHIFT   30

Definition at line 99 of file atl1e.h.

◆ RRS_IS_RSS_IPV4

#define RRS_IS_RSS_IPV4   0x0001

Definition at line 101 of file atl1e.h.

◆ RRS_IS_RSS_IPV4_TCP

#define RRS_IS_RSS_IPV4_TCP   0x0002

Definition at line 102 of file atl1e.h.

◆ RRS_IS_RSS_IPV6

#define RRS_IS_RSS_IPV6   0x0004

Definition at line 103 of file atl1e.h.

◆ RRS_IS_RSS_IPV6_TCP

#define RRS_IS_RSS_IPV6_TCP   0x0008

Definition at line 104 of file atl1e.h.

◆ RRS_IS_IPV6

#define RRS_IS_IPV6   0x0010

Definition at line 105 of file atl1e.h.

◆ RRS_IS_IP_FRAG

#define RRS_IS_IP_FRAG   0x0020

Definition at line 106 of file atl1e.h.

◆ RRS_IS_IP_DF

#define RRS_IS_IP_DF   0x0040

Definition at line 107 of file atl1e.h.

◆ RRS_IS_802_3

#define RRS_IS_802_3   0x0080

Definition at line 108 of file atl1e.h.

◆ RRS_IS_VLAN_TAG

#define RRS_IS_VLAN_TAG   0x0100

Definition at line 109 of file atl1e.h.

◆ RRS_IS_ERR_FRAME

#define RRS_IS_ERR_FRAME   0x0200

Definition at line 110 of file atl1e.h.

◆ RRS_IS_IPV4

#define RRS_IS_IPV4   0x0400

Definition at line 111 of file atl1e.h.

◆ RRS_IS_UDP

#define RRS_IS_UDP   0x0800

Definition at line 112 of file atl1e.h.

◆ RRS_IS_TCP

#define RRS_IS_TCP   0x1000

Definition at line 113 of file atl1e.h.

◆ RRS_IS_BCAST

#define RRS_IS_BCAST   0x2000

Definition at line 114 of file atl1e.h.

◆ RRS_IS_MCAST

#define RRS_IS_MCAST   0x4000

Definition at line 115 of file atl1e.h.

◆ RRS_IS_PAUSE

#define RRS_IS_PAUSE   0x8000

Definition at line 116 of file atl1e.h.

◆ RRS_ERR_BAD_CRC

#define RRS_ERR_BAD_CRC   0x0001

Definition at line 118 of file atl1e.h.

◆ RRS_ERR_CODE

#define RRS_ERR_CODE   0x0002

Definition at line 119 of file atl1e.h.

◆ RRS_ERR_DRIBBLE

#define RRS_ERR_DRIBBLE   0x0004

Definition at line 120 of file atl1e.h.

◆ RRS_ERR_RUNT

#define RRS_ERR_RUNT   0x0008

Definition at line 121 of file atl1e.h.

◆ RRS_ERR_RX_OVERFLOW

#define RRS_ERR_RX_OVERFLOW   0x0010

Definition at line 122 of file atl1e.h.

◆ RRS_ERR_TRUNC

#define RRS_ERR_TRUNC   0x0020

Definition at line 123 of file atl1e.h.

◆ RRS_ERR_IP_CSUM

#define RRS_ERR_IP_CSUM   0x0040

Definition at line 124 of file atl1e.h.

◆ RRS_ERR_L4_CSUM

#define RRS_ERR_L4_CSUM   0x0080

Definition at line 125 of file atl1e.h.

◆ RRS_ERR_LENGTH

#define RRS_ERR_LENGTH   0x0100

Definition at line 126 of file atl1e.h.

◆ RRS_ERR_DES_ADDR

#define RRS_ERR_DES_ADDR   0x0200

Definition at line 127 of file atl1e.h.

◆ AT_WRITE_REG

#define AT_WRITE_REG (   a,
  reg,
  value 
)    writel((value), ((a)->hw_addr + reg))

Definition at line 241 of file atl1e.h.

◆ AT_WRITE_FLUSH

#define AT_WRITE_FLUSH (   a)    readl((a)->hw_addr)

Definition at line 244 of file atl1e.h.

◆ AT_READ_REG

#define AT_READ_REG (   a,
  reg 
)    readl((a)->hw_addr + reg)

Definition at line 247 of file atl1e.h.

◆ AT_WRITE_REGB

#define AT_WRITE_REGB (   a,
  reg,
  value 
)    writeb((value), ((a)->hw_addr + reg))

Definition at line 250 of file atl1e.h.

◆ AT_READ_REGB

#define AT_READ_REGB (   a,
  reg 
)    readb((a)->hw_addr + reg)

Definition at line 253 of file atl1e.h.

◆ AT_WRITE_REGW

#define AT_WRITE_REGW (   a,
  reg,
  value 
)    writew((value), ((a)->hw_addr + reg))

Definition at line 256 of file atl1e.h.

◆ AT_READ_REGW

#define AT_READ_REGW (   a,
  reg 
)    readw((a)->hw_addr + reg)

Definition at line 259 of file atl1e.h.

◆ AT_WRITE_REG_ARRAY

#define AT_WRITE_REG_ARRAY (   a,
  reg,
  offset,
  value 
)    writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))

Definition at line 262 of file atl1e.h.

◆ AT_READ_REG_ARRAY

#define AT_READ_REG_ARRAY (   a,
  reg,
  offset 
)    readl(((a)->hw_addr + reg) + ((offset) << 2))

Definition at line 265 of file atl1e.h.

◆ REG_PM_CTRLSTAT

#define REG_PM_CTRLSTAT   0x44

Definition at line 293 of file atl1e.h.

◆ REG_PCIE_CAP_LIST

#define REG_PCIE_CAP_LIST   0x58

Definition at line 295 of file atl1e.h.

◆ REG_DEVICE_CAP

#define REG_DEVICE_CAP   0x5C

Definition at line 297 of file atl1e.h.

◆ DEVICE_CAP_MAX_PAYLOAD_MASK

#define DEVICE_CAP_MAX_PAYLOAD_MASK   0x7

Definition at line 298 of file atl1e.h.

◆ DEVICE_CAP_MAX_PAYLOAD_SHIFT

#define DEVICE_CAP_MAX_PAYLOAD_SHIFT   0

Definition at line 299 of file atl1e.h.

◆ REG_DEVICE_CTRL

#define REG_DEVICE_CTRL   0x60

Definition at line 301 of file atl1e.h.

◆ DEVICE_CTRL_MAX_PAYLOAD_MASK

#define DEVICE_CTRL_MAX_PAYLOAD_MASK   0x7

Definition at line 302 of file atl1e.h.

◆ DEVICE_CTRL_MAX_PAYLOAD_SHIFT

#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT   5

Definition at line 303 of file atl1e.h.

◆ DEVICE_CTRL_MAX_RREQ_SZ_MASK

#define DEVICE_CTRL_MAX_RREQ_SZ_MASK   0x7

Definition at line 304 of file atl1e.h.

◆ DEVICE_CTRL_MAX_RREQ_SZ_SHIFT

#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT   12

Definition at line 305 of file atl1e.h.

◆ REG_VPD_CAP

#define REG_VPD_CAP   0x6C

Definition at line 307 of file atl1e.h.

◆ VPD_CAP_ID_MASK

#define VPD_CAP_ID_MASK   0xff

Definition at line 308 of file atl1e.h.

◆ VPD_CAP_ID_SHIFT

#define VPD_CAP_ID_SHIFT   0

Definition at line 309 of file atl1e.h.

◆ VPD_CAP_NEXT_PTR_MASK

#define VPD_CAP_NEXT_PTR_MASK   0xFF

Definition at line 310 of file atl1e.h.

◆ VPD_CAP_NEXT_PTR_SHIFT

#define VPD_CAP_NEXT_PTR_SHIFT   8

Definition at line 311 of file atl1e.h.

◆ VPD_CAP_VPD_ADDR_MASK

#define VPD_CAP_VPD_ADDR_MASK   0x7FFF

Definition at line 312 of file atl1e.h.

◆ VPD_CAP_VPD_ADDR_SHIFT

#define VPD_CAP_VPD_ADDR_SHIFT   16

Definition at line 313 of file atl1e.h.

◆ VPD_CAP_VPD_FLAG

#define VPD_CAP_VPD_FLAG   0x80000000

Definition at line 314 of file atl1e.h.

◆ REG_VPD_DATA

#define REG_VPD_DATA   0x70

Definition at line 316 of file atl1e.h.

◆ REG_SPI_FLASH_CTRL

#define REG_SPI_FLASH_CTRL   0x200

Definition at line 318 of file atl1e.h.

◆ SPI_FLASH_CTRL_STS_NON_RDY

#define SPI_FLASH_CTRL_STS_NON_RDY   0x1

Definition at line 319 of file atl1e.h.

◆ SPI_FLASH_CTRL_STS_WEN

#define SPI_FLASH_CTRL_STS_WEN   0x2

Definition at line 320 of file atl1e.h.

◆ SPI_FLASH_CTRL_STS_WPEN

#define SPI_FLASH_CTRL_STS_WPEN   0x80

Definition at line 321 of file atl1e.h.

◆ SPI_FLASH_CTRL_DEV_STS_MASK

#define SPI_FLASH_CTRL_DEV_STS_MASK   0xFF

Definition at line 322 of file atl1e.h.

◆ SPI_FLASH_CTRL_DEV_STS_SHIFT

#define SPI_FLASH_CTRL_DEV_STS_SHIFT   0

Definition at line 323 of file atl1e.h.

◆ SPI_FLASH_CTRL_INS_MASK

#define SPI_FLASH_CTRL_INS_MASK   0x7

Definition at line 324 of file atl1e.h.

◆ SPI_FLASH_CTRL_INS_SHIFT

#define SPI_FLASH_CTRL_INS_SHIFT   8

Definition at line 325 of file atl1e.h.

◆ SPI_FLASH_CTRL_START

#define SPI_FLASH_CTRL_START   0x800

Definition at line 326 of file atl1e.h.

◆ SPI_FLASH_CTRL_EN_VPD

#define SPI_FLASH_CTRL_EN_VPD   0x2000

Definition at line 327 of file atl1e.h.

◆ SPI_FLASH_CTRL_LDSTART

#define SPI_FLASH_CTRL_LDSTART   0x8000

Definition at line 328 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_HI_MASK

#define SPI_FLASH_CTRL_CS_HI_MASK   0x3

Definition at line 329 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_HI_SHIFT

#define SPI_FLASH_CTRL_CS_HI_SHIFT   16

Definition at line 330 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_HOLD_MASK

#define SPI_FLASH_CTRL_CS_HOLD_MASK   0x3

Definition at line 331 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_HOLD_SHIFT

#define SPI_FLASH_CTRL_CS_HOLD_SHIFT   18

Definition at line 332 of file atl1e.h.

◆ SPI_FLASH_CTRL_CLK_LO_MASK

#define SPI_FLASH_CTRL_CLK_LO_MASK   0x3

Definition at line 333 of file atl1e.h.

◆ SPI_FLASH_CTRL_CLK_LO_SHIFT

#define SPI_FLASH_CTRL_CLK_LO_SHIFT   20

Definition at line 334 of file atl1e.h.

◆ SPI_FLASH_CTRL_CLK_HI_MASK

#define SPI_FLASH_CTRL_CLK_HI_MASK   0x3

Definition at line 335 of file atl1e.h.

◆ SPI_FLASH_CTRL_CLK_HI_SHIFT

#define SPI_FLASH_CTRL_CLK_HI_SHIFT   22

Definition at line 336 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_SETUP_MASK

#define SPI_FLASH_CTRL_CS_SETUP_MASK   0x3

Definition at line 337 of file atl1e.h.

◆ SPI_FLASH_CTRL_CS_SETUP_SHIFT

#define SPI_FLASH_CTRL_CS_SETUP_SHIFT   24

Definition at line 338 of file atl1e.h.

◆ SPI_FLASH_CTRL_EROM_PGSZ_MASK

#define SPI_FLASH_CTRL_EROM_PGSZ_MASK   0x3

Definition at line 339 of file atl1e.h.

◆ SPI_FLASH_CTRL_EROM_PGSZ_SHIFT

#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT   26

Definition at line 340 of file atl1e.h.

◆ SPI_FLASH_CTRL_WAIT_READY

#define SPI_FLASH_CTRL_WAIT_READY   0x10000000

Definition at line 341 of file atl1e.h.

◆ REG_SPI_ADDR

#define REG_SPI_ADDR   0x204

Definition at line 343 of file atl1e.h.

◆ REG_SPI_DATA

#define REG_SPI_DATA   0x208

Definition at line 345 of file atl1e.h.

◆ REG_SPI_FLASH_CONFIG

#define REG_SPI_FLASH_CONFIG   0x20C

Definition at line 347 of file atl1e.h.

◆ SPI_FLASH_CONFIG_LD_ADDR_MASK

#define SPI_FLASH_CONFIG_LD_ADDR_MASK   0xFFFFFF

Definition at line 348 of file atl1e.h.

◆ SPI_FLASH_CONFIG_LD_ADDR_SHIFT

#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT   0

Definition at line 349 of file atl1e.h.

◆ SPI_FLASH_CONFIG_VPD_ADDR_MASK

#define SPI_FLASH_CONFIG_VPD_ADDR_MASK   0x3

Definition at line 350 of file atl1e.h.

◆ SPI_FLASH_CONFIG_VPD_ADDR_SHIFT

#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT   24

Definition at line 351 of file atl1e.h.

◆ SPI_FLASH_CONFIG_LD_EXIST

#define SPI_FLASH_CONFIG_LD_EXIST   0x4000000

Definition at line 352 of file atl1e.h.

◆ REG_SPI_FLASH_OP_PROGRAM

#define REG_SPI_FLASH_OP_PROGRAM   0x210

Definition at line 355 of file atl1e.h.

◆ REG_SPI_FLASH_OP_SC_ERASE

#define REG_SPI_FLASH_OP_SC_ERASE   0x211

Definition at line 356 of file atl1e.h.

◆ REG_SPI_FLASH_OP_CHIP_ERASE

#define REG_SPI_FLASH_OP_CHIP_ERASE   0x212

Definition at line 357 of file atl1e.h.

◆ REG_SPI_FLASH_OP_RDID

#define REG_SPI_FLASH_OP_RDID   0x213

Definition at line 358 of file atl1e.h.

◆ REG_SPI_FLASH_OP_WREN

#define REG_SPI_FLASH_OP_WREN   0x214

Definition at line 359 of file atl1e.h.

◆ REG_SPI_FLASH_OP_RDSR

#define REG_SPI_FLASH_OP_RDSR   0x215

Definition at line 360 of file atl1e.h.

◆ REG_SPI_FLASH_OP_WRSR

#define REG_SPI_FLASH_OP_WRSR   0x216

Definition at line 361 of file atl1e.h.

◆ REG_SPI_FLASH_OP_READ

#define REG_SPI_FLASH_OP_READ   0x217

Definition at line 362 of file atl1e.h.

◆ REG_TWSI_CTRL

#define REG_TWSI_CTRL   0x218

Definition at line 364 of file atl1e.h.

◆ TWSI_CTRL_LD_OFFSET_MASK

#define TWSI_CTRL_LD_OFFSET_MASK   0xFF

Definition at line 365 of file atl1e.h.

◆ TWSI_CTRL_LD_OFFSET_SHIFT

#define TWSI_CTRL_LD_OFFSET_SHIFT   0

Definition at line 366 of file atl1e.h.

◆ TWSI_CTRL_LD_SLV_ADDR_MASK

#define TWSI_CTRL_LD_SLV_ADDR_MASK   0x7

Definition at line 367 of file atl1e.h.

◆ TWSI_CTRL_LD_SLV_ADDR_SHIFT

#define TWSI_CTRL_LD_SLV_ADDR_SHIFT   8

Definition at line 368 of file atl1e.h.

◆ TWSI_CTRL_SW_LDSTART

#define TWSI_CTRL_SW_LDSTART   0x800

Definition at line 369 of file atl1e.h.

◆ TWSI_CTRL_HW_LDSTART

#define TWSI_CTRL_HW_LDSTART   0x1000

Definition at line 370 of file atl1e.h.

◆ TWSI_CTRL_SMB_SLV_ADDR_MASK

#define TWSI_CTRL_SMB_SLV_ADDR_MASK   0x0x7F

Definition at line 371 of file atl1e.h.

◆ TWSI_CTRL_SMB_SLV_ADDR_SHIFT

#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT   15

Definition at line 372 of file atl1e.h.

◆ TWSI_CTRL_LD_EXIST

#define TWSI_CTRL_LD_EXIST   0x400000

Definition at line 373 of file atl1e.h.

◆ TWSI_CTRL_READ_FREQ_SEL_MASK

#define TWSI_CTRL_READ_FREQ_SEL_MASK   0x3

Definition at line 374 of file atl1e.h.

◆ TWSI_CTRL_READ_FREQ_SEL_SHIFT

#define TWSI_CTRL_READ_FREQ_SEL_SHIFT   23

Definition at line 375 of file atl1e.h.

◆ TWSI_CTRL_FREQ_SEL_100K

#define TWSI_CTRL_FREQ_SEL_100K   0

Definition at line 376 of file atl1e.h.

◆ TWSI_CTRL_FREQ_SEL_200K

#define TWSI_CTRL_FREQ_SEL_200K   1

Definition at line 377 of file atl1e.h.

◆ TWSI_CTRL_FREQ_SEL_300K

#define TWSI_CTRL_FREQ_SEL_300K   2

Definition at line 378 of file atl1e.h.

◆ TWSI_CTRL_FREQ_SEL_400K

#define TWSI_CTRL_FREQ_SEL_400K   3

Definition at line 379 of file atl1e.h.

◆ TWSI_CTRL_SMB_SLV_ADDR

#define TWSI_CTRL_SMB_SLV_ADDR

Definition at line 380 of file atl1e.h.

◆ TWSI_CTRL_WRITE_FREQ_SEL_MASK

#define TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3

Definition at line 381 of file atl1e.h.

◆ TWSI_CTRL_WRITE_FREQ_SEL_SHIFT

#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT   24

Definition at line 382 of file atl1e.h.

◆ REG_PCIE_DEV_MISC_CTRL

#define REG_PCIE_DEV_MISC_CTRL   0x21C

Definition at line 385 of file atl1e.h.

◆ PCIE_DEV_MISC_CTRL_EXT_PIPE

#define PCIE_DEV_MISC_CTRL_EXT_PIPE   0x2

Definition at line 386 of file atl1e.h.

◆ PCIE_DEV_MISC_CTRL_RETRY_BUFDIS

#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS   0x1

Definition at line 387 of file atl1e.h.

◆ PCIE_DEV_MISC_CTRL_SPIROM_EXIST

#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST   0x4

Definition at line 388 of file atl1e.h.

◆ PCIE_DEV_MISC_CTRL_SERDES_ENDIAN

#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN   0x8

Definition at line 389 of file atl1e.h.

◆ PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN

#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN   0x10

Definition at line 390 of file atl1e.h.

◆ REG_PCIE_PHYMISC

#define REG_PCIE_PHYMISC   0x1000

Definition at line 392 of file atl1e.h.

◆ PCIE_PHYMISC_FORCE_RCV_DET

#define PCIE_PHYMISC_FORCE_RCV_DET   0x4

Definition at line 393 of file atl1e.h.

◆ REG_LTSSM_TEST_MODE

#define REG_LTSSM_TEST_MODE   0x12FC

Definition at line 395 of file atl1e.h.

◆ LTSSM_TEST_MODE_DEF

#define LTSSM_TEST_MODE_DEF   0xE000

Definition at line 396 of file atl1e.h.

◆ REG_MASTER_CTRL

#define REG_MASTER_CTRL   0x1400

Definition at line 399 of file atl1e.h.

◆ MASTER_CTRL_SOFT_RST

#define MASTER_CTRL_SOFT_RST   0x1

Definition at line 400 of file atl1e.h.

◆ MASTER_CTRL_MTIMER_EN

#define MASTER_CTRL_MTIMER_EN   0x2

Definition at line 401 of file atl1e.h.

◆ MASTER_CTRL_ITIMER_EN

#define MASTER_CTRL_ITIMER_EN   0x4

Definition at line 402 of file atl1e.h.

◆ MASTER_CTRL_MANUAL_INT

#define MASTER_CTRL_MANUAL_INT   0x8

Definition at line 403 of file atl1e.h.

◆ MASTER_CTRL_ITIMER2_EN

#define MASTER_CTRL_ITIMER2_EN   0x20

Definition at line 404 of file atl1e.h.

◆ MASTER_CTRL_INT_RDCLR

#define MASTER_CTRL_INT_RDCLR   0x40

Definition at line 405 of file atl1e.h.

◆ MASTER_CTRL_LED_MODE

#define MASTER_CTRL_LED_MODE   0x200

Definition at line 406 of file atl1e.h.

◆ MASTER_CTRL_REV_NUM_SHIFT

#define MASTER_CTRL_REV_NUM_SHIFT   16

Definition at line 407 of file atl1e.h.

◆ MASTER_CTRL_REV_NUM_MASK

#define MASTER_CTRL_REV_NUM_MASK   0xff

Definition at line 408 of file atl1e.h.

◆ MASTER_CTRL_DEV_ID_SHIFT

#define MASTER_CTRL_DEV_ID_SHIFT   24

Definition at line 409 of file atl1e.h.

◆ MASTER_CTRL_DEV_ID_MASK

#define MASTER_CTRL_DEV_ID_MASK   0xff

Definition at line 410 of file atl1e.h.

◆ REG_MANUAL_TIMER_INIT

#define REG_MANUAL_TIMER_INIT   0x1404

Definition at line 413 of file atl1e.h.

◆ REG_IRQ_MODU_TIMER_INIT

#define REG_IRQ_MODU_TIMER_INIT   0x1408 /* w */

Definition at line 417 of file atl1e.h.

◆ REG_IRQ_MODU_TIMER2_INIT

#define REG_IRQ_MODU_TIMER2_INIT   0x140A /* w */

Definition at line 418 of file atl1e.h.

◆ REG_GPHY_CTRL

#define REG_GPHY_CTRL   0x140C

Definition at line 421 of file atl1e.h.

◆ GPHY_CTRL_EXT_RESET

#define GPHY_CTRL_EXT_RESET   1

Definition at line 422 of file atl1e.h.

◆ GPHY_CTRL_PIPE_MOD

#define GPHY_CTRL_PIPE_MOD   2

Definition at line 423 of file atl1e.h.

◆ GPHY_CTRL_TEST_MODE_MASK

#define GPHY_CTRL_TEST_MODE_MASK   3

Definition at line 424 of file atl1e.h.

◆ GPHY_CTRL_TEST_MODE_SHIFT

#define GPHY_CTRL_TEST_MODE_SHIFT   2

Definition at line 425 of file atl1e.h.

◆ GPHY_CTRL_BERT_START

#define GPHY_CTRL_BERT_START   0x10

Definition at line 426 of file atl1e.h.

◆ GPHY_CTRL_GATE_25M_EN

#define GPHY_CTRL_GATE_25M_EN   0x20

Definition at line 427 of file atl1e.h.

◆ GPHY_CTRL_LPW_EXIT

#define GPHY_CTRL_LPW_EXIT   0x40

Definition at line 428 of file atl1e.h.

◆ GPHY_CTRL_PHY_IDDQ

#define GPHY_CTRL_PHY_IDDQ   0x80

Definition at line 429 of file atl1e.h.

◆ GPHY_CTRL_PHY_IDDQ_DIS

#define GPHY_CTRL_PHY_IDDQ_DIS   0x100

Definition at line 430 of file atl1e.h.

◆ GPHY_CTRL_PCLK_SEL_DIS

#define GPHY_CTRL_PCLK_SEL_DIS   0x200

Definition at line 431 of file atl1e.h.

◆ GPHY_CTRL_HIB_EN

#define GPHY_CTRL_HIB_EN   0x400

Definition at line 432 of file atl1e.h.

◆ GPHY_CTRL_HIB_PULSE

#define GPHY_CTRL_HIB_PULSE   0x800

Definition at line 433 of file atl1e.h.

◆ GPHY_CTRL_SEL_ANA_RST

#define GPHY_CTRL_SEL_ANA_RST   0x1000

Definition at line 434 of file atl1e.h.

◆ GPHY_CTRL_PHY_PLL_ON

#define GPHY_CTRL_PHY_PLL_ON   0x2000

Definition at line 435 of file atl1e.h.

◆ GPHY_CTRL_PWDOWN_HW

#define GPHY_CTRL_PWDOWN_HW   0x4000

Definition at line 436 of file atl1e.h.

◆ GPHY_CTRL_DEFAULT

#define GPHY_CTRL_DEFAULT
Value:
(\
GPHY_CTRL_PHY_PLL_ON |\
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN)

Definition at line 437 of file atl1e.h.

◆ GPHY_CTRL_PW_WOL_DIS

#define GPHY_CTRL_PW_WOL_DIS
Value:
(\
GPHY_CTRL_PHY_PLL_ON |\
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN |\
GPHY_CTRL_PWDOWN_HW |\
GPHY_CTRL_PCLK_SEL_DIS |\
GPHY_CTRL_PHY_IDDQ)

Definition at line 443 of file atl1e.h.

◆ REG_CMBDISDMA_TIMER

#define REG_CMBDISDMA_TIMER   0x140E

Definition at line 453 of file atl1e.h.

◆ REG_IDLE_STATUS

#define REG_IDLE_STATUS   0x1410

Definition at line 457 of file atl1e.h.

◆ IDLE_STATUS_RXMAC

#define IDLE_STATUS_RXMAC   1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */

Definition at line 458 of file atl1e.h.

◆ IDLE_STATUS_TXMAC

#define IDLE_STATUS_TXMAC   2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */

Definition at line 459 of file atl1e.h.

◆ IDLE_STATUS_RXQ

#define IDLE_STATUS_RXQ   4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */

Definition at line 460 of file atl1e.h.

◆ IDLE_STATUS_TXQ

#define IDLE_STATUS_TXQ   8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */

Definition at line 461 of file atl1e.h.

◆ IDLE_STATUS_DMAR

#define IDLE_STATUS_DMAR   0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */

Definition at line 462 of file atl1e.h.

◆ IDLE_STATUS_DMAW

#define IDLE_STATUS_DMAW   0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */

Definition at line 463 of file atl1e.h.

◆ IDLE_STATUS_SMB

#define IDLE_STATUS_SMB   0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */

Definition at line 464 of file atl1e.h.

◆ IDLE_STATUS_CMB

#define IDLE_STATUS_CMB   0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */

Definition at line 465 of file atl1e.h.

◆ REG_MDIO_CTRL

#define REG_MDIO_CTRL   0x1414

Definition at line 468 of file atl1e.h.

◆ MDIO_DATA_MASK

#define MDIO_DATA_MASK   0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */

Definition at line 469 of file atl1e.h.

◆ MDIO_DATA_SHIFT

#define MDIO_DATA_SHIFT   0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/

Definition at line 470 of file atl1e.h.

◆ MDIO_REG_ADDR_MASK

#define MDIO_REG_ADDR_MASK   0x1f /* MDIO register address */

Definition at line 471 of file atl1e.h.

◆ MDIO_REG_ADDR_SHIFT

#define MDIO_REG_ADDR_SHIFT   16

Definition at line 472 of file atl1e.h.

◆ MDIO_RW

#define MDIO_RW   0x200000 /* 1: read, 0: write */

Definition at line 473 of file atl1e.h.

◆ MDIO_SUP_PREAMBLE

#define MDIO_SUP_PREAMBLE   0x400000 /* Suppress preamble */

Definition at line 474 of file atl1e.h.

◆ MDIO_START

#define MDIO_START   0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/

Definition at line 475 of file atl1e.h.

◆ MDIO_CLK_SEL_SHIFT

#define MDIO_CLK_SEL_SHIFT   24

Definition at line 476 of file atl1e.h.

◆ MDIO_CLK_25_4

#define MDIO_CLK_25_4   0

Definition at line 477 of file atl1e.h.

◆ MDIO_CLK_25_6

#define MDIO_CLK_25_6   2

Definition at line 478 of file atl1e.h.

◆ MDIO_CLK_25_8

#define MDIO_CLK_25_8   3

Definition at line 479 of file atl1e.h.

◆ MDIO_CLK_25_10

#define MDIO_CLK_25_10   4

Definition at line 480 of file atl1e.h.

◆ MDIO_CLK_25_14

#define MDIO_CLK_25_14   5

Definition at line 481 of file atl1e.h.

◆ MDIO_CLK_25_20

#define MDIO_CLK_25_20   6

Definition at line 482 of file atl1e.h.

◆ MDIO_CLK_25_28

#define MDIO_CLK_25_28   7

Definition at line 483 of file atl1e.h.

◆ MDIO_BUSY

#define MDIO_BUSY   0x8000000

Definition at line 484 of file atl1e.h.

◆ MDIO_AP_EN

#define MDIO_AP_EN   0x10000000

Definition at line 485 of file atl1e.h.

◆ MDIO_WAIT_TIMES

#define MDIO_WAIT_TIMES   10

Definition at line 486 of file atl1e.h.

◆ REG_PHY_STATUS

#define REG_PHY_STATUS   0x1418

Definition at line 489 of file atl1e.h.

◆ PHY_STATUS_100M

#define PHY_STATUS_100M   0x20000

Definition at line 490 of file atl1e.h.

◆ PHY_STATUS_EMI_CA

#define PHY_STATUS_EMI_CA   0x40000

Definition at line 491 of file atl1e.h.

◆ REG_BIST0_CTRL

#define REG_BIST0_CTRL   0x141c

Definition at line 494 of file atl1e.h.

◆ BIST0_NOW

#define BIST0_NOW   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

Definition at line 495 of file atl1e.h.

◆ BIST0_SRAM_FAIL

#define BIST0_SRAM_FAIL   0x2 /* 1: The SRAM failure is un-repairable because it has address */

Definition at line 497 of file atl1e.h.

◆ BIST0_FUSE_FLAG

#define BIST0_FUSE_FLAG   0x4 /* 1: Indicating one cell has been fixed */

Definition at line 499 of file atl1e.h.

◆ REG_BIST1_CTRL

#define REG_BIST1_CTRL   0x1420

Definition at line 502 of file atl1e.h.

◆ BIST1_NOW

#define BIST1_NOW   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */

Definition at line 503 of file atl1e.h.

◆ BIST1_SRAM_FAIL

#define BIST1_SRAM_FAIL   0x2 /* 1: The SRAM failure is un-repairable because it has address */

Definition at line 505 of file atl1e.h.

◆ BIST1_FUSE_FLAG

#define BIST1_FUSE_FLAG   0x4

Definition at line 507 of file atl1e.h.

◆ REG_SERDES_LOCK

#define REG_SERDES_LOCK   0x1424

Definition at line 510 of file atl1e.h.

◆ SERDES_LOCK_DETECT

#define SERDES_LOCK_DETECT   1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */

Definition at line 511 of file atl1e.h.

◆ SERDES_LOCK_DETECT_EN

#define SERDES_LOCK_DETECT_EN   2 /* 1: Enable SerDes Lock detect function */

Definition at line 512 of file atl1e.h.

◆ REG_MAC_CTRL

#define REG_MAC_CTRL   0x1480

Definition at line 515 of file atl1e.h.

◆ MAC_CTRL_TX_EN

#define MAC_CTRL_TX_EN   1 /* 1: Transmit Enable */

Definition at line 516 of file atl1e.h.

◆ MAC_CTRL_RX_EN

#define MAC_CTRL_RX_EN   2 /* 1: Receive Enable */

Definition at line 517 of file atl1e.h.

◆ MAC_CTRL_TX_FLOW

#define MAC_CTRL_TX_FLOW   4 /* 1: Transmit Flow Control Enable */

Definition at line 518 of file atl1e.h.

◆ MAC_CTRL_RX_FLOW

#define MAC_CTRL_RX_FLOW   8 /* 1: Receive Flow Control Enable */

Definition at line 519 of file atl1e.h.

◆ MAC_CTRL_LOOPBACK

#define MAC_CTRL_LOOPBACK   0x10 /* 1: Loop back at G/MII Interface */

Definition at line 520 of file atl1e.h.

◆ MAC_CTRL_DUPLX

#define MAC_CTRL_DUPLX   0x20 /* 1: Full-duplex mode 0: Half-duplex mode */

Definition at line 521 of file atl1e.h.

◆ MAC_CTRL_ADD_CRC

#define MAC_CTRL_ADD_CRC   0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */

Definition at line 522 of file atl1e.h.

◆ MAC_CTRL_PAD

#define MAC_CTRL_PAD   0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */

Definition at line 523 of file atl1e.h.

◆ MAC_CTRL_LENCHK

#define MAC_CTRL_LENCHK   0x100 /* 1: Instruct MAC to check if length field matches the real packet length */

Definition at line 524 of file atl1e.h.

◆ MAC_CTRL_HUGE_EN

#define MAC_CTRL_HUGE_EN   0x200 /* 1: receive Jumbo frame enable */

Definition at line 525 of file atl1e.h.

◆ MAC_CTRL_PRMLEN_SHIFT

#define MAC_CTRL_PRMLEN_SHIFT   10 /* Preamble length */

Definition at line 526 of file atl1e.h.

◆ MAC_CTRL_PRMLEN_MASK

#define MAC_CTRL_PRMLEN_MASK   0xf

Definition at line 527 of file atl1e.h.

◆ MAC_CTRL_RMV_VLAN

#define MAC_CTRL_RMV_VLAN   0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */

Definition at line 528 of file atl1e.h.

◆ MAC_CTRL_PROMIS_EN

#define MAC_CTRL_PROMIS_EN   0x8000 /* 1: Promiscuous Mode Enable */

Definition at line 529 of file atl1e.h.

◆ MAC_CTRL_TX_PAUSE

#define MAC_CTRL_TX_PAUSE   0x10000 /* 1: transmit test pause */

Definition at line 530 of file atl1e.h.

◆ MAC_CTRL_SCNT

#define MAC_CTRL_SCNT   0x20000 /* 1: shortcut slot time counter */

Definition at line 531 of file atl1e.h.

◆ MAC_CTRL_SRST_TX

#define MAC_CTRL_SRST_TX   0x40000 /* 1: synchronized reset Transmit MAC module */

Definition at line 532 of file atl1e.h.

◆ MAC_CTRL_TX_SIMURST

#define MAC_CTRL_TX_SIMURST   0x80000 /* 1: transmit simulation reset */

Definition at line 533 of file atl1e.h.

◆ MAC_CTRL_SPEED_SHIFT

#define MAC_CTRL_SPEED_SHIFT   20 /* 10: gigabit 01:10M/100M */

Definition at line 534 of file atl1e.h.

◆ MAC_CTRL_SPEED_MASK

#define MAC_CTRL_SPEED_MASK   0x300000

Definition at line 535 of file atl1e.h.

◆ MAC_CTRL_SPEED_1000

#define MAC_CTRL_SPEED_1000   2

Definition at line 536 of file atl1e.h.

◆ MAC_CTRL_SPEED_10_100

#define MAC_CTRL_SPEED_10_100   1

Definition at line 537 of file atl1e.h.

◆ MAC_CTRL_DBG_TX_BKPRESURE

#define MAC_CTRL_DBG_TX_BKPRESURE   0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */

Definition at line 538 of file atl1e.h.

◆ MAC_CTRL_TX_HUGE

#define MAC_CTRL_TX_HUGE   0x800000 /* 1: transmit huge enable */

Definition at line 539 of file atl1e.h.

◆ MAC_CTRL_RX_CHKSUM_EN

#define MAC_CTRL_RX_CHKSUM_EN   0x1000000 /* 1: RX checksum enable */

Definition at line 540 of file atl1e.h.

◆ MAC_CTRL_MC_ALL_EN

#define MAC_CTRL_MC_ALL_EN   0x2000000 /* 1: upload all multicast frame without error to system */

Definition at line 541 of file atl1e.h.

◆ MAC_CTRL_BC_EN

#define MAC_CTRL_BC_EN   0x4000000 /* 1: upload all broadcast frame without error to system */

Definition at line 542 of file atl1e.h.

◆ MAC_CTRL_DBG

#define MAC_CTRL_DBG   0x8000000 /* 1: upload all received frame to system (Debug Mode) */

Definition at line 543 of file atl1e.h.

◆ REG_MAC_IPG_IFG

#define REG_MAC_IPG_IFG   0x1484

Definition at line 546 of file atl1e.h.

◆ MAC_IPG_IFG_IPGT_SHIFT

#define MAC_IPG_IFG_IPGT_SHIFT   0 /* Desired back to back inter-packet gap. The default is 96-bit time */

Definition at line 547 of file atl1e.h.

◆ MAC_IPG_IFG_IPGT_MASK

#define MAC_IPG_IFG_IPGT_MASK   0x7f

Definition at line 548 of file atl1e.h.

◆ MAC_IPG_IFG_MIFG_SHIFT

#define MAC_IPG_IFG_MIFG_SHIFT   8 /* Minimum number of IFG to enforce in between RX frames */

Definition at line 549 of file atl1e.h.

◆ MAC_IPG_IFG_MIFG_MASK

#define MAC_IPG_IFG_MIFG_MASK   0xff /* Frame gap below such IFP is dropped */

Definition at line 550 of file atl1e.h.

◆ MAC_IPG_IFG_IPGR1_SHIFT

#define MAC_IPG_IFG_IPGR1_SHIFT   16 /* 64bit Carrier-Sense window */

Definition at line 551 of file atl1e.h.

◆ MAC_IPG_IFG_IPGR1_MASK

#define MAC_IPG_IFG_IPGR1_MASK   0x7f

Definition at line 552 of file atl1e.h.

◆ MAC_IPG_IFG_IPGR2_SHIFT

#define MAC_IPG_IFG_IPGR2_SHIFT   24 /* 96-bit IPG window */

Definition at line 553 of file atl1e.h.

◆ MAC_IPG_IFG_IPGR2_MASK

#define MAC_IPG_IFG_IPGR2_MASK   0x7f

Definition at line 554 of file atl1e.h.

◆ REG_MAC_STA_ADDR

#define REG_MAC_STA_ADDR   0x1488

Definition at line 557 of file atl1e.h.

◆ REG_RX_HASH_TABLE

#define REG_RX_HASH_TABLE   0x1490

Definition at line 560 of file atl1e.h.

◆ REG_MAC_HALF_DUPLX_CTRL

#define REG_MAC_HALF_DUPLX_CTRL   0x1498

Definition at line 564 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_LCOL_SHIFT

#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0 /* Collision Window */

Definition at line 565 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_LCOL_MASK

#define MAC_HALF_DUPLX_CTRL_LCOL_MASK   0x3ff

Definition at line 566 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_RETRY_SHIFT

#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT   12 /* Retransmission maximum, afterwards the packet will be discarded */

Definition at line 567 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_RETRY_MASK

#define MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf

Definition at line 568 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_EXC_DEF_EN

#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */

Definition at line 569 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_NO_BACK_C

#define MAC_HALF_DUPLX_CTRL_NO_BACK_C   0x20000 /* 1: No back-off on collision, immediately start the retransmission */

Definition at line 570 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_NO_BACK_P

#define MAC_HALF_DUPLX_CTRL_NO_BACK_P   0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */

Definition at line 571 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_ABEBE

#define MAC_HALF_DUPLX_CTRL_ABEBE   0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */

Definition at line 572 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT

#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT   20 /* Maximum binary exponential number */

Definition at line 573 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_ABEBT_MASK

#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf

Definition at line 574 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT

#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT   24 /* IPG to start JAM for collision based flow control in half-duplex */

Definition at line 575 of file atl1e.h.

◆ MAC_HALF_DUPLX_CTRL_JAMIPG_MASK

#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK   0xf /* mode. In unit of 8-bit time */

Definition at line 576 of file atl1e.h.

◆ REG_MTU

#define REG_MTU   0x149c

Definition at line 579 of file atl1e.h.

◆ REG_WOL_CTRL

#define REG_WOL_CTRL   0x14a0

Definition at line 582 of file atl1e.h.

◆ WOL_PATTERN_EN

#define WOL_PATTERN_EN   0x00000001

Definition at line 583 of file atl1e.h.

◆ WOL_PATTERN_PME_EN

#define WOL_PATTERN_PME_EN   0x00000002

Definition at line 584 of file atl1e.h.

◆ WOL_MAGIC_EN

#define WOL_MAGIC_EN   0x00000004

Definition at line 585 of file atl1e.h.

◆ WOL_MAGIC_PME_EN

#define WOL_MAGIC_PME_EN   0x00000008

Definition at line 586 of file atl1e.h.

◆ WOL_LINK_CHG_EN

#define WOL_LINK_CHG_EN   0x00000010

Definition at line 587 of file atl1e.h.

◆ WOL_LINK_CHG_PME_EN

#define WOL_LINK_CHG_PME_EN   0x00000020

Definition at line 588 of file atl1e.h.

◆ WOL_PATTERN_ST

#define WOL_PATTERN_ST   0x00000100

Definition at line 589 of file atl1e.h.

◆ WOL_MAGIC_ST

#define WOL_MAGIC_ST   0x00000200

Definition at line 590 of file atl1e.h.

◆ WOL_LINKCHG_ST

#define WOL_LINKCHG_ST   0x00000400

Definition at line 591 of file atl1e.h.

◆ WOL_CLK_SWITCH_EN

#define WOL_CLK_SWITCH_EN   0x00008000

Definition at line 592 of file atl1e.h.

◆ WOL_PT0_EN

#define WOL_PT0_EN   0x00010000

Definition at line 593 of file atl1e.h.

◆ WOL_PT1_EN

#define WOL_PT1_EN   0x00020000

Definition at line 594 of file atl1e.h.

◆ WOL_PT2_EN

#define WOL_PT2_EN   0x00040000

Definition at line 595 of file atl1e.h.

◆ WOL_PT3_EN

#define WOL_PT3_EN   0x00080000

Definition at line 596 of file atl1e.h.

◆ WOL_PT4_EN

#define WOL_PT4_EN   0x00100000

Definition at line 597 of file atl1e.h.

◆ WOL_PT5_EN

#define WOL_PT5_EN   0x00200000

Definition at line 598 of file atl1e.h.

◆ WOL_PT6_EN

#define WOL_PT6_EN   0x00400000

Definition at line 599 of file atl1e.h.

◆ REG_WOL_PATTERN_LEN

#define REG_WOL_PATTERN_LEN   0x14a4

Definition at line 601 of file atl1e.h.

◆ WOL_PT_LEN_MASK

#define WOL_PT_LEN_MASK   0x7f

Definition at line 602 of file atl1e.h.

◆ WOL_PT0_LEN_SHIFT

#define WOL_PT0_LEN_SHIFT   0

Definition at line 603 of file atl1e.h.

◆ WOL_PT1_LEN_SHIFT

#define WOL_PT1_LEN_SHIFT   8

Definition at line 604 of file atl1e.h.

◆ WOL_PT2_LEN_SHIFT

#define WOL_PT2_LEN_SHIFT   16

Definition at line 605 of file atl1e.h.

◆ WOL_PT3_LEN_SHIFT

#define WOL_PT3_LEN_SHIFT   24

Definition at line 606 of file atl1e.h.

◆ WOL_PT4_LEN_SHIFT

#define WOL_PT4_LEN_SHIFT   0

Definition at line 607 of file atl1e.h.

◆ WOL_PT5_LEN_SHIFT

#define WOL_PT5_LEN_SHIFT   8

Definition at line 608 of file atl1e.h.

◆ WOL_PT6_LEN_SHIFT

#define WOL_PT6_LEN_SHIFT   16

Definition at line 609 of file atl1e.h.

◆ REG_SRAM_TRD_ADDR

#define REG_SRAM_TRD_ADDR   0x1518

Definition at line 612 of file atl1e.h.

◆ REG_SRAM_TRD_LEN

#define REG_SRAM_TRD_LEN   0x151C

Definition at line 613 of file atl1e.h.

◆ REG_SRAM_RXF_ADDR

#define REG_SRAM_RXF_ADDR   0x1520

Definition at line 614 of file atl1e.h.

◆ REG_SRAM_RXF_LEN

#define REG_SRAM_RXF_LEN   0x1524

Definition at line 615 of file atl1e.h.

◆ REG_SRAM_TXF_ADDR

#define REG_SRAM_TXF_ADDR   0x1528

Definition at line 616 of file atl1e.h.

◆ REG_SRAM_TXF_LEN

#define REG_SRAM_TXF_LEN   0x152C

Definition at line 617 of file atl1e.h.

◆ REG_SRAM_TCPH_ADDR

#define REG_SRAM_TCPH_ADDR   0x1530

Definition at line 618 of file atl1e.h.

◆ REG_SRAM_PKTH_ADDR

#define REG_SRAM_PKTH_ADDR   0x1532

Definition at line 619 of file atl1e.h.

◆ REG_LOAD_PTR

#define REG_LOAD_PTR   0x1534 /* Software sets this bit after the initialization of the head and tail */

Definition at line 622 of file atl1e.h.

◆ REG_RXF3_BASE_ADDR_HI

#define REG_RXF3_BASE_ADDR_HI   0x153C

Definition at line 632 of file atl1e.h.

◆ REG_DESC_BASE_ADDR_HI

#define REG_DESC_BASE_ADDR_HI   0x1540

Definition at line 633 of file atl1e.h.

◆ REG_RXF0_BASE_ADDR_HI

#define REG_RXF0_BASE_ADDR_HI   0x1540 /* share with DESC BASE ADDR HI */

Definition at line 634 of file atl1e.h.

◆ REG_HOST_RXF0_PAGE0_LO

#define REG_HOST_RXF0_PAGE0_LO   0x1544

Definition at line 635 of file atl1e.h.

◆ REG_HOST_RXF0_PAGE1_LO

#define REG_HOST_RXF0_PAGE1_LO   0x1548

Definition at line 636 of file atl1e.h.

◆ REG_TPD_BASE_ADDR_LO

#define REG_TPD_BASE_ADDR_LO   0x154C

Definition at line 637 of file atl1e.h.

◆ REG_RXF1_BASE_ADDR_HI

#define REG_RXF1_BASE_ADDR_HI   0x1550

Definition at line 638 of file atl1e.h.

◆ REG_RXF2_BASE_ADDR_HI

#define REG_RXF2_BASE_ADDR_HI   0x1554

Definition at line 639 of file atl1e.h.

◆ REG_HOST_RXFPAGE_SIZE

#define REG_HOST_RXFPAGE_SIZE   0x1558

Definition at line 640 of file atl1e.h.

◆ REG_TPD_RING_SIZE

#define REG_TPD_RING_SIZE   0x155C

Definition at line 641 of file atl1e.h.

◆ REG_RSS_KEY0

#define REG_RSS_KEY0   0x14B0

Definition at line 643 of file atl1e.h.

◆ REG_RSS_KEY1

#define REG_RSS_KEY1   0x14B4

Definition at line 644 of file atl1e.h.

◆ REG_RSS_KEY2

#define REG_RSS_KEY2   0x14B8

Definition at line 645 of file atl1e.h.

◆ REG_RSS_KEY3

#define REG_RSS_KEY3   0x14BC

Definition at line 646 of file atl1e.h.

◆ REG_RSS_KEY4

#define REG_RSS_KEY4   0x14C0

Definition at line 647 of file atl1e.h.

◆ REG_RSS_KEY5

#define REG_RSS_KEY5   0x14C4

Definition at line 648 of file atl1e.h.

◆ REG_RSS_KEY6

#define REG_RSS_KEY6   0x14C8

Definition at line 649 of file atl1e.h.

◆ REG_RSS_KEY7

#define REG_RSS_KEY7   0x14CC

Definition at line 650 of file atl1e.h.

◆ REG_RSS_KEY8

#define REG_RSS_KEY8   0x14D0

Definition at line 651 of file atl1e.h.

◆ REG_RSS_KEY9

#define REG_RSS_KEY9   0x14D4

Definition at line 652 of file atl1e.h.

◆ REG_IDT_TABLE4

#define REG_IDT_TABLE4   0x14E0

Definition at line 653 of file atl1e.h.

◆ REG_IDT_TABLE5

#define REG_IDT_TABLE5   0x14E4

Definition at line 654 of file atl1e.h.

◆ REG_IDT_TABLE6

#define REG_IDT_TABLE6   0x14E8

Definition at line 655 of file atl1e.h.

◆ REG_IDT_TABLE7

#define REG_IDT_TABLE7   0x14EC

Definition at line 656 of file atl1e.h.

◆ REG_IDT_TABLE0

#define REG_IDT_TABLE0   0x1560

Definition at line 657 of file atl1e.h.

◆ REG_IDT_TABLE1

#define REG_IDT_TABLE1   0x1564

Definition at line 658 of file atl1e.h.

◆ REG_IDT_TABLE2

#define REG_IDT_TABLE2   0x1568

Definition at line 659 of file atl1e.h.

◆ REG_IDT_TABLE3

#define REG_IDT_TABLE3   0x156C

Definition at line 660 of file atl1e.h.

◆ REG_IDT_TABLE

#define REG_IDT_TABLE   REG_IDT_TABLE0

Definition at line 661 of file atl1e.h.

◆ REG_RSS_HASH_VALUE

#define REG_RSS_HASH_VALUE   0x1570

Definition at line 662 of file atl1e.h.

◆ REG_RSS_HASH_FLAG

#define REG_RSS_HASH_FLAG   0x1574

Definition at line 663 of file atl1e.h.

◆ REG_BASE_CPU_NUMBER

#define REG_BASE_CPU_NUMBER   0x157C

Definition at line 664 of file atl1e.h.

◆ REG_TXQ_CTRL

#define REG_TXQ_CTRL   0x1580

Definition at line 668 of file atl1e.h.

◆ TXQ_CTRL_NUM_TPD_BURST_MASK

#define TXQ_CTRL_NUM_TPD_BURST_MASK   0xF

Definition at line 669 of file atl1e.h.

◆ TXQ_CTRL_NUM_TPD_BURST_SHIFT

#define TXQ_CTRL_NUM_TPD_BURST_SHIFT   0

Definition at line 670 of file atl1e.h.

◆ TXQ_CTRL_EN

#define TXQ_CTRL_EN   0x20 /* 1: Enable TXQ */

Definition at line 671 of file atl1e.h.

◆ TXQ_CTRL_ENH_MODE

#define TXQ_CTRL_ENH_MODE   0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */

Definition at line 672 of file atl1e.h.

◆ TXQ_CTRL_TXF_BURST_NUM_SHIFT

#define TXQ_CTRL_TXF_BURST_NUM_SHIFT   16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */

Definition at line 673 of file atl1e.h.

◆ TXQ_CTRL_TXF_BURST_NUM_MASK

#define TXQ_CTRL_TXF_BURST_NUM_MASK   0xffff

Definition at line 674 of file atl1e.h.

◆ REG_TX_EARLY_TH

#define REG_TX_EARLY_TH   0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */

Definition at line 677 of file atl1e.h.

◆ TX_TX_EARLY_TH_MASK

#define TX_TX_EARLY_TH_MASK   0x7ff

Definition at line 679 of file atl1e.h.

◆ TX_TX_EARLY_TH_SHIFT

#define TX_TX_EARLY_TH_SHIFT   0

Definition at line 680 of file atl1e.h.

◆ REG_RXQ_CTRL

#define REG_RXQ_CTRL   0x15A0

Definition at line 684 of file atl1e.h.

◆ RXQ_CTRL_PBA_ALIGN_32

#define RXQ_CTRL_PBA_ALIGN_32   0 /* rx-packet alignment */

Definition at line 685 of file atl1e.h.

◆ RXQ_CTRL_PBA_ALIGN_64

#define RXQ_CTRL_PBA_ALIGN_64   1

Definition at line 686 of file atl1e.h.

◆ RXQ_CTRL_PBA_ALIGN_128

#define RXQ_CTRL_PBA_ALIGN_128   2

Definition at line 687 of file atl1e.h.

◆ RXQ_CTRL_PBA_ALIGN_256

#define RXQ_CTRL_PBA_ALIGN_256   3

Definition at line 688 of file atl1e.h.

◆ RXQ_CTRL_Q1_EN

#define RXQ_CTRL_Q1_EN   0x10

Definition at line 689 of file atl1e.h.

◆ RXQ_CTRL_Q2_EN

#define RXQ_CTRL_Q2_EN   0x20

Definition at line 690 of file atl1e.h.

◆ RXQ_CTRL_Q3_EN

#define RXQ_CTRL_Q3_EN   0x40

Definition at line 691 of file atl1e.h.

◆ RXQ_CTRL_IPV6_XSUM_VERIFY_EN

#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN   0x80

Definition at line 692 of file atl1e.h.

◆ RXQ_CTRL_HASH_TLEN_SHIFT

#define RXQ_CTRL_HASH_TLEN_SHIFT   8

Definition at line 693 of file atl1e.h.

◆ RXQ_CTRL_HASH_TLEN_MASK

#define RXQ_CTRL_HASH_TLEN_MASK   0xFF

Definition at line 694 of file atl1e.h.

◆ RXQ_CTRL_HASH_TYPE_IPV4

#define RXQ_CTRL_HASH_TYPE_IPV4   0x10000

Definition at line 695 of file atl1e.h.

◆ RXQ_CTRL_HASH_TYPE_IPV4_TCP

#define RXQ_CTRL_HASH_TYPE_IPV4_TCP   0x20000

Definition at line 696 of file atl1e.h.

◆ RXQ_CTRL_HASH_TYPE_IPV6

#define RXQ_CTRL_HASH_TYPE_IPV6   0x40000

Definition at line 697 of file atl1e.h.

◆ RXQ_CTRL_HASH_TYPE_IPV6_TCP

#define RXQ_CTRL_HASH_TYPE_IPV6_TCP   0x80000

Definition at line 698 of file atl1e.h.

◆ RXQ_CTRL_RSS_MODE_DISABLE

#define RXQ_CTRL_RSS_MODE_DISABLE   0

Definition at line 699 of file atl1e.h.

◆ RXQ_CTRL_RSS_MODE_SQSINT

#define RXQ_CTRL_RSS_MODE_SQSINT   0x4000000

Definition at line 700 of file atl1e.h.

◆ RXQ_CTRL_RSS_MODE_MQUESINT

#define RXQ_CTRL_RSS_MODE_MQUESINT   0x8000000

Definition at line 701 of file atl1e.h.

◆ RXQ_CTRL_RSS_MODE_MQUEMINT

#define RXQ_CTRL_RSS_MODE_MQUEMINT   0xC000000

Definition at line 702 of file atl1e.h.

◆ RXQ_CTRL_NIP_QUEUE_SEL_TBL

#define RXQ_CTRL_NIP_QUEUE_SEL_TBL   0x10000000

Definition at line 703 of file atl1e.h.

◆ RXQ_CTRL_HASH_ENABLE

#define RXQ_CTRL_HASH_ENABLE   0x20000000

Definition at line 704 of file atl1e.h.

◆ RXQ_CTRL_CUT_THRU_EN

#define RXQ_CTRL_CUT_THRU_EN   0x40000000

Definition at line 705 of file atl1e.h.

◆ RXQ_CTRL_EN

#define RXQ_CTRL_EN   0x80000000

Definition at line 706 of file atl1e.h.

◆ REG_RXQ_JMBOSZ_RRDTIM

#define REG_RXQ_JMBOSZ_RRDTIM   0x15A4

Definition at line 709 of file atl1e.h.

◆ RXQ_JMBOSZ_TH_MASK

#define RXQ_JMBOSZ_TH_MASK   0x7ff

Definition at line 715 of file atl1e.h.

◆ RXQ_JMBOSZ_TH_SHIFT

#define RXQ_JMBOSZ_TH_SHIFT   0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/

Definition at line 716 of file atl1e.h.

◆ RXQ_JMBO_LKAH_MASK

#define RXQ_JMBO_LKAH_MASK   0xf

Definition at line 717 of file atl1e.h.

◆ RXQ_JMBO_LKAH_SHIFT

#define RXQ_JMBO_LKAH_SHIFT   11

Definition at line 718 of file atl1e.h.

◆ REG_RXQ_RXF_PAUSE_THRESH

#define REG_RXQ_RXF_PAUSE_THRESH   0x15A8

Definition at line 721 of file atl1e.h.

◆ RXQ_RXF_PAUSE_TH_HI_SHIFT

#define RXQ_RXF_PAUSE_TH_HI_SHIFT   0

Definition at line 722 of file atl1e.h.

◆ RXQ_RXF_PAUSE_TH_HI_MASK

#define RXQ_RXF_PAUSE_TH_HI_MASK   0xfff

Definition at line 723 of file atl1e.h.

◆ RXQ_RXF_PAUSE_TH_LO_SHIFT

#define RXQ_RXF_PAUSE_TH_LO_SHIFT   16

Definition at line 724 of file atl1e.h.

◆ RXQ_RXF_PAUSE_TH_LO_MASK

#define RXQ_RXF_PAUSE_TH_LO_MASK   0xfff

Definition at line 725 of file atl1e.h.

◆ REG_DMA_CTRL

#define REG_DMA_CTRL   0x15C0

Definition at line 729 of file atl1e.h.

◆ DMA_CTRL_DMAR_IN_ORDER

#define DMA_CTRL_DMAR_IN_ORDER   0x1

Definition at line 730 of file atl1e.h.

◆ DMA_CTRL_DMAR_ENH_ORDER

#define DMA_CTRL_DMAR_ENH_ORDER   0x2

Definition at line 731 of file atl1e.h.

◆ DMA_CTRL_DMAR_OUT_ORDER

#define DMA_CTRL_DMAR_OUT_ORDER   0x4

Definition at line 732 of file atl1e.h.

◆ DMA_CTRL_RCB_VALUE

#define DMA_CTRL_RCB_VALUE   0x8

Definition at line 733 of file atl1e.h.

◆ DMA_CTRL_DMAR_BURST_LEN_SHIFT

#define DMA_CTRL_DMAR_BURST_LEN_SHIFT   4

Definition at line 734 of file atl1e.h.

◆ DMA_CTRL_DMAR_BURST_LEN_MASK

#define DMA_CTRL_DMAR_BURST_LEN_MASK   7

Definition at line 735 of file atl1e.h.

◆ DMA_CTRL_DMAW_BURST_LEN_SHIFT

#define DMA_CTRL_DMAW_BURST_LEN_SHIFT   7

Definition at line 736 of file atl1e.h.

◆ DMA_CTRL_DMAW_BURST_LEN_MASK

#define DMA_CTRL_DMAW_BURST_LEN_MASK   7

Definition at line 737 of file atl1e.h.

◆ DMA_CTRL_DMAR_REQ_PRI

#define DMA_CTRL_DMAR_REQ_PRI   0x400

Definition at line 738 of file atl1e.h.

◆ DMA_CTRL_DMAR_DLY_CNT_MASK

#define DMA_CTRL_DMAR_DLY_CNT_MASK   0x1F

Definition at line 739 of file atl1e.h.

◆ DMA_CTRL_DMAR_DLY_CNT_SHIFT

#define DMA_CTRL_DMAR_DLY_CNT_SHIFT   11

Definition at line 740 of file atl1e.h.

◆ DMA_CTRL_DMAW_DLY_CNT_MASK

#define DMA_CTRL_DMAW_DLY_CNT_MASK   0xF

Definition at line 741 of file atl1e.h.

◆ DMA_CTRL_DMAW_DLY_CNT_SHIFT

#define DMA_CTRL_DMAW_DLY_CNT_SHIFT   16

Definition at line 742 of file atl1e.h.

◆ DMA_CTRL_TXCMB_EN

#define DMA_CTRL_TXCMB_EN   0x100000

Definition at line 743 of file atl1e.h.

◆ DMA_CTRL_RXCMB_EN

#define DMA_CTRL_RXCMB_EN   0x200000

Definition at line 744 of file atl1e.h.

◆ REG_SMB_STAT_TIMER

#define REG_SMB_STAT_TIMER   0x15C4

Definition at line 748 of file atl1e.h.

◆ REG_TRIG_RRD_THRESH

#define REG_TRIG_RRD_THRESH   0x15CA

Definition at line 749 of file atl1e.h.

◆ REG_TRIG_TPD_THRESH

#define REG_TRIG_TPD_THRESH   0x15C8

Definition at line 750 of file atl1e.h.

◆ REG_TRIG_TXTIMER

#define REG_TRIG_TXTIMER   0x15CC

Definition at line 751 of file atl1e.h.

◆ REG_TRIG_RXTIMER

#define REG_TRIG_RXTIMER   0x15CE

Definition at line 752 of file atl1e.h.

◆ REG_HOST_RXF1_PAGE0_LO

#define REG_HOST_RXF1_PAGE0_LO   0x15D0

Definition at line 755 of file atl1e.h.

◆ REG_HOST_RXF1_PAGE1_LO

#define REG_HOST_RXF1_PAGE1_LO   0x15D4

Definition at line 756 of file atl1e.h.

◆ REG_HOST_RXF2_PAGE0_LO

#define REG_HOST_RXF2_PAGE0_LO   0x15D8

Definition at line 757 of file atl1e.h.

◆ REG_HOST_RXF2_PAGE1_LO

#define REG_HOST_RXF2_PAGE1_LO   0x15DC

Definition at line 758 of file atl1e.h.

◆ REG_HOST_RXF3_PAGE0_LO

#define REG_HOST_RXF3_PAGE0_LO   0x15E0

Definition at line 759 of file atl1e.h.

◆ REG_HOST_RXF3_PAGE1_LO

#define REG_HOST_RXF3_PAGE1_LO   0x15E4

Definition at line 760 of file atl1e.h.

◆ REG_MB_RXF1_RADDR

#define REG_MB_RXF1_RADDR   0x15B4

Definition at line 763 of file atl1e.h.

◆ REG_MB_RXF2_RADDR

#define REG_MB_RXF2_RADDR   0x15B8

Definition at line 764 of file atl1e.h.

◆ REG_MB_RXF3_RADDR

#define REG_MB_RXF3_RADDR   0x15BC

Definition at line 765 of file atl1e.h.

◆ REG_MB_TPD_PROD_IDX

#define REG_MB_TPD_PROD_IDX   0x15F0

Definition at line 766 of file atl1e.h.

◆ REG_HOST_RXF0_PAGE0_VLD

#define REG_HOST_RXF0_PAGE0_VLD   0x15F4

Definition at line 769 of file atl1e.h.

◆ HOST_RXF_VALID

#define HOST_RXF_VALID   1

Definition at line 770 of file atl1e.h.

◆ HOST_RXF_PAGENO_SHIFT

#define HOST_RXF_PAGENO_SHIFT   1

Definition at line 771 of file atl1e.h.

◆ HOST_RXF_PAGENO_MASK

#define HOST_RXF_PAGENO_MASK   0x7F

Definition at line 772 of file atl1e.h.

◆ REG_HOST_RXF0_PAGE1_VLD

#define REG_HOST_RXF0_PAGE1_VLD   0x15F5

Definition at line 773 of file atl1e.h.

◆ REG_HOST_RXF1_PAGE0_VLD

#define REG_HOST_RXF1_PAGE0_VLD   0x15F6

Definition at line 774 of file atl1e.h.

◆ REG_HOST_RXF1_PAGE1_VLD

#define REG_HOST_RXF1_PAGE1_VLD   0x15F7

Definition at line 775 of file atl1e.h.

◆ REG_HOST_RXF2_PAGE0_VLD

#define REG_HOST_RXF2_PAGE0_VLD   0x15F8

Definition at line 776 of file atl1e.h.

◆ REG_HOST_RXF2_PAGE1_VLD

#define REG_HOST_RXF2_PAGE1_VLD   0x15F9

Definition at line 777 of file atl1e.h.

◆ REG_HOST_RXF3_PAGE0_VLD

#define REG_HOST_RXF3_PAGE0_VLD   0x15FA

Definition at line 778 of file atl1e.h.

◆ REG_HOST_RXF3_PAGE1_VLD

#define REG_HOST_RXF3_PAGE1_VLD   0x15FB

Definition at line 779 of file atl1e.h.

◆ REG_ISR

#define REG_ISR   0x1600

Definition at line 782 of file atl1e.h.

◆ ISR_SMB

#define ISR_SMB   1

Definition at line 783 of file atl1e.h.

◆ ISR_TIMER

#define ISR_TIMER   2 /* Interrupt when Timer is counted down to zero */

Definition at line 784 of file atl1e.h.

◆ ISR_MANUAL

#define ISR_MANUAL   4

Definition at line 789 of file atl1e.h.

◆ ISR_HW_RXF_OV

#define ISR_HW_RXF_OV   8 /* RXF overflow interrupt */

Definition at line 790 of file atl1e.h.

◆ ISR_HOST_RXF0_OV

#define ISR_HOST_RXF0_OV   0x10

Definition at line 791 of file atl1e.h.

◆ ISR_HOST_RXF1_OV

#define ISR_HOST_RXF1_OV   0x20

Definition at line 792 of file atl1e.h.

◆ ISR_HOST_RXF2_OV

#define ISR_HOST_RXF2_OV   0x40

Definition at line 793 of file atl1e.h.

◆ ISR_HOST_RXF3_OV

#define ISR_HOST_RXF3_OV   0x80

Definition at line 794 of file atl1e.h.

◆ ISR_TXF_UN

#define ISR_TXF_UN   0x100

Definition at line 795 of file atl1e.h.

◆ ISR_RX0_PAGE_FULL

#define ISR_RX0_PAGE_FULL   0x200

Definition at line 796 of file atl1e.h.

◆ ISR_DMAR_TO_RST

#define ISR_DMAR_TO_RST   0x400

Definition at line 797 of file atl1e.h.

◆ ISR_DMAW_TO_RST

#define ISR_DMAW_TO_RST   0x800

Definition at line 798 of file atl1e.h.

◆ ISR_GPHY

#define ISR_GPHY   0x1000

Definition at line 799 of file atl1e.h.

◆ ISR_TX_CREDIT

#define ISR_TX_CREDIT   0x2000

Definition at line 800 of file atl1e.h.

◆ ISR_GPHY_LPW

#define ISR_GPHY_LPW   0x4000 /* GPHY low power state interrupt */

Definition at line 801 of file atl1e.h.

◆ ISR_RX_PKT

#define ISR_RX_PKT   0x10000 /* One packet received, triggered by RFD */

Definition at line 802 of file atl1e.h.

◆ ISR_TX_PKT

#define ISR_TX_PKT   0x20000 /* One packet transmitted, triggered by TPD */

Definition at line 803 of file atl1e.h.

◆ ISR_TX_DMA

#define ISR_TX_DMA   0x40000

Definition at line 804 of file atl1e.h.

◆ ISR_RX_PKT_1

#define ISR_RX_PKT_1   0x80000

Definition at line 805 of file atl1e.h.

◆ ISR_RX_PKT_2

#define ISR_RX_PKT_2   0x100000

Definition at line 806 of file atl1e.h.

◆ ISR_RX_PKT_3

#define ISR_RX_PKT_3   0x200000

Definition at line 807 of file atl1e.h.

◆ ISR_MAC_RX

#define ISR_MAC_RX   0x400000

Definition at line 808 of file atl1e.h.

◆ ISR_MAC_TX

#define ISR_MAC_TX   0x800000

Definition at line 809 of file atl1e.h.

◆ ISR_UR_DETECTED

#define ISR_UR_DETECTED   0x1000000

Definition at line 810 of file atl1e.h.

◆ ISR_FERR_DETECTED

#define ISR_FERR_DETECTED   0x2000000

Definition at line 811 of file atl1e.h.

◆ ISR_NFERR_DETECTED

#define ISR_NFERR_DETECTED   0x4000000

Definition at line 812 of file atl1e.h.

◆ ISR_CERR_DETECTED

#define ISR_CERR_DETECTED   0x8000000

Definition at line 813 of file atl1e.h.

◆ ISR_PHY_LINKDOWN

#define ISR_PHY_LINKDOWN   0x10000000

Definition at line 814 of file atl1e.h.

◆ ISR_DIS_INT

#define ISR_DIS_INT   0x80000000

Definition at line 815 of file atl1e.h.

◆ REG_IMR

#define REG_IMR   0x1604

Definition at line 819 of file atl1e.h.

◆ IMR_NORMAL_MASK

#define IMR_NORMAL_MASK
Value:
(\
ISR_SMB |\
ISR_TXF_UN |\
ISR_HW_RXF_OV |\
ISR_HOST_RXF0_OV|\
ISR_MANUAL |\
ISR_GPHY |\
ISR_GPHY_LPW |\
ISR_DMAR_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_PHY_LINKDOWN|\
ISR_RX_PKT |\
ISR_TX_PKT)

Definition at line 822 of file atl1e.h.

◆ ISR_TX_EVENT

#define ISR_TX_EVENT   (ISR_TXF_UN | ISR_TX_PKT)

Definition at line 836 of file atl1e.h.

◆ ISR_RX_EVENT

#define ISR_RX_EVENT   (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)

Definition at line 837 of file atl1e.h.

◆ REG_MAC_RX_STATUS_BIN

#define REG_MAC_RX_STATUS_BIN   0x1700

Definition at line 839 of file atl1e.h.

◆ REG_MAC_RX_STATUS_END

#define REG_MAC_RX_STATUS_END   0x175c

Definition at line 840 of file atl1e.h.

◆ REG_MAC_TX_STATUS_BIN

#define REG_MAC_TX_STATUS_BIN   0x1760

Definition at line 841 of file atl1e.h.

◆ REG_MAC_TX_STATUS_END

#define REG_MAC_TX_STATUS_END   0x17c0

Definition at line 842 of file atl1e.h.

◆ REG_HOST_RXF0_PAGEOFF

#define REG_HOST_RXF0_PAGEOFF   0x1800

Definition at line 845 of file atl1e.h.

◆ REG_TPD_CONS_IDX

#define REG_TPD_CONS_IDX   0x1804

Definition at line 846 of file atl1e.h.

◆ REG_HOST_RXF1_PAGEOFF

#define REG_HOST_RXF1_PAGEOFF   0x1808

Definition at line 847 of file atl1e.h.

◆ REG_HOST_RXF2_PAGEOFF

#define REG_HOST_RXF2_PAGEOFF   0x180C

Definition at line 848 of file atl1e.h.

◆ REG_HOST_RXF3_PAGEOFF

#define REG_HOST_RXF3_PAGEOFF   0x1810

Definition at line 849 of file atl1e.h.

◆ REG_HOST_RXF0_MB0_LO

#define REG_HOST_RXF0_MB0_LO   0x1820

Definition at line 852 of file atl1e.h.

◆ REG_HOST_RXF0_MB1_LO

#define REG_HOST_RXF0_MB1_LO   0x1824

Definition at line 853 of file atl1e.h.

◆ REG_HOST_RXF1_MB0_LO

#define REG_HOST_RXF1_MB0_LO   0x1828

Definition at line 854 of file atl1e.h.

◆ REG_HOST_RXF1_MB1_LO

#define REG_HOST_RXF1_MB1_LO   0x182C

Definition at line 855 of file atl1e.h.

◆ REG_HOST_RXF2_MB0_LO

#define REG_HOST_RXF2_MB0_LO   0x1830

Definition at line 856 of file atl1e.h.

◆ REG_HOST_RXF2_MB1_LO

#define REG_HOST_RXF2_MB1_LO   0x1834

Definition at line 857 of file atl1e.h.

◆ REG_HOST_RXF3_MB0_LO

#define REG_HOST_RXF3_MB0_LO   0x1838

Definition at line 858 of file atl1e.h.

◆ REG_HOST_RXF3_MB1_LO

#define REG_HOST_RXF3_MB1_LO   0x183C

Definition at line 859 of file atl1e.h.

◆ REG_HOST_TX_CMB_LO

#define REG_HOST_TX_CMB_LO   0x1840

Definition at line 862 of file atl1e.h.

◆ REG_HOST_SMB_ADDR_LO

#define REG_HOST_SMB_ADDR_LO   0x1844

Definition at line 863 of file atl1e.h.

◆ REG_DEBUG_DATA0

#define REG_DEBUG_DATA0   0x1900

Definition at line 866 of file atl1e.h.

◆ REG_DEBUG_DATA1

#define REG_DEBUG_DATA1   0x1904

Definition at line 867 of file atl1e.h.

◆ MII_BMCR

#define MII_BMCR   0x00

Definition at line 871 of file atl1e.h.

◆ MII_BMSR

#define MII_BMSR   0x01

Definition at line 872 of file atl1e.h.

◆ MII_PHYSID1

#define MII_PHYSID1   0x02

Definition at line 873 of file atl1e.h.

◆ MII_PHYSID2

#define MII_PHYSID2   0x03

Definition at line 874 of file atl1e.h.

◆ MII_ADVERTISE

#define MII_ADVERTISE   0x04

Definition at line 875 of file atl1e.h.

◆ MII_LPA

#define MII_LPA   0x05

Definition at line 876 of file atl1e.h.

◆ MII_EXPANSION

#define MII_EXPANSION   0x06

Definition at line 877 of file atl1e.h.

◆ MII_AT001_CR

#define MII_AT001_CR   0x09

Definition at line 878 of file atl1e.h.

◆ MII_AT001_SR

#define MII_AT001_SR   0x0A

Definition at line 879 of file atl1e.h.

◆ MII_AT001_ESR

#define MII_AT001_ESR   0x0F

Definition at line 880 of file atl1e.h.

◆ MII_AT001_PSCR

#define MII_AT001_PSCR   0x10

Definition at line 881 of file atl1e.h.

◆ MII_AT001_PSSR

#define MII_AT001_PSSR   0x11

Definition at line 882 of file atl1e.h.

◆ MII_INT_CTRL

#define MII_INT_CTRL   0x12

Definition at line 883 of file atl1e.h.

◆ MII_INT_STATUS

#define MII_INT_STATUS   0x13

Definition at line 884 of file atl1e.h.

◆ MII_SMARTSPEED

#define MII_SMARTSPEED   0x14

Definition at line 885 of file atl1e.h.

◆ MII_RERRCOUNTER

#define MII_RERRCOUNTER   0x15

Definition at line 886 of file atl1e.h.

◆ MII_SREVISION

#define MII_SREVISION   0x16

Definition at line 887 of file atl1e.h.

◆ MII_RESV1

#define MII_RESV1   0x17

Definition at line 888 of file atl1e.h.

◆ MII_LBRERROR

#define MII_LBRERROR   0x18

Definition at line 889 of file atl1e.h.

◆ MII_PHYADDR

#define MII_PHYADDR   0x19

Definition at line 890 of file atl1e.h.

◆ MII_RESV2

#define MII_RESV2   0x1a

Definition at line 891 of file atl1e.h.

◆ MII_TPISTATUS

#define MII_TPISTATUS   0x1b

Definition at line 892 of file atl1e.h.

◆ MII_NCONFIG

#define MII_NCONFIG   0x1c

Definition at line 893 of file atl1e.h.

◆ MII_DBG_ADDR

#define MII_DBG_ADDR   0x1D

Definition at line 895 of file atl1e.h.

◆ MII_DBG_DATA

#define MII_DBG_DATA   0x1E

Definition at line 896 of file atl1e.h.

◆ MII_CR_SPEED_SELECT_MSB

#define MII_CR_SPEED_SELECT_MSB   0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */

Definition at line 900 of file atl1e.h.

◆ MII_CR_COLL_TEST_ENABLE

#define MII_CR_COLL_TEST_ENABLE   0x0080 /* Collision test enable */

Definition at line 901 of file atl1e.h.

◆ MII_CR_FULL_DUPLEX

#define MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */

Definition at line 902 of file atl1e.h.

◆ MII_CR_RESTART_AUTO_NEG

#define MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */

Definition at line 903 of file atl1e.h.

◆ MII_CR_ISOLATE

#define MII_CR_ISOLATE   0x0400 /* Isolate PHY from MII */

Definition at line 904 of file atl1e.h.

◆ MII_CR_POWER_DOWN

#define MII_CR_POWER_DOWN   0x0800 /* Power down */

Definition at line 905 of file atl1e.h.

◆ MII_CR_AUTO_NEG_EN

#define MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */

Definition at line 906 of file atl1e.h.

◆ MII_CR_SPEED_SELECT_LSB

#define MII_CR_SPEED_SELECT_LSB   0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */

Definition at line 907 of file atl1e.h.

◆ MII_CR_LOOPBACK

#define MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */

Definition at line 908 of file atl1e.h.

◆ MII_CR_RESET

#define MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */

Definition at line 909 of file atl1e.h.

◆ MII_CR_SPEED_MASK

#define MII_CR_SPEED_MASK   0x2040

Definition at line 910 of file atl1e.h.

◆ MII_CR_SPEED_1000

#define MII_CR_SPEED_1000   0x0040

Definition at line 911 of file atl1e.h.

◆ MII_CR_SPEED_100

#define MII_CR_SPEED_100   0x2000

Definition at line 912 of file atl1e.h.

◆ MII_CR_SPEED_10

#define MII_CR_SPEED_10   0x0000

Definition at line 913 of file atl1e.h.

◆ MII_SR_EXTENDED_CAPS

#define MII_SR_EXTENDED_CAPS   0x0001 /* Extended register capabilities */

Definition at line 917 of file atl1e.h.

◆ MII_SR_JABBER_DETECT

#define MII_SR_JABBER_DETECT   0x0002 /* Jabber Detected */

Definition at line 918 of file atl1e.h.

◆ MII_SR_LINK_STATUS

#define MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */

Definition at line 919 of file atl1e.h.

◆ MII_SR_AUTONEG_CAPS

#define MII_SR_AUTONEG_CAPS   0x0008 /* Auto Neg Capable */

Definition at line 920 of file atl1e.h.

◆ MII_SR_REMOTE_FAULT

#define MII_SR_REMOTE_FAULT   0x0010 /* Remote Fault Detect */

Definition at line 921 of file atl1e.h.

◆ MII_SR_AUTONEG_COMPLETE

#define MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */

Definition at line 922 of file atl1e.h.

◆ MII_SR_PREAMBLE_SUPPRESS

#define MII_SR_PREAMBLE_SUPPRESS   0x0040 /* Preamble may be suppressed */

Definition at line 923 of file atl1e.h.

◆ MII_SR_EXTENDED_STATUS

#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */

Definition at line 924 of file atl1e.h.

◆ MII_SR_100T2_HD_CAPS

#define MII_SR_100T2_HD_CAPS   0x0200 /* 100T2 Half Duplex Capable */

Definition at line 925 of file atl1e.h.

◆ MII_SR_100T2_FD_CAPS

#define MII_SR_100T2_FD_CAPS   0x0400 /* 100T2 Full Duplex Capable */

Definition at line 926 of file atl1e.h.

◆ MII_SR_10T_HD_CAPS

#define MII_SR_10T_HD_CAPS   0x0800 /* 10T Half Duplex Capable */

Definition at line 927 of file atl1e.h.

◆ MII_SR_10T_FD_CAPS

#define MII_SR_10T_FD_CAPS   0x1000 /* 10T Full Duplex Capable */

Definition at line 928 of file atl1e.h.

◆ MII_SR_100X_HD_CAPS

#define MII_SR_100X_HD_CAPS   0x2000 /* 100X Half Duplex Capable */

Definition at line 929 of file atl1e.h.

◆ MII_SR_100X_FD_CAPS

#define MII_SR_100X_FD_CAPS   0x4000 /* 100X Full Duplex Capable */

Definition at line 930 of file atl1e.h.

◆ MII_SR_100T4_CAPS

#define MII_SR_100T4_CAPS   0x8000 /* 100T4 Capable */

Definition at line 931 of file atl1e.h.

◆ MII_LPA_SLCT

#define MII_LPA_SLCT   0x001f /* Same as advertise selector */

Definition at line 934 of file atl1e.h.

◆ MII_LPA_10HALF

#define MII_LPA_10HALF   0x0020 /* Can do 10mbps half-duplex */

Definition at line 935 of file atl1e.h.

◆ MII_LPA_10FULL

#define MII_LPA_10FULL   0x0040 /* Can do 10mbps full-duplex */

Definition at line 936 of file atl1e.h.

◆ MII_LPA_100HALF

#define MII_LPA_100HALF   0x0080 /* Can do 100mbps half-duplex */

Definition at line 937 of file atl1e.h.

◆ MII_LPA_100FULL

#define MII_LPA_100FULL   0x0100 /* Can do 100mbps full-duplex */

Definition at line 938 of file atl1e.h.

◆ MII_LPA_100BASE4

#define MII_LPA_100BASE4   0x0200 /* 100BASE-T4 */

Definition at line 939 of file atl1e.h.

◆ MII_LPA_PAUSE

#define MII_LPA_PAUSE   0x0400 /* PAUSE */

Definition at line 940 of file atl1e.h.

◆ MII_LPA_ASYPAUSE

#define MII_LPA_ASYPAUSE   0x0800 /* Asymmetrical PAUSE */

Definition at line 941 of file atl1e.h.

◆ MII_LPA_RFAULT

#define MII_LPA_RFAULT   0x2000 /* Link partner faulted */

Definition at line 942 of file atl1e.h.

◆ MII_LPA_LPACK

#define MII_LPA_LPACK   0x4000 /* Link partner acked us */

Definition at line 943 of file atl1e.h.

◆ MII_LPA_NPAGE

#define MII_LPA_NPAGE   0x8000 /* Next page bit */

Definition at line 944 of file atl1e.h.

◆ MII_AR_SELECTOR_FIELD

#define MII_AR_SELECTOR_FIELD   0x0001 /* indicates IEEE 802.3 CSMA/CD */

Definition at line 947 of file atl1e.h.

◆ MII_AR_10T_HD_CAPS

#define MII_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */

Definition at line 948 of file atl1e.h.

◆ MII_AR_10T_FD_CAPS

#define MII_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */

Definition at line 949 of file atl1e.h.

◆ MII_AR_100TX_HD_CAPS

#define MII_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */

Definition at line 950 of file atl1e.h.

◆ MII_AR_100TX_FD_CAPS

#define MII_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */

Definition at line 951 of file atl1e.h.

◆ MII_AR_100T4_CAPS

#define MII_AR_100T4_CAPS   0x0200 /* 100T4 Capable */

Definition at line 952 of file atl1e.h.

◆ MII_AR_PAUSE

#define MII_AR_PAUSE   0x0400 /* Pause operation desired */

Definition at line 953 of file atl1e.h.

◆ MII_AR_ASM_DIR

#define MII_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */

Definition at line 954 of file atl1e.h.

◆ MII_AR_REMOTE_FAULT

#define MII_AR_REMOTE_FAULT   0x2000 /* Remote Fault detected */

Definition at line 955 of file atl1e.h.

◆ MII_AR_NEXT_PAGE

#define MII_AR_NEXT_PAGE   0x8000 /* Next Page ability supported */

Definition at line 956 of file atl1e.h.

◆ MII_AR_SPEED_MASK

#define MII_AR_SPEED_MASK   0x01E0

Definition at line 957 of file atl1e.h.

◆ MII_AR_DEFAULT_CAP_MASK

#define MII_AR_DEFAULT_CAP_MASK   0x0DE0

Definition at line 958 of file atl1e.h.

◆ MII_AT001_CR_1000T_HD_CAPS

#define MII_AT001_CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */

Definition at line 961 of file atl1e.h.

◆ MII_AT001_CR_1000T_FD_CAPS

#define MII_AT001_CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */

Definition at line 962 of file atl1e.h.

◆ MII_AT001_CR_1000T_REPEATER_DTE

#define MII_AT001_CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port */

Definition at line 963 of file atl1e.h.

◆ MII_AT001_CR_1000T_MS_VALUE

#define MII_AT001_CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */

Definition at line 965 of file atl1e.h.

◆ MII_AT001_CR_1000T_MS_ENABLE

#define MII_AT001_CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */

Definition at line 967 of file atl1e.h.

◆ MII_AT001_CR_1000T_TEST_MODE_NORMAL

#define MII_AT001_CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */

Definition at line 969 of file atl1e.h.

◆ MII_AT001_CR_1000T_TEST_MODE_1

#define MII_AT001_CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */

Definition at line 970 of file atl1e.h.

◆ MII_AT001_CR_1000T_TEST_MODE_2

#define MII_AT001_CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */

Definition at line 971 of file atl1e.h.

◆ MII_AT001_CR_1000T_TEST_MODE_3

#define MII_AT001_CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */

Definition at line 972 of file atl1e.h.

◆ MII_AT001_CR_1000T_TEST_MODE_4

#define MII_AT001_CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */

Definition at line 973 of file atl1e.h.

◆ MII_AT001_CR_1000T_SPEED_MASK

#define MII_AT001_CR_1000T_SPEED_MASK   0x0300

Definition at line 974 of file atl1e.h.

◆ MII_AT001_CR_1000T_DEFAULT_CAP_MASK

#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK   0x0300

Definition at line 975 of file atl1e.h.

◆ MII_AT001_SR_1000T_LP_HD_CAPS

#define MII_AT001_SR_1000T_LP_HD_CAPS   0x0400 /* LP is 1000T HD capable */

Definition at line 978 of file atl1e.h.

◆ MII_AT001_SR_1000T_LP_FD_CAPS

#define MII_AT001_SR_1000T_LP_FD_CAPS   0x0800 /* LP is 1000T FD capable */

Definition at line 979 of file atl1e.h.

◆ MII_AT001_SR_1000T_REMOTE_RX_STATUS

#define MII_AT001_SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */

Definition at line 980 of file atl1e.h.

◆ MII_AT001_SR_1000T_LOCAL_RX_STATUS

#define MII_AT001_SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */

Definition at line 981 of file atl1e.h.

◆ MII_AT001_SR_1000T_MS_CONFIG_RES

#define MII_AT001_SR_1000T_MS_CONFIG_RES   0x4000 /* 1=Local TX is Master, 0=Slave */

Definition at line 982 of file atl1e.h.

◆ MII_AT001_SR_1000T_MS_CONFIG_FAULT

#define MII_AT001_SR_1000T_MS_CONFIG_FAULT   0x8000 /* Master/Slave config fault */

Definition at line 983 of file atl1e.h.

◆ MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT

#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT   12

Definition at line 984 of file atl1e.h.

◆ MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT

#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT   13

Definition at line 985 of file atl1e.h.

◆ MII_AT001_ESR_1000T_HD_CAPS

#define MII_AT001_ESR_1000T_HD_CAPS   0x1000 /* 1000T HD capable */

Definition at line 988 of file atl1e.h.

◆ MII_AT001_ESR_1000T_FD_CAPS

#define MII_AT001_ESR_1000T_FD_CAPS   0x2000 /* 1000T FD capable */

Definition at line 989 of file atl1e.h.

◆ MII_AT001_ESR_1000X_HD_CAPS

#define MII_AT001_ESR_1000X_HD_CAPS   0x4000 /* 1000X HD capable */

Definition at line 990 of file atl1e.h.

◆ MII_AT001_ESR_1000X_FD_CAPS

#define MII_AT001_ESR_1000X_FD_CAPS   0x8000 /* 1000X FD capable */

Definition at line 991 of file atl1e.h.

◆ MII_AT001_PSCR_JABBER_DISABLE

#define MII_AT001_PSCR_JABBER_DISABLE   0x0001 /* 1=Jabber Function disabled */

Definition at line 994 of file atl1e.h.

◆ MII_AT001_PSCR_POLARITY_REVERSAL

#define MII_AT001_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */

Definition at line 995 of file atl1e.h.

◆ MII_AT001_PSCR_SQE_TEST

#define MII_AT001_PSCR_SQE_TEST   0x0004 /* 1=SQE Test enabled */

Definition at line 996 of file atl1e.h.

◆ MII_AT001_PSCR_MAC_POWERDOWN

#define MII_AT001_PSCR_MAC_POWERDOWN   0x0008

Definition at line 997 of file atl1e.h.

◆ MII_AT001_PSCR_CLK125_DISABLE

#define MII_AT001_PSCR_CLK125_DISABLE
Value:
0x0010 /* 1=CLK125 low,
* 0=CLK125 toggling
*/

Definition at line 998 of file atl1e.h.

◆ MII_AT001_PSCR_MDI_MANUAL_MODE

#define MII_AT001_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */

Definition at line 1001 of file atl1e.h.

◆ MII_AT001_PSCR_MDIX_MANUAL_MODE

#define MII_AT001_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */

Definition at line 1003 of file atl1e.h.

◆ MII_AT001_PSCR_AUTO_X_1000T

#define MII_AT001_PSCR_AUTO_X_1000T
Value:
0x0040 /* 1000BASE-T: Auto crossover,
* 100BASE-TX/10BASE-T:
* MDI Mode
*/

Definition at line 1004 of file atl1e.h.

◆ MII_AT001_PSCR_AUTO_X_MODE

#define MII_AT001_PSCR_AUTO_X_MODE
Value:
0x0060 /* Auto crossover enabled
* all speeds.
*/

Definition at line 1008 of file atl1e.h.

◆ MII_AT001_PSCR_10BT_EXT_DIST_ENABLE

#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE   0x0080

Definition at line 1011 of file atl1e.h.

◆ MII_AT001_PSCR_MII_5BIT_ENABLE

#define MII_AT001_PSCR_MII_5BIT_ENABLE   0x0100

Definition at line 1015 of file atl1e.h.

◆ MII_AT001_PSCR_SCRAMBLER_DISABLE

#define MII_AT001_PSCR_SCRAMBLER_DISABLE   0x0200 /* 1=Scrambler disable */

Definition at line 1018 of file atl1e.h.

◆ MII_AT001_PSCR_FORCE_LINK_GOOD

#define MII_AT001_PSCR_FORCE_LINK_GOOD   0x0400 /* 1=Force link good */

Definition at line 1019 of file atl1e.h.

◆ MII_AT001_PSCR_ASSERT_CRS_ON_TX

#define MII_AT001_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */

Definition at line 1020 of file atl1e.h.

◆ MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT

#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT   1

Definition at line 1021 of file atl1e.h.

◆ MII_AT001_PSCR_AUTO_X_MODE_SHIFT

#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT   5

Definition at line 1022 of file atl1e.h.

◆ MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT

#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT   7

Definition at line 1023 of file atl1e.h.

◆ MII_AT001_PSSR_SPD_DPLX_RESOLVED

#define MII_AT001_PSSR_SPD_DPLX_RESOLVED   0x0800 /* 1=Speed & Duplex resolved */

Definition at line 1025 of file atl1e.h.

◆ MII_AT001_PSSR_DPLX

#define MII_AT001_PSSR_DPLX   0x2000 /* 1=Duplex 0=Half Duplex */

Definition at line 1026 of file atl1e.h.

◆ MII_AT001_PSSR_SPEED

#define MII_AT001_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */

Definition at line 1027 of file atl1e.h.

◆ MII_AT001_PSSR_10MBS

#define MII_AT001_PSSR_10MBS   0x0000 /* 00=10Mbs */

Definition at line 1028 of file atl1e.h.

◆ MII_AT001_PSSR_100MBS

#define MII_AT001_PSSR_100MBS   0x4000 /* 01=100Mbs */

Definition at line 1029 of file atl1e.h.

◆ MII_AT001_PSSR_1000MBS

#define MII_AT001_PSSR_1000MBS   0x8000 /* 10=1000Mbs */

Definition at line 1030 of file atl1e.h.

Enumeration Type Documentation

◆ atl1e_dma_req_block

Enumerator
atl1e_dma_req_128 
atl1e_dma_req_256 
atl1e_dma_req_512 
atl1e_dma_req_1024 
atl1e_dma_req_2048 
atl1e_dma_req_4096 

Definition at line 139 of file atl1e.h.

◆ atl1e_nic_type

Enumerator
athr_l1e 
athr_l2e_revA 
athr_l2e_revB 

Definition at line 148 of file atl1e.h.

148  {
149  athr_l1e = 0,
150  athr_l2e_revA = 1,
151  athr_l2e_revB = 2
152 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ atl1e_up()

int atl1e_up ( struct atl1e_adapter adapter)

Definition at line 986 of file atl1e.c.

987 {
988  struct net_device *netdev = adapter->netdev;
989  int err = 0;
990  u32 val;
991 
992  /* hardware has been reset, we need to reload some things */
993  err = atl1e_init_hw(&adapter->hw);
994  if (err) {
995  return -EIO;
996  }
997  atl1e_init_ring_ptrs(adapter);
998 
999  memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN);
1000 
1001  if (atl1e_configure(adapter) != 0) {
1002  return -EIO;
1003  }
1004 
1005  atl1e_irq_disable(adapter);
1006 
1007  val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1008  AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1010 
1011  return err;
1012 }
u8 mac_addr[ETH_ALEN]
Definition: atl1e.h:158
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
Definition: atl1e.c:339
static int atl1e_configure(struct atl1e_adapter *adapter)
Definition: atl1e.c:643
static struct net_device * netdev
Definition: gdbudp.c:52
#define MASTER_CTRL_MANUAL_INT
Definition: atl1e.h:403
int atl1e_init_hw(struct atl1e_hw *hw)
Definition: atl1e.c:1670
static void atl1e_irq_disable(struct atl1e_adapter *adapter)
Definition: atl1e.c:103
struct atl1e_hw hw
Definition: atl1e.h:225
A network device.
Definition: netdevice.h:348
#define ETH_ALEN
Definition: if_ether.h:8
void __asmcall int val
Definition: setjmp.h:28
#define REG_MASTER_CTRL
Definition: atl1e.h:399
struct net_device * netdev
Definition: atl1e.h:222
#define EIO
Input/output error.
Definition: errno.h:433
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:381
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_READ_REG, AT_WRITE_REG, atl1e_configure(), atl1e_init_hw(), atl1e_init_ring_ptrs(), atl1e_irq_disable(), EIO, ETH_ALEN, atl1e_adapter::hw, net_device::ll_addr, atl1e_hw::mac_addr, MASTER_CTRL_MANUAL_INT, memcpy(), netdev, atl1e_adapter::netdev, REG_MASTER_CTRL, and val.

Referenced by atl1e_open(), and atl1e_reset().

◆ atl1e_down()

void atl1e_down ( struct atl1e_adapter adapter)

Definition at line 1024 of file atl1e.c.

1025 {
1026  struct net_device *netdev = adapter->netdev;
1027 
1028  /* reset MAC to disable all RX/TX */
1029  atl1e_reset_hw(&adapter->hw);
1030  mdelay(1);
1031 
1033  adapter->link_speed = SPEED_0;
1034  adapter->link_duplex = -1;
1035 
1036  atl1e_clean_tx_ring(adapter);
1037  atl1e_clean_rx_ring(adapter);
1038 }
#define SPEED_0
Definition: atl1e.h:49
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
u16 link_duplex
Definition: atl1e.h:228
static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
Definition: atl1e.c:258
static struct net_device * netdev
Definition: gdbudp.c:52
int atl1e_reset_hw(struct atl1e_hw *hw)
Definition: atl1e.c:1614
struct atl1e_hw hw
Definition: atl1e.h:225
A network device.
Definition: netdevice.h:348
static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
Definition: atl1e.c:288
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
struct net_device * netdev
Definition: atl1e.h:222
u16 link_speed
Definition: atl1e.h:227

References atl1e_clean_rx_ring(), atl1e_clean_tx_ring(), atl1e_reset_hw(), atl1e_adapter::hw, atl1e_adapter::link_duplex, atl1e_adapter::link_speed, mdelay(), netdev, atl1e_adapter::netdev, netdev_link_down(), and SPEED_0.

Referenced by atl1e_close(), and atl1e_reset().

◆ atl1e_reset_hw()

s32 atl1e_reset_hw ( struct atl1e_hw hw)

Definition at line 1614 of file atl1e.c.

1615 {
1616  struct atl1e_adapter *adapter = hw->adapter;
1617  struct pci_device *pdev = adapter->pdev;
1618  int timeout = 0;
1619  u32 idle_status_data = 0;
1620  u16 pci_cfg_cmd_word = 0;
1621 
1622  /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
1623  pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word);
1624  if ((pci_cfg_cmd_word & (PCI_COMMAND_IO | PCI_COMMAND_MEM |
1627  PCI_COMMAND_MASTER)) {
1628  pci_cfg_cmd_word |= (PCI_COMMAND_IO | PCI_COMMAND_MEM |
1630  pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word);
1631  }
1632 
1633  /*
1634  * Issue Soft Reset to the MAC. This will reset the chip's
1635  * transmit, receive, DMA. It will not effect
1636  * the current PCI configuration. The global reset bit is self-
1637  * clearing, and should clear within a microsecond.
1638  */
1641  wmb();
1642  mdelay(1);
1643 
1644  /* Wait at least 10ms for All module to be Idle */
1645  for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1646  idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
1647  if (idle_status_data == 0)
1648  break;
1649  mdelay(1);
1650  }
1651 
1652  if (timeout >= AT_HW_MAX_IDLE_DELAY) {
1653  DBG("atl1e: MAC reset timeout\n");
1654  return AT_ERR_TIMEOUT;
1655  }
1656 
1657  return 0;
1658 }
uint16_t u16
Definition: stdint.h:21
wmb()
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
#define REG_IDLE_STATUS
Definition: atl1e.h:457
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
#define PCI_COMMAND
PCI command.
Definition: pci.h:24
Definition: hw.c:16
#define PCI_COMMAND_MASTER
Bus master.
Definition: pci.h:27
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
#define PCI_COMMAND_IO
I/O space.
Definition: pci.h:25
A PCI device.
Definition: pci.h:187
#define MASTER_CTRL_SOFT_RST
Definition: atl1e.h:400
#define AT_HW_MAX_IDLE_DELAY
Definition: atl1e.h:71
struct pci_device * pdev
Definition: atl1e.h:223
#define AT_ERR_TIMEOUT
Definition: atl1e.h:65
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define REG_MASTER_CTRL
Definition: atl1e.h:399
#define MASTER_CTRL_LED_MODE
Definition: atl1e.h:406
void timeout(int)
#define PCI_COMMAND_MEM
Memory space.
Definition: pci.h:26
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_ERR_TIMEOUT, AT_HW_MAX_IDLE_DELAY, AT_READ_REG, AT_WRITE_REG, DBG, MASTER_CTRL_LED_MODE, MASTER_CTRL_SOFT_RST, mdelay(), PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, pci_read_config_word(), pci_write_config_word(), atl1e_adapter::pdev, REG_IDLE_STATUS, REG_MASTER_CTRL, timeout(), and wmb().

Referenced by atl1e_down(), atl1e_open(), and atl1e_probe().

◆ atl1e_read_mac_addr()

s32 atl1e_read_mac_addr ( struct atl1e_hw hw)

Definition at line 1335 of file atl1e.c.

1336 {
1337  int err = 0;
1338 
1340  if (err)
1341  return AT_ERR_EEPROM;
1342  memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
1343  return 0;
1344 }
Definition: hw.c:16
#define AT_ERR_EEPROM
Definition: atl1e.h:57
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static int atl1e_get_permanent_address(struct atl1e_hw *hw)
Definition: atl1e.c:1288

References AT_ERR_EEPROM, atl1e_get_permanent_address(), and memcpy().

Referenced by atl1e_probe().

◆ atl1e_init_hw()

s32 atl1e_init_hw ( struct atl1e_hw hw)

Definition at line 1670 of file atl1e.c.

1671 {
1672  s32 ret_val = 0;
1673 
1675 
1676  /* Zero out the Multicast HASH table */
1677  /* clear the old settings from the multicast hash table */
1680 
1681  ret_val = atl1e_phy_init(hw);
1682 
1683  return ret_val;
1684 }
int32_t s32
Definition: stdint.h:22
Definition: hw.c:16
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
int atl1e_phy_init(struct atl1e_hw *hw)
Definition: atl1e.c:1522
#define AT_WRITE_REG_ARRAY(a, reg, offset, value)
Definition: atl1e.h:262
#define REG_RX_HASH_TABLE
Definition: atl1e.h:560
static void atl1e_init_pcie(struct atl1e_hw *hw)
Definition: atl1e.c:1416

References AT_WRITE_REG, AT_WRITE_REG_ARRAY, atl1e_init_pcie(), atl1e_phy_init(), and REG_RX_HASH_TABLE.

Referenced by atl1e_up().

◆ atl1e_phy_commit()

s32 atl1e_phy_commit ( struct atl1e_hw hw)

Definition at line 1491 of file atl1e.c.

1492 {
1493  int ret_val;
1494  u16 phy_data;
1495 
1497 
1498  ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
1499  if (ret_val) {
1500  u32 val;
1501  int i;
1502  /**************************************
1503  * pcie serdes link may be down !
1504  **************************************/
1505  for (i = 0; i < 25; i++) {
1506  mdelay(1);
1508  if (!(val & (MDIO_START | MDIO_BUSY)))
1509  break;
1510  }
1511 
1512  if (0 != (val & (MDIO_START | MDIO_BUSY))) {
1513  DBG("atl1e: PCI-E link down for at least 25ms\n");
1514  return ret_val;
1515  }
1516 
1517  DBG("atl1e: PCI-E link up after %d ms\n", i);
1518  }
1519  return 0;
1520 }
uint16_t u16
Definition: stdint.h:21
#define MII_CR_RESTART_AUTO_NEG
Definition: atl1e.h:903
int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
Definition: atl1e.c:1385
#define MDIO_BUSY
Definition: atl1e.h:484
#define MII_CR_RESET
Definition: atl1e.h:909
#define REG_MDIO_CTRL
Definition: atl1e.h:468
Definition: hw.c:16
#define MII_BMCR
Definition: atl1e.h:871
void __asmcall int val
Definition: setjmp.h:28
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define MII_CR_AUTO_NEG_EN
Definition: atl1e.h:906
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define MDIO_START
Definition: atl1e.h:475
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_READ_REG, atl1e_write_phy_reg(), DBG, mdelay(), MDIO_BUSY, MDIO_START, MII_BMCR, MII_CR_AUTO_NEG_EN, MII_CR_RESET, MII_CR_RESTART_AUTO_NEG, REG_MDIO_CTRL, and val.

Referenced by atl1e_phy_init().

◆ atl1e_get_speed_and_duplex()

s32 atl1e_get_speed_and_duplex ( struct atl1e_hw hw,
u16 speed,
u16 duplex 
)

Definition at line 1693 of file atl1e.c.

1694 {
1695  int err;
1696  u16 phy_data;
1697 
1698  /* Read PHY Specific Status Register (17) */
1699  err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
1700  if (err)
1701  return err;
1702 
1703  if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
1704  return AT_ERR_PHY_RES;
1705 
1706  switch (phy_data & MII_AT001_PSSR_SPEED) {
1708  *speed = SPEED_1000;
1709  break;
1710  case MII_AT001_PSSR_100MBS:
1711  *speed = SPEED_100;
1712  break;
1713  case MII_AT001_PSSR_10MBS:
1714  *speed = SPEED_10;
1715  break;
1716  default:
1717  return AT_ERR_PHY_SPEED;
1718  break;
1719  }
1720 
1721  if (phy_data & MII_AT001_PSSR_DPLX)
1722  *duplex = FULL_DUPLEX;
1723  else
1724  *duplex = HALF_DUPLEX;
1725 
1726  return 0;
1727 }
#define SPEED_1000
Definition: atl1e.h:52
uint16_t u16
Definition: stdint.h:21
#define MII_AT001_PSSR_DPLX
Definition: atl1e.h:1026
#define AT_ERR_PHY_SPEED
Definition: atl1e.h:63
#define MII_AT001_PSSR
Definition: atl1e.h:882
#define SPEED_10
Definition: atl1e.h:50
Definition: hw.c:16
#define SPEED_100
Definition: atl1e.h:51
#define MII_AT001_PSSR_1000MBS
Definition: atl1e.h:1030
#define MII_AT001_PSSR_100MBS
Definition: atl1e.h:1029
int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
Definition: atl1e.c:1351
duplex
Definition: nic.h:40
#define MII_AT001_PSSR_SPEED
Definition: atl1e.h:1027
#define MII_AT001_PSSR_SPD_DPLX_RESOLVED
Definition: atl1e.h:1025
#define MII_AT001_PSSR_10MBS
Definition: atl1e.h:1028
#define AT_ERR_PHY_RES
Definition: atl1e.h:64

References AT_ERR_PHY_RES, AT_ERR_PHY_SPEED, atl1e_read_phy_reg(), FULL_DUPLEX, HALF_DUPLEX, MII_AT001_PSSR, MII_AT001_PSSR_1000MBS, MII_AT001_PSSR_100MBS, MII_AT001_PSSR_10MBS, MII_AT001_PSSR_DPLX, MII_AT001_PSSR_SPD_DPLX_RESOLVED, MII_AT001_PSSR_SPEED, SPEED_10, SPEED_100, and SPEED_1000.

Referenced by atl1e_check_link().

◆ atl1e_auto_get_fc()

u32 atl1e_auto_get_fc ( struct atl1e_adapter adapter,
u16  duplex 
)

◆ atl1e_read_phy_reg()

s32 atl1e_read_phy_reg ( struct atl1e_hw hw,
u16  reg_addr,
u16 phy_data 
)

Definition at line 1351 of file atl1e.c.

1352 {
1353  u32 val;
1354  int i;
1355 
1356  val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
1359 
1361 
1362  wmb();
1363 
1364  for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1365  udelay(2);
1367  if (!(val & (MDIO_START | MDIO_BUSY)))
1368  break;
1369  wmb();
1370  }
1371  if (!(val & (MDIO_START | MDIO_BUSY))) {
1372  *phy_data = (u16)val;
1373  return 0;
1374  }
1375 
1376  return AT_ERR_PHY;
1377 }
#define u16
Definition: vga.h:20
wmb()
#define MDIO_REG_ADDR_SHIFT
Definition: atl1e.h:472
#define MDIO_BUSY
Definition: atl1e.h:484
#define MDIO_SUP_PREAMBLE
Definition: atl1e.h:474
#define REG_MDIO_CTRL
Definition: atl1e.h:468
Definition: hw.c:16
#define AT_ERR_PHY
Definition: atl1e.h:58
#define MDIO_REG_ADDR_MASK
Definition: atl1e.h:471
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
#define u32
Definition: vga.h:21
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define MDIO_RW
Definition: atl1e.h:473
#define MDIO_WAIT_TIMES
Definition: atl1e.h:486
void __asmcall int val
Definition: setjmp.h:28
#define MDIO_CLK_SEL_SHIFT
Definition: atl1e.h:476
#define MDIO_START
Definition: atl1e.h:475
#define MDIO_CLK_25_4
Definition: atl1e.h:477
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_ERR_PHY, AT_READ_REG, AT_WRITE_REG, MDIO_BUSY, MDIO_CLK_25_4, MDIO_CLK_SEL_SHIFT, MDIO_REG_ADDR_MASK, MDIO_REG_ADDR_SHIFT, MDIO_RW, MDIO_START, MDIO_SUP_PREAMBLE, MDIO_WAIT_TIMES, REG_MDIO_CTRL, u16, u32, udelay(), val, and wmb().

Referenced by atl1e_check_link(), atl1e_clear_phy_int(), atl1e_get_speed_and_duplex(), and atl1e_mdio_read().

◆ atl1e_write_phy_reg()

s32 atl1e_write_phy_reg ( struct atl1e_hw hw,
u32  reg_addr,
u16  phy_data 
)

Definition at line 1385 of file atl1e.c.

1386 {
1387  int i;
1388  u32 val;
1389 
1390  val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
1391  (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
1393  MDIO_START |
1395 
1397  wmb();
1398 
1399  for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1400  udelay(2);
1402  if (!(val & (MDIO_START | MDIO_BUSY)))
1403  break;
1404  wmb();
1405  }
1406 
1407  if (!(val & (MDIO_START | MDIO_BUSY)))
1408  return 0;
1409 
1410  return AT_ERR_PHY;
1411 }
wmb()
#define MDIO_REG_ADDR_SHIFT
Definition: atl1e.h:472
#define MDIO_BUSY
Definition: atl1e.h:484
#define MDIO_SUP_PREAMBLE
Definition: atl1e.h:474
#define REG_MDIO_CTRL
Definition: atl1e.h:468
Definition: hw.c:16
#define AT_ERR_PHY
Definition: atl1e.h:58
#define MDIO_REG_ADDR_MASK
Definition: atl1e.h:471
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
#define MDIO_DATA_MASK
Definition: atl1e.h:469
#define u32
Definition: vga.h:21
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define MDIO_WAIT_TIMES
Definition: atl1e.h:486
#define MDIO_DATA_SHIFT
Definition: atl1e.h:470
void __asmcall int val
Definition: setjmp.h:28
#define MDIO_CLK_SEL_SHIFT
Definition: atl1e.h:476
#define MDIO_START
Definition: atl1e.h:475
#define MDIO_CLK_25_4
Definition: atl1e.h:477
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_ERR_PHY, AT_READ_REG, AT_WRITE_REG, MDIO_BUSY, MDIO_CLK_25_4, MDIO_CLK_SEL_SHIFT, MDIO_DATA_MASK, MDIO_DATA_SHIFT, MDIO_REG_ADDR_MASK, MDIO_REG_ADDR_SHIFT, MDIO_START, MDIO_SUP_PREAMBLE, MDIO_WAIT_TIMES, REG_MDIO_CTRL, u32, udelay(), val, and wmb().

Referenced by atl1e_mdio_write(), atl1e_phy_commit(), atl1e_phy_init(), atl1e_phy_setup_autoneg_adv(), and atl1e_restart_autoneg().

◆ atl1e_validate_mdi_setting()

s32 atl1e_validate_mdi_setting ( struct atl1e_hw hw)

◆ atl1e_hw_set_mac_addr()

void atl1e_hw_set_mac_addr ( struct atl1e_hw hw)

Definition at line 1265 of file atl1e.c.

1266 {
1267  u32 value;
1268  /*
1269  * 00-0B-6A-F6-00-DC
1270  * 0: 6AF600DC 1: 000B
1271  * low dword
1272  */
1273  value = (((u32)hw->mac_addr[2]) << 24) |
1274  (((u32)hw->mac_addr[3]) << 16) |
1275  (((u32)hw->mac_addr[4]) << 8) |
1276  (((u32)hw->mac_addr[5])) ;
1278  /* hight dword */
1279  value = (((u32)hw->mac_addr[0]) << 8) |
1280  (((u32)hw->mac_addr[1])) ;
1282 }
Definition: hw.c:16
#define u32
Definition: vga.h:21
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define AT_WRITE_REG_ARRAY(a, reg, offset, value)
Definition: atl1e.h:262
uint32_t u32
Definition: stdint.h:23
#define REG_MAC_STA_ADDR
Definition: atl1e.h:557

References AT_WRITE_REG_ARRAY, REG_MAC_STA_ADDR, u32, and value.

Referenced by atl1e_configure().

◆ atl1e_phy_enter_power_saving()

s32 atl1e_phy_enter_power_saving ( struct atl1e_hw hw)

◆ atl1e_phy_leave_power_saving()

s32 atl1e_phy_leave_power_saving ( struct atl1e_hw hw)

◆ atl1e_phy_init()

s32 atl1e_phy_init ( struct atl1e_hw hw)

Definition at line 1522 of file atl1e.c.

1523 {
1524  s32 ret_val;
1525  u16 phy_val;
1526 
1527  if (hw->phy_configured) {
1528  if (hw->re_autoneg) {
1529  hw->re_autoneg = 0;
1530  return atl1e_restart_autoneg(hw);
1531  }
1532  return 0;
1533  }
1534 
1535  /* RESET GPHY Core */
1537  mdelay(2);
1540  mdelay(2);
1541 
1542  /* patches */
1543  /* p1. eable hibernation mode */
1544  ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
1545  if (ret_val)
1546  return ret_val;
1547  ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
1548  if (ret_val)
1549  return ret_val;
1550  /* p2. set Class A/B for all modes */
1551  ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
1552  if (ret_val)
1553  return ret_val;
1554  phy_val = 0x02ef;
1555  /* remove Class AB */
1556  /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
1557  ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
1558  if (ret_val)
1559  return ret_val;
1560  /* p3. 10B ??? */
1561  ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
1562  if (ret_val)
1563  return ret_val;
1564  ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
1565  if (ret_val)
1566  return ret_val;
1567  /* p4. 1000T power */
1568  ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
1569  if (ret_val)
1570  return ret_val;
1571  ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
1572  if (ret_val)
1573  return ret_val;
1574 
1575  ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
1576  if (ret_val)
1577  return ret_val;
1578  ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
1579  if (ret_val)
1580  return ret_val;
1581 
1582  mdelay(1);
1583 
1584  /*Enable PHY LinkChange Interrupt */
1585  ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
1586  if (ret_val) {
1587  DBG("atl1e: Error enable PHY linkChange Interrupt\n");
1588  return ret_val;
1589  }
1590  /* setup AutoNeg parameters */
1591  ret_val = atl1e_phy_setup_autoneg_adv(hw);
1592  if (ret_val) {
1593  DBG("atl1e: Error Setting up Auto-Negotiation\n");
1594  return ret_val;
1595  }
1596  /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
1597  DBG("atl1e: Restarting Auto-Neg");
1598  ret_val = atl1e_phy_commit(hw);
1599  if (ret_val) {
1600  DBG("atl1e: Error Resetting the phy");
1601  return ret_val;
1602  }
1603 
1604  hw->phy_configured = 1;
1605 
1606  return 0;
1607 }
uint16_t u16
Definition: stdint.h:21
#define MII_INT_CTRL
Definition: atl1e.h:883
int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
Definition: atl1e.c:1385
#define GPHY_CTRL_EXT_RESET
Definition: atl1e.h:422
int32_t s32
Definition: stdint.h:22
#define REG_GPHY_CTRL
Definition: atl1e.h:421
#define AT_WRITE_REGW(a, reg, value)
Definition: atl1e.h:256
int atl1e_phy_commit(struct atl1e_hw *hw)
Definition: atl1e.c:1491
Definition: hw.c:16
static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
Definition: atl1e.c:1434
#define GPHY_CTRL_DEFAULT
Definition: atl1e.h:437
#define MII_DBG_DATA
Definition: atl1e.h:896
#define MII_DBG_ADDR
Definition: atl1e.h:895
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
int atl1e_restart_autoneg(struct atl1e_hw *hw)
Definition: atl1e.c:1729
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References AT_WRITE_REGW, atl1e_phy_commit(), atl1e_phy_setup_autoneg_adv(), atl1e_restart_autoneg(), atl1e_write_phy_reg(), DBG, GPHY_CTRL_DEFAULT, GPHY_CTRL_EXT_RESET, mdelay(), MII_DBG_ADDR, MII_DBG_DATA, MII_INT_CTRL, and REG_GPHY_CTRL.

Referenced by atl1e_init_hw(), and atl1e_probe().

◆ atl1e_check_eeprom_exist()

int atl1e_check_eeprom_exist ( struct atl1e_hw hw)

Definition at line 1252 of file atl1e.c.

1253 {
1254  u32 value;
1255 
1257  if (value & SPI_FLASH_CTRL_EN_VPD) {
1260  }
1262  return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
1263 }
#define AT_READ_REGW(a, reg)
Definition: atl1e.h:259
Definition: hw.c:16
#define REG_PCIE_CAP_LIST
Definition: atl1e.h:295
#define AT_WRITE_REG(a, reg, value)
Definition: atl1e.h:241
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define REG_SPI_FLASH_CTRL
Definition: atl1e.h:318
#define SPI_FLASH_CTRL_EN_VPD
Definition: atl1e.h:327
uint32_t u32
Definition: stdint.h:23
#define AT_READ_REG(a, reg)
Definition: atl1e.h:247

References AT_READ_REG, AT_READ_REGW, AT_WRITE_REG, REG_PCIE_CAP_LIST, REG_SPI_FLASH_CTRL, SPI_FLASH_CTRL_EN_VPD, and value.

Referenced by atl1e_get_permanent_address().

◆ atl1e_force_ps()

void atl1e_force_ps ( struct atl1e_hw hw)

Definition at line 1324 of file atl1e.c.

1325 {
1328 }
#define GPHY_CTRL_EXT_RESET
Definition: atl1e.h:422
#define REG_GPHY_CTRL
Definition: atl1e.h:421
#define AT_WRITE_REGW(a, reg, value)
Definition: atl1e.h:256
#define GPHY_CTRL_PW_WOL_DIS
Definition: atl1e.h:443
Definition: hw.c:16

References AT_WRITE_REGW, GPHY_CTRL_EXT_RESET, GPHY_CTRL_PW_WOL_DIS, and REG_GPHY_CTRL.

Referenced by atl1e_remove().

◆ atl1e_restart_autoneg()

s32 atl1e_restart_autoneg ( struct atl1e_hw hw)

Definition at line 1729 of file atl1e.c.

1730 {
1731  int err = 0;
1732 
1733  err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1734  if (err)
1735  return err;
1736 
1737  if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
1739  hw->mii_1000t_ctrl_reg);
1740  if (err)
1741  return err;
1742  }
1743 
1747  return err;
1748 }
#define MII_ADVERTISE
Definition: atl1e.h:875
#define MII_CR_RESTART_AUTO_NEG
Definition: atl1e.h:903
int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
Definition: atl1e.c:1385
#define MII_CR_RESET
Definition: atl1e.h:909
Definition: hw.c:16
#define MII_AT001_CR
Definition: atl1e.h:878
#define MII_BMCR
Definition: atl1e.h:871
#define MII_CR_AUTO_NEG_EN
Definition: atl1e.h:906

References athr_l1e, athr_l2e_revA, atl1e_write_phy_reg(), MII_ADVERTISE, MII_AT001_CR, MII_BMCR, MII_CR_AUTO_NEG_EN, MII_CR_RESET, and MII_CR_RESTART_AUTO_NEG.

Referenced by atl1e_phy_init(), and atl1e_probe().