Data Structures
struct	dma_desc

struct	rx_header

struct	b44_private
	Driver private state. More...

Macros
#define	_B44_H

#define	B44_DEVCTRL 0x0000UL /* Device Control */

#define	DEVCTRL_MPM 0x00000040 /* MP PME Enable (B0 only) */

#define	DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */

#define	DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */

#define	DEVCTRL_EPR 0x00008000 /* EPHY Reset */

#define	DEVCTRL_PME 0x00001000 /* PHY Mode Enable */

#define	DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */

#define	DEVCTRL_PADDR 0x0007c000 /* PHY Address */

#define	DEVCTRL_PADDR_SHIFT 18

#define	B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */

#define	B44_WKUP_LEN 0x0010UL /* Wakeup Length */

#define	WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */

#define	WKUP_LEN_D0 0x00000080

#define	WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */

#define	WKUP_LEN_P1_SHIFT 8

#define	WKUP_LEN_D1 0x00008000

#define	WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */

#define	WKUP_LEN_P2_SHIFT 16

#define	WKUP_LEN_D2 0x00000000

#define	WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */

#define	WKUP_LEN_P3_SHIFT 24

#define	WKUP_LEN_D3 0x80000000

#define	WKUP_LEN_DISABLE 0x80808080

#define	WKUP_LEN_ENABLE_TWO 0x80800000

#define	WKUP_LEN_ENABLE_THREE 0x80000000

#define	B44_ISTAT 0x0020UL /* Interrupt Status */

#define	ISTAT_LS 0x00000020 /* Link Change (B0 only) */

#define	ISTAT_PME 0x00000040 /* Power Management Event */

#define	ISTAT_TO 0x00000080 /* General Purpose Timeout */

#define	ISTAT_DSCE 0x00000400 /* Descriptor Error */

#define	ISTAT_DATAE 0x00000800 /* Data Error */

#define	ISTAT_DPE 0x00001000 /* Descr. Protocol Error */

#define	ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */

#define	ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */

#define	ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */

#define	ISTAT_RX 0x00010000 /* RX Interrupt */

#define	ISTAT_TX 0x01000000 /* TX Interrupt */

#define	ISTAT_EMAC 0x04000000 /* EMAC Interrupt */

#define	ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */

#define	ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */

#define	ISTAT_ERRORS

#define	B44_IMASK 0x0024UL /* Interrupt Mask */

#define	IMASK_DEF (ISTAT_ERRORS \| ISTAT_RX \| ISTAT_TX)

#define	IMASK_DISABLE 0

#define	B44_GPTIMER 0x0028UL /* General Purpose Timer */

#define	B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */

#define	B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */

#define	B44_FILT_ADDR 0x0090UL /* ENET Filter Address */

#define	B44_FILT_DATA 0x0094UL /* ENET Filter Data */

#define	B44_TXBURST 0x00A0UL /* TX Max Burst Length */

#define	B44_RXBURST 0x00A4UL /* RX Max Burst Length */

#define	B44_MAC_CTRL 0x00A8UL /* MAC Control */

#define	MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */

#define	MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */

#define	MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected*/

#define	MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */

#define	MAC_CTRL_PHY_LEDCTRL_SHIFT 5

#define	B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */

#define	MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */

#define	MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enbl Pause Frm Generation */

#define	B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */

#define	RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */

#define	RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */

#define	RCV_LAZY_FC_SHIFT 24

#define	B44_DMATX_CTRL 0x0200UL /* DMA TX Control */

#define	DMATX_CTRL_ENABLE 0x00000001 /* Enable */

#define	DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */

#define	DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */

#define	DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */

#define	DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */

#define	B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Addr */

#define	B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Desc. */

#define	B44_DMATX_STAT 0x020CUL /* DMA TX Cur Actve Desc. + Sts */

#define	DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */

#define	DMATX_STAT_SMASK 0x0000f000 /* State Mask */

#define	DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */

#define	DMATX_STAT_SACTIVE 0x00001000 /* State Active */

#define	DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */

#define	DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */

#define	DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */

#define	DMATX_STAT_EMASK 0x000f0000 /* Error Mask */

#define	DMATX_STAT_ENONE 0x00000000 /* Error None */

#define	DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */

#define	DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */

#define	DMATX_STAT_EBEBR 0x00030000 /* Bus Error on Buffer Read */

#define	DMATX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */

#define	DMATX_STAT_FLUSHED 0x00100000 /* Flushed */

#define	B44_DMARX_CTRL 0x0210UL /* DMA RX Control */

#define	DMARX_CTRL_ENABLE 0x00000001 /* Enable */

#define	DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */

#define	DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */

#define	B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Addr */

#define	B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Desc */

#define	B44_DMARX_STAT 0x021CUL /* Cur Active Desc. + Status */

#define	DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */

#define	DMARX_STAT_SMASK 0x0000f000 /* State Mask */

#define	DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */

#define	DMARX_STAT_SACTIVE 0x00001000 /* State Active */

#define	DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */

#define	DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */

#define	DMARX_STAT_EMASK 0x000f0000 /* Error Mask */

#define	DMARX_STAT_ENONE 0x00000000 /* Error None */

#define	DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */

#define	DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */

#define	DMARX_STAT_EBEBW 0x00030000 /* Error on Buffer Write */

#define	DMARX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */

#define	B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */

#define	DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */

#define	DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */

#define	DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */

#define	DMAFIFO_AD_SXDP 0x00010000 /* Sel Transmit DMA Pointers */

#define	DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */

#define	DMAFIFO_AD_SRDP 0x00050000 /* Sel Receive DMA Pointers */

#define	DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */

#define	DMAFIFO_AD_SXFP 0x00090000 /* Sel Transmit FIFO Pointers */

#define	DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */

#define	DMAFIFO_AD_SRFP 0x000c0000 /* Sel Receive FIFO Pointers */

#define	B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */

#define	B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */

#define	B44_RXCONFIG 0x0400UL /* EMAC RX Config */

#define	RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */

#define	RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */

#define	RXCONFIG_NORX_WHILE_TX 0x00000004 /* Rcv Disble While TX */

#define	RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */

#define	RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */

#define	RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */

#define	RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept UFC Frame */

#define	RXCONFIG_RFILT 0x00000080 /* Reject Filter */

#define	B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */

#define	B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */

#define	B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */

#define	MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */

#define	MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */

#define	B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */

#define	MDIO_DATA_DATA 0x0000ffff /* R/W Data */

#define	MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */

#define	MDIO_DATA_TA_SHIFT 16

#define	MDIO_TA_VALID 2

#define	MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */

#define	MDIO_DATA_RA_SHIFT 18

#define	MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */

#define	MDIO_DATA_PMD_SHIFT 23

#define	MDIO_DATA_OP_MASK 0x30000000 /* Opcode */

#define	MDIO_DATA_OP_SHIFT 28

#define	MDIO_OP_WRITE 1

#define	MDIO_OP_READ 2

#define	MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */

#define	MDIO_DATA_SB_SHIFT 30

#define	MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */

#define	B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */

#define	B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */

#define	EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */

#define	EMAC_INT_MIB 0x00000002 /* MIB Interrupt */

#define	EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */

#define	B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */

#define	B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */

#define	CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */

#define	B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */

#define	CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */

#define	CAM_CTRL_MSEL 0x00000002 /* Mask Select */

#define	CAM_CTRL_READ 0x00000004 /* Read */

#define	CAM_CTRL_WRITE 0x00000008 /* Read */

#define	CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */

#define	CAM_CTRL_INDEX_SHIFT 16

#define	CAM_CTRL_BUSY 0x80000000 /* CAM Busy */

#define	B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */

#define	ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */

#define	ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */

#define	ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */

#define	ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */

#define	B44_TX_CTRL 0x0430UL /* EMAC TX Control */

#define	TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */

#define	TX_CTRL_FMODE 0x00000002 /* Flow Mode */

#define	TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */

#define	TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */

#define	B44_TX_HIWMARK 0x0434UL /* EMAC TX High Watermark */

#define	TX_HIWMARK_DEFLT 56 /* Default used in all drivers */

#define	B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */

#define	MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */

#define	B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */

#define	B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */

#define	B44_TX_O 0x0508UL /* MIB TX Octets */

#define	B44_TX_P 0x050CUL /* MIB TX Packets */

#define	B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */

#define	B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */

#define	B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */

#define	B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Pkts */

#define	B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Pkts */

#define	B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Pkts */

#define	B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Pkts */

#define	B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Pkts */

#define	B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */

#define	B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */

#define	B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */

#define	B44_TX_URUNS 0x053CUL /* MIB TX Underruns */

#define	B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */

#define	B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */

#define	B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */

#define	B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */

#define	B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */

#define	B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */

#define	B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */

#define	B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */

#define	B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */

#define	B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */

#define	B44_RX_O 0x0588UL /* MIB RX Octets */

#define	B44_RX_P 0x058CUL /* MIB RX Packets */

#define	B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */

#define	B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */

#define	B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */

#define	B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Pkts */

#define	B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Pkts */

#define	B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Pkts */

#define	B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Pkts */

#define	B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Pkts */

#define	B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */

#define	B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */

#define	B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */

#define	B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */

#define	B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */

#define	B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */

#define	B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */

#define	B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */

#define	B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */

#define	B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */

#define	B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */

#define	B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */

#define	SBIMSTATE_PC 0x0000000f /* Pipe Count */

#define	SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */

#define	SBIMSTATE_AP_BOTH 0x00000000 /* both timeslices and token */

#define	SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */

#define	SBIMSTATE_AP_TK 0x00000020 /* Use token only */

#define	SBIMSTATE_AP_RSV 0x00000030 /* Reserved */

#define	SBIMSTATE_IBE 0x00020000 /* In Band Error */

#define	SBIMSTATE_TO 0x00040000 /* Timeout */

#define	SBIMSTATE_BAD ( SBIMSTATE_IBE \| SBIMSTATE_TO )

#define	B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */

#define	SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */

#define	SBINTVEC_ENET0 0x00000002 /* Enable ints for enet 0 */

#define	SBINTVEC_ILINE20 0x00000004 /* Enable ints for iline20 */

#define	SBINTVEC_CODEC 0x00000008 /* Enable ints for v90 codec */

#define	SBINTVEC_USB 0x00000010 /* Enable intts for usb */

#define	SBINTVEC_EXTIF 0x00000020 /* Enable ints for ext i/f */

#define	SBINTVEC_ENET1 0x00000040 /* Enable ints for enet 1 */

#define	B44_SBTMSLOW 0x0F98UL /* SB Target State Low */

#define	SBTMSLOW_RESET 0x00000001 /* Reset */

#define	SBTMSLOW_REJECT 0x00000002 /* Reject */

#define	SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */

#define	SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */

#define	SBTMSLOW_PE 0x40000000 /* Power Management Enable */

#define	SBTMSLOW_BE 0x80000000 /* BIST Enable */

#define	B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */

#define	SBTMSHIGH_SERR 0x00000001 /* S-error */

#define	SBTMSHIGH_INT 0x00000002 /* Interrupt */

#define	SBTMSHIGH_BUSY 0x00000004 /* Busy */

#define	SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */

#define	SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */

#define	SBTMSHIGH_BISTD 0x80000000 /* BIST Done */

#define	B44_SBIDHIGH 0x0FFCUL /* SB Identification High */

#define	SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */

#define	SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */

#define	SBIDHIGH_CC_SHIFT 4

#define	SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */

#define	SBIDHIGH_VC_SHIFT 16

#define	SSB_PMCSR 0x44

#define	SSB_PE 0x100

#define	SSB_BAR0_WIN 0x80

#define	SSB_BAR1_WIN 0x84

#define	SSB_SPROM_CONTROL 0x88

#define	SSB_BAR1_CONTROL 0x8c

#define	SSB_CONTROL 0x0000UL

#define	SSB_ARBCONTROL 0x0010UL

#define	SSB_ISTAT 0x0020UL

#define	SSB_IMASK 0x0024UL

#define	SSB_MBOX 0x0028UL

#define	SSB_BCAST_ADDR 0x0050UL

#define	SSB_BCAST_DATA 0x0054UL

#define	SSB_PCI_TRANS_0 0x0100UL

#define	SSB_PCI_TRANS_1 0x0104UL

#define	SSB_PCI_TRANS_2 0x0108UL

#define	SSB_SPROM 0x0800UL

#define	SSB_PCI_MEM 0x00000000

#define	SSB_PCI_IO 0x00000001

#define	SSB_PCI_CFG0 0x00000002

#define	SSB_PCI_CFG1 0x00000003

#define	SSB_PCI_PREF 0x00000004

#define	SSB_PCI_BURST 0x00000008

#define	SSB_PCI_MASK0 0xfc000000

#define	SSB_PCI_MASK1 0xfc000000

#define	SSB_PCI_MASK2 0xc0000000

#define	B44_MII_AUXCTRL 24 /* Auxiliary Control */

#define	MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */

#define	MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */

#define	MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */

#define	B44_MII_ALEDCTRL 26 /* Activity LED */

#define	MII_ALEDCTRL_ALLMSK 0x7fff

#define	B44_MII_TLEDCTRL 27 /* Traffic Meter LED */

#define	MII_TLEDCTRL_ENABLE 0x0040

#define	B44_DMA_ALIGNMENT 4096

#define	B44_30BIT_DMA_MASK 0x3fffffff

#define	DESC_CTRL_LEN 0x00001fff

#define	DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */

#define	DESC_CTRL_EOT 0x10000000 /* End of Table */

#define	DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */

#define	DESC_CTRL_EOF 0x40000000 /* End of Frame */

#define	DESC_CTRL_SOF 0x80000000 /* Start of Frame */

#define	RX_HEADER_LEN 28

#define	RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */

#define	RX_FLAG_CRCERR 0x00000002 /* CRC Error */

#define	RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */

#define	RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */

#define	RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */

#define	RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */

#define	RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */

#define	RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */

#define	RX_FLAG_LAST 0x00000800 /* Last buffer in frame */

#define	RX_FLAG_ERRORS

#define	SB_PCI_DMA 0x40000000

#define	BCM4400_PCI_CORE_ADDR 0x18002000

#define	B44_MIN_MTU 60

#define	B44_MAX_MTU 1500

#define	B44_RING_SIZE 8

#define	B44_RING_LAST ( B44_RING_SIZE - 1 )

#define	B44_RX_RING_LEN_BYTES ( sizeof bp->rx[0] * B44_RING_SIZE )

#define	B44_TX_RING_LEN_BYTES ( sizeof bp->tx[0] * B44_RING_SIZE )

#define	RX_PKT_OFFSET 30

#define	RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)

#define	B44_FULL_RESET 1

#define	B44_FULL_RESET_SKIP_PHY 2

#define	B44_PARTIAL_RESET 3

#define	B44_CHIP_RESET_FULL 4

#define	B44_CHIP_RESET_PARTIAL 5

#define	SSB_CORE_DOWN ( SBTMSLOW_RESET \| SBTMSLOW_REJECT )

#define	B44_REGS_SIZE 8192

Functions
	FILE_LICENCE (GPL2_OR_LATER)

static void	ssb_core_reset (struct b44_private *bp)

static void	ssb_core_disable (struct b44_private *bp)

static u32	ssb_pci_setup (struct b44_private *bp, u32 cores)

static void	b44_chip_reset (struct b44_private *bp, int reset_kind)

static void	b44_init_hw (struct b44_private *bp, int reset_kind)

static void	b44_cam_write (struct b44_private bp, u8 data, int index)

static void	b44_set_mac_addr (struct b44_private *bp)

static void	b44_set_rx_mode (struct net_device *netdev)

static void	b44_halt (struct b44_private *)

static int	b44_phy_reset (struct b44_private *bp)

static int	b44_phy_write (struct b44_private *bp, int reg, u32 val)

static int	b44_phy_read (struct b44_private bp, int reg, u32 val)

static int	b44_init_tx_ring (struct b44_private *bp)

static void	b44_free_tx_ring (struct b44_private *bp)

static int	b44_init_rx_ring (struct b44_private *bp)

static void	b44_free_rx_ring (struct b44_private *bp)

static void	b44_rx_refill (struct b44_private *bp, u32 pending)

static void	b44_populate_rx_descriptor (struct b44_private *bp, u32 index)

static int	b44_probe (struct pci_device *pci)

static void	b44_remove (struct pci_device *pci)

static int	b44_open (struct net_device *netdev)

static void	b44_close (struct net_device *netdev)

static void	b44_irq (struct net_device *netdev, int enable)

static void	b44_poll (struct net_device *netdev)

static void	b44_process_rx_packets (struct b44_private *bp)

static int	b44_transmit (struct net_device netdev, struct io_buffer iobuf)

Variables
static struct net_device_operations	b44_operations

Macro Definition Documentation

◆ _B44_H

#define _B44_H

Definition at line 35 of file b44.h.

◆ B44_DEVCTRL

#define B44_DEVCTRL 0x0000UL /* Device Control */

Definition at line 38 of file b44.h.

◆ DEVCTRL_MPM

#define DEVCTRL_MPM 0x00000040 /* MP PME Enable (B0 only) */

Definition at line 39 of file b44.h.

◆ DEVCTRL_PFE

#define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */

Definition at line 40 of file b44.h.

◆ DEVCTRL_IPP

#define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */

Definition at line 41 of file b44.h.

◆ DEVCTRL_EPR

#define DEVCTRL_EPR 0x00008000 /* EPHY Reset */

Definition at line 42 of file b44.h.

◆ DEVCTRL_PME

#define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */

Definition at line 43 of file b44.h.

◆ DEVCTRL_PMCE

#define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */

Definition at line 44 of file b44.h.

◆ DEVCTRL_PADDR

#define DEVCTRL_PADDR 0x0007c000 /* PHY Address */

Definition at line 45 of file b44.h.

◆ DEVCTRL_PADDR_SHIFT

#define DEVCTRL_PADDR_SHIFT 18

Definition at line 46 of file b44.h.

◆ B44_BIST_STAT

#define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */

Definition at line 47 of file b44.h.

◆ B44_WKUP_LEN

#define B44_WKUP_LEN 0x0010UL /* Wakeup Length */

Definition at line 48 of file b44.h.

◆ WKUP_LEN_P0_MASK

#define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */

Definition at line 49 of file b44.h.

◆ WKUP_LEN_D0

#define WKUP_LEN_D0 0x00000080

Definition at line 50 of file b44.h.

◆ WKUP_LEN_P1_MASK

#define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */

Definition at line 51 of file b44.h.

◆ WKUP_LEN_P1_SHIFT

#define WKUP_LEN_P1_SHIFT 8

Definition at line 52 of file b44.h.

◆ WKUP_LEN_D1

#define WKUP_LEN_D1 0x00008000

Definition at line 53 of file b44.h.

◆ WKUP_LEN_P2_MASK

#define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */

Definition at line 54 of file b44.h.

◆ WKUP_LEN_P2_SHIFT

#define WKUP_LEN_P2_SHIFT 16

Definition at line 55 of file b44.h.

◆ WKUP_LEN_D2

#define WKUP_LEN_D2 0x00000000

Definition at line 56 of file b44.h.

◆ WKUP_LEN_P3_MASK

#define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */

Definition at line 57 of file b44.h.

◆ WKUP_LEN_P3_SHIFT

#define WKUP_LEN_P3_SHIFT 24

Definition at line 58 of file b44.h.

◆ WKUP_LEN_D3

#define WKUP_LEN_D3 0x80000000

Definition at line 59 of file b44.h.

◆ WKUP_LEN_DISABLE

#define WKUP_LEN_DISABLE 0x80808080

Definition at line 60 of file b44.h.

◆ WKUP_LEN_ENABLE_TWO

#define WKUP_LEN_ENABLE_TWO 0x80800000

Definition at line 61 of file b44.h.

◆ WKUP_LEN_ENABLE_THREE

#define WKUP_LEN_ENABLE_THREE 0x80000000

Definition at line 62 of file b44.h.

◆ B44_ISTAT

#define B44_ISTAT 0x0020UL /* Interrupt Status */

Definition at line 63 of file b44.h.

◆ ISTAT_LS

#define ISTAT_LS 0x00000020 /* Link Change (B0 only) */

Definition at line 64 of file b44.h.

◆ ISTAT_PME

#define ISTAT_PME 0x00000040 /* Power Management Event */

Definition at line 65 of file b44.h.

◆ ISTAT_TO

#define ISTAT_TO 0x00000080 /* General Purpose Timeout */

Definition at line 66 of file b44.h.

◆ ISTAT_DSCE

#define ISTAT_DSCE 0x00000400 /* Descriptor Error */

Definition at line 67 of file b44.h.

◆ ISTAT_DATAE

#define ISTAT_DATAE 0x00000800 /* Data Error */

Definition at line 68 of file b44.h.

◆ ISTAT_DPE

#define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */

Definition at line 69 of file b44.h.

◆ ISTAT_RDU

#define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */

Definition at line 70 of file b44.h.

◆ ISTAT_RFO

#define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */

Definition at line 71 of file b44.h.

◆ ISTAT_TFU

#define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */

Definition at line 72 of file b44.h.

◆ ISTAT_RX

#define ISTAT_RX 0x00010000 /* RX Interrupt */

Definition at line 73 of file b44.h.

◆ ISTAT_TX

#define ISTAT_TX 0x01000000 /* TX Interrupt */

Definition at line 74 of file b44.h.

◆ ISTAT_EMAC

#define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */

Definition at line 75 of file b44.h.

◆ ISTAT_MII_WRITE

#define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */

Definition at line 76 of file b44.h.

◆ ISTAT_MII_READ

#define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */

Definition at line 77 of file b44.h.

◆ ISTAT_ERRORS

#define ISTAT_ERRORS

Value:

(ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|\

ISTAT_RDU|ISTAT_RFO|ISTAT_TFU)

ISTAT_RFO

#define ISTAT_RFO

Definition: b44.h:71

ISTAT_DPE

#define ISTAT_DPE

Definition: b44.h:69

ISTAT_DATAE

#define ISTAT_DATAE

Definition: b44.h:68

ISTAT_TFU

#define ISTAT_TFU

Definition: b44.h:72

ISTAT_DSCE

#define ISTAT_DSCE

Definition: b44.h:67

Definition at line 78 of file b44.h.

◆ B44_IMASK

#define B44_IMASK 0x0024UL /* Interrupt Mask */

Definition at line 80 of file b44.h.

◆ IMASK_DEF

#define IMASK_DEF (ISTAT_ERRORS | ISTAT_RX | ISTAT_TX)

Definition at line 81 of file b44.h.

◆ IMASK_DISABLE

#define IMASK_DISABLE 0

Definition at line 82 of file b44.h.

◆ B44_GPTIMER

#define B44_GPTIMER 0x0028UL /* General Purpose Timer */

Definition at line 83 of file b44.h.

◆ B44_ADDR_LO

#define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */

Definition at line 84 of file b44.h.

◆ B44_ADDR_HI

#define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */

Definition at line 85 of file b44.h.

◆ B44_FILT_ADDR

#define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */

Definition at line 86 of file b44.h.

◆ B44_FILT_DATA

#define B44_FILT_DATA 0x0094UL /* ENET Filter Data */

Definition at line 87 of file b44.h.

◆ B44_TXBURST

#define B44_TXBURST 0x00A0UL /* TX Max Burst Length */

Definition at line 88 of file b44.h.

◆ B44_RXBURST

#define B44_RXBURST 0x00A4UL /* RX Max Burst Length */

Definition at line 89 of file b44.h.

◆ B44_MAC_CTRL

#define B44_MAC_CTRL 0x00A8UL /* MAC Control */

Definition at line 90 of file b44.h.

◆ MAC_CTRL_CRC32_ENAB

#define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */

Definition at line 91 of file b44.h.

◆ MAC_CTRL_PHY_PDOWN

#define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */

Definition at line 92 of file b44.h.

◆ MAC_CTRL_PHY_EDET

#define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected*/

Definition at line 93 of file b44.h.

◆ MAC_CTRL_PHY_LEDCTRL

#define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */

Definition at line 94 of file b44.h.

◆ MAC_CTRL_PHY_LEDCTRL_SHIFT

#define MAC_CTRL_PHY_LEDCTRL_SHIFT 5

Definition at line 95 of file b44.h.

◆ B44_MAC_FLOW

#define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */

Definition at line 96 of file b44.h.

◆ MAC_FLOW_RX_HI_WATER

#define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */

Definition at line 97 of file b44.h.

◆ MAC_FLOW_PAUSE_ENAB

#define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enbl Pause Frm Generation */

Definition at line 98 of file b44.h.

◆ B44_RCV_LAZY

#define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */

Definition at line 99 of file b44.h.

◆ RCV_LAZY_TO_MASK

#define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */

Definition at line 100 of file b44.h.

◆ RCV_LAZY_FC_MASK

#define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */

Definition at line 101 of file b44.h.

◆ RCV_LAZY_FC_SHIFT

#define RCV_LAZY_FC_SHIFT 24

Definition at line 102 of file b44.h.

◆ B44_DMATX_CTRL

#define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */

Definition at line 103 of file b44.h.

◆ DMATX_CTRL_ENABLE

#define DMATX_CTRL_ENABLE 0x00000001 /* Enable */

Definition at line 104 of file b44.h.

◆ DMATX_CTRL_SUSPEND

#define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */

Definition at line 105 of file b44.h.

◆ DMATX_CTRL_LPBACK

#define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */

Definition at line 106 of file b44.h.

◆ DMATX_CTRL_FAIRPRIOR

#define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */

Definition at line 107 of file b44.h.

◆ DMATX_CTRL_FLUSH

#define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */

Definition at line 108 of file b44.h.

◆ B44_DMATX_ADDR

#define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Addr */

Definition at line 109 of file b44.h.

◆ B44_DMATX_PTR

#define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Desc. */

Definition at line 110 of file b44.h.

◆ B44_DMATX_STAT

#define B44_DMATX_STAT 0x020CUL /* DMA TX Cur Actve Desc. + Sts */

Definition at line 111 of file b44.h.

◆ DMATX_STAT_CDMASK

#define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */

Definition at line 112 of file b44.h.

◆ DMATX_STAT_SMASK

#define DMATX_STAT_SMASK 0x0000f000 /* State Mask */

Definition at line 113 of file b44.h.

◆ DMATX_STAT_SDISABLED

#define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */

Definition at line 114 of file b44.h.

◆ DMATX_STAT_SACTIVE

#define DMATX_STAT_SACTIVE 0x00001000 /* State Active */

Definition at line 115 of file b44.h.

◆ DMATX_STAT_SIDLE

#define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */

Definition at line 116 of file b44.h.

◆ DMATX_STAT_SSTOPPED

#define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */

Definition at line 117 of file b44.h.

◆ DMATX_STAT_SSUSP

#define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */

Definition at line 118 of file b44.h.

◆ DMATX_STAT_EMASK

#define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */

Definition at line 119 of file b44.h.

◆ DMATX_STAT_ENONE

#define DMATX_STAT_ENONE 0x00000000 /* Error None */

Definition at line 120 of file b44.h.

◆ DMATX_STAT_EDPE

#define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */

Definition at line 121 of file b44.h.

◆ DMATX_STAT_EDFU

#define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */

Definition at line 122 of file b44.h.

◆ DMATX_STAT_EBEBR

#define DMATX_STAT_EBEBR 0x00030000 /* Bus Error on Buffer Read */

Definition at line 123 of file b44.h.

◆ DMATX_STAT_EBEDA

#define DMATX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */

Definition at line 124 of file b44.h.

◆ DMATX_STAT_FLUSHED

#define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */

Definition at line 125 of file b44.h.

◆ B44_DMARX_CTRL

#define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */

Definition at line 126 of file b44.h.

◆ DMARX_CTRL_ENABLE

#define DMARX_CTRL_ENABLE 0x00000001 /* Enable */

Definition at line 127 of file b44.h.

◆ DMARX_CTRL_ROMASK

#define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */

Definition at line 128 of file b44.h.

◆ DMARX_CTRL_ROSHIFT

#define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */

Definition at line 129 of file b44.h.

◆ B44_DMARX_ADDR

#define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Addr */

Definition at line 130 of file b44.h.

◆ B44_DMARX_PTR

#define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Desc */

Definition at line 131 of file b44.h.

◆ B44_DMARX_STAT

#define B44_DMARX_STAT 0x021CUL /* Cur Active Desc. + Status */

Definition at line 132 of file b44.h.

◆ DMARX_STAT_CDMASK

#define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */

Definition at line 133 of file b44.h.

◆ DMARX_STAT_SMASK

#define DMARX_STAT_SMASK 0x0000f000 /* State Mask */

Definition at line 134 of file b44.h.

◆ DMARX_STAT_SDISABLED

#define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */

Definition at line 135 of file b44.h.

◆ DMARX_STAT_SACTIVE

#define DMARX_STAT_SACTIVE 0x00001000 /* State Active */

Definition at line 136 of file b44.h.

◆ DMARX_STAT_SIDLE

#define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */

Definition at line 137 of file b44.h.

◆ DMARX_STAT_SSTOPPED

#define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */

Definition at line 138 of file b44.h.

◆ DMARX_STAT_EMASK

#define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */

Definition at line 139 of file b44.h.

◆ DMARX_STAT_ENONE

#define DMARX_STAT_ENONE 0x00000000 /* Error None */

Definition at line 140 of file b44.h.

◆ DMARX_STAT_EDPE

#define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */

Definition at line 141 of file b44.h.

◆ DMARX_STAT_EDFO

#define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */

Definition at line 142 of file b44.h.

◆ DMARX_STAT_EBEBW

#define DMARX_STAT_EBEBW 0x00030000 /* Error on Buffer Write */

Definition at line 143 of file b44.h.

◆ DMARX_STAT_EBEDA

#define DMARX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */

Definition at line 144 of file b44.h.

◆ B44_DMAFIFO_AD

#define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */

Definition at line 145 of file b44.h.

◆ DMAFIFO_AD_OMASK

#define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */

Definition at line 146 of file b44.h.

◆ DMAFIFO_AD_SMASK

#define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */

Definition at line 147 of file b44.h.

◆ DMAFIFO_AD_SXDD

#define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */

Definition at line 148 of file b44.h.

◆ DMAFIFO_AD_SXDP

#define DMAFIFO_AD_SXDP 0x00010000 /* Sel Transmit DMA Pointers */

Definition at line 149 of file b44.h.

◆ DMAFIFO_AD_SRDD

#define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */

Definition at line 150 of file b44.h.

◆ DMAFIFO_AD_SRDP

#define DMAFIFO_AD_SRDP 0x00050000 /* Sel Receive DMA Pointers */

Definition at line 151 of file b44.h.

◆ DMAFIFO_AD_SXFD

#define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */

Definition at line 152 of file b44.h.

◆ DMAFIFO_AD_SXFP

#define DMAFIFO_AD_SXFP 0x00090000 /* Sel Transmit FIFO Pointers */

Definition at line 153 of file b44.h.

◆ DMAFIFO_AD_SRFD

#define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */

Definition at line 154 of file b44.h.

◆ DMAFIFO_AD_SRFP

#define DMAFIFO_AD_SRFP 0x000c0000 /* Sel Receive FIFO Pointers */

Definition at line 155 of file b44.h.

◆ B44_DMAFIFO_LO

#define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */

Definition at line 156 of file b44.h.

◆ B44_DMAFIFO_HI

#define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */

Definition at line 157 of file b44.h.

◆ B44_RXCONFIG

#define B44_RXCONFIG 0x0400UL /* EMAC RX Config */

Definition at line 158 of file b44.h.

◆ RXCONFIG_DBCAST

#define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */

Definition at line 159 of file b44.h.

◆ RXCONFIG_ALLMULTI

#define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */

Definition at line 160 of file b44.h.

◆ RXCONFIG_NORX_WHILE_TX

#define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Rcv Disble While TX */

Definition at line 161 of file b44.h.

◆ RXCONFIG_PROMISC

#define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */

Definition at line 162 of file b44.h.

◆ RXCONFIG_LPBACK

#define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */

Definition at line 163 of file b44.h.

◆ RXCONFIG_FLOW

#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */

Definition at line 164 of file b44.h.

◆ RXCONFIG_FLOW_ACCEPT

#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept UFC Frame */

Definition at line 165 of file b44.h.

◆ RXCONFIG_RFILT

#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */

Definition at line 166 of file b44.h.

◆ B44_RXMAXLEN

#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */

Definition at line 167 of file b44.h.

◆ B44_TXMAXLEN

#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */

Definition at line 168 of file b44.h.

◆ B44_MDIO_CTRL

#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */

Definition at line 169 of file b44.h.

◆ MDIO_CTRL_MAXF_MASK

#define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */

Definition at line 170 of file b44.h.

◆ MDIO_CTRL_PREAMBLE

#define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */

Definition at line 171 of file b44.h.

◆ B44_MDIO_DATA

#define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */

Definition at line 172 of file b44.h.

◆ MDIO_DATA_DATA

#define MDIO_DATA_DATA 0x0000ffff /* R/W Data */

Definition at line 173 of file b44.h.

◆ MDIO_DATA_TA_MASK

#define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */

Definition at line 174 of file b44.h.

◆ MDIO_DATA_TA_SHIFT

#define MDIO_DATA_TA_SHIFT 16

Definition at line 175 of file b44.h.

◆ MDIO_TA_VALID

#define MDIO_TA_VALID 2

Definition at line 176 of file b44.h.

◆ MDIO_DATA_RA_MASK

#define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */

Definition at line 177 of file b44.h.

◆ MDIO_DATA_RA_SHIFT

#define MDIO_DATA_RA_SHIFT 18

Definition at line 178 of file b44.h.

◆ MDIO_DATA_PMD_MASK

#define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */

Definition at line 179 of file b44.h.

◆ MDIO_DATA_PMD_SHIFT

#define MDIO_DATA_PMD_SHIFT 23

Definition at line 180 of file b44.h.

◆ MDIO_DATA_OP_MASK

#define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */

Definition at line 181 of file b44.h.

◆ MDIO_DATA_OP_SHIFT

#define MDIO_DATA_OP_SHIFT 28

Definition at line 182 of file b44.h.

◆ MDIO_OP_WRITE

#define MDIO_OP_WRITE 1

Definition at line 183 of file b44.h.

◆ MDIO_OP_READ

#define MDIO_OP_READ 2

Definition at line 184 of file b44.h.

◆ MDIO_DATA_SB_MASK

#define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */

Definition at line 185 of file b44.h.

◆ MDIO_DATA_SB_SHIFT

#define MDIO_DATA_SB_SHIFT 30

Definition at line 186 of file b44.h.

◆ MDIO_DATA_SB_START

#define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */

Definition at line 187 of file b44.h.

◆ B44_EMAC_IMASK

#define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */

Definition at line 188 of file b44.h.

◆ B44_EMAC_ISTAT

#define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */

Definition at line 189 of file b44.h.

◆ EMAC_INT_MII

#define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */

Definition at line 190 of file b44.h.

◆ EMAC_INT_MIB

#define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */

Definition at line 191 of file b44.h.

◆ EMAC_INT_FLOW

#define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */

Definition at line 192 of file b44.h.

◆ B44_CAM_DATA_LO

#define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */

Definition at line 193 of file b44.h.

◆ B44_CAM_DATA_HI

#define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */

Definition at line 194 of file b44.h.

◆ CAM_DATA_HI_VALID

#define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */

Definition at line 195 of file b44.h.

◆ B44_CAM_CTRL

#define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */

Definition at line 196 of file b44.h.

◆ CAM_CTRL_ENABLE

#define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */

Definition at line 197 of file b44.h.

◆ CAM_CTRL_MSEL

#define CAM_CTRL_MSEL 0x00000002 /* Mask Select */

Definition at line 198 of file b44.h.

◆ CAM_CTRL_READ

#define CAM_CTRL_READ 0x00000004 /* Read */

Definition at line 199 of file b44.h.

◆ CAM_CTRL_WRITE

#define CAM_CTRL_WRITE 0x00000008 /* Read */

Definition at line 200 of file b44.h.

◆ CAM_CTRL_INDEX_MASK

#define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */

Definition at line 201 of file b44.h.

◆ CAM_CTRL_INDEX_SHIFT

#define CAM_CTRL_INDEX_SHIFT 16

Definition at line 202 of file b44.h.

◆ CAM_CTRL_BUSY

#define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */

Definition at line 203 of file b44.h.

◆ B44_ENET_CTRL

#define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */

Definition at line 204 of file b44.h.

◆ ENET_CTRL_ENABLE

#define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */

Definition at line 205 of file b44.h.

◆ ENET_CTRL_DISABLE

#define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */

Definition at line 206 of file b44.h.

◆ ENET_CTRL_SRST

#define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */

Definition at line 207 of file b44.h.

◆ ENET_CTRL_EPSEL

#define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */

Definition at line 208 of file b44.h.

◆ B44_TX_CTRL

#define B44_TX_CTRL 0x0430UL /* EMAC TX Control */

Definition at line 209 of file b44.h.

◆ TX_CTRL_DUPLEX

#define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */

Definition at line 210 of file b44.h.

◆ TX_CTRL_FMODE

#define TX_CTRL_FMODE 0x00000002 /* Flow Mode */

Definition at line 211 of file b44.h.

◆ TX_CTRL_SBENAB

#define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */

Definition at line 212 of file b44.h.

◆ TX_CTRL_SMALL_SLOT

#define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */

Definition at line 213 of file b44.h.

◆ B44_TX_HIWMARK

#define B44_TX_HIWMARK 0x0434UL /* EMAC TX High Watermark */

Definition at line 214 of file b44.h.

◆ TX_HIWMARK_DEFLT

#define TX_HIWMARK_DEFLT 56 /* Default used in all drivers */

Definition at line 215 of file b44.h.

◆ B44_MIB_CTRL

#define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */

Definition at line 216 of file b44.h.

◆ MIB_CTRL_CLR_ON_READ

#define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */

Definition at line 217 of file b44.h.

◆ B44_TX_GOOD_O

#define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */

Definition at line 218 of file b44.h.

◆ B44_TX_GOOD_P

#define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */

Definition at line 219 of file b44.h.

◆ B44_TX_O

#define B44_TX_O 0x0508UL /* MIB TX Octets */

Definition at line 220 of file b44.h.

◆ B44_TX_P

#define B44_TX_P 0x050CUL /* MIB TX Packets */

Definition at line 221 of file b44.h.

◆ B44_TX_BCAST

#define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */

Definition at line 222 of file b44.h.

◆ B44_TX_MCAST

#define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */

Definition at line 223 of file b44.h.

◆ B44_TX_64

#define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */

Definition at line 224 of file b44.h.

◆ B44_TX_65_127

#define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Pkts */

Definition at line 225 of file b44.h.

◆ B44_TX_128_255

#define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Pkts */

Definition at line 226 of file b44.h.

◆ B44_TX_256_511

#define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Pkts */

Definition at line 227 of file b44.h.

◆ B44_TX_512_1023

#define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Pkts */

Definition at line 228 of file b44.h.

◆ B44_TX_1024_MAX

#define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Pkts */

Definition at line 229 of file b44.h.

◆ B44_TX_JABBER

#define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */

Definition at line 230 of file b44.h.

◆ B44_TX_OSIZE

#define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */

Definition at line 231 of file b44.h.

◆ B44_TX_FRAG

#define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */

Definition at line 232 of file b44.h.

◆ B44_TX_URUNS

#define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */

Definition at line 233 of file b44.h.

◆ B44_TX_TCOLS

#define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */

Definition at line 234 of file b44.h.

◆ B44_TX_SCOLS

#define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */

Definition at line 235 of file b44.h.

◆ B44_TX_MCOLS

#define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */

Definition at line 236 of file b44.h.

◆ B44_TX_ECOLS

#define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */

Definition at line 237 of file b44.h.

◆ B44_TX_LCOLS

#define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */

Definition at line 238 of file b44.h.

◆ B44_TX_DEFERED

#define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */

Definition at line 239 of file b44.h.

◆ B44_TX_CLOST

#define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */

Definition at line 240 of file b44.h.

◆ B44_TX_PAUSE

#define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */

Definition at line 241 of file b44.h.

◆ B44_RX_GOOD_O

#define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */

Definition at line 242 of file b44.h.

◆ B44_RX_GOOD_P

#define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */

Definition at line 243 of file b44.h.

◆ B44_RX_O

#define B44_RX_O 0x0588UL /* MIB RX Octets */

Definition at line 244 of file b44.h.

◆ B44_RX_P

#define B44_RX_P 0x058CUL /* MIB RX Packets */

Definition at line 245 of file b44.h.

◆ B44_RX_BCAST

#define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */

Definition at line 246 of file b44.h.

◆ B44_RX_MCAST

#define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */

Definition at line 247 of file b44.h.

◆ B44_RX_64

#define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */

Definition at line 248 of file b44.h.

◆ B44_RX_65_127

#define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Pkts */

Definition at line 249 of file b44.h.

◆ B44_RX_128_255

#define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Pkts */

Definition at line 250 of file b44.h.

◆ B44_RX_256_511

#define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Pkts */

Definition at line 251 of file b44.h.

◆ B44_RX_512_1023

#define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Pkts */

Definition at line 252 of file b44.h.

◆ B44_RX_1024_MAX

#define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Pkts */

Definition at line 253 of file b44.h.

◆ B44_RX_JABBER

#define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */

Definition at line 254 of file b44.h.

◆ B44_RX_OSIZE

#define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */

Definition at line 255 of file b44.h.

◆ B44_RX_FRAG

#define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */

Definition at line 256 of file b44.h.

◆ B44_RX_MISS

#define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */

Definition at line 257 of file b44.h.

◆ B44_RX_CRCA

#define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */

Definition at line 258 of file b44.h.

◆ B44_RX_USIZE

#define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */

Definition at line 259 of file b44.h.

◆ B44_RX_CRC

#define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */

Definition at line 260 of file b44.h.

◆ B44_RX_ALIGN

#define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */

Definition at line 261 of file b44.h.

◆ B44_RX_SYM

#define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */

Definition at line 262 of file b44.h.

◆ B44_RX_PAUSE

#define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */

Definition at line 263 of file b44.h.

◆ B44_RX_NPAUSE

#define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */

Definition at line 264 of file b44.h.

◆ B44_SBIMSTATE

#define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */

Definition at line 267 of file b44.h.

◆ SBIMSTATE_PC

#define SBIMSTATE_PC 0x0000000f /* Pipe Count */

Definition at line 268 of file b44.h.

◆ SBIMSTATE_AP_MASK

#define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */

Definition at line 269 of file b44.h.

◆ SBIMSTATE_AP_BOTH

#define SBIMSTATE_AP_BOTH 0x00000000 /* both timeslices and token */

Definition at line 270 of file b44.h.

◆ SBIMSTATE_AP_TS

#define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */

Definition at line 271 of file b44.h.

◆ SBIMSTATE_AP_TK

#define SBIMSTATE_AP_TK 0x00000020 /* Use token only */

Definition at line 272 of file b44.h.

◆ SBIMSTATE_AP_RSV

#define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */

Definition at line 273 of file b44.h.

◆ SBIMSTATE_IBE

#define SBIMSTATE_IBE 0x00020000 /* In Band Error */

Definition at line 274 of file b44.h.

◆ SBIMSTATE_TO

#define SBIMSTATE_TO 0x00040000 /* Timeout */

Definition at line 275 of file b44.h.

◆ SBIMSTATE_BAD

#define SBIMSTATE_BAD ( SBIMSTATE_IBE | SBIMSTATE_TO )

Definition at line 276 of file b44.h.

◆ B44_SBINTVEC

#define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */

Definition at line 277 of file b44.h.

◆ SBINTVEC_PCI

#define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */

Definition at line 278 of file b44.h.

◆ SBINTVEC_ENET0

#define SBINTVEC_ENET0 0x00000002 /* Enable ints for enet 0 */

Definition at line 279 of file b44.h.

◆ SBINTVEC_ILINE20

#define SBINTVEC_ILINE20 0x00000004 /* Enable ints for iline20 */

Definition at line 280 of file b44.h.

◆ SBINTVEC_CODEC

#define SBINTVEC_CODEC 0x00000008 /* Enable ints for v90 codec */

Definition at line 281 of file b44.h.

◆ SBINTVEC_USB

#define SBINTVEC_USB 0x00000010 /* Enable intts for usb */

Definition at line 282 of file b44.h.

◆ SBINTVEC_EXTIF

#define SBINTVEC_EXTIF 0x00000020 /* Enable ints for ext i/f */

Definition at line 283 of file b44.h.

◆ SBINTVEC_ENET1

#define SBINTVEC_ENET1 0x00000040 /* Enable ints for enet 1 */

Definition at line 284 of file b44.h.

◆ B44_SBTMSLOW

#define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */

Definition at line 285 of file b44.h.

◆ SBTMSLOW_RESET

#define SBTMSLOW_RESET 0x00000001 /* Reset */

Definition at line 286 of file b44.h.

◆ SBTMSLOW_REJECT

#define SBTMSLOW_REJECT 0x00000002 /* Reject */

Definition at line 287 of file b44.h.

◆ SBTMSLOW_CLOCK

#define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */

Definition at line 288 of file b44.h.

◆ SBTMSLOW_FGC

#define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */

Definition at line 289 of file b44.h.

◆ SBTMSLOW_PE

#define SBTMSLOW_PE 0x40000000 /* Power Management Enable */

Definition at line 290 of file b44.h.

◆ SBTMSLOW_BE

#define SBTMSLOW_BE 0x80000000 /* BIST Enable */

Definition at line 291 of file b44.h.

◆ B44_SBTMSHIGH

#define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */

Definition at line 292 of file b44.h.

◆ SBTMSHIGH_SERR

#define SBTMSHIGH_SERR 0x00000001 /* S-error */

Definition at line 293 of file b44.h.

◆ SBTMSHIGH_INT

#define SBTMSHIGH_INT 0x00000002 /* Interrupt */

Definition at line 294 of file b44.h.

◆ SBTMSHIGH_BUSY

#define SBTMSHIGH_BUSY 0x00000004 /* Busy */

Definition at line 295 of file b44.h.

◆ SBTMSHIGH_GCR

#define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */

Definition at line 296 of file b44.h.

◆ SBTMSHIGH_BISTF

#define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */

Definition at line 297 of file b44.h.

◆ SBTMSHIGH_BISTD

#define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */

Definition at line 298 of file b44.h.

◆ B44_SBIDHIGH

#define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */

Definition at line 299 of file b44.h.

◆ SBIDHIGH_RC_MASK

#define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */

Definition at line 300 of file b44.h.

◆ SBIDHIGH_CC_MASK

#define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */

Definition at line 301 of file b44.h.

◆ SBIDHIGH_CC_SHIFT

#define SBIDHIGH_CC_SHIFT 4

Definition at line 302 of file b44.h.

◆ SBIDHIGH_VC_MASK

#define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */

Definition at line 303 of file b44.h.

◆ SBIDHIGH_VC_SHIFT

#define SBIDHIGH_VC_SHIFT 16

Definition at line 304 of file b44.h.

◆ SSB_PMCSR

#define SSB_PMCSR 0x44

Definition at line 307 of file b44.h.

◆ SSB_PE

#define SSB_PE 0x100

Definition at line 308 of file b44.h.

◆ SSB_BAR0_WIN

#define SSB_BAR0_WIN 0x80

Definition at line 309 of file b44.h.

◆ SSB_BAR1_WIN

#define SSB_BAR1_WIN 0x84

Definition at line 310 of file b44.h.

◆ SSB_SPROM_CONTROL

#define SSB_SPROM_CONTROL 0x88

Definition at line 311 of file b44.h.

◆ SSB_BAR1_CONTROL

#define SSB_BAR1_CONTROL 0x8c

Definition at line 312 of file b44.h.

◆ SSB_CONTROL

#define SSB_CONTROL 0x0000UL

Definition at line 315 of file b44.h.

◆ SSB_ARBCONTROL

#define SSB_ARBCONTROL 0x0010UL

Definition at line 316 of file b44.h.

◆ SSB_ISTAT

#define SSB_ISTAT 0x0020UL

Definition at line 317 of file b44.h.

◆ SSB_IMASK

#define SSB_IMASK 0x0024UL

Definition at line 318 of file b44.h.

◆ SSB_MBOX

#define SSB_MBOX 0x0028UL

Definition at line 319 of file b44.h.

◆ SSB_BCAST_ADDR

#define SSB_BCAST_ADDR 0x0050UL

Definition at line 320 of file b44.h.

◆ SSB_BCAST_DATA

#define SSB_BCAST_DATA 0x0054UL

Definition at line 321 of file b44.h.

◆ SSB_PCI_TRANS_0

#define SSB_PCI_TRANS_0 0x0100UL

Definition at line 322 of file b44.h.

◆ SSB_PCI_TRANS_1

#define SSB_PCI_TRANS_1 0x0104UL

Definition at line 323 of file b44.h.

◆ SSB_PCI_TRANS_2

#define SSB_PCI_TRANS_2 0x0108UL

Definition at line 324 of file b44.h.

◆ SSB_SPROM

#define SSB_SPROM 0x0800UL

Definition at line 325 of file b44.h.

◆ SSB_PCI_MEM

#define SSB_PCI_MEM 0x00000000

Definition at line 327 of file b44.h.

◆ SSB_PCI_IO

#define SSB_PCI_IO 0x00000001

Definition at line 328 of file b44.h.

◆ SSB_PCI_CFG0

#define SSB_PCI_CFG0 0x00000002

Definition at line 329 of file b44.h.

◆ SSB_PCI_CFG1

#define SSB_PCI_CFG1 0x00000003

Definition at line 330 of file b44.h.

◆ SSB_PCI_PREF

#define SSB_PCI_PREF 0x00000004

Definition at line 331 of file b44.h.

◆ SSB_PCI_BURST

#define SSB_PCI_BURST 0x00000008

Definition at line 332 of file b44.h.

◆ SSB_PCI_MASK0

#define SSB_PCI_MASK0 0xfc000000

Definition at line 333 of file b44.h.

◆ SSB_PCI_MASK1

#define SSB_PCI_MASK1 0xfc000000

Definition at line 334 of file b44.h.

◆ SSB_PCI_MASK2

#define SSB_PCI_MASK2 0xc0000000

Definition at line 335 of file b44.h.

◆ B44_MII_AUXCTRL

#define B44_MII_AUXCTRL 24 /* Auxiliary Control */

Definition at line 338 of file b44.h.

◆ MII_AUXCTRL_DUPLEX

#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */

Definition at line 339 of file b44.h.

◆ MII_AUXCTRL_SPEED

#define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */

Definition at line 340 of file b44.h.

◆ MII_AUXCTRL_FORCED

#define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */

Definition at line 341 of file b44.h.

◆ B44_MII_ALEDCTRL

#define B44_MII_ALEDCTRL 26 /* Activity LED */

Definition at line 342 of file b44.h.

◆ MII_ALEDCTRL_ALLMSK

#define MII_ALEDCTRL_ALLMSK 0x7fff

Definition at line 343 of file b44.h.

◆ B44_MII_TLEDCTRL

#define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */

Definition at line 344 of file b44.h.

◆ MII_TLEDCTRL_ENABLE

#define MII_TLEDCTRL_ENABLE 0x0040

Definition at line 345 of file b44.h.

◆ B44_DMA_ALIGNMENT

#define B44_DMA_ALIGNMENT 4096

Definition at line 356 of file b44.h.

◆ B44_30BIT_DMA_MASK

#define B44_30BIT_DMA_MASK 0x3fffffff

Definition at line 360 of file b44.h.

◆ DESC_CTRL_LEN

#define DESC_CTRL_LEN 0x00001fff

Definition at line 362 of file b44.h.

◆ DESC_CTRL_CMASK

#define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */

Definition at line 363 of file b44.h.

◆ DESC_CTRL_EOT

#define DESC_CTRL_EOT 0x10000000 /* End of Table */

Definition at line 364 of file b44.h.

◆ DESC_CTRL_IOC

#define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */

Definition at line 365 of file b44.h.

◆ DESC_CTRL_EOF

#define DESC_CTRL_EOF 0x40000000 /* End of Frame */

Definition at line 366 of file b44.h.

◆ DESC_CTRL_SOF

#define DESC_CTRL_SOF 0x80000000 /* Start of Frame */

Definition at line 367 of file b44.h.

◆ RX_HEADER_LEN

#define RX_HEADER_LEN 28

Definition at line 374 of file b44.h.

◆ RX_FLAG_OFIFO

#define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */

Definition at line 376 of file b44.h.

◆ RX_FLAG_CRCERR

#define RX_FLAG_CRCERR 0x00000002 /* CRC Error */

Definition at line 377 of file b44.h.

◆ RX_FLAG_SERR

#define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */

Definition at line 378 of file b44.h.

◆ RX_FLAG_ODD

#define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */

Definition at line 379 of file b44.h.

◆ RX_FLAG_LARGE

#define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */

Definition at line 380 of file b44.h.

◆ RX_FLAG_MCAST

#define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */

Definition at line 381 of file b44.h.

◆ RX_FLAG_BCAST

#define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */

Definition at line 382 of file b44.h.

◆ RX_FLAG_MISS

#define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */

Definition at line 383 of file b44.h.

◆ RX_FLAG_LAST

#define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */

Definition at line 384 of file b44.h.

◆ RX_FLAG_ERRORS

#define RX_FLAG_ERRORS

Value:

(RX_FLAG_ODD | RX_FLAG_SERR |\

RX_FLAG_CRCERR | RX_FLAG_OFIFO)

RX_FLAG_SERR

#define RX_FLAG_SERR

Definition: b44.h:378

RX_FLAG_ODD

#define RX_FLAG_ODD

Definition: b44.h:379

RX_FLAG_OFIFO

#define RX_FLAG_OFIFO

Definition: b44.h:376

Definition at line 385 of file b44.h.

◆ SB_PCI_DMA

#define SB_PCI_DMA 0x40000000

Definition at line 389 of file b44.h.

◆ BCM4400_PCI_CORE_ADDR

#define BCM4400_PCI_CORE_ADDR 0x18002000

Definition at line 392 of file b44.h.

◆ B44_MIN_MTU

#define B44_MIN_MTU 60

Definition at line 395 of file b44.h.

◆ B44_MAX_MTU

#define B44_MAX_MTU 1500

Definition at line 396 of file b44.h.

◆ B44_RING_SIZE

#define B44_RING_SIZE 8

Definition at line 398 of file b44.h.

◆ B44_RING_LAST

#define B44_RING_LAST ( B44_RING_SIZE - 1 )

Definition at line 399 of file b44.h.

◆ B44_RX_RING_LEN_BYTES

#define B44_RX_RING_LEN_BYTES ( sizeof bp->rx[0] * B44_RING_SIZE )

Definition at line 401 of file b44.h.

◆ B44_TX_RING_LEN_BYTES

#define B44_TX_RING_LEN_BYTES ( sizeof bp->tx[0] * B44_RING_SIZE )

Definition at line 402 of file b44.h.

◆ RX_PKT_OFFSET

#define RX_PKT_OFFSET 30

Definition at line 404 of file b44.h.

◆ RX_PKT_BUF_SZ

#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)

Definition at line 405 of file b44.h.

◆ B44_FULL_RESET

#define B44_FULL_RESET 1

Definition at line 407 of file b44.h.

◆ B44_FULL_RESET_SKIP_PHY

#define B44_FULL_RESET_SKIP_PHY 2

Definition at line 408 of file b44.h.

◆ B44_PARTIAL_RESET

#define B44_PARTIAL_RESET 3

Definition at line 409 of file b44.h.

◆ B44_CHIP_RESET_FULL

#define B44_CHIP_RESET_FULL 4

Definition at line 410 of file b44.h.

◆ B44_CHIP_RESET_PARTIAL

#define B44_CHIP_RESET_PARTIAL 5

Definition at line 411 of file b44.h.

◆ SSB_CORE_DOWN

#define SSB_CORE_DOWN ( SBTMSLOW_RESET | SBTMSLOW_REJECT )

Definition at line 413 of file b44.h.

◆ B44_REGS_SIZE

#define B44_REGS_SIZE 8192

Definition at line 415 of file b44.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER )

◆ ssb_core_reset()

static void ssb_core_reset ( struct b44_private * bp )

static

◆ ssb_core_disable()

static void ssb_core_disable ( struct b44_private * bp )

static

◆ ssb_pci_setup()

static u32 ssb_pci_setup	(	struct b44_private *	bp,
		u32	cores
	)

static

◆ b44_chip_reset()

static void b44_chip_reset	(	struct b44_private *	bp,
		int	reset_kind
	)

static

◆ b44_init_hw()

static void b44_init_hw	(	struct b44_private *	bp,
		int	reset_kind
	)

static

◆ b44_cam_write()

static void b44_cam_write	(	struct b44_private *	bp,
		u8 *	data,
		int	index
	)

static

◆ b44_set_mac_addr()

static void b44_set_mac_addr ( struct b44_private * bp )

static

◆ b44_set_rx_mode()

static void b44_set_rx_mode ( struct net_device * netdev )

static

◆ b44_halt()

static void b44_halt ( struct b44_private * )

static

◆ b44_phy_reset()

static int b44_phy_reset ( struct b44_private * bp )

static

◆ b44_phy_write()

static int b44_phy_write	(	struct b44_private *	bp,
		int	reg,
		u32	val
	)

static

◆ b44_phy_read()

static int b44_phy_read	(	struct b44_private *	bp,
		int	reg,
		u32 *	val
	)

static

◆ b44_init_tx_ring()

static int b44_init_tx_ring ( struct b44_private * bp )

static

◆ b44_free_tx_ring()

static void b44_free_tx_ring ( struct b44_private * bp )

static

◆ b44_init_rx_ring()

static int b44_init_rx_ring ( struct b44_private * bp )

static

◆ b44_free_rx_ring()

static void b44_free_rx_ring ( struct b44_private * bp )

static

◆ b44_rx_refill()

static void b44_rx_refill	(	struct b44_private *	bp,
		u32	pending
	)

static

◆ b44_populate_rx_descriptor()

static void b44_populate_rx_descriptor	(	struct b44_private *	bp,
		u32	index
	)

static

◆ b44_probe()

static int b44_probe ( struct pci_device * pci )

static

◆ b44_remove()

static void b44_remove ( struct pci_device * pci )

static

◆ b44_open()

static int b44_open ( struct net_device * netdev )

static

◆ b44_close()

static void b44_close ( struct net_device * netdev )

static

◆ b44_irq()

static void b44_irq	(	struct net_device *	netdev,
		int	enable
	)

static

◆ b44_poll()

static void b44_poll ( struct net_device * netdev )

static

◆ b44_process_rx_packets()

static void b44_process_rx_packets ( struct b44_private * bp )

static

◆ b44_transmit()

static int b44_transmit	(	struct net_device *	netdev,
		struct io_buffer *	iobuf
	)

static

Variable Documentation

◆ b44_operations

struct net_device_operations b44_operations

static

Definition at line 468 of file b44.h.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

◆ _B44_H

◆ B44_DEVCTRL

◆ DEVCTRL_MPM

◆ DEVCTRL_PFE

◆ DEVCTRL_IPP

◆ DEVCTRL_EPR

◆ DEVCTRL_PME

◆ DEVCTRL_PMCE

◆ DEVCTRL_PADDR

◆ DEVCTRL_PADDR_SHIFT

◆ B44_BIST_STAT

◆ B44_WKUP_LEN

◆ WKUP_LEN_P0_MASK

◆ WKUP_LEN_D0

◆ WKUP_LEN_P1_MASK

◆ WKUP_LEN_P1_SHIFT

◆ WKUP_LEN_D1

◆ WKUP_LEN_P2_MASK

◆ WKUP_LEN_P2_SHIFT

◆ WKUP_LEN_D2

◆ WKUP_LEN_P3_MASK

◆ WKUP_LEN_P3_SHIFT

◆ WKUP_LEN_D3

◆ WKUP_LEN_DISABLE

◆ WKUP_LEN_ENABLE_TWO

◆ WKUP_LEN_ENABLE_THREE

◆ B44_ISTAT

◆ ISTAT_LS

◆ ISTAT_PME

◆ ISTAT_TO

◆ ISTAT_DSCE

◆ ISTAT_DATAE

◆ ISTAT_DPE

◆ ISTAT_RDU

◆ ISTAT_RFO

◆ ISTAT_TFU

◆ ISTAT_RX

◆ ISTAT_TX

◆ ISTAT_EMAC

◆ ISTAT_MII_WRITE

◆ ISTAT_MII_READ

◆ ISTAT_ERRORS

◆ B44_IMASK

◆ IMASK_DEF

◆ IMASK_DISABLE

◆ B44_GPTIMER

◆ B44_ADDR_LO

◆ B44_ADDR_HI

◆ B44_FILT_ADDR

◆ B44_FILT_DATA

◆ B44_TXBURST

◆ B44_RXBURST

◆ B44_MAC_CTRL

◆ MAC_CTRL_CRC32_ENAB

◆ MAC_CTRL_PHY_PDOWN

◆ MAC_CTRL_PHY_EDET

◆ MAC_CTRL_PHY_LEDCTRL

◆ MAC_CTRL_PHY_LEDCTRL_SHIFT

◆ B44_MAC_FLOW

◆ MAC_FLOW_RX_HI_WATER

◆ MAC_FLOW_PAUSE_ENAB

◆ B44_RCV_LAZY

◆ RCV_LAZY_TO_MASK

◆ RCV_LAZY_FC_MASK

◆ RCV_LAZY_FC_SHIFT

◆ B44_DMATX_CTRL

◆ DMATX_CTRL_ENABLE

◆ DMATX_CTRL_SUSPEND

◆ DMATX_CTRL_LPBACK

◆ DMATX_CTRL_FAIRPRIOR

◆ DMATX_CTRL_FLUSH

◆ B44_DMATX_ADDR

◆ B44_DMATX_PTR

◆ B44_DMATX_STAT

◆ DMATX_STAT_CDMASK