iPXE
bnx2.h
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1 /* bnx2.h: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan (mchan@broadcom.com)
10  */
11 
12 FILE_LICENCE ( GPL_ANY );
13 
14 #ifndef BNX2_H
15 #define BNX2_H
16 
17 #define L1_CACHE_BYTES 128 /* Rough approximaition of the cache line size */
18 #define L1_CACHE_ALIGN(X) (((X) + L1_CACHE_BYTES-1)&~(L1_CACHE_BYTES -1))
19 
20 typedef unsigned long dma_addr_t;
21 
22 /* From pci.h */
23 typedef int pci_power_t;
24 
25 #define PCI_D0 ((pci_power_t) 0)
26 #define PCI_D1 ((pci_power_t) 1)
27 #define PCI_D2 ((pci_power_t) 2)
28 #define PCI_D3hot ((pci_power_t) 3)
29 #define PCI_D3cold ((pci_power_t) 4)
30 #define PCI_UNKNOWN ((pci_power_t) 5)
31 #define PCI_POWER_ERROR ((pci_power_t) -1)
32 
33 /* From pci_regs.h */
34 
35 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
36 #define PCI_X_CMD 2 /* Modes & Features */
37 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
38 
39 /* From mii.h */
40 
41 /* Indicates what features are advertised by the interface. */
42 #define ADVERTISED_10baseT_Half (1 << 0)
43 #define ADVERTISED_10baseT_Full (1 << 1)
44 #define ADVERTISED_100baseT_Half (1 << 2)
45 #define ADVERTISED_100baseT_Full (1 << 3)
46 #define ADVERTISED_1000baseT_Half (1 << 4)
47 #define ADVERTISED_1000baseT_Full (1 << 5)
48 #define ADVERTISED_Autoneg (1 << 6)
49 #define ADVERTISED_TP (1 << 7)
50 #define ADVERTISED_AUI (1 << 8)
51 #define ADVERTISED_MII (1 << 9)
52 #define ADVERTISED_FIBRE (1 << 10)
53 #define ADVERTISED_BNC (1 << 11)
54 
55 /* The following are all involved in forcing a particular link
56  * mode for the device for setting things. When getting the
57  * devices settings, these indicate the current mode and whether
58  * it was foced up into this mode or autonegotiated.
59  */
60 
61 /* Duplex, half or full. */
62 #define DUPLEX_HALF 0x00
63 #define DUPLEX_FULL 0x01
64 #define DUPLEX_INVALID 0x02
65 
66 /* Which connector port. */
67 #define PORT_TP 0x00
68 #define PORT_AUI 0x01
69 #define PORT_MII 0x02
70 #define PORT_FIBRE 0x03
71 #define PORT_BNC 0x04
72 
73 /* Which tranceiver to use. */
74 #define XCVR_INTERNAL 0x00
75 #define XCVR_EXTERNAL 0x01
76 #define XCVR_DUMMY1 0x02
77 #define XCVR_DUMMY2 0x03
78 #define XCVR_DUMMY3 0x04
79 
80 /* Enable or disable autonegotiation. If this is set to enable,
81  * the forced link modes above are completely ignored.
82  */
83 #define AUTONEG_DISABLE 0x00
84 #define AUTONEG_ENABLE 0x01
85 
86 /* Wake-On-Lan options. */
87 #define WAKE_PHY (1 << 0)
88 #define WAKE_UCAST (1 << 1)
89 #define WAKE_MCAST (1 << 2)
90 #define WAKE_BCAST (1 << 3)
91 #define WAKE_ARP (1 << 4)
92 #define WAKE_MAGIC (1 << 5)
93 #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
94 
95 /* The following are all involved in forcing a particular link
96  * * mode for the device for setting things. When getting the
97  * * devices settings, these indicate the current mode and whether
98  * * it was foced up into this mode or autonegotiated.
99  * */
100 
101 /* The forced speed, 10Mb, 100Mb, gigabit. */
102 #define SPEED_10 10
103 #define SPEED_100 100
104 #define SPEED_1000 1000
105 #define SPEED_2500 2500
106 #define SPEED_INVALID 0 /* XXX was 3 */
107 
108 
109 /* Duplex, half or full. */
110 #define DUPLEX_HALF 0x00
111 #define DUPLEX_FULL 0x01
112 #define DUPLEX_INVALID 0x02
113 
114 /* Which connector port. */
115 #define PORT_TP 0x00
116 #define PORT_AUI 0x01
117 #define PORT_MII 0x02
118 #define PORT_FIBRE 0x03
119 #define PORT_BNC 0x04
120 
121 /* Which tranceiver to use. */
122 #define XCVR_INTERNAL 0x00
123 #define XCVR_EXTERNAL 0x01
124 #define XCVR_DUMMY1 0x02
125 #define XCVR_DUMMY2 0x03
126 #define XCVR_DUMMY3 0x04
127 
128 /* Enable or disable autonegotiation. If this is set to enable,
129  * * the forced link modes above are completely ignored.
130  * */
131 #define AUTONEG_DISABLE 0x00
132 #define AUTONEG_ENABLE 0x01
133 
134 /* Wake-On-Lan options. */
135 #define WAKE_PHY (1 << 0)
136 #define WAKE_UCAST (1 << 1)
137 #define WAKE_MCAST (1 << 2)
138 #define WAKE_BCAST (1 << 3)
139 #define WAKE_ARP (1 << 4)
140 #define WAKE_MAGIC (1 << 5)
141 #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
142 
143 /* Hardware data structures and register definitions automatically
144  * generated from RTL code. Do not modify.
145  */
146 
147 /*
148  * tx_bd definition
149  */
150 struct tx_bd {
155  #define TX_BD_FLAGS_CONN_FAULT (1<<0)
156  #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
157  #define TX_BD_FLAGS_IP_CKSUM (1<<2)
158  #define TX_BD_FLAGS_VLAN_TAG (1<<3)
159  #define TX_BD_FLAGS_COAL_NOW (1<<4)
160  #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
161  #define TX_BD_FLAGS_END (1<<6)
162  #define TX_BD_FLAGS_START (1<<7)
163  #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
164  #define TX_BD_FLAGS_SW_FLAGS (1<<13)
165  #define TX_BD_FLAGS_SW_SNAP (1<<14)
166  #define TX_BD_FLAGS_SW_LSO (1<<15)
167 
168 };
169 
170 
171 /*
172  * rx_bd definition
173  */
174 struct rx_bd {
179  #define RX_BD_FLAGS_NOPUSH (1<<0)
180  #define RX_BD_FLAGS_DUMMY (1<<1)
181  #define RX_BD_FLAGS_END (1<<2)
182  #define RX_BD_FLAGS_START (1<<3)
183 
184 };
185 
186 
187 /*
188  * status_block definition
189  */
190 struct status_block {
192  #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
193  #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
194  #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
195  #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
196  #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
197  #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
198  #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
199  #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
200  #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
201  #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
202  #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
203  #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
204  #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
205  #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
206  #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
207  #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
208  #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
209  #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
210  #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
211  #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
212  #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
213  #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
214  #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
215  #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
216  #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
217  #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
218  #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
219  #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
220  #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
221 
223 #if __BYTE_ORDER == __BIG_ENDIAN
248 #elif __BYTE_ORDER == __LITTLE_ENDIAN
272  u16 status_idx;
273 #endif
274 };
275 
276 
277 /*
278  * statistics_block definition
279  */
361 };
362 
363 
364 /*
365  * l2_fhdr definition
366  */
367 struct l2_fhdr {
369  #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
370  #define L2_FHDR_STATUS_RULE_P2 (1<<3)
371  #define L2_FHDR_STATUS_RULE_P3 (1<<4)
372  #define L2_FHDR_STATUS_RULE_P4 (1<<5)
373  #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
374  #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
375  #define L2_FHDR_STATUS_RSS_HASH (1<<8)
376  #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
377  #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
378  #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
379 
380  #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
381  #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
382  #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
383  #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
384  #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
385  #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
386  #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
387 
389 #if __BYTE_ORDER == __BIG_ENDIAN
394 #elif __BYTE_ORDER == __LITTLE_ENDIAN
399 #endif
400 };
401 
402 
403 /*
404  * l2_context definition
405  */
406 #define BNX2_L2CTX_TYPE 0x00000000
407 #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
408 #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
409 #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
410 #define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
411 
412 #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
413 #define BNX2_L2CTX_EST_NBD 0x00000088
414 #define BNX2_L2CTX_CMD_TYPE 0x00000088
415 #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
416 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
417 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
418 
419 #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
420 #define BNX2_L2CTX_TSCH_BSEQ 0x00000094
421 #define BNX2_L2CTX_TBDR_BSEQ 0x00000098
422 #define BNX2_L2CTX_TBDR_BOFF 0x0000009c
423 #define BNX2_L2CTX_TBDR_BIDX 0x0000009c
424 #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
425 #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
426 #define BNX2_L2CTX_TXP_BOFF 0x000000a8
427 #define BNX2_L2CTX_TXP_BIDX 0x000000a8
428 #define BNX2_L2CTX_TXP_BSEQ 0x000000ac
429 
430 
431 /*
432  * l2_bd_chain_context definition
433  */
434 #define BNX2_L2CTX_BD_PRE_READ 0x00000000
435 #define BNX2_L2CTX_CTX_SIZE 0x00000000
436 #define BNX2_L2CTX_CTX_TYPE 0x00000000
437 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
438 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
439 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
440 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
441 
442 #define BNX2_L2CTX_HOST_BDIDX 0x00000004
443 #define BNX2_L2CTX_HOST_BSEQ 0x00000008
444 #define BNX2_L2CTX_NX_BSEQ 0x0000000c
445 #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
446 #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
447 #define BNX2_L2CTX_NX_BDIDX 0x00000018
448 
449 
450 /*
451  * pci_config_l definition
452  * offset: 0000
453  */
454 #define BNX2_PCICFG_MISC_CONFIG 0x00000068
455 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
456 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
457 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
458 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
459 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
460 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
461 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
462 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
463 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
464 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
465 
466 #define BNX2_PCICFG_MISC_STATUS 0x0000006c
467 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
468 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
469 #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
470 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
471 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
472 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
473 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
474 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
475 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
476 
477 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
478 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
479 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
480 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
481 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
482 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
483 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
484 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
485 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
486 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
487 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
488 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
489 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
490 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
491 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
492 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
493 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
494 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
495 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
496 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
497 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
498 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
499 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
500 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
501 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
502 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
503 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
504 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
505 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
506 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
507 
508 #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
509 #define BNX2_PCICFG_REG_WINDOW 0x00000080
510 #define BNX2_PCICFG_INT_ACK_CMD 0x00000084
511 #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
512 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
513 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
514 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
515 
516 #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
517 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
518 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
519 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
520 
521 
522 /*
523  * pci_reg definition
524  * offset: 0x400
525  */
526 #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
527 #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
528 
529 #define BNX2_PCI_CONFIG_1 0x00000404
530 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
531 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
532 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
533 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
534 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
535 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
536 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
537 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
538 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
539 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
540 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
541 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
542 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
543 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
544 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
545 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
546 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
547 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
548 
549 #define BNX2_PCI_CONFIG_2 0x00000408
550 #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
551 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
552 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
553 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
554 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
555 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
556 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
557 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
558 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
559 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
560 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
561 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
562 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
563 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
564 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
565 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
566 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
567 #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
568 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
569 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
570 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
571 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
572 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
573 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
574 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
575 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
576 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
577 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
578 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
579 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
580 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
581 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
582 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
583 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
584 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
585 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
586 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
587 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
588 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
589 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
590 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
591 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
592 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
593 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
594 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
595 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
596 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
597 
598 #define BNX2_PCI_CONFIG_3 0x0000040c
599 #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
600 #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
601 #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
602 #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
603 #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
604 #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
605 #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
606 
607 #define BNX2_PCI_PM_DATA_A 0x00000410
608 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
609 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
610 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
611 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
612 
613 #define BNX2_PCI_PM_DATA_B 0x00000414
614 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
615 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
616 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
617 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
618 
619 #define BNX2_PCI_SWAP_DIAG0 0x00000418
620 #define BNX2_PCI_SWAP_DIAG1 0x0000041c
621 #define BNX2_PCI_EXP_ROM_ADDR 0x00000420
622 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
623 #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
624 
625 #define BNX2_PCI_EXP_ROM_DATA 0x00000424
626 #define BNX2_PCI_VPD_INTF 0x00000428
627 #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
628 
629 #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
630 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
631 #define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
632 
633 #define BNX2_PCI_VPD_DATA 0x00000430
634 #define BNX2_PCI_ID_VAL1 0x00000434
635 #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
636 #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
637 
638 #define BNX2_PCI_ID_VAL2 0x00000438
639 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
640 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
641 
642 #define BNX2_PCI_ID_VAL3 0x0000043c
643 #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
644 #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
645 
646 #define BNX2_PCI_ID_VAL4 0x00000440
647 #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
648 #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
649 #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
650 #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
651 #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
652 #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
653 #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
654 #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
655 #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
656 #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
657 #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
658 #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
659 #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
660 #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
661 #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
662 #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
663 #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
664 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
665 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
666 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
667 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
668 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
669 #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
670 #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
671 #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
672 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
673 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
674 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
675 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
676 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
677 
678 #define BNX2_PCI_ID_VAL5 0x00000444
679 #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
680 #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
681 #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
682 #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
683 #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
684 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
685 
686 #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
687 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
688 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
689 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
690 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
691 
692 #define BNX2_PCI_ID_VAL6 0x0000044c
693 #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
694 #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
695 #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
696 
697 #define BNX2_PCI_MSI_DATA 0x00000450
698 #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
699 
700 #define BNX2_PCI_MSI_ADDR_H 0x00000454
701 #define BNX2_PCI_MSI_ADDR_L 0x00000458
702 
703 
704 /*
705  * misc_reg definition
706  * offset: 0x800
707  */
708 #define BNX2_MISC_COMMAND 0x00000800
709 #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
710 #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
711 #define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
712 #define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
713 #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
714 #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
715 
716 #define BNX2_MISC_CFG 0x00000804
717 #define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
718 #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
719 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
720 #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
721 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
722 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
723 #define BNX2_MISC_CFG_BIST_EN (1L<<3)
724 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
725 #define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
726 #define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
727 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
728 #define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
729 #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
730 #define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
731 #define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
732 
733 #define BNX2_MISC_ID 0x00000808
734 #define BNX2_MISC_ID_BOND_ID (0xfL<<0)
735 #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
736 #define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
737 #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
738 
739 #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
740 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
741 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
742 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
743 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
744 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
745 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
746 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
747 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
748 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
749 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
750 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
751 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
752 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
753 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
754 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
755 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
756 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
757 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
758 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
759 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
760 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
761 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
762 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
763 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
764 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
765 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
766 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
767 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
768 
769 #define BNX2_MISC_ENABLE_SET_BITS 0x00000810
770 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
771 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
772 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
773 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
774 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
775 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
776 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
777 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
778 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
779 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
780 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
781 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
782 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
783 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
784 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
785 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
786 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
787 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
788 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
789 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
790 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
791 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
792 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
793 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
794 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
795 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
796 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
797 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
798 
799 #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
800 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
801 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
802 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
803 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
804 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
805 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
806 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
807 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
808 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
809 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
810 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
811 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
812 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
813 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
814 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
815 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
816 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
817 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
818 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
819 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
820 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
821 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
822 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
823 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
824 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
825 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
826 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
827 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
828 
829 #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
830 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
831 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
832 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
833 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
834 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
835 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
836 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
837 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
838 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
839 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
840 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
841 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
842 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
843 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
844 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
845 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
846 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
847 #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
848 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
849 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
850 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
851 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
852 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
853 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
854 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
855 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
856 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
857 #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
858 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
859 
860 #define BNX2_MISC_GPIO 0x0000081c
861 #define BNX2_MISC_GPIO_VALUE (0xffL<<0)
862 #define BNX2_MISC_GPIO_SET (0xffL<<8)
863 #define BNX2_MISC_GPIO_CLR (0xffL<<16)
864 #define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
865 
866 #define BNX2_MISC_GPIO_INT 0x00000820
867 #define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
868 #define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
869 #define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
870 #define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
871 
872 #define BNX2_MISC_CONFIG_LFSR 0x00000824
873 #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
874 
875 #define BNX2_MISC_LFSR_MASK_BITS 0x00000828
876 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
877 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
878 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
879 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
880 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
881 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
882 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
883 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
884 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
885 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
886 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
887 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
888 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
889 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
890 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
891 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
892 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
893 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
894 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
895 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
896 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
897 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
898 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
899 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
900 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
901 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
902 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
903 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
904 
905 #define BNX2_MISC_ARB_REQ0 0x0000082c
906 #define BNX2_MISC_ARB_REQ1 0x00000830
907 #define BNX2_MISC_ARB_REQ2 0x00000834
908 #define BNX2_MISC_ARB_REQ3 0x00000838
909 #define BNX2_MISC_ARB_REQ4 0x0000083c
910 #define BNX2_MISC_ARB_FREE0 0x00000840
911 #define BNX2_MISC_ARB_FREE1 0x00000844
912 #define BNX2_MISC_ARB_FREE2 0x00000848
913 #define BNX2_MISC_ARB_FREE3 0x0000084c
914 #define BNX2_MISC_ARB_FREE4 0x00000850
915 #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
916 #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
917 #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
918 #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
919 #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
920 #define BNX2_MISC_ARB_GNT0 0x00000868
921 #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
922 #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
923 #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
924 #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
925 #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
926 #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
927 #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
928 #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
929 
930 #define BNX2_MISC_ARB_GNT1 0x0000086c
931 #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
932 #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
933 #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
934 #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
935 #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
936 #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
937 #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
938 #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
939 
940 #define BNX2_MISC_ARB_GNT2 0x00000870
941 #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
942 #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
943 #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
944 #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
945 #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
946 #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
947 #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
948 #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
949 
950 #define BNX2_MISC_ARB_GNT3 0x00000874
951 #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
952 #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
953 #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
954 #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
955 #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
956 #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
957 #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
958 #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
959 
960 #define BNX2_MISC_PRBS_CONTROL 0x00000878
961 #define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
962 #define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
963 #define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
964 #define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
965 #define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
966 #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
967 #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
968 #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
969 #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
970 
971 #define BNX2_MISC_PRBS_STATUS 0x0000087c
972 #define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
973 #define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
974 #define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
975 #define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
976 
977 #define BNX2_MISC_SM_ASF_CONTROL 0x00000880
978 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
979 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
980 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
981 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
982 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
983 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
984 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
985 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
986 #define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
987 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
988 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
989 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
990 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
991 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
992 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
993 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
994 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
995 
996 #define BNX2_MISC_SMB_IN 0x00000884
997 #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
998 #define BNX2_MISC_SMB_IN_RDY (1L<<8)
999 #define BNX2_MISC_SMB_IN_DONE (1L<<9)
1000 #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1001 #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
1002 #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1003 #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1004 #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1005 #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1006 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1007 
1008 #define BNX2_MISC_SMB_OUT 0x00000888
1009 #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1010 #define BNX2_MISC_SMB_OUT_RDY (1L<<8)
1011 #define BNX2_MISC_SMB_OUT_START (1L<<9)
1012 #define BNX2_MISC_SMB_OUT_LAST (1L<<10)
1013 #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1014 #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
1015 #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1016 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1017 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1018 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1019 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1020 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1021 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1022 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1023 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1024 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1025 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1026 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
1027 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1028 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1029 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1030 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1031 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1032 
1033 #define BNX2_MISC_SMB_WATCHDOG 0x0000088c
1034 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1035 
1036 #define BNX2_MISC_SMB_HEARTBEAT 0x00000890
1037 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1038 
1039 #define BNX2_MISC_SMB_POLL_ASF 0x00000894
1040 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1041 
1042 #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
1043 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1044 
1045 #define BNX2_MISC_SMB_RETRAN 0x0000089c
1046 #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1047 
1048 #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
1049 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1050 
1051 #define BNX2_MISC_PERR_ENA0 0x000008a4
1052 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1053 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1054 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1055 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1056 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1057 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1058 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1059 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1060 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1061 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1062 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1063 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1064 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1065 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1066 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1067 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1068 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1069 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1070 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1071 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1072 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1073 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1074 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1075 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1076 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1077 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1078 #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1079 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1080 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1081 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1082 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1083 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1084 
1085 #define BNX2_MISC_PERR_ENA1 0x000008a8
1086 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1087 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1088 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1089 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1090 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1091 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1092 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1093 #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1094 #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1095 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1096 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1097 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1098 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1099 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1100 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1101 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1102 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1103 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1104 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1105 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1106 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1107 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1108 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1109 #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1110 #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1111 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1112 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1113 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1114 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1115 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1116 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1117 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1118 
1119 #define BNX2_MISC_PERR_ENA2 0x000008ac
1120 #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1121 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1122 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1123 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1124 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1125 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1126 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1127 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1128 #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1129 
1130 #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1131 #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1132 #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1133 
1134 #define BNX2_MISC_VREG_CONTROL 0x000008b4
1135 #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1136 #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1137 
1138 #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1139 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1140 
1141 #define BNX2_MISC_UNUSED0 0x000008bc
1142 
1143 
1144 /*
1145  * nvm_reg definition
1146  * offset: 0x6400
1147  */
1148 #define BNX2_NVM_COMMAND 0x00006400
1149 #define BNX2_NVM_COMMAND_RST (1L<<0)
1150 #define BNX2_NVM_COMMAND_DONE (1L<<3)
1151 #define BNX2_NVM_COMMAND_DOIT (1L<<4)
1152 #define BNX2_NVM_COMMAND_WR (1L<<5)
1153 #define BNX2_NVM_COMMAND_ERASE (1L<<6)
1154 #define BNX2_NVM_COMMAND_FIRST (1L<<7)
1155 #define BNX2_NVM_COMMAND_LAST (1L<<8)
1156 #define BNX2_NVM_COMMAND_WREN (1L<<16)
1157 #define BNX2_NVM_COMMAND_WRDI (1L<<17)
1158 #define BNX2_NVM_COMMAND_EWSR (1L<<18)
1159 #define BNX2_NVM_COMMAND_WRSR (1L<<19)
1160 
1161 #define BNX2_NVM_STATUS 0x00006404
1162 #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1163 #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1164 #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1165 
1166 #define BNX2_NVM_WRITE 0x00006408
1167 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1168 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1169 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1170 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1171 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1172 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1173 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1174 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1175 
1176 #define BNX2_NVM_ADDR 0x0000640c
1177 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1178 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1179 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1180 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1181 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1182 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1183 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1184 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1185 
1186 #define BNX2_NVM_READ 0x00006410
1187 #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1188 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1189 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1190 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1191 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1192 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1193 #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1194 #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1195 
1196 #define BNX2_NVM_CFG1 0x00006414
1197 #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1198 #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
1199 #define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
1200 #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
1201 #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
1202 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1203 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1204 #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1205 #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1206 #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1207 #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1208 #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1209 
1210 #define BNX2_NVM_CFG2 0x00006418
1211 #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1212 #define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1213 #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1214 
1215 #define BNX2_NVM_CFG3 0x0000641c
1216 #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1217 #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
1218 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1219 #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
1220 
1221 #define BNX2_NVM_SW_ARB 0x00006420
1222 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1223 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1224 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1225 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1226 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1227 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1228 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1229 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1230 #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1231 #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1232 #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1233 #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1234 #define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
1235 #define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
1236 #define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
1237 #define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
1238 
1239 #define BNX2_NVM_ACCESS_ENABLE 0x00006424
1240 #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1241 #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1242 
1243 #define BNX2_NVM_WRITE1 0x00006428
1244 #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
1245 #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1246 #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1247 
1248 
1249 
1250 /*
1251  * dma_reg definition
1252  * offset: 0xc00
1253  */
1254 #define BNX2_DMA_COMMAND 0x00000c00
1255 #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1256 
1257 #define BNX2_DMA_STATUS 0x00000c04
1258 #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1259 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1260 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1261 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1262 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1263 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1264 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1265 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1266 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1267 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1268 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1269 
1270 #define BNX2_DMA_CONFIG 0x00000c08
1271 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1272 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1273 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1274 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1275 #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
1276 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1277 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1278 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1279 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1280 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1281 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1282 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1283 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1284 #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1285 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1286 #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1287 #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1288 #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1289 #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1290 
1291 #define BNX2_DMA_BLACKOUT 0x00000c0c
1292 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1293 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1294 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1295 
1296 #define BNX2_DMA_RCHAN_STAT 0x00000c30
1297 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1298 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1299 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1300 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1301 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1302 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1303 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1304 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1305 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1306 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1307 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1308 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1309 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1310 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1311 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1312 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1313 
1314 #define BNX2_DMA_WCHAN_STAT 0x00000c34
1315 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1316 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1317 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1318 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1319 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1320 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1321 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1322 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1323 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1324 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1325 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1326 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1327 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1328 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1329 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1330 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1331 
1332 #define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
1333 #define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1334 #define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1335 #define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1336 #define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1337 #define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1338 #define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1339 #define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1340 #define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1341 
1342 #define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1343 #define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1344 #define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1345 #define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1346 #define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1347 #define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1348 #define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1349 #define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1350 #define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1351 
1352 #define BNX2_DMA_RCHAN_STAT_00 0x00000c40
1353 #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1354 
1355 #define BNX2_DMA_RCHAN_STAT_01 0x00000c44
1356 #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1357 
1358 #define BNX2_DMA_RCHAN_STAT_02 0x00000c48
1359 #define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1360 #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1361 #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1362 #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1363 
1364 #define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
1365 #define BNX2_DMA_RCHAN_STAT_11 0x00000c50
1366 #define BNX2_DMA_RCHAN_STAT_12 0x00000c54
1367 #define BNX2_DMA_RCHAN_STAT_20 0x00000c58
1368 #define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
1369 #define BNX2_DMA_RCHAN_STAT_22 0x00000c60
1370 #define BNX2_DMA_RCHAN_STAT_30 0x00000c64
1371 #define BNX2_DMA_RCHAN_STAT_31 0x00000c68
1372 #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
1373 #define BNX2_DMA_RCHAN_STAT_40 0x00000c70
1374 #define BNX2_DMA_RCHAN_STAT_41 0x00000c74
1375 #define BNX2_DMA_RCHAN_STAT_42 0x00000c78
1376 #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
1377 #define BNX2_DMA_RCHAN_STAT_51 0x00000c80
1378 #define BNX2_DMA_RCHAN_STAT_52 0x00000c84
1379 #define BNX2_DMA_RCHAN_STAT_60 0x00000c88
1380 #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
1381 #define BNX2_DMA_RCHAN_STAT_62 0x00000c90
1382 #define BNX2_DMA_RCHAN_STAT_70 0x00000c94
1383 #define BNX2_DMA_RCHAN_STAT_71 0x00000c98
1384 #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
1385 #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
1386 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1387 
1388 #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
1389 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1390 
1391 #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
1392 #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1393 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1394 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1395 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1396 
1397 #define BNX2_DMA_WCHAN_STAT_10 0x00000cac
1398 #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
1399 #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
1400 #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
1401 #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
1402 #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
1403 #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
1404 #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
1405 #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
1406 #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
1407 #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
1408 #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
1409 #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
1410 #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
1411 #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
1412 #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
1413 #define BNX2_DMA_WCHAN_STAT_61 0x00000cec
1414 #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
1415 #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
1416 #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
1417 #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
1418 #define BNX2_DMA_ARB_STAT_00 0x00000d00
1419 #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1420 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1421 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1422 
1423 #define BNX2_DMA_ARB_STAT_01 0x00000d04
1424 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1425 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1426 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1427 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1428 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1429 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1430 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1431 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1432 
1433 #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
1434 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1435 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1436 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1437 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1438 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1439 
1440 #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
1441 #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
1442 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1443 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1444 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1445 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1446 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1447 
1448 #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
1449 #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
1450 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1451 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1452 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1453 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1454 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1455 
1456 #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
1457 
1458 
1459 /*
1460  * context_reg definition
1461  * offset: 0x1000
1462  */
1463 #define BNX2_CTX_COMMAND 0x00001000
1464 #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
1465 
1466 #define BNX2_CTX_STATUS 0x00001004
1467 #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
1468 #define BNX2_CTX_STATUS_READ_STAT (1L<<16)
1469 #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
1470 #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1471 #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
1472 
1473 #define BNX2_CTX_VIRT_ADDR 0x00001008
1474 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
1475 
1476 #define BNX2_CTX_PAGE_TBL 0x0000100c
1477 #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
1478 
1479 #define BNX2_CTX_DATA_ADR 0x00001010
1480 #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
1481 
1482 #define BNX2_CTX_DATA 0x00001014
1483 #define BNX2_CTX_LOCK 0x00001018
1484 #define BNX2_CTX_LOCK_TYPE (0x7L<<0)
1485 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1486 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1487 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1488 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1489 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
1490 #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1491 #define BNX2_CTX_LOCK_GRANTED (1L<<26)
1492 #define BNX2_CTX_LOCK_MODE (0x7L<<27)
1493 #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
1494 #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
1495 #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
1496 #define BNX2_CTX_LOCK_STATUS (1L<<30)
1497 #define BNX2_CTX_LOCK_REQ (1L<<31)
1498 
1499 #define BNX2_CTX_ACCESS_STATUS 0x00001040
1500 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
1501 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
1502 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
1503 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
1504 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
1505 
1506 #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
1507 #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
1508 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
1509 
1510 #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
1511 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
1512 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
1513 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
1514 
1515 #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
1516 #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
1517 #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
1518 #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
1519 #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
1520 #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
1521 #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
1522 #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
1523 
1524 
1525 /*
1526  * emac_reg definition
1527  * offset: 0x1400
1528  */
1529 #define BNX2_EMAC_MODE 0x00001400
1530 #define BNX2_EMAC_MODE_RESET (1L<<0)
1531 #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
1532 #define BNX2_EMAC_MODE_PORT (0x3L<<2)
1533 #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1534 #define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1535 #define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
1536 #define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
1537 #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
1538 #define BNX2_EMAC_MODE_25G (1L<<5)
1539 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1540 #define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1541 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
1542 #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
1543 #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
1544 #define BNX2_EMAC_MODE_MPKT (1L<<18)
1545 #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
1546 #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
1547 
1548 #define BNX2_EMAC_STATUS 0x00001404
1549 #define BNX2_EMAC_STATUS_LINK (1L<<11)
1550 #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
1551 #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
1552 #define BNX2_EMAC_STATUS_MI_INT (1L<<23)
1553 #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
1554 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
1555 
1556 #define BNX2_EMAC_ATTENTION_ENA 0x00001408
1557 #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
1558 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
1559 #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
1560 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
1561 
1562 #define BNX2_EMAC_LED 0x0000140c
1563 #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
1564 #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
1565 #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
1566 #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
1567 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
1568 #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
1569 #define BNX2_EMAC_LED_TRAFFIC (1L<<6)
1570 #define BNX2_EMAC_LED_1000MB (1L<<7)
1571 #define BNX2_EMAC_LED_100MB (1L<<8)
1572 #define BNX2_EMAC_LED_10MB (1L<<9)
1573 #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
1574 #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
1575 #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
1576 
1577 #define BNX2_EMAC_MAC_MATCH0 0x00001410
1578 #define BNX2_EMAC_MAC_MATCH1 0x00001414
1579 #define BNX2_EMAC_MAC_MATCH2 0x00001418
1580 #define BNX2_EMAC_MAC_MATCH3 0x0000141c
1581 #define BNX2_EMAC_MAC_MATCH4 0x00001420
1582 #define BNX2_EMAC_MAC_MATCH5 0x00001424
1583 #define BNX2_EMAC_MAC_MATCH6 0x00001428
1584 #define BNX2_EMAC_MAC_MATCH7 0x0000142c
1585 #define BNX2_EMAC_MAC_MATCH8 0x00001430
1586 #define BNX2_EMAC_MAC_MATCH9 0x00001434
1587 #define BNX2_EMAC_MAC_MATCH10 0x00001438
1588 #define BNX2_EMAC_MAC_MATCH11 0x0000143c
1589 #define BNX2_EMAC_MAC_MATCH12 0x00001440
1590 #define BNX2_EMAC_MAC_MATCH13 0x00001444
1591 #define BNX2_EMAC_MAC_MATCH14 0x00001448
1592 #define BNX2_EMAC_MAC_MATCH15 0x0000144c
1593 #define BNX2_EMAC_MAC_MATCH16 0x00001450
1594 #define BNX2_EMAC_MAC_MATCH17 0x00001454
1595 #define BNX2_EMAC_MAC_MATCH18 0x00001458
1596 #define BNX2_EMAC_MAC_MATCH19 0x0000145c
1597 #define BNX2_EMAC_MAC_MATCH20 0x00001460
1598 #define BNX2_EMAC_MAC_MATCH21 0x00001464
1599 #define BNX2_EMAC_MAC_MATCH22 0x00001468
1600 #define BNX2_EMAC_MAC_MATCH23 0x0000146c
1601 #define BNX2_EMAC_MAC_MATCH24 0x00001470
1602 #define BNX2_EMAC_MAC_MATCH25 0x00001474
1603 #define BNX2_EMAC_MAC_MATCH26 0x00001478
1604 #define BNX2_EMAC_MAC_MATCH27 0x0000147c
1605 #define BNX2_EMAC_MAC_MATCH28 0x00001480
1606 #define BNX2_EMAC_MAC_MATCH29 0x00001484
1607 #define BNX2_EMAC_MAC_MATCH30 0x00001488
1608 #define BNX2_EMAC_MAC_MATCH31 0x0000148c
1609 #define BNX2_EMAC_BACKOFF_SEED 0x00001498
1610 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
1611 
1612 #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
1613 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
1614 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1615 
1616 #define BNX2_EMAC_SERDES_CNTL 0x000014a4
1617 #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
1618 #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
1619 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
1620 #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
1621 #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
1622 #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
1623 #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
1624 #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
1625 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
1626 #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
1627 #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
1628 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
1629 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
1630 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
1631 #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
1632 #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
1633 
1634 #define BNX2_EMAC_SERDES_STATUS 0x000014a8
1635 #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
1636 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
1637 
1638 #define BNX2_EMAC_MDIO_COMM 0x000014ac
1639 #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
1640 #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
1641 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
1642 #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
1643 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
1644 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
1645 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
1646 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
1647 #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
1648 #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
1649 #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
1650 
1651 #define BNX2_EMAC_MDIO_STATUS 0x000014b0
1652 #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
1653 #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
1654 
1655 #define BNX2_EMAC_MDIO_MODE 0x000014b4
1656 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
1657 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1658 #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
1659 #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
1660 #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
1661 #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
1662 #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
1663 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
1664 
1665 #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
1666 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
1667 
1668 #define BNX2_EMAC_TX_MODE 0x000014bc
1669 #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
1670 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1671 #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
1672 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
1673 #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
1674 #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
1675 
1676 #define BNX2_EMAC_TX_STATUS 0x000014c0
1677 #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
1678 #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
1679 #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
1680 #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
1681 #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
1682 
1683 #define BNX2_EMAC_TX_LENGTHS 0x000014c4
1684 #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
1685 #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
1686 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
1687 
1688 #define BNX2_EMAC_RX_MODE 0x000014c8
1689 #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
1690 #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
1691 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1692 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
1693 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
1694 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
1695 #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
1696 #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1697 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
1698 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1699 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
1700 #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
1701 
1702 #define BNX2_EMAC_RX_STATUS 0x000014cc
1703 #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
1704 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
1705 #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
1706 
1707 #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
1708 #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
1709 #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
1710 #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
1711 #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
1712 #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
1713 #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
1714 #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
1715 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
1716 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
1717 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
1718 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
1719 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
1720 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
1721 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
1722 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
1723 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
1724 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
1725 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
1726 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
1727 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
1728 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
1729 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
1730 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
1731 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
1732 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
1733 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
1734 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
1735 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
1736 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
1737 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
1738 #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
1739 #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
1740 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
1741 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
1742 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
1743 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
1744 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
1745 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
1746 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
1747 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
1748 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
1749 
1750 #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
1751 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
1752 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
1753 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
1754 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
1755 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
1756 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
1757 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
1758 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
1759 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
1760 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
1761 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
1762 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
1763 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
1764 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
1765 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
1766 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
1767 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
1768 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
1769 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
1770 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
1771 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
1772 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
1773 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
1774 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
1775 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
1776 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
1777 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
1778 
1779 #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
1780 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
1781 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
1782 
1783 #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
1784 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
1785 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
1786 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
1787 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
1788 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
1789 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
1790 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1791 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
1792 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
1793 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
1794 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
1795 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
1796 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
1797 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
1798 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
1799 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
1800 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
1801 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
1802 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
1803 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
1804 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
1805 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
1806 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
1807 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
1808 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
1809 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
1810 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
1811 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
1812 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
1813 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
1814 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
1815 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
1816 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
1817 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
1818 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
1819 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
1820 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
1821 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
1822 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
1823 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
1824 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
1825 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
1826 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
1827 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
1828 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
1829 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
1830 #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
1831 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
1832 #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
1833 
1834 #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
1835 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
1836 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
1837 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
1838 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
1839 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
1840 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
1841 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
1842 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
1843 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
1844 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
1845 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
1846 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
1847 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
1848 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
1849 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
1850 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
1851 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
1852 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
1853 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
1854 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
1855 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
1856 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
1857 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
1858 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
1859 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
1860 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
1861 
1862 #define BNX2_EMAC_RX_STAT_AC0 0x00001580
1863 #define BNX2_EMAC_RX_STAT_AC1 0x00001584
1864 #define BNX2_EMAC_RX_STAT_AC2 0x00001588
1865 #define BNX2_EMAC_RX_STAT_AC3 0x0000158c
1866 #define BNX2_EMAC_RX_STAT_AC4 0x00001590
1867 #define BNX2_EMAC_RX_STAT_AC5 0x00001594
1868 #define BNX2_EMAC_RX_STAT_AC6 0x00001598
1869 #define BNX2_EMAC_RX_STAT_AC7 0x0000159c
1870 #define BNX2_EMAC_RX_STAT_AC8 0x000015a0
1871 #define BNX2_EMAC_RX_STAT_AC9 0x000015a4
1872 #define BNX2_EMAC_RX_STAT_AC10 0x000015a8
1873 #define BNX2_EMAC_RX_STAT_AC11 0x000015ac
1874 #define BNX2_EMAC_RX_STAT_AC12 0x000015b0
1875 #define BNX2_EMAC_RX_STAT_AC13 0x000015b4
1876 #define BNX2_EMAC_RX_STAT_AC14 0x000015b8
1877 #define BNX2_EMAC_RX_STAT_AC15 0x000015bc
1878 #define BNX2_EMAC_RX_STAT_AC16 0x000015c0
1879 #define BNX2_EMAC_RX_STAT_AC17 0x000015c4
1880 #define BNX2_EMAC_RX_STAT_AC18 0x000015c8
1881 #define BNX2_EMAC_RX_STAT_AC19 0x000015cc
1882 #define BNX2_EMAC_RX_STAT_AC20 0x000015d0
1883 #define BNX2_EMAC_RX_STAT_AC21 0x000015d4
1884 #define BNX2_EMAC_RX_STAT_AC22 0x000015d8
1885 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
1886 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
1887 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
1888 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
1889 #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
1890 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
1891 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
1892 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
1893 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
1894 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
1895 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
1896 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
1897 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
1898 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
1899 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
1900 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
1901 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
1902 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
1903 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
1904 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
1905 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
1906 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
1907 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
1908 #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
1909 #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
1910 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
1911 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
1912 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
1913 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
1914 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
1915 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
1916 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
1917 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
1918 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
1919 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
1920 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
1921 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
1922 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
1923 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
1924 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
1925 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
1926 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
1927 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
1928 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
1929 
1930 #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
1931 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
1932 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
1933 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
1934 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
1935 
1936 #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
1937 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
1938 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
1939 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
1940 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
1941 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
1942 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
1943 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
1944 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
1945 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
1946 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
1947 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
1948 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
1949 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
1950 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
1951 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
1952 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
1953 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
1954 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
1955 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
1956 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
1957 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
1958 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
1959 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
1960 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
1961 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
1962 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
1963 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
1964 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
1965 
1966 #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
1967 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
1968 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
1969 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
1970 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
1971 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
1972 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
1973 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
1974 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1975 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
1976 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1977 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1978 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
1979 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
1980 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
1981 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
1982 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
1983 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
1984 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
1985 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
1986 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
1987 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
1988 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
1989 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
1990 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
1991 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
1992 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
1993 #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
1994 
1995 #define BNX2_EMAC_TX_STAT_AC0 0x00001680
1996 #define BNX2_EMAC_TX_STAT_AC1 0x00001684
1997 #define BNX2_EMAC_TX_STAT_AC2 0x00001688
1998 #define BNX2_EMAC_TX_STAT_AC3 0x0000168c
1999 #define BNX2_EMAC_TX_STAT_AC4 0x00001690
2000 #define BNX2_EMAC_TX_STAT_AC5 0x00001694
2001 #define BNX2_EMAC_TX_STAT_AC6 0x00001698
2002 #define BNX2_EMAC_TX_STAT_AC7 0x0000169c
2003 #define BNX2_EMAC_TX_STAT_AC8 0x000016a0
2004 #define BNX2_EMAC_TX_STAT_AC9 0x000016a4
2005 #define BNX2_EMAC_TX_STAT_AC10 0x000016a8
2006 #define BNX2_EMAC_TX_STAT_AC11 0x000016ac
2007 #define BNX2_EMAC_TX_STAT_AC12 0x000016b0
2008 #define BNX2_EMAC_TX_STAT_AC13 0x000016b4
2009 #define BNX2_EMAC_TX_STAT_AC14 0x000016b8
2010 #define BNX2_EMAC_TX_STAT_AC15 0x000016bc
2011 #define BNX2_EMAC_TX_STAT_AC16 0x000016c0
2012 #define BNX2_EMAC_TX_STAT_AC17 0x000016c4
2013 #define BNX2_EMAC_TX_STAT_AC18 0x000016c8
2014 #define BNX2_EMAC_TX_STAT_AC19 0x000016cc
2015 #define BNX2_EMAC_TX_STAT_AC20 0x000016d0
2016 #define BNX2_EMAC_TX_STAT_AC21 0x000016d4
2017 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
2018 
2019 
2020 /*
2021  * rpm_reg definition
2022  * offset: 0x1800
2023  */
2024 #define BNX2_RPM_COMMAND 0x00001800
2025 #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
2026 #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
2027 
2028 #define BNX2_RPM_STATUS 0x00001804
2029 #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
2030 #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
2031 
2032 #define BNX2_RPM_CONFIG 0x00001808
2033 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
2034 #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
2035 #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
2036 #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
2037 #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
2038 #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
2039 
2040 #define BNX2_RPM_VLAN_MATCH0 0x00001810
2041 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
2042 
2043 #define BNX2_RPM_VLAN_MATCH1 0x00001814
2044 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
2045 
2046 #define BNX2_RPM_VLAN_MATCH2 0x00001818
2047 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
2048 
2049 #define BNX2_RPM_VLAN_MATCH3 0x0000181c
2050 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
2051 
2052 #define BNX2_RPM_SORT_USER0 0x00001820
2053 #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
2054 #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
2055 #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
2056 #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
2057 #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
2058 #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
2059 #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
2060 #define BNX2_RPM_SORT_USER0_ENA (1L<<31)
2061 
2062 #define BNX2_RPM_SORT_USER1 0x00001824
2063 #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
2064 #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
2065 #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
2066 #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
2067 #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
2068 #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
2069 #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
2070 #define BNX2_RPM_SORT_USER1_ENA (1L<<31)
2071 
2072 #define BNX2_RPM_SORT_USER2 0x00001828
2073 #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
2074 #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
2075 #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
2076 #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
2077 #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
2078 #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
2079 #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
2080 #define BNX2_RPM_SORT_USER2_ENA (1L<<31)
2081 
2082 #define BNX2_RPM_SORT_USER3 0x0000182c
2083 #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
2084 #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
2085 #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
2086 #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2087 #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
2088 #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2089 #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2090 #define BNX2_RPM_SORT_USER3_ENA (1L<<31)
2091 
2092 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2093 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2094 #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
2095 #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2096 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2097 #define BNX2_RPM_STAT_AC0 0x00001880
2098 #define BNX2_RPM_STAT_AC1 0x00001884
2099 #define BNX2_RPM_STAT_AC2 0x00001888
2100 #define BNX2_RPM_STAT_AC3 0x0000188c
2101 #define BNX2_RPM_STAT_AC4 0x00001890
2102 #define BNX2_RPM_RC_CNTL_0 0x00001900
2103 #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2104 #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2105 #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2106 #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
2107 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2108 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2109 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2110 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2111 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2112 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2113 #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
2114 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2115 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2116 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2117 #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2118 #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
2119 #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2120 #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
2121 #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
2122 #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
2123 #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
2124 #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
2125 #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
2126 #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
2127 
2128 #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
2129 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2130 #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2131 
2132 #define BNX2_RPM_RC_CNTL_1 0x00001908
2133 #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2134 #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
2135 
2136 #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
2137 #define BNX2_RPM_RC_CNTL_2 0x00001910
2138 #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2139 #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
2140 
2141 #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
2142 #define BNX2_RPM_RC_CNTL_3 0x00001918
2143 #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2144 #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
2145 
2146 #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
2147 #define BNX2_RPM_RC_CNTL_4 0x00001920
2148 #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2149 #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
2150 
2151 #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
2152 #define BNX2_RPM_RC_CNTL_5 0x00001928
2153 #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2154 #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
2155 
2156 #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
2157 #define BNX2_RPM_RC_CNTL_6 0x00001930
2158 #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2159 #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
2160 
2161 #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
2162 #define BNX2_RPM_RC_CNTL_7 0x00001938
2163 #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2164 #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
2165 
2166 #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
2167 #define BNX2_RPM_RC_CNTL_8 0x00001940
2168 #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2169 #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
2170 
2171 #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
2172 #define BNX2_RPM_RC_CNTL_9 0x00001948
2173 #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2174 #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
2175 
2176 #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
2177 #define BNX2_RPM_RC_CNTL_10 0x00001950
2178 #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2179 #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
2180 
2181 #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
2182 #define BNX2_RPM_RC_CNTL_11 0x00001958
2183 #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2184 #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
2185 
2186 #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
2187 #define BNX2_RPM_RC_CNTL_12 0x00001960
2188 #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2189 #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
2190 
2191 #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
2192 #define BNX2_RPM_RC_CNTL_13 0x00001968
2193 #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2194 #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
2195 
2196 #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
2197 #define BNX2_RPM_RC_CNTL_14 0x00001970
2198 #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2199 #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
2200 
2201 #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
2202 #define BNX2_RPM_RC_CNTL_15 0x00001978
2203 #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2204 #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
2205 
2206 #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
2207 #define BNX2_RPM_RC_CONFIG 0x00001980
2208 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2209 #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2210 
2211 #define BNX2_RPM_DEBUG0 0x00001984
2212 #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2213 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2214 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2215 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2216 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2217 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2218 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2219 #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
2220 #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
2221 #define BNX2_RPM_DEBUG0_DONE (1L<<24)
2222 #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2223 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2224 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2225 #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2226 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2227 
2228 #define BNX2_RPM_DEBUG1 0x00001988
2229 #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2230 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2231 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2232 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2233 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2234 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2235 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2236 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2237 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2238 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2239 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2240 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2241 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2242 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2243 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2244 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2245 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2246 #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2247 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2248 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2249 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2250 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2251 
2252 #define BNX2_RPM_DEBUG2 0x0000198c
2253 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2254 #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2255 #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2256 #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2257 #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2258 #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2259 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2260 #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
2261 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2262 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2263 
2264 #define BNX2_RPM_DEBUG3 0x00001990
2265 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2266 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2267 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2268 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2269 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2270 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2271 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2272 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2273 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2274 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2275 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2276 #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
2277 #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2278 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2279 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2280 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2281 #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2282 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2283 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2284 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2285 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2286 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2287 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2288 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2289 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2290 #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2291 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2292 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2293 #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2294 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2295 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2296 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2297 
2298 #define BNX2_RPM_DEBUG4 0x00001994
2299 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2300 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2301 #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2302 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2303 
2304 #define BNX2_RPM_DEBUG5 0x00001998
2305 #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2306 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2307 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2308 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2309 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2310 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2311 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2312 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2313 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2314 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2315 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2316 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2317 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2318 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2319 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2320 #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2321 
2322 #define BNX2_RPM_DEBUG6 0x0000199c
2323 #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2324 #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
2325 
2326 #define BNX2_RPM_DEBUG7 0x000019a0
2327 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2328 
2329 #define BNX2_RPM_DEBUG8 0x000019a4
2330 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2331 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2332 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2333 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2334 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2335 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2336 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2337 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2338 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2339 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2340 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2341 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2342 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2343 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2344 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2345 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2346 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2347 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2348 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2349 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2350 #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
2351 #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
2352 #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2353 #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
2354 #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2355 #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2356 
2357 #define BNX2_RPM_DEBUG9 0x000019a8
2358 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2359 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2360 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2361 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2362 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2363 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2364 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2365 
2366 #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
2367 #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
2368 #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
2369 #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
2370 #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
2371 #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
2372 #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
2373 #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
2374 #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
2375 #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
2376 #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
2377 #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
2378 #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
2379 #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
2380 #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
2381 #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
2382 
2383 
2384 /*
2385  * rbuf_reg definition
2386  * offset: 0x200000
2387  */
2388 #define BNX2_RBUF_COMMAND 0x00200000
2389 #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
2390 #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
2391 #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
2392 #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
2393 #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2394 
2395 #define BNX2_RBUF_STATUS1 0x00200004
2396 #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2397 
2398 #define BNX2_RBUF_STATUS2 0x00200008
2399 #define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2400 #define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2401 
2402 #define BNX2_RBUF_CONFIG 0x0020000c
2403 #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2404 #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2405 
2406 #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
2407 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2408 
2409 #define BNX2_RBUF_FW_BUF_FREE 0x00200014
2410 #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2411 #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2412 #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2413 
2414 #define BNX2_RBUF_FW_BUF_SEL 0x00200018
2415 #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2416 #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2417 #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2418 
2419 #define BNX2_RBUF_CONFIG2 0x0020001c
2420 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2421 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2422 
2423 #define BNX2_RBUF_CONFIG3 0x00200020
2424 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2425 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2426 
2427 #define BNX2_RBUF_PKT_DATA 0x00208000
2428 #define BNX2_RBUF_CLIST_DATA 0x00210000
2429 #define BNX2_RBUF_BUF_DATA 0x00220000
2430 
2431 
2432 /*
2433  * rv2p_reg definition
2434  * offset: 0x2800
2435  */
2436 #define BNX2_RV2P_COMMAND 0x00002800
2437 #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
2438 #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2439 #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2440 #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
2441 #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
2442 #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
2443 #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
2444 #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
2445 #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
2446 #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
2447 #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
2448 #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2449 
2450 #define BNX2_RV2P_STATUS 0x00002804
2451 #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
2452 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2453 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2454 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2455 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2456 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
2457 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
2458 
2459 #define BNX2_RV2P_CONFIG 0x00002808
2460 #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
2461 #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
2462 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
2463 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
2464 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
2465 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
2466 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
2467 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
2468 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
2469 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
2470 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
2471 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
2472 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
2473 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
2474 #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
2475 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
2476 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
2477 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
2478 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
2479 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
2480 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
2481 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
2482 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
2483 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
2484 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
2485 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
2486 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
2487 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
2488 
2489 #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
2490 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
2491 
2492 #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
2493 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
2494 
2495 #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
2496 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
2497 
2498 #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
2499 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
2500 
2501 #define BNX2_RV2P_INSTR_HIGH 0x00002830
2502 #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
2503 
2504 #define BNX2_RV2P_INSTR_LOW 0x00002834
2505 #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
2506 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
2507 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
2508 
2509 #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
2510 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
2511 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
2512 
2513 #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
2514 #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
2515 #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
2516 #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
2517 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2518 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2519 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2520 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2521 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2522 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2523 
2524 #define BNX2_RV2P_PFTQ_DATA 0x00002b40
2525 #define BNX2_RV2P_PFTQ_CMD 0x00002b78
2526 #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
2527 #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
2528 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
2529 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
2530 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
2531 #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
2532 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
2533 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
2534 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
2535 #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
2536 #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
2537 
2538 #define BNX2_RV2P_PFTQ_CTL 0x00002b7c
2539 #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
2540 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
2541 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
2542 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2543 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2544 
2545 #define BNX2_RV2P_TFTQ_DATA 0x00002b80
2546 #define BNX2_RV2P_TFTQ_CMD 0x00002bb8
2547 #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
2548 #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
2549 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
2550 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
2551 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
2552 #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
2553 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
2554 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
2555 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
2556 #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
2557 #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
2558 
2559 #define BNX2_RV2P_TFTQ_CTL 0x00002bbc
2560 #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
2561 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
2562 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
2563 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2564 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2565 
2566 #define BNX2_RV2P_MFTQ_DATA 0x00002bc0
2567 #define BNX2_RV2P_MFTQ_CMD 0x00002bf8
2568 #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
2569 #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
2570 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
2571 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
2572 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
2573 #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
2574 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
2575 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
2576 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
2577 #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
2578 #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
2579 
2580 #define BNX2_RV2P_MFTQ_CTL 0x00002bfc
2581 #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
2582 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
2583 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
2584 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2585 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2586 
2587 
2588 
2589 /*
2590  * mq_reg definition
2591  * offset: 0x3c00
2592  */
2593 #define BNX2_MQ_COMMAND 0x00003c00
2594 #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
2595 #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
2596 #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
2597 #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
2598 
2599 #define BNX2_MQ_STATUS 0x00003c04
2600 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
2601 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
2602 #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
2603 
2604 #define BNX2_MQ_CONFIG 0x00003c08
2605 #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
2606 #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
2607 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
2608 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
2609 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
2610 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
2611 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
2612 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
2613 #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
2614 #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
2615 
2616 #define BNX2_MQ_ENQUEUE1 0x00003c0c
2617 #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
2618 #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
2619 #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
2620 #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
2621 
2622 #define BNX2_MQ_ENQUEUE2 0x00003c10
2623 #define BNX2_MQ_BAD_WR_ADDR 0x00003c14
2624 #define BNX2_MQ_BAD_RD_ADDR 0x00003c18
2625 #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
2626 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
2627 
2628 #define BNX2_MQ_KNL_WIND_END 0x00003c20
2629 #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
2630 
2631 #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
2632 #define BNX2_MQ_KNL_TX_MASK1 0x00003c28
2633 #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
2634 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
2635 #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
2636 #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
2637 #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
2638 #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
2639 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
2640 #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
2641 #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
2642 #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
2643 #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
2644 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
2645 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
2646 #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
2647 #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
2648 #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
2649 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
2650 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
2651 #define BNX2_MQ_MEM_WR_ADDR 0x00003c74
2652 #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
2653 
2654 #define BNX2_MQ_MEM_WR_DATA0 0x00003c78
2655 #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
2656 
2657 #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
2658 #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
2659 
2660 #define BNX2_MQ_MEM_WR_DATA2 0x00003c80
2661 #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
2662 
2663 #define BNX2_MQ_MEM_RD_ADDR 0x00003c84
2664 #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
2665 
2666 #define BNX2_MQ_MEM_RD_DATA0 0x00003c88
2667 #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
2668 
2669 #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
2670 #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
2671 
2672 #define BNX2_MQ_MEM_RD_DATA2 0x00003c90
2673 #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
2674 
2675 
2676 
2677 /*
2678  * tbdr_reg definition
2679  * offset: 0x5000
2680  */
2681 #define BNX2_TBDR_COMMAND 0x00005000
2682 #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
2683 #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
2684 #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
2685 
2686 #define BNX2_TBDR_STATUS 0x00005004
2687 #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
2688 #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
2689 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
2690 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
2691 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
2692 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
2693 #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
2694 
2695 #define BNX2_TBDR_CONFIG 0x00005008
2696 #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
2697 #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
2698 #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
2699 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
2700 #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
2701 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
2702 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
2703 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
2704 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
2705 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
2706 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
2707 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
2708 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
2709 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
2710 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
2711 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
2712 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
2713 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
2714 
2715 #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
2716 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2717 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2718 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2719 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2720 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2721 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2722 
2723 #define BNX2_TBDR_FTQ_DATA 0x000053c0
2724 #define BNX2_TBDR_FTQ_CMD 0x000053f8
2725 #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
2726 #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
2727 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
2728 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
2729 #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
2730 #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
2731 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
2732 #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
2733 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
2734 #define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
2735 #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
2736 
2737 #define BNX2_TBDR_FTQ_CTL 0x000053fc
2738 #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
2739 #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
2740 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2741 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2742 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2743 
2744 
2745 
2746 /*
2747  * tdma_reg definition
2748  * offset: 0x5c00
2749  */
2750 #define BNX2_TDMA_COMMAND 0x00005c00
2751 #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
2752 #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
2753 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
2754 
2755 #define BNX2_TDMA_STATUS 0x00005c04
2756 #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
2757 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
2758 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
2759 #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
2760 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
2761 #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
2762 
2763 #define BNX2_TDMA_CONFIG 0x00005c08
2764 #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
2765 #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
2766 #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
2767 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
2768 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
2769 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
2770 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
2771 #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
2772 #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
2773 #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
2774 #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
2775 #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
2776 #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
2777 #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
2778 #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
2779 
2780 #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
2781 #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
2782 
2783 #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
2784 #define BNX2_TDMA_DBG_TRIGGER 0x00005c14
2785 #define BNX2_TDMA_DMAD_FSM 0x00005c80
2786 #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
2787 #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
2788 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
2789 #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
2790 #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
2791 #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
2792 #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
2793 
2794 #define BNX2_TDMA_DMAD_STATUS 0x00005c84
2795 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
2796 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
2797 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
2798 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
2799 
2800 #define BNX2_TDMA_DR_INTF_FSM 0x00005c88
2801 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
2802 #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
2803 #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
2804 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
2805 #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
2806 
2807 #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
2808 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
2809 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
2810 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
2811 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
2812 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
2813 
2814 #define BNX2_TDMA_FTQ_DATA 0x00005fc0
2815 #define BNX2_TDMA_FTQ_CMD 0x00005ff8
2816 #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
2817 #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
2818 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
2819 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
2820 #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
2821 #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
2822 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
2823 #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
2824 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
2825 #define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
2826 #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
2827 
2828 #define BNX2_TDMA_FTQ_CTL 0x00005ffc
2829 #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
2830 #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
2831 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2832 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2833 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2834 
2835 
2836 
2837 /*
2838  * hc_reg definition
2839  * offset: 0x6800
2840  */
2841 #define BNX2_HC_COMMAND 0x00006800
2842 #define BNX2_HC_COMMAND_ENABLE (1L<<0)
2843 #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
2844 #define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
2845 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
2846 #define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
2847 #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
2848 #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
2849 #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
2850 #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
2851 #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
2852 #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
2853 
2854 #define BNX2_HC_STATUS 0x00006804
2855 #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
2856 #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
2857 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
2858 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
2859 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
2860 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
2861 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
2862 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
2863 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
2864 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
2865 
2866 #define BNX2_HC_CONFIG 0x00006808
2867 #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
2868 #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
2869 #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
2870 #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
2871 #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
2872 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
2873 #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
2874 #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
2875 
2876 #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
2877 #define BNX2_HC_STATUS_ADDR_L 0x00006810
2878 #define BNX2_HC_STATUS_ADDR_H 0x00006814
2879 #define BNX2_HC_STATISTICS_ADDR_L 0x00006818
2880 #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
2881 #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
2882 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2883 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
2884 
2885 #define BNX2_HC_COMP_PROD_TRIP 0x00006824
2886 #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
2887 #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
2888 
2889 #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
2890 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2891 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
2892 
2893 #define BNX2_HC_RX_TICKS 0x0000682c
2894 #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
2895 #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
2896 
2897 #define BNX2_HC_TX_TICKS 0x00006830
2898 #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
2899 #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
2900 
2901 #define BNX2_HC_COM_TICKS 0x00006834
2902 #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
2903 #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
2904 
2905 #define BNX2_HC_CMD_TICKS 0x00006838
2906 #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
2907 #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
2908 
2909 #define BNX2_HC_PERIODIC_TICKS 0x0000683c
2910 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
2911 
2912 #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
2913 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
2914 
2915 #define BNX2_HC_STATS_TICKS 0x00006844
2916 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
2917 
2918 #define BNX2_HC_STAT_MEM_DATA 0x0000684c
2919 #define BNX2_HC_STAT_GEN_SEL_0 0x00006850
2920 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
2921 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
2922 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
2923 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
2924 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
2925 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
2926 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
2927 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
2928 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
2929 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
2930 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
2931 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
2932 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
2933 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
2934 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
2935 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
2936 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
2937 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
2938 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
2939 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
2940 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
2941 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
2942 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
2943 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
2944 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
2945 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
2946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
2947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
2948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
2949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
2950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
2951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
2952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
2953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
2954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
2955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
2956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
2957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
2958 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
2959 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
2960 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
2961 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
2962 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
2963 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
2964 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
2965 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
2966 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
2967 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
2968 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
2969 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
2970 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
2971 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
2972 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
2973 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
2974 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
2975 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
2976 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
2977 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
2978 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
2979 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
2980 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
2981 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
2982 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
2983 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
2984 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
2985 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
2986 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
2987 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
2988 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
2989 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
2990 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
2991 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
2992 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
2993 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
2994 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
2995 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
2996 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
2997 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
2998 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
2999 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
3000 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
3001 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
3002 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
3003 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
3004 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
3005 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
3006 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
3007 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
3008 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
3009 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
3010 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
3011 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
3012 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
3013 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
3014 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
3015 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
3016 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
3017 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
3018 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
3019 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
3020 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
3021 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
3022 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
3023 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
3024 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
3025 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
3026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
3027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
3028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
3029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
3030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
3031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
3032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
3033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
3034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
3035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
3036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
3037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
3038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
3039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
3040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
3041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
3042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
3043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
3044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
3045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
3046 
3047 #define BNX2_HC_STAT_GEN_SEL_1 0x00006854
3048 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
3049 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
3050 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
3051 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
3052 
3053 #define BNX2_HC_STAT_GEN_SEL_2 0x00006858
3054 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
3055 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
3056 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
3057 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
3058 
3059 #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
3060 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
3061 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
3062 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
3063 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
3064 
3065 #define BNX2_HC_STAT_GEN_STAT0 0x00006888
3066 #define BNX2_HC_STAT_GEN_STAT1 0x0000688c
3067 #define BNX2_HC_STAT_GEN_STAT2 0x00006890
3068 #define BNX2_HC_STAT_GEN_STAT3 0x00006894
3069 #define BNX2_HC_STAT_GEN_STAT4 0x00006898
3070 #define BNX2_HC_STAT_GEN_STAT5 0x0000689c
3071 #define BNX2_HC_STAT_GEN_STAT6 0x000068a0
3072 #define BNX2_HC_STAT_GEN_STAT7 0x000068a4
3073 #define BNX2_HC_STAT_GEN_STAT8 0x000068a8
3074 #define BNX2_HC_STAT_GEN_STAT9 0x000068ac
3075 #define BNX2_HC_STAT_GEN_STAT10 0x000068b0
3076 #define BNX2_HC_STAT_GEN_STAT11 0x000068b4
3077 #define BNX2_HC_STAT_GEN_STAT12 0x000068b8
3078 #define BNX2_HC_STAT_GEN_STAT13 0x000068bc
3079 #define BNX2_HC_STAT_GEN_STAT14 0x000068c0
3080 #define BNX2_HC_STAT_GEN_STAT15 0x000068c4
3081 #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
3082 #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
3083 #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
3084 #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
3085 #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
3086 #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
3087 #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
3088 #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
3089 #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
3090 #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
3091 #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
3092 #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
3093 #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
3094 #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
3095 #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
3096 #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
3097 #define BNX2_HC_VIS 0x00006908
3098 #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3099 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3100 #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3101 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3102 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3103 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3104 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3105 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3106 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3107 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3108 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3109 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3110 #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3111 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3112 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3113 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3114 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3115 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3116 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3117 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3118 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3119 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3120 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3121 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3122 #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3123 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3124 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3125 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3126 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3127 
3128 #define BNX2_HC_VIS_1 0x0000690c
3129 #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3130 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3131 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3132 #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3133 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3134 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3135 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3136 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3137 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3138 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3139 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3140 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3141 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3142 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3143 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3144 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3145 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3146 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3147 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3148 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3149 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3150 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3151 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3152 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3153 #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
3154 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3155 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3156 #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3157 #define BNX2_HC_VIS_1_INT_B (1L<<27)
3158 
3159 #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
3160 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3161 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3162 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3163 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3164 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3165 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3166 
3167 
3168 
3169 /*
3170  * txp_reg definition
3171  * offset: 0x40000
3172  */
3173 #define BNX2_TXP_CPU_MODE 0x00045000
3174 #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3175 #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
3176 #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3177 #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3178 #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3179 #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3180 #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3181 #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3182 #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3183 #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3184 #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3185 
3186 #define BNX2_TXP_CPU_STATE 0x00045004
3187 #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3188 #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3189 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3190 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3191 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3192 #define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3193 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3194 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3195 #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3196 #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3197 #define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3198 #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3199 #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3200 #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3201 
3202 #define BNX2_TXP_CPU_EVENT_MASK 0x00045008
3203 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3204 #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3205 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3206 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3207 #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3208 #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3209 #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3210 #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3211 #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3212 #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3213 #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3214 
3215 #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3216 #define BNX2_TXP_CPU_INSTRUCTION 0x00045020
3217 #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
3218 #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3219 #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3220 #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3221 #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
3222 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3223 #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3224 
3225 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3226 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3227 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3228 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3229 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3230 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3231 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3232 
3233 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3234 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3235 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3236 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3237 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3238 
3239 #define BNX2_TXP_CPU_REG_FILE 0x00045200
3240 #define BNX2_TXP_FTQ_DATA 0x000453c0
3241 #define BNX2_TXP_FTQ_CMD 0x000453f8
3242 #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3243 #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
3244 #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3245 #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3246 #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3247 #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
3248 #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3249 #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3250 #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3251 #define BNX2_TXP_FTQ_CMD_POP (1L<<30)
3252 #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
3253 
3254 #define BNX2_TXP_FTQ_CTL 0x000453fc
3255 #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
3256 #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3257 #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3258 #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3259 #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3260 
3261 #define BNX2_TXP_SCRATCH 0x00060000
3262 
3263 
3264 /*
3265  * tpat_reg definition
3266  * offset: 0x80000
3267  */
3268 #define BNX2_TPAT_CPU_MODE 0x00085000
3269 #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3270 #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3271 #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3272 #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3273 #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3274 #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3275 #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3276 #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3277 #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3278 #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3279 #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3280 
3281 #define BNX2_TPAT_CPU_STATE 0x00085004
3282 #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3283 #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3284 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3285 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3286 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3287 #define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3288 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3289 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3290 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3291 #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3292 #define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3293 #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3294 #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3295 #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3296 
3297 #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
3298 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3299 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3300 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3301 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3302 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3303 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3304 #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3305 #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3306 #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3307 #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3308 #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3309 
3310 #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3311 #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
3312 #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
3313 #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3314 #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3315 #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3316 #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
3317 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3318 #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3319 
3320 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3321 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3322 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3323 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3324 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3325 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3326 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3327 
3328 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3329 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3330 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3331 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3332 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3333 
3334 #define BNX2_TPAT_CPU_REG_FILE 0x00085200
3335 #define BNX2_TPAT_FTQ_DATA 0x000853c0
3336 #define BNX2_TPAT_FTQ_CMD 0x000853f8
3337 #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3338 #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3339 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3340 #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3341 #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3342 #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3343 #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3344 #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3345 #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3346 #define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
3347 #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
3348 
3349 #define BNX2_TPAT_FTQ_CTL 0x000853fc
3350 #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3351 #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3352 #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3353 #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3354 #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3355 
3356 #define BNX2_TPAT_SCRATCH 0x000a0000
3357 
3358 
3359 /*
3360  * rxp_reg definition
3361  * offset: 0xc0000
3362  */
3363 #define BNX2_RXP_CPU_MODE 0x000c5000
3364 #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3365 #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
3366 #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3367 #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3368 #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3369 #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3370 #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3371 #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3372 #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3373 #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3374 #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3375 
3376 #define BNX2_RXP_CPU_STATE 0x000c5004
3377 #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3378 #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3379 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3380 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3381 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3382 #define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3383 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3384 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3385 #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3386 #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3387 #define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3388 #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3389 #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3390 #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3391 
3392 #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
3393 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3394 #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3395 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3396 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3397 #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3398 #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3399 #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3400 #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3401 #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3402 #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3403 #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3404 
3405 #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3406 #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
3407 #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
3408 #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3409 #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3410 #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3411 #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
3412 #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3413 #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3414 
3415 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3416 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3417 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3418 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3419 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3420 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3421 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3422 
3423 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3424 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3425 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3426 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3427 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3428 
3429 #define BNX2_RXP_CPU_REG_FILE 0x000c5200
3430 #define BNX2_RXP_CFTQ_DATA 0x000c5380
3431 #define BNX2_RXP_CFTQ_CMD 0x000c53b8
3432 #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3433 #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3434 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3435 #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3436 #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3437 #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3438 #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3439 #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3440 #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3441 #define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
3442 #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
3443 
3444 #define BNX2_RXP_CFTQ_CTL 0x000c53bc
3445 #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3446 #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3447 #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3448 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3449 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3450 
3451 #define BNX2_RXP_FTQ_DATA 0x000c53c0
3452 #define BNX2_RXP_FTQ_CMD 0x000c53f8
3453 #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3454 #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
3455 #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3456 #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3457 #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
3458 #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
3459 #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3460 #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
3461 #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3462 #define BNX2_RXP_FTQ_CMD_POP (1L<<30)
3463 #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
3464 
3465 #define BNX2_RXP_FTQ_CTL 0x000c53fc
3466 #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
3467 #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
3468 #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3469 #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3470 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3471 
3472 #define BNX2_RXP_SCRATCH 0x000e0000
3473 
3474 
3475 /*
3476  * com_reg definition
3477  * offset: 0x100000
3478  */
3479 #define BNX2_COM_CPU_MODE 0x00105000
3480 #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
3481 #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
3482 #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3483 #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3484 #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
3485 #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
3486 #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
3487 #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3488 #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3489 #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3490 #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3491 
3492 #define BNX2_COM_CPU_STATE 0x00105004
3493 #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
3494 #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
3495 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3496 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3497 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3498 #define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
3499 #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
3500 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3501 #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
3502 #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3503 #define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
3504 #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3505 #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
3506 #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
3507 
3508 #define BNX2_COM_CPU_EVENT_MASK 0x00105008
3509 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3510 #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3511 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3512 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3513 #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3514 #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3515 #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3516 #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3517 #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3518 #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3519 #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3520 
3521 #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
3522 #define BNX2_COM_CPU_INSTRUCTION 0x00105020
3523 #define BNX2_COM_CPU_DATA_ACCESS 0x00105024
3524 #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
3525 #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
3526 #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
3527 #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
3528 #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3529 #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3530 
3531 #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
3532 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3533 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3534 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3535 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3536 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3537 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3538 
3539 #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
3540 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3541 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3542 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3543 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3544 
3545 #define BNX2_COM_CPU_REG_FILE 0x00105200
3546 #define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
3547 #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
3548 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3549 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
3550 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3551 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3552 #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
3553 #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
3554 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3555 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
3556 #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3557 #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
3558 #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
3559 
3560 #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
3561 #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
3562 #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
3563 #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3564 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3565 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3566 
3567 #define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
3568 #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
3569 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3570 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
3571 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3572 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3573 #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
3574 #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
3575 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3576 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
3577 #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3578 #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
3579 #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
3580 
3581 #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
3582 #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
3583 #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
3584 #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3585 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3586 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3587 
3588 #define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
3589 #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
3590 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3591 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
3592 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3593 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3594 #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
3595 #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
3596 #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3597 #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
3598 #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3599 #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
3600 #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
3601 
3602 #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
3603 #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
3604 #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
3605 #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3606 #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3607 #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3608 
3609 #define BNX2_COM_SCRATCH 0x00120000
3610 
3611 
3612 /*
3613  * cp_reg definition
3614  * offset: 0x180000
3615  */
3616 #define BNX2_CP_CPU_MODE 0x00185000
3617 #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
3618 #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
3619 #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3620 #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3621 #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
3622 #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3623 #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
3624 #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3625 #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3626 #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3627 #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3628 
3629 #define BNX2_CP_CPU_STATE 0x00185004
3630 #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
3631 #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3632 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3633 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3634 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3635 #define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3636 #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
3637 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3638 #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
3639 #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3640 #define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
3641 #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3642 #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3643 #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
3644 
3645 #define BNX2_CP_CPU_EVENT_MASK 0x00185008
3646 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3647 #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3648 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3649 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3650 #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3651 #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3652 #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3653 #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3654 #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3655 #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3656 #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3657 
3658 #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
3659 #define BNX2_CP_CPU_INSTRUCTION 0x00185020
3660 #define BNX2_CP_CPU_DATA_ACCESS 0x00185024
3661 #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
3662 #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
3663 #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
3664 #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
3665 #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3666 #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3667 
3668 #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
3669 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3670 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3671 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3672 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3673 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3674 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3675 
3676 #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
3677 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3678 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3679 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3680 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3681 
3682 #define BNX2_CP_CPU_REG_FILE 0x00185200
3683 #define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
3684 #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
3685 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3686 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
3687 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3688 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3689 #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
3690 #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
3691 #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3692 #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
3693 #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3694 #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
3695 #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
3696 
3697 #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
3698 #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
3699 #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
3700 #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3701 #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3702 #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3703 
3704 #define BNX2_CP_SCRATCH 0x001a0000
3705 
3706 
3707 /*
3708  * mcp_reg definition
3709  * offset: 0x140000
3710  */
3711 #define BNX2_MCP_CPU_MODE 0x00145000
3712 #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
3713 #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
3714 #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3715 #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3716 #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
3717 #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3718 #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
3719 #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3720 #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3721 #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3722 #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3723 
3724 #define BNX2_MCP_CPU_STATE 0x00145004
3725 #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
3726 #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3727 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3728 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3729 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3730 #define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3731 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
3732 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3733 #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
3734 #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3735 #define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
3736 #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3737 #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3738 #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
3739 
3740 #define BNX2_MCP_CPU_EVENT_MASK 0x00145008
3741 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3742 #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3743 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3744 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3745 #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3746 #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3747 #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3748 #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3749 #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3750 #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3751 #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3752 
3753 #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
3754 #define BNX2_MCP_CPU_INSTRUCTION 0x00145020
3755 #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
3756 #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
3757 #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
3758 #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
3759 #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
3760 #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3761 #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3762 
3763 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
3764 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3765 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3766 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3767 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3768 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3769 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3770 
3771 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
3772 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3773 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3774 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3775 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3776 
3777 #define BNX2_MCP_CPU_REG_FILE 0x00145200
3778 #define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
3779 #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
3780 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3781 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
3782 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3783 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3784 #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
3785 #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
3786 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3787 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
3788 #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3789 #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
3790 #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
3791 
3792 #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
3793 #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
3794 #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
3795 #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3796 #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3797 #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3798 
3799 #define BNX2_MCP_ROM 0x00150000
3800 #define BNX2_MCP_SCRATCH 0x00160000
3801 
3802 #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
3803 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
3804 #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
3805 #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
3806 #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
3807 
3808 #define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
3809 #define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
3810 
3811 
3812 #define NUM_MC_HASH_REGISTERS 8
3813 
3814 
3815 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
3816 #define PHY_BCM5706_PHY_ID 0x00206160
3817 
3818 #define PHY_ID(id) ((id) & 0xfffffff0)
3819 #define PHY_REV_ID(id) ((id) & 0xf)
3820 
3821 /* 5708 Serdes PHY registers */
3822 
3823 #define BCM5708S_UP1 0xb
3824 
3825 #define BCM5708S_UP1_2G5 0x1
3826 
3827 #define BCM5708S_BLK_ADDR 0x1f
3828 
3829 #define BCM5708S_BLK_ADDR_DIG 0x0000
3830 #define BCM5708S_BLK_ADDR_DIG3 0x0002
3831 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
3832 
3833 /* Digital Block */
3834 #define BCM5708S_1000X_CTL1 0x10
3835 
3836 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
3837 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
3838 
3839 #define BCM5708S_1000X_CTL2 0x11
3840 
3841 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
3842 
3843 #define BCM5708S_1000X_STAT1 0x14
3844 
3845 #define BCM5708S_1000X_STAT1_SGMII 0x0001
3846 #define BCM5708S_1000X_STAT1_LINK 0x0002
3847 #define BCM5708S_1000X_STAT1_FD 0x0004
3848 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
3849 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
3850 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
3851 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
3852 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
3853 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
3854 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
3855 
3856 /* Digital3 Block */
3857 #define BCM5708S_DIG_3_0 0x10
3858 
3859 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
3860 
3861 /* Tx/Misc Block */
3862 #define BCM5708S_TX_ACTL1 0x15
3863 
3864 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
3865 
3866 #define BCM5708S_TX_ACTL3 0x17
3867 
3868 #define MIN_ETHERNET_PACKET_SIZE 60
3869 #define MAX_ETHERNET_PACKET_SIZE 1514
3870 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
3871 
3872 #define RX_COPY_THRESH 92
3873 
3874 #define DMA_READ_CHANS 5
3875 #define DMA_WRITE_CHANS 3
3876 
3877 #define BCM_PAGE_BITS 12
3878 #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
3879 
3880 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
3881 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
3882 
3883 #define MAX_RX_RINGS 4
3884 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
3885 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
3886 #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
3887 
3888 #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
3889  (MAX_TX_DESC_CNT - 1)) ? \
3890  (x) + 2 : (x) + 1
3891 
3892 #define PREV_TX_BD(x) ((((x)-1) & (MAX_TX_DESC_CNT)) == \
3893  (MAX_TX_DESC_CNT)) ? \
3894  (x) - 2 : (x) - 1
3895 
3896 #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
3897 
3898 #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
3899  (MAX_RX_DESC_CNT - 1)) ? \
3900  (x) + 2 : (x) + 1
3901 
3902 #define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
3903 
3904 //#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
3905 #define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
3906 
3907 /* Context size. */
3908 #define CTX_SHIFT 7
3909 #define CTX_SIZE (1 << CTX_SHIFT)
3910 #define CTX_MASK (CTX_SIZE - 1)
3911 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
3912 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
3913 
3914 #define PHY_CTX_SHIFT 6
3915 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
3916 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
3917 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
3918 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
3919 
3920 #define MB_KERNEL_CTX_SHIFT 8
3921 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
3922 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
3923 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
3924 
3925 #define MAX_CID_CNT 0x4000
3926 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
3927 #define INVALID_CID_ADDR 0xffffffff
3928 
3929 #define TX_CID 16
3930 #define RX_CID 0
3931 
3932 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
3933 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
3934 
3935 #if 0
3936 struct sw_bd {
3937  struct sk_buff *skb;
3938  DECLARE_PCI_UNMAP_ADDR(mapping)
3939 };
3940 #endif
3941 
3942 /* Buffered flash (Atmel: AT45DB011B) specific information */
3943 #define SEEPROM_PAGE_BITS 2
3944 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
3945 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
3946 #define SEEPROM_PAGE_SIZE 4
3947 #define SEEPROM_TOTAL_SIZE 65536
3948 
3949 #define BUFFERED_FLASH_PAGE_BITS 9
3950 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
3951 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
3952 #define BUFFERED_FLASH_PAGE_SIZE 264
3953 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
3954 
3955 #define SAIFUN_FLASH_PAGE_BITS 8
3956 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
3957 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
3958 #define SAIFUN_FLASH_PAGE_SIZE 256
3959 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
3960 
3961 #define ST_MICRO_FLASH_PAGE_BITS 8
3962 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
3963 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
3964 #define ST_MICRO_FLASH_PAGE_SIZE 256
3965 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
3966 
3967 #define NVRAM_TIMEOUT_COUNT 30000
3968 
3969 
3970 #define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
3971  BNX2_NVM_CFG1_BUFFER_MODE | \
3972  BNX2_NVM_CFG1_PROTECT_MODE | \
3973  BNX2_NVM_CFG1_FLASH_SIZE)
3974 
3975 #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
3976 
3977 struct flash_spec {
3988  char *name;
3989 };
3990 
3991 struct bnx2 {
3992  /* Fields used in the tx and intr/napi performance paths are grouped */
3993  /* together in the beginning of the structure. */
3994  void /*__iomem*/ *regview;
3995 
3996  struct nic *nic;
3997  struct pci_device *pdev;
3998 
3999  /* atomic_t intr_sem; */
4000 
4003 
4005 #define PCIX_FLAG 1
4006 #define PCI_32BIT_FLAG 2
4007 #define ONE_TDMA_FLAG 4 /* no longer used */
4008 #define NO_WOL_FLAG 8
4009 #define USING_DAC_FLAG 0x10
4010 #define USING_MSI_FLAG 0x20
4011 #define ASF_ENABLE_FLAG 0x40
4012 
4013  /* Put tx producer and consumer fields in separate cache lines. */
4014  u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
4016 
4018  struct sw_bd *tx_buf_ring;
4020 
4021  u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
4023 
4024 #ifdef BCM_VLAN
4025  struct vlan_group *vlgrp;
4026 #endif
4027 
4029  u32 rx_buf_use_size; /* useable size */
4030  u32 rx_buf_size; /* with alignment */
4032 
4037 
4039 
4040 #if 0
4041  struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
4042 #endif
4044 
4045  /* End of fields used in the performance code paths. */
4046 
4047  char *name;
4048 
4049 #if 0
4050  int timer_interval;
4051  int current_interval;
4052  struct timer_list timer;
4053  struct work_struct reset_task;
4054  int in_reset_task;
4055 
4056  /* Used to synchronize phy accesses. */
4057  spinlock_t phy_lock;
4058 #endif
4059 
4061 #define PHY_SERDES_FLAG 1
4062 #define PHY_CRC_FIX_FLAG 2
4063 #define PHY_PARALLEL_DETECT_FLAG 4
4064 #define PHY_2_5G_CAPABLE_FLAG 8
4065 #define PHY_INT_MODE_MASK_FLAG 0x300
4066 #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
4067 #define PHY_INT_MODE_LINK_READY_FLAG 0x200
4068 
4070  /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
4071 #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
4072 #define CHIP_NUM_5706 0x57060000
4073 #define CHIP_NUM_5708 0x57080000
4074 
4075 #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
4076 #define CHIP_REV_Ax 0x00000000
4077 #define CHIP_REV_Bx 0x00001000
4078 #define CHIP_REV_Cx 0x00002000
4079 
4080 #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
4081 #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
4082 
4083 #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
4084 #define CHIP_ID_5706_A0 0x57060000
4085 #define CHIP_ID_5706_A1 0x57060010
4086 #define CHIP_ID_5706_A2 0x57060020
4087 #define CHIP_ID_5708_A0 0x57080000
4088 #define CHIP_ID_5708_B0 0x57081000
4089 #define CHIP_ID_5708_B1 0x57081010
4090 
4091 #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
4092 
4093 /* A serdes chip will have the first bit of the bond id set. */
4094 #define CHIP_BOND_ID_SERDES_BIT 0x01
4095 
4098 
4101 
4103 
4106 
4108 
4109 
4112 #if 0
4114 #endif
4116 
4131 
4133 
4135 
4138 
4141 
4144 
4146 
4149  u8 flow_ctrl; /* actual flow ctrl settings */
4150  /* may be different from */
4151  /* req_flow_ctrl if autoneg */
4152 #define FLOW_CTRL_TX 1
4153 #define FLOW_CTRL_RX 2
4154 
4156 
4157  u8 req_flow_ctrl; /* flow ctrl advertisement */
4158  /* settings or forced */
4159  /* settings */
4161 #define AUTONEG_SPEED 1
4162 #define AUTONEG_FLOW_CTRL 2
4163 
4165 #define MAC_LOOPBACK 1
4166 #define PHY_LOOPBACK 2
4167 
4169 #define SERDES_AN_TIMEOUT (HZ / 3)
4170 
4172 
4174 
4176 
4177  int pm_cap;
4179 
4180  /* struct net_device_stats net_stats; */
4181 
4184 
4186 };
4187 
4188 static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
4189 static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
4190 
4191 #define REG_RD(bp, offset) \
4192  readl(bp->regview + offset)
4193 
4194 #define REG_WR(bp, offset, val) \
4195  writel(val, bp->regview + offset)
4196 
4197 #define REG_WR16(bp, offset, val) \
4198  writew(val, bp->regview + offset)
4199 
4200 #define REG_RD_IND(bp, offset) \
4201  bnx2_reg_rd_ind(bp, offset)
4202 
4203 #define REG_WR_IND(bp, offset, val) \
4204  bnx2_reg_wr_ind(bp, offset, val)
4205 
4206 /* Indirect context access. Unlike the MBQ_WR, these macros will not
4207  * trigger a chip event. */
4208 static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
4209 
4210 #define CTX_WR(bp, cid_addr, offset, val) \
4211  bnx2_ctx_wr(bp, cid_addr, offset, val)
4212 
4213 struct cpu_reg {
4217 
4220 
4226 
4228 
4230 };
4231 
4232 struct fw_info {
4236 
4238 
4239  /* Text section. */
4244 
4245  /* Data section. */
4250 
4251  /* SBSS section. */
4256 
4257  /* BSS section. */
4262 
4263  /* Read-only section. */
4268 };
4269 
4270 #define RV2P_PROC1 0
4271 #define RV2P_PROC2 1
4272 
4273 
4274 /* This value (in milliseconds) determines the frequency of the driver
4275  * issuing the PULSE message code. The firmware monitors this periodic
4276  * pulse to determine when to switch to an OS-absent mode. */
4277 #define DRV_PULSE_PERIOD_MS 250
4278 
4279 /* This value (in milliseconds) determines how long the driver should
4280  * wait for an acknowledgement from the firmware before timing out. Once
4281  * the firmware has timed out, the driver will assume there is no firmware
4282  * running and there won't be any firmware-driver synchronization during a
4283  * driver reset. */
4284 #define FW_ACK_TIME_OUT_MS 100
4285 
4286 
4287 #define BNX2_DRV_RESET_SIGNATURE 0x00000000
4288 #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
4289 //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
4290 
4291 #define BNX2_DRV_MB 0x00000004
4292 #define BNX2_DRV_MSG_CODE 0xff000000
4293 #define BNX2_DRV_MSG_CODE_RESET 0x01000000
4294 #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
4295 #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
4296 #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
4297 #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
4298 #define BNX2_DRV_MSG_CODE_PULSE 0x06000000
4299 #define BNX2_DRV_MSG_CODE_DIAG 0x07000000
4300 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
4301 
4302 #define BNX2_DRV_MSG_DATA 0x00ff0000
4303 #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
4304 #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
4305 #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
4306 #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
4307 
4308 #define BNX2_DRV_MSG_SEQ 0x0000ffff
4309 
4310 #define BNX2_FW_MB 0x00000008
4311 #define BNX2_FW_MSG_ACK 0x0000ffff
4312 #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
4313 #define BNX2_FW_MSG_STATUS_OK 0x00000000
4314 #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
4315 
4316 #define BNX2_LINK_STATUS 0x0000000c
4317 #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
4318 #define BNX2_LINK_STATUS_LINK_UP 0x1
4319 #define BNX2_LINK_STATUS_LINK_DOWN 0x0
4320 #define BNX2_LINK_STATUS_SPEED_MASK 0x1e
4321 #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
4322 #define BNX2_LINK_STATUS_10HALF (1<<1)
4323 #define BNX2_LINK_STATUS_10FULL (2<<1)
4324 #define BNX2_LINK_STATUS_100HALF (3<<1)
4325 #define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
4326 #define BNX2_LINK_STATUS_100FULL (5<<1)
4327 #define BNX2_LINK_STATUS_1000HALF (6<<1)
4328 #define BNX2_LINK_STATUS_1000FULL (7<<1)
4329 #define BNX2_LINK_STATUS_2500HALF (8<<1)
4330 #define BNX2_LINK_STATUS_2500FULL (9<<1)
4331 #define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
4332 #define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
4333 #define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
4334 #define BNX2_LINK_STATUS_RESERVED (1<<8)
4335 #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
4336 #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
4337 #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
4338 #define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
4339 #define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
4340 #define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
4341 #define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
4342 #define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
4343 #define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
4344 #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
4345 #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
4346 #define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
4347 #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
4348 #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
4349 
4350 #define BNX2_DRV_PULSE_MB 0x00000010
4351 #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
4352 
4353 /* Indicate to the firmware not to go into the