iPXE
davicom.c
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1 #ifdef ALLMULTI
2 #error multicast support is not yet implemented
3 #endif
4 /*
5  DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
6 
7  This driver was ported from Marty Connor's Tulip Etherboot driver.
8  Thanks Marty Connor (mdc@etherboot.org)
9 
10  This davicom etherboot driver supports DM9009/DM9102/DM9102A/
11  DM9102A+DM9801/DM9102A+DM9802 NICs.
12 
13  This software may be used and distributed according to the terms
14  of the GNU Public License, incorporated herein by reference.
15 
16 */
17 
18 FILE_LICENCE ( GPL_ANY );
19 
20 /*********************************************************************/
21 /* Revision History */
22 /*********************************************************************/
23 
24 /*
25  19 OCT 2000 Sten 1.00
26  Different half and full duplex mode
27  Do the different programming for DM9801/DM9802
28 
29  12 OCT 2000 Sten 0.90
30  This driver was ported from tulip driver and it
31  has the following difference.
32  Changed symbol tulip/TULIP to davicom/DAVICOM
33  Deleted some code that did not use in this driver.
34  Used chain-strcture to replace ring structure
35  for both TX/RX descriptor.
36  Allocated two tx descriptor.
37  According current media mode to set operating
38  register(CR6)
39 */
40 
41 
42 /*********************************************************************/
43 /* Declarations */
44 /*********************************************************************/
45 
46 #include "etherboot.h"
47 #include "nic.h"
48 #include <ipxe/pci.h>
49 #include <ipxe/ethernet.h>
50 
51 #define TX_TIME_OUT 2*TICKS_PER_SEC
52 
53 /* Register offsets for davicom device */
55  CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
56  CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
57  CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
58 };
59 
60 /* EEPROM Address width definitions */
61 #define EEPROM_ADDRLEN 6
62 #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
63 /* Used to be 128, but we only need to read enough to get the MAC
64  address at bytes 20..25 */
65 
66 /* Data Read from the EEPROM */
67 static unsigned char ee_data[EEPROM_SIZE];
68 
69 /* The EEPROM commands include the alway-set leading bit. */
70 #define EE_WRITE_CMD (5 << addr_len)
71 #define EE_READ_CMD (6 << addr_len)
72 #define EE_ERASE_CMD (7 << addr_len)
73 
74 /* EEPROM_Ctrl bits. */
75 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
76 #define EE_CS 0x01 /* EEPROM chip select. */
77 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
78 #define EE_WRITE_0 0x01
79 #define EE_WRITE_1 0x05
80 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
81 #define EE_ENB (0x4800 | EE_CS)
82 
83 /* Sten 10/11 for phyxcer */
84 #define PHY_DATA_0 0x0
85 #define PHY_DATA_1 0x20000
86 #define MDCLKH 0x10000
87 
88 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
89  implementations don't overrun the EEPROM clock. We add a bus
90  turn-around to insure that this remains true. */
91 #define eeprom_delay() inl(ee_addr)
92 
93 /* helpful macro if on a big_endian machine for changing byte order.
94  not strictly needed on Intel
95  Already defined in Etherboot includes
96 #define le16_to_cpu(val) (val)
97 */
98 
99 /* transmit and receive descriptor format */
100 struct txdesc {
101  volatile unsigned long status; /* owner, status */
102  unsigned long buf1sz:11, /* size of buffer 1 */
103  buf2sz:11, /* size of buffer 2 */
104  control:10; /* control bits */
105  const unsigned char *buf1addr; /* buffer 1 address */
106  const unsigned char *buf2addr; /* buffer 2 address */
107 };
108 
109 struct rxdesc {
110  volatile unsigned long status; /* owner, status */
111  unsigned long buf1sz:11, /* size of buffer 1 */
112  buf2sz:11, /* size of buffer 2 */
113  control:10; /* control bits */
114  unsigned char *buf1addr; /* buffer 1 address */
115  unsigned char *buf2addr; /* buffer 2 address */
116 };
117 
118 /* Size of transmit and receive buffers */
119 #define BUFLEN 1536
120 
121 /*********************************************************************/
122 /* Global Storage */
123 /*********************************************************************/
124 
126 
127 /* PCI Bus parameters */
128 static unsigned short vendor, dev_id;
129 static unsigned long ioaddr;
130 
131 /* Note: transmit and receive buffers must be longword aligned and
132  longword divisable */
133 
134 /* transmit descriptor and buffer */
135 #define NTXD 2
136 #define NRXD 4
137 struct {
138  struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
139  unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
140  struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
141  unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
142 } davicom_bufs __shared;
143 #define txd davicom_bufs.txd
144 #define txb davicom_bufs.txb
145 #define rxd davicom_bufs.rxd
146 #define rxb davicom_bufs.rxb
147 static int rxd_tail;
148 static int TxPtr;
149 
150 
151 /*********************************************************************/
152 /* Function Prototypes */
153 /*********************************************************************/
154 static void whereami(const char *str);
155 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
156 static int davicom_probe(struct nic *nic,struct pci_device *pci);
157 static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
158 static void davicom_reset(struct nic *nic);
159 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
160  unsigned int s, const char *p);
161 static int davicom_poll(struct nic *nic, int retrieve);
162 static void davicom_disable(struct nic *nic);
163 static void davicom_wait(unsigned int nticks);
164 static int phy_read(int);
165 static void phy_write(int, u16);
166 static void phy_write_1bit(u32, u32);
167 static int phy_read_1bit(u32);
168 static void davicom_media_chk(struct nic *);
169 
170 
171 /*********************************************************************/
172 /* Utility Routines */
173 /*********************************************************************/
174 static inline void whereami(const char *str)
175 {
176  DBGP("%s\n", str);
177  /* sleep(2); */
178 }
179 
180 static void davicom_wait(unsigned int nticks)
181 {
182  unsigned int to = currticks() + nticks;
183  while (currticks() < to)
184  /* wait */ ;
185 }
186 
187 
188 /*********************************************************************/
189 /* For DAVICOM phyxcer register by MII interface */
190 /*********************************************************************/
191 /*
192  Read a word data from phy register
193 */
194 static int phy_read(int location)
195 {
196  int i, phy_addr=1;
197  u16 phy_data;
198  u32 io_dcr9;
199 
200  whereami("phy_read\n");
201 
202  io_dcr9 = ioaddr + CSR9;
203 
204  /* Send 33 synchronization clock to Phy controller */
205  for (i=0; i<34; i++)
206  phy_write_1bit(io_dcr9, PHY_DATA_1);
207 
208  /* Send start command(01) to Phy */
209  phy_write_1bit(io_dcr9, PHY_DATA_0);
210  phy_write_1bit(io_dcr9, PHY_DATA_1);
211 
212  /* Send read command(10) to Phy */
213  phy_write_1bit(io_dcr9, PHY_DATA_1);
214  phy_write_1bit(io_dcr9, PHY_DATA_0);
215 
216  /* Send Phy address */
217  for (i=0x10; i>0; i=i>>1)
218  phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
219 
220  /* Send register address */
221  for (i=0x10; i>0; i=i>>1)
222  phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
223 
224  /* Skip transition state */
225  phy_read_1bit(io_dcr9);
226 
227  /* read 16bit data */
228  for (phy_data=0, i=0; i<16; i++) {
229  phy_data<<=1;
230  phy_data|=phy_read_1bit(io_dcr9);
231  }
232 
233  return phy_data;
234 }
235 
236 /*
237  Write a word to Phy register
238 */
239 static void phy_write(int location, u16 phy_data)
240 {
241  u16 i, phy_addr=1;
242  u32 io_dcr9;
243 
244  whereami("phy_write\n");
245 
246  io_dcr9 = ioaddr + CSR9;
247 
248  /* Send 33 synchronization clock to Phy controller */
249  for (i=0; i<34; i++)
250  phy_write_1bit(io_dcr9, PHY_DATA_1);
251 
252  /* Send start command(01) to Phy */
253  phy_write_1bit(io_dcr9, PHY_DATA_0);
254  phy_write_1bit(io_dcr9, PHY_DATA_1);
255 
256  /* Send write command(01) to Phy */
257  phy_write_1bit(io_dcr9, PHY_DATA_0);
258  phy_write_1bit(io_dcr9, PHY_DATA_1);
259 
260  /* Send Phy address */
261  for (i=0x10; i>0; i=i>>1)
262  phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
263 
264  /* Send register address */
265  for (i=0x10; i>0; i=i>>1)
266  phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
267 
268  /* written trasnition */
269  phy_write_1bit(io_dcr9, PHY_DATA_1);
270  phy_write_1bit(io_dcr9, PHY_DATA_0);
271 
272  /* Write a word data to PHY controller */
273  for (i=0x8000; i>0; i>>=1)
274  phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
275 }
276 
277 /*
278  Write one bit data to Phy Controller
279 */
280 static void phy_write_1bit(u32 ee_addr, u32 phy_data)
281 {
282  whereami("phy_write_1bit\n");
283  outl(phy_data, ee_addr); /* MII Clock Low */
284  eeprom_delay();
285  outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
286  eeprom_delay();
287  outl(phy_data, ee_addr); /* MII Clock Low */
288  eeprom_delay();
289 }
290 
291 /*
292  Read one bit phy data from PHY controller
293 */
294 static int phy_read_1bit(u32 ee_addr)
295 {
296  int phy_data;
297 
298  whereami("phy_read_1bit\n");
299 
300  outl(0x50000, ee_addr);
301  eeprom_delay();
302 
303  phy_data=(inl(ee_addr)>>19) & 0x1;
304 
305  outl(0x40000, ee_addr);
306  eeprom_delay();
307 
308  return phy_data;
309 }
310 
311 /*
312  DM9801/DM9802 present check and program
313 */
314 static void HPNA_process(void)
315 {
316 
317  if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
318  if ( phy_read(31) == 0x4404 ) {
319  /* DM9801 present */
320  if (phy_read(3) == 0xb901)
321  phy_write(16, 0x5); /* DM9801 E4 */
322  else
323  phy_write(16, 0x1005); /* DM9801 E3 and others */
324  phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
325  } else {
326  /* DM9802 present */
327  phy_write(16, 0x5);
328  phy_write(25, (phy_read(25) & 0xff00) + 2);
329  }
330  }
331 }
332 
333 /*
334  Sense media mode and set CR6
335 */
336 static void davicom_media_chk(struct nic * nic __unused)
337 {
338  unsigned long to, csr6;
339 
340  csr6 = 0x00200000; /* SF */
341  outl(csr6, ioaddr + CSR6);
342 
343 #define PCI_VENDOR_ID_DAVICOM 0x1282
344 #define PCI_DEVICE_ID_DM9009 0x9009
346  /* Set to 10BaseT mode for DM9009 */
347  phy_write(0, 0);
348  } else {
349  /* For DM9102/DM9102A */
350  to = currticks() + 2 * TICKS_PER_SEC;
351  while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
352  /* wait */ ;
353 
354  if ( (phy_read(1) & 0x24) == 0x24 ) {
355  if (phy_read(17) & 0xa000)
356  csr6 |= 0x00000200; /* Full Duplex mode */
357  } else
358  csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
359  }
360 
361  /* set the chip's operating mode */
362  outl(csr6, ioaddr + CSR6);
363 
364  /* DM9801/DM9802 present check & program */
365  if (csr6 & 0x40000)
366  HPNA_process();
367 }
368 
369 
370 /*********************************************************************/
371 /* EEPROM Reading Code */
372 /*********************************************************************/
373 /* EEPROM routines adapted from the Linux Tulip Code */
374 /* Reading a serial EEPROM is a "bit" grungy, but we work our way
375  through:->.
376 */
377 static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
378 {
379  int i;
380  unsigned short retval = 0;
381  long ee_addr = ioaddr + CSR9;
382  int read_cmd = location | EE_READ_CMD;
383 
384  whereami("read_eeprom\n");
385 
386  outl(EE_ENB & ~EE_CS, ee_addr);
387  outl(EE_ENB, ee_addr);
388 
389  /* Shift the read command bits out. */
390  for (i = 4 + addr_len; i >= 0; i--) {
391  short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
392  outl(EE_ENB | dataval, ee_addr);
393  eeprom_delay();
394  outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
395  eeprom_delay();
396  }
397  outl(EE_ENB, ee_addr);
398 
399  for (i = 16; i > 0; i--) {
400  outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
401  eeprom_delay();
402  retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
403  outl(EE_ENB, ee_addr);
404  eeprom_delay();
405  }
406 
407  /* Terminate the EEPROM access. */
408  outl(EE_ENB & ~EE_CS, ee_addr);
409  return retval;
410 }
411 
412 /*********************************************************************/
413 /* davicom_init_chain - setup the tx and rx descriptors */
414 /* Sten 10/9 */
415 /*********************************************************************/
416 static void davicom_init_chain(struct nic *nic)
417 {
418  int i;
419 
420  /* setup the transmit descriptor */
421  /* Sten: Set 2 TX descriptor but use one TX buffer because
422  it transmit a packet and wait complete every time. */
423  for (i=0; i<NTXD; i++) {
424  txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
425  txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
426  txd[i].buf1sz = 0;
427  txd[i].buf2sz = 0;
428  txd[i].control = 0x184; /* Begin/End/Chain */
429  txd[i].status = 0x00000000; /* give ownership to Host */
430  }
431 
432  /* construct perfect filter frame with mac address as first match
433  and broadcast address for all others */
434  for (i=0; i<192; i++) txb[i] = 0xFF;
435  txb[0] = nic->node_addr[0];
436  txb[1] = nic->node_addr[1];
437  txb[4] = nic->node_addr[2];
438  txb[5] = nic->node_addr[3];
439  txb[8] = nic->node_addr[4];
440  txb[9] = nic->node_addr[5];
441 
442  /* setup receive descriptor */
443  for (i=0; i<NRXD; i++) {
444  rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
445  rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
446  rxd[i].buf1sz = BUFLEN;
447  rxd[i].buf2sz = 0; /* not used */
448  rxd[i].control = 0x4; /* Chain Structure */
449  rxd[i].status = 0x80000000; /* give ownership to device */
450  }
451 
452  /* Chain the last descriptor to first */
453  txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
454  rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
455  TxPtr = 0;
456  rxd_tail = 0;
457 }
458 
459 
460 /*********************************************************************/
461 /* davicom_reset - Reset adapter */
462 /*********************************************************************/
463 static void davicom_reset(struct nic *nic)
464 {
465  unsigned long to;
466 
467  whereami("davicom_reset\n");
468 
469  /* Stop Tx and RX */
470  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
471 
472  /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
473  outl(0x00000001, ioaddr + CSR0);
474 
476 
477  /* TX/RX descriptor burst */
478  outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
479 
480  /* set up transmit and receive descriptors */
481  davicom_init_chain(nic); /* Sten 10/9 */
482 
483  /* Point to receive descriptor */
484  outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
485  outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
486 
487  /* According phyxcer media mode to set CR6,
488  DM9102/A phyxcer can auto-detect media mode */
490 
491  /* Prepare Setup Frame Sten 10/9 */
492  txd[TxPtr].buf1sz = 192;
493  txd[TxPtr].control = 0x024; /* SF/CE */
494  txd[TxPtr].status = 0x80000000; /* Give ownership to device */
495 
496  /* Start Tx */
497  outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
498  /* immediate transmit demand */
499  outl(0, ioaddr + CSR1);
500 
501  to = currticks() + TX_TIME_OUT;
502  while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
503  /* wait */ ;
504 
505  if (currticks() >= to) {
506  DBG ("TX Setup Timeout!\n");
507  }
508  /* Point to next TX descriptor */
509  TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
510 
511  DBG("txd.status = %lX\n", txd[TxPtr].status);
512  DBG("ticks = %ld\n", currticks() - (to - TX_TIME_OUT));
513  DBG_MORE();
514 
515  /* enable RX */
516  outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
517  /* immediate poll demand */
518  outl(0, ioaddr + CSR2);
519 }
520 
521 
522 /*********************************************************************/
523 /* eth_transmit - Transmit a frame */
524 /*********************************************************************/
525 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
526  unsigned int s, const char *p)
527 {
528  unsigned long to;
529 
530  whereami("davicom_transmit\n");
531 
532  /* Stop Tx */
533  /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
534 
535  /* setup ethernet header */
536  memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
537  memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
538  txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
539  txb[ETH_ALEN*2+1] = t & 0xFF;
540  memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
541 
542  /* setup the transmit descriptor */
543  txd[TxPtr].buf1sz = ETH_HLEN+s;
544  txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
545  txd[TxPtr].status = 0x80000000; /* give ownership to device */
546 
547  /* immediate transmit demand */
548  outl(0, ioaddr + CSR1);
549 
550  to = currticks() + TX_TIME_OUT;
551  while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
552  /* wait */ ;
553 
554  if (currticks() >= to) {
555  DBG ("TX Timeout!\n");
556  }
557 
558  /* Point to next TX descriptor */
559  TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
560 
561 }
562 
563 /*********************************************************************/
564 /* eth_poll - Wait for a frame */
565 /*********************************************************************/
566 static int davicom_poll(struct nic *nic, int retrieve)
567 {
568  whereami("davicom_poll\n");
569 
570  if (rxd[rxd_tail].status & 0x80000000)
571  return 0;
572 
573  if ( ! retrieve ) return 1;
574 
575  whereami("davicom_poll got one\n");
576 
577  nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
578 
579  if( rxd[rxd_tail].status & 0x00008000){
580  rxd[rxd_tail].status = 0x80000000;
581  rxd_tail++;
582  if (rxd_tail == NRXD) rxd_tail = 0;
583  return 0;
584  }
585 
586  /* copy packet to working buffer */
587  /* XXX - this copy could be avoided with a little more work
588  but for now we are content with it because the optimised
589  memcpy is quite fast */
590 
592 
593  /* return the descriptor and buffer to receive ring */
594  rxd[rxd_tail].status = 0x80000000;
595  rxd_tail++;
596  if (rxd_tail == NRXD) rxd_tail = 0;
597 
598  return 1;
599 }
600 
601 /*********************************************************************/
602 /* eth_disable - Disable the interface */
603 /*********************************************************************/
604 static void davicom_disable ( struct nic *nic ) {
605 
606  whereami("davicom_disable\n");
607 
609 
610  /* disable interrupts */
611  outl(0x00000000, ioaddr + CSR7);
612 
613  /* Stop the chip's Tx and Rx processes. */
614  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
615 
616  /* Clear the missed-packet counter. */
617  inl(ioaddr + CSR8);
618 }
619 
620 
621 /*********************************************************************/
622 /* eth_irq - enable, disable and force interrupts */
623 /*********************************************************************/
624 static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
625 {
626  switch ( action ) {
627  case DISABLE :
628  break;
629  case ENABLE :
630  break;
631  case FORCE :
632  break;
633  }
634 }
635 
636 
637 /*********************************************************************/
638 /* eth_probe - Look for an adapter */
639 /*********************************************************************/
640 static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
641 
642  unsigned int i;
643 
644  whereami("davicom_probe\n");
645 
646  if (pci->ioaddr == 0)
647  return 0;
648 
649  vendor = pci->vendor;
650  dev_id = pci->device;
651  ioaddr = pci->ioaddr;
652 
653  nic->ioaddr = pci->ioaddr;
654  nic->irqno = 0;
655 
656  /* wakeup chip */
657  pci_write_config_dword(pci, 0x40, 0x00000000);
658 
659  /* Stop the chip's Tx and Rx processes. */
660  outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
661 
662  /* Clear the missed-packet counter. */
663  inl(ioaddr + CSR8);
664 
665  /* Get MAC Address */
666  /* read EEPROM data */
667  for (i = 0; i < sizeof(ee_data)/2; i++)
668  ((unsigned short *)ee_data)[i] =
670 
671  /* extract MAC address from EEPROM buffer */
672  for (i=0; i<ETH_ALEN; i++)
673  nic->node_addr[i] = ee_data[20+i];
674 
675  DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
676 
677  /* initialize device */
680  return 1;
681 }
682 
683 static struct nic_operations davicom_operations = {
685  .poll = davicom_poll,
686  .transmit = davicom_transmit,
687  .irq = davicom_irq,
688 
689 };
690 
691 static struct pci_device_id davicom_nics[] = {
692 PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
693 PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
694 PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
695 PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */
696 };
697 
698 PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
699 
700 DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
702 
703 /*
704  * Local variables:
705  * c-basic-offset: 8
706  * c-indent-level: 8
707  * tab-width: 8
708  * End:
709  */
static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
Definition: davicom.c:377
unsigned char irqno
Definition: nic.h:56
uint16_t u16
Definition: stdint.h:21
#define __attribute__(x)
Definition: compiler.h:10
#define DBG_MORE(...)
Definition: compiler.h:504
#define EE_READ_CMD
Definition: davicom.c:71
Definition: nic.h:35
PCI_DRIVER(davicom_driver, davicom_nics, PCI_NO_CLASS)
Definition: davicom.c:56
Definition: davicom.c:56
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
#define TX_TIME_OUT
Definition: davicom.c:51
A PCI driver.
Definition: pci.h:224
struct @36 __shared
static void phy_write_1bit(u32, u32)
Definition: davicom.c:280
const unsigned char * buf1addr
Definition: davicom.c:105
#define rxb
Definition: davicom.c:146
Definition: davicom.c:57
static void phy_write(int, u16)
Definition: davicom.c:239
static void HPNA_process(void)
Definition: davicom.c:314
unsigned long ioaddr
I/O address.
Definition: pci.h:200
static int rxd_tail
Definition: davicom.c:147
#define EE_DATA_READ
Definition: davicom.c:80
static unsigned short vendor
Definition: davicom.c:128
#define EEPROM_ADDRLEN
Definition: davicom.c:61
Definition: davicom.c:57
static int phy_read(int)
Definition: davicom.c:194
Definition: davicom.c:55
static unsigned char ee_data[EEPROM_SIZE]
Definition: davicom.c:67
davicom_offsets
Definition: davicom.c:54
static int davicom_poll(struct nic *nic, int retrieve)
Definition: davicom.c:566
#define EE_ENB
Definition: davicom.c:81
static void davicom_disable(struct nic *nic)
Definition: davicom.c:604
Definition: davicom.c:55
static void whereami(const char *str)
Definition: davicom.c:174
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
#define EEPROM_SIZE
Definition: davicom.c:62
Definition: davicom.c:57
Definition: davicom.c:55
Definition: davicom.c:56
uint8_t status
Status.
Definition: ena.h:16
DRIVER("DAVICOM", nic_driver, pci_driver, davicom_driver, davicom_probe, davicom_disable)
volatile unsigned long status
Definition: davicom.c:110
static unsigned long ioaddr
Definition: davicom.c:129
void * memcpy(void *dest, const void *src, size_t len) __nonnull
unsigned int ioaddr
Definition: nic.h:55
unsigned long buf1sz
Definition: davicom.c:111
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
uint16_t device
Device ID.
Definition: pci.h:204
#define ETH_HLEN
Definition: if_ether.h:9
#define DBGP(...)
Definition: compiler.h:532
Ethernet protocol.
static struct pci_device_id davicom_nics[]
Definition: davicom.c:691
static struct nic_operations davicom_operations
Definition: davicom.c:125
A 16-bit general register.
Definition: registers.h:24
irq_action_t
Definition: nic.h:34
unsigned long control
Definition: davicom.c:102
#define EE_SHIFT_CLK
Definition: davicom.c:75
Definition: davicom.c:57
static int TxPtr
Definition: davicom.c:148
#define NTXD
Definition: davicom.c:135
unsigned int packetlen
Definition: nic.h:54
#define PCI_DEVICE_ID_DM9009
#define txd
Definition: davicom.c:143
#define outl(data, io_addr)
Definition: io.h:329
#define eeprom_delay()
Definition: davicom.c:91
PCI bus.
A PCI device.
Definition: pci.h:187
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
#define txb
Definition: davicom.c:144
unsigned long buf2sz
Definition: davicom.c:111
static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: davicom.c:624
#define BUFLEN
Definition: davicom.c:119
#define PHY_DATA_0
Definition: davicom.c:84
#define ETH_ALEN
Definition: if_ether.h:8
A PCI device ID list entry.
Definition: pci.h:151
Definition: nic.h:37
#define le16_to_cpu(value)
Definition: byteswap.h:112
Definition: nic.h:49
Definition: davicom.c:56
uint16_t vendor
Vendor ID.
Definition: pci.h:202
unsigned long retval
Definition: xen.h:45
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
Definition: nic.h:36
unsigned long control
Definition: davicom.c:111
#define EE_CS
Definition: davicom.c:76
unsigned char * packet
Definition: nic.h:53
#define MDCLKH
Definition: davicom.c:86
unsigned char * node_addr
Definition: nic.h:52
Definition: davicom.c:55
unsigned long buf1sz
Definition: davicom.c:102
unsigned long buf2sz
Definition: davicom.c:102
unsigned char * buf2addr
Definition: davicom.c:115
static void davicom_media_chk(struct nic *)
static int davicom_probe(struct nic *nic, struct pci_device *pci)
Definition: davicom.c:640
static void davicom_wait(unsigned int nticks)
Definition: davicom.c:180
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
int pci_write_config_dword(struct pci_device *pci, unsigned int where, uint32_t value)
Write 32-bit dword to PCI configuration space.
Definition: davicom.c:55
FILE_LICENCE(GPL_ANY)
unsigned char * buf1addr
Definition: davicom.c:114
#define PHY_DATA_1
Definition: davicom.c:85
static unsigned short dev_id
Definition: davicom.c:128
volatile unsigned long status
Definition: davicom.c:101
Definition: davicom.c:56
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
Definition: davicom.c:525
#define EE_DATA_WRITE
Definition: davicom.c:77
#define PCI_VENDOR_ID_DAVICOM
static int phy_read_1bit(u32)
Definition: davicom.c:294
#define NRXD
Definition: davicom.c:136
int(* connect)(struct nic *)
Definition: nic.h:63
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
Definition: davicom.c:56
Definition: davicom.c:55
static void davicom_reset(struct nic *nic)
Definition: davicom.c:463
Definition: davicom.c:57
uint32_t u32
Definition: stdint.h:23
Definition: davicom.c:57
static void davicom_init_chain(struct nic *nic)
Definition: davicom.c:416
const unsigned char * buf2addr
Definition: davicom.c:106
#define rxd
Definition: davicom.c:145