iPXE
exanic.h
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1 #ifndef _EXANIC_H
2 #define _EXANIC_H
3 
4 /** @file
5  *
6  * Exablaze ExaNIC driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/pci.h>
14 #include <ipxe/ethernet.h>
15 #include <ipxe/uaccess.h>
16 #include <ipxe/retry.h>
17 #include <ipxe/i2c.h>
18 #include <ipxe/bitbash.h>
19 
20 /** Maximum number of ports */
21 #define EXANIC_MAX_PORTS 8
22 
23 /** Register BAR */
24 #define EXANIC_REGS_BAR PCI_BASE_ADDRESS_0
25 
26 /** Transmit region BAR */
27 #define EXANIC_TX_BAR PCI_BASE_ADDRESS_2
28 
29 /** Alignment for DMA regions */
30 #define EXANIC_ALIGN 0x1000
31 
32 /** Flag for 32-bit DMA addresses */
33 #define EXANIC_DMA_32_BIT 0x00000001UL
34 
35 /** Register set length */
36 #define EXANIC_REGS_LEN 0x2000
37 
38 /** Transmit feedback region length */
39 #define EXANIC_TXF_LEN 0x1000
40 
41 /** Transmit feedback slot
42  *
43  * This is a policy decision.
44  */
45 #define EXANIC_TXF_SLOT( index ) ( 0x40 * (index) )
46 
47 /** Receive region length */
48 #define EXANIC_RX_LEN 0x200000
49 
50 /** Transmit feedback base address register */
51 #define EXANIC_TXF_BASE 0x0014
52 
53 /** Capabilities register */
54 #define EXANIC_CAPS 0x0038
55 #define EXANIC_CAPS_100M 0x01000000UL /**< 100Mbps supported */
56 #define EXANIC_CAPS_1G 0x02000000UL /**< 1Gbps supported */
57 #define EXANIC_CAPS_10G 0x04000000UL /**< 10Gbps supported */
58 #define EXANIC_CAPS_40G 0x08000000UL /**< 40Gbps supported */
59 #define EXANIC_CAPS_100G 0x10000000UL /**< 100Gbps supported */
60 #define EXANIC_CAPS_SPEED_MASK 0x1f000000UL /**< Supported speeds mask */
61 
62 /** I2C GPIO register */
63 #define EXANIC_I2C 0x012c
64 
65 /** Power control register */
66 #define EXANIC_POWER 0x0138
67 #define EXANIC_POWER_ON 0x000000f0UL /**< Power on PHYs */
68 
69 /** Port register offset */
70 #define EXANIC_PORT_REGS( index ) ( 0x0200 + ( 0x40 * (index) ) )
71 
72 /** Port enable register */
73 #define EXANIC_PORT_ENABLE 0x0000
74 #define EXANIC_PORT_ENABLE_ENABLED 0x00000001UL /**< Port is enabled */
75 
76 /** Port speed register */
77 #define EXANIC_PORT_SPEED 0x0004
78 
79 /** Port status register */
80 #define EXANIC_PORT_STATUS 0x0008
81 #define EXANIC_PORT_STATUS_LINK 0x00000008UL /**< Link is up */
82 #define EXANIC_PORT_STATUS_ABSENT 0x80000000UL /**< Port is not present */
83 
84 /** Port MAC address (second half) register */
85 #define EXANIC_PORT_MAC 0x000c
86 
87 /** Port flags register */
88 #define EXANIC_PORT_FLAGS 0x0010
89 #define EXANIC_PORT_FLAGS_PROMISC 0x00000001UL /**< Promiscuous mode */
90 
91 /** Port receive chunk base address register */
92 #define EXANIC_PORT_RX_BASE 0x0014
93 
94 /** Port transmit command register */
95 #define EXANIC_PORT_TX_COMMAND 0x0020
96 
97 /** Port transmit region offset register */
98 #define EXANIC_PORT_TX_OFFSET 0x0024
99 
100 /** Port transmit region length register */
101 #define EXANIC_PORT_TX_LEN 0x0028
102 
103 /** Port MAC address (first half) register */
104 #define EXANIC_PORT_OUI 0x0030
105 
106 /** Port interrupt configuration register */
107 #define EXANIC_PORT_IRQ 0x0034
108 
109 /** An ExaNIC transmit chunk descriptor */
111  /** Feedback ID */
113  /** Feedback slot */
115  /** Payload length (including padding */
117  /** Payload type */
119  /** Flags */
121 } __attribute__ (( packed ));
122 
123 /** An ExaNIC transmit chunk */
125  /** Descriptor */
127  /** Padding */
129  /** Payload data */
130  uint8_t data[2038];
131 } __attribute__ (( packed ));
132 
133 /** Raw Ethernet frame type */
134 #define EXANIC_TYPE_RAW 0x01
135 
136 /** An ExaNIC receive chunk descriptor */
138  /** Timestamp */
140  /** Status (valid only on final chunk) */
142  /** Length (zero except on the final chunk) */
144  /** Filter number */
146  /** Generation */
148 } __attribute__ (( packed ));
149 
150 /** An ExaNIC receive chunk */
152  /** Payload data */
153  uint8_t data[120];
154  /** Descriptor */
156 } __attribute__ (( packed ));
157 
158 /** Receive status error mask */
159 #define EXANIC_STATUS_ERROR_MASK 0x0f
160 
161 /** An ExaNIC I2C bus configuration */
163  /** GPIO bit for pulling SCL low */
165  /** GPIO bit for pulling SDA low */
167  /** GPIO bit for reading SDA */
169 };
170 
171 /** EEPROM address */
172 #define EXANIC_EEPROM_ADDRESS 0x50
173 
174 /** An ExaNIC port */
175 struct exanic_port {
176  /** Network device */
178  /** Port registers */
179  void *regs;
180 
181  /** Transmit region offset */
182  size_t tx_offset;
183  /** Transmit region */
184  void *tx;
185  /** Number of transmit descriptors */
187  /** Transmit producer counter */
189  /** Transmit consumer counter */
191  /** Transmit feedback slot */
193  /** Transmit feedback region */
195 
196  /** Receive region */
198  /** Receive consumer counter */
199  unsigned int rx_cons;
200  /** Receive I/O buffer (if any) */
202  /** Receive status */
203  int rx_rc;
204 
205  /** Port status */
207  /** Default link speed (as raw register value) */
209  /** Speed capability bitmask */
211  /** Current attempted link speed (as a capability bit index) */
212  unsigned int speed;
213  /** Port status check timer */
215 };
216 
217 /** An ExaNIC */
218 struct exanic {
219  /** Registers */
220  void *regs;
221  /** Transmit region */
222  void *tx;
223  /** Transmit feedback region */
224  void *txf;
225 
226  /** I2C bus configuration */
228  /** I2C bit-bashing interface */
230  /** I2C serial EEPROM */
232 
233  /** Capabilities */
235  /** Base MAC address */
237 
238  /** Ports */
240 };
241 
242 /** Maximum used length of transmit region
243  *
244  * This is a policy decision to avoid overflowing the 16-bit transmit
245  * producer and consumer counters.
246  */
247 #define EXANIC_MAX_TX_LEN ( 256 * sizeof ( struct exanic_tx_chunk ) )
248 
249 /** Maximum length of received packet
250  *
251  * This is a policy decision.
252  */
253 #define EXANIC_MAX_RX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
254 
255 /** Interval between link state checks
256  *
257  * This is a policy decision.
258  */
259 #define EXANIC_LINK_INTERVAL ( 1 * TICKS_PER_SEC )
260 
261 #endif /* _EXANIC_H */
#define __attribute__(x)
Definition: compiler.h:10
uint16_t txf_slot
Transmit feedback slot.
Definition: exanic.h:192
unsigned short uint16_t
Definition: stdint.h:11
void * regs
Port registers.
Definition: exanic.h:179
userptr_t rx
Receive region.
Definition: exanic.h:197
uint8_t getsda
GPIO bit for reading SDA.
Definition: exanic.h:168
struct exanic_i2c_config i2cfg
I2C bus configuration.
Definition: exanic.h:227
void * tx
Transmit region.
Definition: exanic.h:222
uint8_t setscl
GPIO bit for pulling SCL low.
Definition: exanic.h:164
uint8_t generation
Generation.
Definition: exanic.h:147
Retry timers.
struct exanic_tx_descriptor desc
Descriptor.
Definition: exanic.h:126
A retry timer.
Definition: retry.h:21
uint8_t pad[2]
Padding.
Definition: exanic.h:128
struct exanic_rx_descriptor desc
Descriptor.
Definition: exanic.h:155
uint8_t len
Length (zero except on the final chunk)
Definition: exanic.h:143
A bit-bashing I2C interface.
Definition: i2c.h:91
uint32_t status
Port status.
Definition: exanic.h:206
struct exanic_port * port[EXANIC_MAX_PORTS]
Ports.
Definition: exanic.h:239
uint16_t tx_cons
Transmit consumer counter.
Definition: exanic.h:190
An ExaNIC receive chunk.
Definition: exanic.h:151
Access to external ("user") memory.
An ExaNIC transmit chunk.
Definition: exanic.h:124
A timer.
Definition: timer.h:28
eeprom
Definition: 3c90x.h:232
uint8_t setsda
GPIO bit for pulling SDA low.
Definition: exanic.h:166
An ExaNIC.
Definition: exanic.h:218
An ExaNIC port.
Definition: exanic.h:175
uint16_t txf_slot
Feedback slot.
Definition: exanic.h:114
uint32_t speeds
Speed capability bitmask.
Definition: exanic.h:210
void * txf
Transmit feedback region.
Definition: exanic.h:224
Ethernet protocol.
size_t tx_offset
Transmit region offset.
Definition: exanic.h:182
An ExaNIC receive chunk descriptor.
Definition: exanic.h:137
Bit-bashing interfaces.
void * tx
Transmit region.
Definition: exanic.h:184
uint8_t status
Status (valid only on final chunk)
Definition: exanic.h:141
uint16_t len
Payload length (including padding.
Definition: exanic.h:116
uint16_t * txf
Transmit feedback region.
Definition: exanic.h:194
uint32_t caps
Capabilities.
Definition: exanic.h:234
An ExaNIC transmit chunk descriptor.
Definition: exanic.h:110
struct net_device * netdev
Network device.
Definition: exanic.h:177
PCI bus.
unsigned int speed
Current attempted link speed (as a capability bit index)
Definition: exanic.h:212
A network device.
Definition: netdevice.h:348
unsigned int rx_cons
Receive consumer counter.
Definition: exanic.h:199
uint8_t type
Payload type.
Definition: exanic.h:118
unsigned char uint8_t
Definition: stdint.h:10
uint16_t txf_id
Feedback ID.
Definition: exanic.h:112
#define ETH_ALEN
Definition: if_ether.h:8
unsigned int uint32_t
Definition: stdint.h:12
#define EXANIC_MAX_PORTS
Maximum number of ports.
Definition: exanic.h:21
uint8_t data[120]
Payload data.
Definition: exanic.h:153
struct io_buffer * rx_iobuf
Receive I/O buffer (if any)
Definition: exanic.h:201
uint16_t tx_prod
Transmit producer counter.
Definition: exanic.h:188
uint32_t default_speed
Default link speed (as raw register value)
Definition: exanic.h:208
struct i2c_bit_basher basher
I2C bit-bashing interface.
Definition: exanic.h:229
uint8_t filter
Filter number.
Definition: exanic.h:145
uint16_t tx_count
Number of transmit descriptors.
Definition: exanic.h:186
uint8_t data[2038]
Payload data.
Definition: exanic.h:130
void * regs
Registers.
Definition: exanic.h:220
uint8_t mac[ETH_ALEN]
Base MAC address.
Definition: exanic.h:236
int rx_rc
Receive status.
Definition: exanic.h:203
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
uint32_t timestamp
Timestamp.
Definition: exanic.h:139
An I2C device.
Definition: i2c.h:20
An ExaNIC I2C bus configuration.
Definition: exanic.h:162
unsigned long userptr_t
A pointer to a user buffer.
Definition: uaccess.h:33
A persistent I/O buffer.
Definition: iobuf.h:32
uint8_t flags
Flags.
Definition: exanic.h:120
I2C interface.