iPXE
Macros | Typedefs | Functions
mlx_pci_gw.h File Reference
#include "mlx_utils.h"

Go to the source code of this file.

Macros

#define PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET   0x34
 
#define PCI_GW_CAPABILITY_ID   0x9
 
#define PCI_GW_CAPABILITY_ID_OFFSET   0x0
 
#define PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET   0x1
 
#define PCI_GW_CAPABILITY_SPACE_OFFSET   0x4
 
#define PCI_GW_CAPABILITY_STATUS_OFFSET   0x7
 
#define PCI_GW_CAPABILITY_COUNTER_OFFSET   0x8
 
#define PCI_GW_CAPABILITY_SEMAPHORE_OFFSET   0xC
 
#define PCI_GW_CAPABILITY_ADDRESS_OFFSET   0x10
 
#define PCI_GW_CAPABILITY_FLAG_OFFSET   0x10
 
#define PCI_GW_CAPABILITY_DATA_OFFSET   0x14
 
#define PCI_GW_SEMPHORE_TRIES   3000000
 
#define PCI_GW_GET_OWNERSHIP_TRIES   5000
 
#define PCI_GW_READ_FLAG_TRIES   3000000
 
#define PCI_GW_WRITE_FLAG   0x80000000
 
#define PCI_GW_SPACE_NODNIC   0x4
 
#define PCI_GW_SPACE_ALL_ICMD   0x3
 
#define PCI_GW_SPACE_SEMAPHORE   0xa
 
#define PCI_GW_SPACE_CR0   0x2
 

Typedefs

typedef mlx_uint32 mlx_pci_gw_buffer
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
mlx_status mlx_pci_gw_init (IN mlx_utils *utils)
 
mlx_status mlx_pci_gw_teardown (IN mlx_utils *utils)
 
mlx_status mlx_pci_gw_read (IN mlx_utils *utils, IN mlx_pci_gw_space space, IN mlx_uint32 address, OUT mlx_pci_gw_buffer *buffer)
 
mlx_status mlx_pci_gw_write (IN mlx_utils *utils, IN mlx_pci_gw_space space, IN mlx_uint32 address, IN mlx_pci_gw_buffer buffer)
 

Macro Definition Documentation

◆ PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET

#define PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET   0x34

Definition at line 27 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_ID

#define PCI_GW_CAPABILITY_ID   0x9

Definition at line 29 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_ID_OFFSET

#define PCI_GW_CAPABILITY_ID_OFFSET   0x0

Definition at line 31 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET

#define PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET   0x1

Definition at line 32 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_SPACE_OFFSET

#define PCI_GW_CAPABILITY_SPACE_OFFSET   0x4

Definition at line 33 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_STATUS_OFFSET

#define PCI_GW_CAPABILITY_STATUS_OFFSET   0x7

Definition at line 34 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_COUNTER_OFFSET

#define PCI_GW_CAPABILITY_COUNTER_OFFSET   0x8

Definition at line 35 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_SEMAPHORE_OFFSET

#define PCI_GW_CAPABILITY_SEMAPHORE_OFFSET   0xC

Definition at line 36 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_ADDRESS_OFFSET

#define PCI_GW_CAPABILITY_ADDRESS_OFFSET   0x10

Definition at line 37 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_FLAG_OFFSET

#define PCI_GW_CAPABILITY_FLAG_OFFSET   0x10

Definition at line 38 of file mlx_pci_gw.h.

◆ PCI_GW_CAPABILITY_DATA_OFFSET

#define PCI_GW_CAPABILITY_DATA_OFFSET   0x14

Definition at line 39 of file mlx_pci_gw.h.

◆ PCI_GW_SEMPHORE_TRIES

#define PCI_GW_SEMPHORE_TRIES   3000000

Definition at line 41 of file mlx_pci_gw.h.

◆ PCI_GW_GET_OWNERSHIP_TRIES

#define PCI_GW_GET_OWNERSHIP_TRIES   5000

Definition at line 42 of file mlx_pci_gw.h.

◆ PCI_GW_READ_FLAG_TRIES

#define PCI_GW_READ_FLAG_TRIES   3000000

Definition at line 43 of file mlx_pci_gw.h.

◆ PCI_GW_WRITE_FLAG

#define PCI_GW_WRITE_FLAG   0x80000000

Definition at line 45 of file mlx_pci_gw.h.

◆ PCI_GW_SPACE_NODNIC

#define PCI_GW_SPACE_NODNIC   0x4

Definition at line 47 of file mlx_pci_gw.h.

◆ PCI_GW_SPACE_ALL_ICMD

#define PCI_GW_SPACE_ALL_ICMD   0x3

Definition at line 48 of file mlx_pci_gw.h.

◆ PCI_GW_SPACE_SEMAPHORE

#define PCI_GW_SPACE_SEMAPHORE   0xa

Definition at line 49 of file mlx_pci_gw.h.

◆ PCI_GW_SPACE_CR0

#define PCI_GW_SPACE_CR0   0x2

Definition at line 50 of file mlx_pci_gw.h.

Typedef Documentation

◆ mlx_pci_gw_buffer

Definition at line 52 of file mlx_pci_gw.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ mlx_pci_gw_init()

mlx_status mlx_pci_gw_init ( IN mlx_utils utils)

Definition at line 218 of file mlx_pci_gw.c.

221 {
223  mlx_pci_gw *pci_gw = NULL;
224 
225  if( utils == NULL){
227  goto bad_param;
228  }
229 
230  pci_gw = &utils->pci_gw;
231 
233  MLX_CHECK_STATUS(utils, status, cap_err,
234  "mlx_pci_gw_search_capability failed");
235 
236 #if ! defined ( VSEC_DEBUG )
238  MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
239 ownership_err:
240 #endif
241 cap_err:
242 bad_param:
243  return status;
244 }
#define MLX_INVALID_PARAMETER
mlx_uint32 pci_cmd_offset
Definition: mlx_utils.h:34
uint8_t status
Status.
Definition: ena.h:16
static mlx_status mlx_pci_gw_search_capability(IN mlx_utils *utils, OUT mlx_uint32 *cap_offset)
Definition: mlx_pci_gw.c:171
#define MLX_SUCCESS
int mlx_status
static mlx_status mlx_pci_gw_get_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:51
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References MLX_CHECK_STATUS, MLX_INVALID_PARAMETER, mlx_pci_gw_get_ownership(), mlx_pci_gw_search_capability(), MLX_SUCCESS, NULL, mlx_pci_gw::pci_cmd_offset, and status.

Referenced by flexboot_nodnic_is_supported(), and init_mlx_utils().

◆ mlx_pci_gw_teardown()

mlx_status mlx_pci_gw_teardown ( IN mlx_utils utils)

Definition at line 247 of file mlx_pci_gw.c.

250 {
251 #if ! defined ( VSEC_DEBUG )
253 #endif
254  return MLX_SUCCESS;
255 }
#define MLX_SUCCESS
static mlx_status mlx_pci_gw_free_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:103

References mlx_pci_gw_free_ownership(), and MLX_SUCCESS.

Referenced by flexboot_nodnic_is_supported(), free_mlx_utils(), and init_mlx_utils().

◆ mlx_pci_gw_read()

mlx_status mlx_pci_gw_read ( IN mlx_utils utils,
IN mlx_pci_gw_space  space,
IN mlx_uint32  address,
OUT mlx_pci_gw_buffer buffer 
)

Definition at line 258 of file mlx_pci_gw.c.

264 {
266  mlx_pci_gw *pci_gw = NULL;
267  mlx_uint32 cap_offset = 0;
268 
269  if (utils == NULL || buffer == NULL || utils->pci_gw.pci_cmd_offset == 0) {
271  goto bad_param;
272  }
273 
274  mlx_utils_acquire_lock(utils);
275 
276  pci_gw = &utils->pci_gw;
277  cap_offset = pci_gw->pci_cmd_offset;
278 
279 #if ! defined ( VSEC_DEBUG )
280  if (pci_gw->space != space) {
281  status = mlx_pci_gw_set_space(utils, space);
282  MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
283  pci_gw->space = space;
284  }
285 #else
287  MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
288 
289  status = mlx_pci_gw_set_space(utils, space);
290  MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
291  pci_gw->space = space;
292 #endif
293 
295  MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability address");
296 
297 #if defined ( DEVICE_CX3 )
298  /* WA for PCI issue (race) */
299  mlx_utils_delay_in_us ( 10 );
300 #endif
301 
303  MLX_CHECK_STATUS(utils, status, read_error, "flag failed to change");
304 
306  MLX_CHECK_STATUS(utils, status, read_error,"failed to read capability data");
307 
308 #if defined ( VSEC_DEBUG )
310  MLX_CHECK_STATUS(utils, status, free_err,
311  "mlx_pci_gw_free_ownership failed");
312 free_err:
313  mlx_utils_release_lock(utils);
314  return status;
315 #endif
316 read_error:
317 space_error:
318 #if defined ( VSEC_DEBUG )
320 ownership_err:
321 #endif
323 bad_param:
324  return status;
325 }
#define MLX_INVALID_PARAMETER
mlx_uint32 pci_cmd_offset
Definition: mlx_utils.h:34
uint64_t address
Base address.
Definition: ena.h:24
#define PCI_GW_CAPABILITY_DATA_OFFSET
Definition: mlx_pci_gw.h:39
mlx_status mlx_utils_release_lock(IN OUT mlx_utils *utils)
Definition: mlx_utils.c:108
mlx_pci_gw_space space
Definition: mlx_utils.h:35
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
mlx_status mlx_utils_delay_in_us(IN mlx_uint32 usecs)
Definition: mlx_utils.c:65
mlx_status mlx_pci_read(IN mlx_utils *utils, IN mlx_pci_width width, IN mlx_uint32 offset, IN mlx_uintn count, OUT mlx_void *buffer)
Definition: mlx_pci.c:58
mlx_status mlx_pci_write(IN mlx_utils *utils, IN mlx_pci_width width, IN mlx_uint32 offset, IN mlx_uintn count, IN mlx_void *buffer)
Definition: mlx_pci.c:77
static mlx_status mlx_pci_gw_wait_for_flag_value(IN mlx_utils *utils, IN mlx_boolean value)
Definition: mlx_pci_gw.c:146
uint8_t status
Status.
Definition: ena.h:16
uint32_t mlx_uint32
static mlx_status mlx_pci_gw_set_space(IN mlx_utils *utils, IN mlx_pci_gw_space space)
Definition: mlx_pci_gw.c:120
#define MLX_SUCCESS
#define TRUE
Definition: tlan.h:46
static mlx_status mlx_pci_gw_free_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:103
mlx_status mlx_utils_acquire_lock(IN OUT mlx_utils *utils)
Definition: mlx_utils.c:100
#define PCI_GW_CAPABILITY_ADDRESS_OFFSET
Definition: mlx_pci_gw.h:37
int mlx_status
static mlx_status mlx_pci_gw_get_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:51
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References address, buffer, MLX_CHECK_STATUS, MLX_INVALID_PARAMETER, mlx_pci_gw_free_ownership(), mlx_pci_gw_get_ownership(), mlx_pci_gw_set_space(), mlx_pci_gw_wait_for_flag_value(), mlx_pci_read(), mlx_pci_write(), MLX_SUCCESS, mlx_utils_acquire_lock(), mlx_utils_delay_in_us(), mlx_utils_release_lock(), MlxPciWidthUint32, NULL, mlx_pci_gw::pci_cmd_offset, PCI_GW_CAPABILITY_ADDRESS_OFFSET, PCI_GW_CAPABILITY_DATA_OFFSET, mlx_pci_gw::space, status, and TRUE.

Referenced by flexboot_nodnic_is_supported(), mlx_icmd_get_semaphore(), mlx_icmd_get_status(), mlx_icmd_go(), mlx_icmd_init(), mlx_icmd_read_buffer(), mlx_icmd_set_opcode(), and nodnic_cmd_read().

◆ mlx_pci_gw_write()

mlx_status mlx_pci_gw_write ( IN mlx_utils utils,
IN mlx_pci_gw_space  space,
IN mlx_uint32  address,
IN mlx_pci_gw_buffer  buffer 
)

Definition at line 328 of file mlx_pci_gw.c.

334 {
336  mlx_pci_gw *pci_gw = NULL;
337  mlx_uint32 cap_offset = 0;
338  mlx_uint32 fixed_address = address | PCI_GW_WRITE_FLAG;
339 
340  if (utils == NULL || utils->pci_gw.pci_cmd_offset == 0) {
342  goto bad_param;
343  }
344 
345  mlx_utils_acquire_lock(utils);
346 
347  pci_gw = &utils->pci_gw;
348  cap_offset = pci_gw->pci_cmd_offset;
349 
350 #if ! defined ( VSEC_DEBUG )
351  if (pci_gw->space != space) {
352  status = mlx_pci_gw_set_space(utils, space);
353  MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
354  pci_gw->space = space;
355  }
356 #else
358  MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
359 
360  status = mlx_pci_gw_set_space(utils, space);
361  MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
362  pci_gw->space = space;
363 #endif
365  MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability data");
366 
367  status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_ADDRESS_OFFSET, 1, &fixed_address);
368  MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability address");
369 
371  MLX_CHECK_STATUS(utils, status, read_error, "flag failed to change");
372 #if defined ( VSEC_DEBUG )
374  MLX_CHECK_STATUS(utils, status, free_err,
375  "mlx_pci_gw_free_ownership failed");
376 free_err:
378  return status;
379 #endif
380 read_error:
381 space_error:
382 #if defined ( VSEC_DEBUG )
384 ownership_err:
385 #endif
387 bad_param:
388  return status;
389 }
#define MLX_INVALID_PARAMETER
mlx_uint32 pci_cmd_offset
Definition: mlx_utils.h:34
uint64_t address
Base address.
Definition: ena.h:24
#define PCI_GW_CAPABILITY_DATA_OFFSET
Definition: mlx_pci_gw.h:39
mlx_status mlx_utils_release_lock(IN OUT mlx_utils *utils)
Definition: mlx_utils.c:108
mlx_pci_gw_space space
Definition: mlx_utils.h:35
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
mlx_status mlx_pci_write(IN mlx_utils *utils, IN mlx_pci_width width, IN mlx_uint32 offset, IN mlx_uintn count, IN mlx_void *buffer)
Definition: mlx_pci.c:77
static mlx_status mlx_pci_gw_wait_for_flag_value(IN mlx_utils *utils, IN mlx_boolean value)
Definition: mlx_pci_gw.c:146
uint8_t status
Status.
Definition: ena.h:16
uint32_t mlx_uint32
static mlx_status mlx_pci_gw_set_space(IN mlx_utils *utils, IN mlx_pci_gw_space space)
Definition: mlx_pci_gw.c:120
#define MLX_SUCCESS
#define PCI_GW_WRITE_FLAG
Definition: mlx_pci_gw.h:45
static mlx_status mlx_pci_gw_free_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:103
mlx_status mlx_utils_acquire_lock(IN OUT mlx_utils *utils)
Definition: mlx_utils.c:100
#define PCI_GW_CAPABILITY_ADDRESS_OFFSET
Definition: mlx_pci_gw.h:37
#define FALSE
Definition: tlan.h:45
int mlx_status
static mlx_status mlx_pci_gw_get_ownership(IN mlx_utils *utils)
Definition: mlx_pci_gw.c:51
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References address, buffer, FALSE, MLX_CHECK_STATUS, MLX_INVALID_PARAMETER, mlx_pci_gw_free_ownership(), mlx_pci_gw_get_ownership(), mlx_pci_gw_set_space(), mlx_pci_gw_wait_for_flag_value(), mlx_pci_write(), MLX_SUCCESS, mlx_utils_acquire_lock(), mlx_utils_release_lock(), MlxPciWidthUint32, NULL, mlx_pci_gw::pci_cmd_offset, PCI_GW_CAPABILITY_ADDRESS_OFFSET, PCI_GW_CAPABILITY_DATA_OFFSET, PCI_GW_WRITE_FLAG, mlx_pci_gw::space, and status.

Referenced by mlx_icmd_clear_semaphore(), mlx_icmd_get_semaphore(), mlx_icmd_go(), mlx_icmd_set_opcode(), mlx_icmd_write_buffer(), and nodnic_cmd_write().