22 #include "../../include/public/mlx_pci_gw.h" 23 #include "../../include/public/mlx_bail.h" 24 #include "../../include/public/mlx_pci.h" 25 #include "../../include/public/mlx_logging.h" 56 mlx_uint32 cap_offset = utils->pci_gw.pci_cmd_offset;
88 if( counter == semaphore ){
92 if( counter != semaphore ){
108 mlx_uint32 cap_offset = utils->pci_gw.pci_cmd_offset;
126 mlx_uint32 cap_offset = utils->pci_gw.pci_cmd_offset;;
135 if( (space_status & 0x20) == 0){
137 goto space_unsupported;
153 mlx_uint32 cap_offset = utils->pci_gw.pci_cmd_offset;
159 if( ((
flag & 0x80000000) != 0) ==
value ){
180 if( cap_offset ==
NULL || utils ==
NULL){
189 "failed to read capability pointer");
192 while( cap_pointer != 0 ){
195 ,
"failed to check capability id");
197 if( is_capability ==
TRUE ){
198 *cap_offset = cap_pointer;
206 "failed to read capability pointer");
208 if( is_capability !=
TRUE ){
230 pci_gw = &utils->pci_gw;
234 "mlx_pci_gw_search_capability failed");
236 #if ! defined ( VSEC_DEBUG ) 251 #if ! defined ( VSEC_DEBUG ) 269 if (utils ==
NULL ||
buffer ==
NULL || utils->pci_gw.pci_cmd_offset == 0) {
276 pci_gw = &utils->pci_gw;
279 #if ! defined ( VSEC_DEBUG ) 280 if (pci_gw->
space != space) {
283 pci_gw->
space = space;
291 pci_gw->
space = space;
297 #if defined ( DEVICE_CX3 ) 308 #if defined ( VSEC_DEBUG ) 311 "mlx_pci_gw_free_ownership failed");
318 #if defined ( VSEC_DEBUG ) 340 if (utils ==
NULL || utils->pci_gw.pci_cmd_offset == 0) {
347 pci_gw = &utils->pci_gw;
350 #if ! defined ( VSEC_DEBUG ) 351 if (pci_gw->
space != space) {
354 pci_gw->
space = space;
362 pci_gw->
space = space;
372 #if defined ( VSEC_DEBUG ) 375 "mlx_pci_gw_free_ownership failed");
382 #if defined ( VSEC_DEBUG )
#define PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET
#define MLX_INVALID_PARAMETER
mlx_uint32 pci_cmd_offset
mlx_status mlx_pci_gw_write(IN mlx_utils *utils, IN mlx_pci_gw_space space, IN mlx_uint32 address, IN mlx_pci_gw_buffer buffer)
#define PCI_GW_CAPABILITY_FLAG_OFFSET
#define PCI_GW_READ_FLAG_TRIES
uint64_t address
Base address.
#define PCI_GW_CAPABILITY_DATA_OFFSET
mlx_status mlx_utils_release_lock(IN OUT mlx_utils *utils)
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
mlx_status mlx_utils_delay_in_us(IN mlx_uint32 usecs)
mlx_status mlx_pci_read(IN mlx_utils *utils, IN mlx_pci_width width, IN mlx_uint32 offset, IN mlx_uintn count, OUT mlx_void *buffer)
mlx_status mlx_pci_write(IN mlx_utils *utils, IN mlx_pci_width width, IN mlx_uint32 offset, IN mlx_uintn count, IN mlx_void *buffer)
#define PCI_GW_CAPABILITY_ID
#define PCI_GW_CAPABILITY_SPACE_OFFSET
static mlx_status mlx_pci_gw_wait_for_flag_value(IN mlx_utils *utils, IN mlx_boolean value)
static mlx_status mlx_pci_gw_set_space(IN mlx_utils *utils, IN mlx_pci_gw_space space)
FILE_LICENCE(GPL2_OR_LATER)
static mlx_status mlx_pci_gw_search_capability(IN mlx_utils *utils, OUT mlx_uint32 *cap_offset)
pseudo_bit_t value[0x00020]
#define PCI_GW_CAPABILITY_COUNTER_OFFSET
A 16-bit general register.
mlx_status mlx_pci_gw_teardown(IN mlx_utils *utils)
#define PCI_GW_WRITE_FLAG
mlx_status mlx_pci_gw_init(IN mlx_utils *utils)
mlx_status mlx_pci_gw_read(IN mlx_utils *utils, IN mlx_pci_gw_space space, IN mlx_uint32 address, OUT mlx_pci_gw_buffer *buffer)
#define PCI_GW_SEMPHORE_TRIES
static mlx_status mlx_pci_gw_check_capability_id(IN mlx_utils *utils, IN mlx_uint8 cap_pointer, OUT mlx_boolean *bool)
#define PCI_GW_CAPABILITY_ID_OFFSET
static mlx_status mlx_pci_gw_free_ownership(IN mlx_utils *utils)
mlx_status mlx_utils_acquire_lock(IN OUT mlx_utils *utils)
#define PCI_GW_CAPABILITY_STATUS_OFFSET
#define PCI_GW_CAPABILITY_ADDRESS_OFFSET
#define PCI_GW_CAPABILITY_SEMAPHORE_OFFSET
#define PCI_GW_GET_OWNERSHIP_TRIES
uint16_t offset
Offset to command line.
static mlx_status mlx_pci_gw_get_ownership(IN mlx_utils *utils)
uint32_t flag
Flag number.
#define MLX_CHECK_STATUS(id, status, label, message)
#define NULL
NULL pointer (VOID *)
#define PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET
mlx_uint32 mlx_pci_gw_buffer
mlx_uint16 mlx_pci_gw_space