iPXE
natsemi.h
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1 #ifndef _NATSEMI_H
2 #define _NATSEMI_H
3 
4 /** @file
5  *
6  * National Semiconductor "MacPhyter" network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER );
11 
12 #include <stdint.h>
13 #include <ipxe/spi.h>
14 #include <ipxe/spi_bit.h>
15 
16 /** BAR size */
17 #define NATSEMI_BAR_SIZE 0x100
18 
19 /** A 32-bit packet descriptor */
21  /** Link to next descriptor */
23  /** Command / status */
25  /** Buffer pointer */
27 } __attribute__ (( packed ));
28 
29 /** A 64-bit packet descriptor */
31  /** Link to next descriptor */
33  /** Buffer pointer */
35  /** Command / status */
37  /** Extended status */
39 } __attribute__ (( packed ));
40 
41 /** A packet descriptor
42  *
43  * The 32-bit and 64-bit variants are overlaid such that "cmdsts" can
44  * be accessed as a common field, and the overall size is a power of
45  * two (to allow the descriptor ring length to be used as an
46  * alignment).
47  */
49  /** Common fields */
50  struct {
51  /** Reserved */
53  /** Command / status */
55  /** Reserved */
57  } __attribute__ (( packed )) common;
58  /** 64-bit descriptor */
60  /** 32-bit descriptor */
61  struct {
62  /** Reserved */
64  /** Descriptor */
66  } __attribute__ (( packed )) d32pad;
67 };
68 
69 /** Descriptor buffer size mask */
70 #define NATSEMI_DESC_SIZE_MASK 0xfff
71 
72 /** Packet descriptor flags */
74  /** Descriptor is owned by NIC */
75  NATSEMI_DESC_OWN = 0x80000000UL,
76  /** Request descriptor interrupt */
77  NATSEMI_DESC_INTR = 0x20000000UL,
78  /** Packet OK */
79  NATSEMI_DESC_OK = 0x08000000UL,
80 };
81 
82 /** Command Register */
83 #define NATSEMI_CR 0x0000
84 #define NATSEMI_CR_RST 0x00000100UL /**< Reset */
85 #define NATSEMI_CR_RXR 0x00000020UL /**< Receiver reset */
86 #define NATSEMI_CR_TXR 0x00000010UL /**< Transmit reset */
87 #define NATSEMI_CR_RXE 0x00000004UL /**< Receiver enable */
88 #define NATSEMI_CR_TXE 0x00000001UL /**< Transmit enable */
89 
90 /** Maximum time to wait for a reset, in milliseconds */
91 #define NATSEMI_RESET_MAX_WAIT_MS 100
92 
93 /** Configuration and Media Status Register */
94 #define NATSEMI_CFG 0x0004
95 #define NATSEMI_CFG_LNKSTS 0x80000000UL /**< Link status */
96 #define NATSEMI_CFG_SPDSTS1 0x40000000UL /**< Speed status bit 1 */
97 #define NATSEMI_CFG_MODE_1000 0x00400000UL /**< 1000 Mb/s mode control */
98 #define NATSEMI_CFG_PCI64_DET 0x00002000UL /**< PCI 64-bit bus detected */
99 #define NATSEMI_CFG_DATA64_EN 0x00001000UL /**< 64-bit data enable */
100 #define NATSEMI_CFG_M64ADDR 0x00000800UL /**< 64-bit address enable */
101 #define NATSEMI_CFG_EXTSTS_EN 0x00000100UL /**< Extended status enable */
102 
103 /** EEPROM Access Register */
104 #define NATSEMI_MEAR 0x0008
105 #define NATSEMI_MEAR_EESEL 0x00000008UL /**< EEPROM chip select */
106 #define NATSEMI_MEAR_EECLK 0x00000004UL /**< EEPROM serial clock */
107 #define NATSEMI_MEAR_EEDO 0x00000002UL /**< EEPROM data out */
108 #define NATSEMI_MEAR_EEDI 0x00000001UL /**< EEPROM data in */
109 
110 /** Size of EEPROM (in bytes) */
111 #define NATSEMI_EEPROM_SIZE 32
112 
113 /** Word offset of MAC address within sane EEPROM layout */
114 #define NATSEMI_EEPROM_MAC_SANE 0x0a
115 
116 /** Word offset of MAC address within insane EEPROM layout */
117 #define NATSEMI_EEPROM_MAC_INSANE 0x06
118 
119 /** PCI Test Control Register */
120 #define NATSEMI_PTSCR 0x000c
121 #define NATSEMI_PTSCR_EELOAD_EN 0x00000004UL /**< Enable EEPROM load */
122 
123 /** Maximum time to wait for a configuration reload, in milliseconds */
124 #define NATSEMI_EELOAD_MAX_WAIT_MS 100
125 
126 /** Interrupt Status Register */
127 #define NATSEMI_ISR 0x0010
128 #define NATSEMI_IRQ_TXDESC 0x00000080UL /**< TX descriptor */
129 #define NATSEMI_IRQ_RXDESC 0x00000002UL /**< RX descriptor */
130 
131 /** Interrupt Mask Register */
132 #define NATSEMI_IMR 0x0014
133 
134 /** Interrupt Enable Register */
135 #define NATSEMI_IER 0x0018
136 #define NATSEMI_IER_IE 0x00000001UL /**< Interrupt enable */
137 
138 /** Transmit Descriptor Pointer */
139 #define NATSEMI_TXDP 0x0020
140 
141 /** Transmit Descriptor Pointer High Dword (64-bit) */
142 #define NATSEMI_TXDP_HI_64 0x0024
143 
144 /** Number of transmit descriptors */
145 #define NATSEMI_NUM_TX_DESC 4
146 
147 /** Transmit configuration register (32-bit) */
148 #define NATSEMI_TXCFG_32 0x24
149 
150 /** Transmit configuration register (64-bit) */
151 #define NATSEMI_TXCFG_64 0x28
152 #define NATSEMI_TXCFG_CSI 0x80000000UL /**< Carrier sense ignore */
153 #define NATSEMI_TXCFG_HBI 0x40000000UL /**< Heartbeat ignore */
154 #define NATSEMI_TXCFG_ATP 0x10000000UL /**< Automatic padding */
155 #define NATSEMI_TXCFG_ECRETRY 0x00800000UL /**< Excess collision retry */
156 #define NATSEMI_TXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
157 #define NATSEMI_TXCFG_FLTH(x) ( (x) << 8 ) /**< Fill threshold */
158 #define NATSEMI_TXCFG_DRTH(x) ( (x) << 0 ) /**< Drain threshold */
159 
160 /** Max DMA burst size (encoded value)
161  *
162  * This represents 256-byte bursts on 83815 controllers and 512-byte
163  * bursts on 83820 controllers.
164  */
165 #define NATSEMI_TXCFG_MXDMA_DEFAULT NATSEMI_TXCFG_MXDMA ( 0x7 )
166 
167 /** Fill threshold (in units of 32 bytes)
168  *
169  * Must be at least as large as the max DMA burst size, so use a value
170  * of 512 bytes.
171  */
172 #define NATSEMI_TXCFG_FLTH_DEFAULT NATSEMI_TXCFG_FLTH ( 512 / 32 )
173 
174 /** Drain threshold (in units of 32 bytes)
175  *
176  * Start transmission once we receive a conservative 1024 bytes, to
177  * avoid FIFO underrun errors. (83815 does not allow us to specify a
178  * value of 0 for "wait until whole packet is present".)
179  *
180  * Fill threshold plus drain threshold must be less than the transmit
181  * FIFO size, which is 2kB on 83815 and 8kB on 83820.
182  */
183 #define NATSEMI_TXCFG_DRTH_DEFAULT NATSEMI_TXCFG_DRTH ( 1024 / 32 )
184 
185 /** Receive Descriptor Pointer */
186 #define NATSEMI_RXDP 0x0030
187 
188 /** Receive Descriptor Pointer High Dword (64-bit) */
189 #define NATSEMI_RXDP_HI_64 0x0034
190 
191 /** Number of receive descriptors */
192 #define NATSEMI_NUM_RX_DESC 4
193 
194 /** Receive buffer length */
195 #define NATSEMI_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
196 
197 /** Receive configuration register (32-bit) */
198 #define NATSEMI_RXCFG_32 0x34
199 
200 /** Receive configuration register (64-bit) */
201 #define NATSEMI_RXCFG_64 0x38
202 #define NATSEMI_RXCFG_ARP 0x40000000UL /**< Accept runt packets */
203 #define NATSEMI_RXCFG_ATX 0x10000000UL /**< Accept transmit packets */
204 #define NATSEMI_RXCFG_ALP 0x08000000UL /**< Accept long packets */
205 #define NATSEMI_RXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
206 #define NATSEMI_RXCFG_DRTH(x) ( (x) << 1 ) /**< Drain threshold */
207 
208 /** Max DMA burst size (encoded value)
209  *
210  * This represents 256-byte bursts on 83815 controllers and 512-byte
211  * bursts on 83820 controllers.
212  */
213 #define NATSEMI_RXCFG_MXDMA_DEFAULT NATSEMI_RXCFG_MXDMA ( 0x7 )
214 
215 /** Drain threshold (in units of 8 bytes)
216  *
217  * Start draining after 64 bytes.
218  *
219  * Must be large enough to allow packet's accept/reject status to be
220  * determined before draining begins.
221  */
222 #define NATSEMI_RXCFG_DRTH_DEFAULT NATSEMI_RXCFG_DRTH ( 64 / 8 )
223 
224 /** Receive Filter/Match Control Register */
225 #define NATSEMI_RFCR 0x0048
226 #define NATSEMI_RFCR_RFEN 0x80000000UL /**< RX filter enable */
227 #define NATSEMI_RFCR_AAB 0x40000000UL /**< Accept all broadcast */
228 #define NATSEMI_RFCR_AAM 0x20000000UL /**< Accept all multicast */
229 #define NATSEMI_RFCR_AAU 0x10000000UL /**< Accept all unicast */
230 #define NATSEMI_RFCR_RFADDR( addr ) ( (addr) << 0 ) /**< Extended address */
231 #define NATSEMI_RFCR_RFADDR_MASK NATSEMI_RFCR_RFADDR ( 0x3ff )
232 
233 /** Perfect match filter address base */
234 #define NATSEMI_RFADDR_PMATCH_BASE 0x000
235 
236 /** Receive Filter/Match Data Register */
237 #define NATSEMI_RFDR 0x004c
238 #define NATSEMI_RFDR_BMASK 0x00030000UL /**< Byte mask */
239 #define NATSEMI_RFDR_DATA( value ) ( (value) & 0xffff ) /**< Filter data */
240 
241 /** National Semiconductor network card flags */
243  /** EEPROM is little-endian */
245  /** EEPROM layout is insane */
247  /** Card supports 64-bit operation */
248  NATSEMI_64BIT = 0x0004,
249  /** Card supports 1000Mbps link */
250  NATSEMI_1000 = 0x0008,
251 };
252 
253 /** A National Semiconductor descriptor ring */
254 struct natsemi_ring {
255  /** Descriptors */
257  /** Producer index */
258  unsigned int prod;
259  /** Consumer index */
260  unsigned int cons;
261 
262  /** Number of descriptors */
263  unsigned int count;
264  /** Descriptor start address register */
265  unsigned int reg;
266 };
267 
268 /**
269  * Initialise descriptor ring
270  *
271  * @v ring Descriptor ring
272  * @v count Number of descriptors
273  * @v reg Descriptor start address register
274  */
275 static inline __attribute__ (( always_inline)) void
276 natsemi_init_ring ( struct natsemi_ring *ring, unsigned int count,
277  unsigned int reg ) {
278  ring->count = count;
279  ring->reg = reg;
280 }
281 
282 /** A National Semiconductor network card */
283 struct natsemi_nic {
284  /** Flags */
285  unsigned int flags;
286  /** Registers */
287  void *regs;
288  /** SPI bit-bashing interface */
290  /** EEPROM */
292 
293  /** Transmit descriptor ring */
294  struct natsemi_ring tx;
295  /** Receive descriptor ring */
296  struct natsemi_ring rx;
297  /** Receive I/O buffers */
299 
300  /** Link status (cache) */
302 };
303 
304 /**
305  * Check if card can access physical address
306  *
307  * @v natsemi National Semiconductor device
308  * @v address Physical address
309  * @v address_ok Card can access physical address
310  */
311 static inline __attribute__ (( always_inline )) int
312 natsemi_address_ok ( struct natsemi_nic *natsemi, physaddr_t address ) {
313 
314  /* In a 32-bit build, all addresses can be accessed */
315  if ( sizeof ( physaddr_t ) <= sizeof ( uint32_t ) )
316  return 1;
317 
318  /* A 64-bit card can access all addresses */
319  if ( natsemi->flags & NATSEMI_64BIT )
320  return 1;
321 
322  /* A 32-bit card can access all addresses below 4GB */
323  if ( ( address & ~0xffffffffULL ) == 0 )
324  return 1;
325 
326  return 0;
327 }
328 
329 #endif /* _NATSEMI_H */
unsigned int prod
Producer index.
Definition: natsemi.h:258
struct natsemi_ring rx
Receive descriptor ring.
Definition: natsemi.h:296
uint32_t cmdsts
Command / status.
Definition: natsemi.h:24
uint32_t extsts
Extended status.
Definition: natsemi.h:38
natsemi_nic_flags
National Semiconductor network card flags.
Definition: natsemi.h:242
Card supports 64-bit operation.
Definition: natsemi.h:248
struct natsemi_ring tx
Transmit descriptor ring.
Definition: natsemi.h:294
uint8_t reserved_a[16]
Reserved.
Definition: natsemi.h:52
Packet OK.
Definition: natsemi.h:79
unsigned int cons
Consumer index.
Definition: natsemi.h:260
SPI bit-bashing interface.
uint32_t cmdsts
Command / status.
Definition: natsemi.h:36
static unsigned int count
Definition: natsemi.h:276
unsigned long long uint64_t
Definition: stdint.h:13
uint32_t cfg
Link status (cache)
Definition: natsemi.h:301
uint32_t bufptr
Buffer pointer.
Definition: natsemi.h:26
uint32_t cmdsts
Command / status.
Definition: natsemi.h:54
A 32-bit packet descriptor.
Definition: natsemi.h:20
eeprom
Definition: 3c90x.h:232
static physaddr_t address
Definition: natsemi.h:312
A packet descriptor.
Definition: natsemi.h:48
union natsemi_descriptor * desc
Descriptors.
Definition: natsemi.h:256
SPI interface.
unsigned int count
Number of descriptors.
Definition: natsemi.h:263
natsemi_descriptor_flags
Packet descriptor flags.
Definition: natsemi.h:73
uint64_t link
Link to next descriptor.
Definition: natsemi.h:32
unsigned int flags
Flags.
Definition: natsemi.h:285
A bit-bashing SPI bus.
Definition: spi_bit.h:16
A 64-bit packet descriptor.
Definition: natsemi.h:30
unsigned int reg
Descriptor start address register.
Definition: natsemi.h:265
uint32_t link
Link to next descriptor.
Definition: natsemi.h:22
struct spi_bit_basher spibit
SPI bit-bashing interface.
Definition: natsemi.h:289
EEPROM layout is insane.
Definition: natsemi.h:246
union natsemi_descriptor __attribute__
A National Semiconductor descriptor ring.
Definition: natsemi.h:254
unsigned char uint8_t
Definition: stdint.h:10
struct natsemi_descriptor_64 d64
64-bit descriptor
Definition: natsemi.h:59
struct natsemi_descriptor_32 d32
Descriptor.
Definition: natsemi.h:65
unsigned int uint32_t
Definition: stdint.h:12
struct ib_cm_common common
Definition: ib_mad.h:11
Card supports 1000Mbps link.
Definition: natsemi.h:250
void * regs
Registers.
Definition: natsemi.h:287
unsigned long physaddr_t
Definition: stdint.h:20
static unsigned int unsigned int reg
Definition: natsemi.h:277
EEPROM is little-endian.
Definition: natsemi.h:244
Descriptor is owned by NIC.
Definition: natsemi.h:75
An SPI device.
Definition: spi.h:86
Request descriptor interrupt.
Definition: natsemi.h:77
FILE_LICENCE(GPL2_OR_LATER)
struct io_buffer * rx_iobuf[NATSEMI_NUM_RX_DESC]
Receive I/O buffers.
Definition: natsemi.h:298
struct natsemi_descriptor::@76 __attribute__((packed)) common
Common fields.
uint8_t reserved[12]
Reserved.
Definition: natsemi.h:63
A National Semiconductor network card.
Definition: natsemi.h:283
#define NATSEMI_NUM_RX_DESC
Number of receive descriptors.
Definition: natsemi.h:192
uint64_t bufptr
Buffer pointer.
Definition: natsemi.h:34
uint8_t reserved_b[12]
Reserved.
Definition: natsemi.h:56
A persistent I/O buffer.
Definition: iobuf.h:32