iPXE
thunderx.h
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1 #ifndef _THUNDERX_H
2 #define _THUNDERX_H
3 
4 /** @file
5  *
6  * Cavium ThunderX Ethernet driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/list.h>
14 #include <ipxe/netdevice.h>
15 #include <ipxe/uaccess.h>
16 
17 /******************************************************************************
18  *
19  * Address space
20  *
21  ******************************************************************************
22  */
23 
24 /** Size of a cache line */
25 #define TXNIC_LINE_SIZE 128
26 
27 /** Virtual function BAR size */
28 #define TXNIC_VF_BAR_SIZE 0x200000UL
29 
30 /** Physical function BAR size */
31 #define TXNIC_PF_BAR_SIZE 0x40000000UL
32 
33 /** BGX BAR size */
34 #define TXNIC_BGX_BAR_SIZE 0x400000UL
35 
36 /** Maximum number of BGX Ethernet interfaces (per node) */
37 #define TXNIC_NUM_BGX 2
38 
39 /** Maximum number of Logical MACs (per BGX) */
40 #define TXNIC_NUM_LMAC 4
41 
42 /** Maximum number of destination MAC addresses (per BGX) */
43 #define TXNIC_NUM_DMAC 32
44 
45 /** Maximum number of steering rules (per BGX) */
46 #define TXNIC_NUM_STEERING 8
47 
48 /**
49  * Calculate node ID
50  *
51  * @v addr PCI BAR base address
52  * @ret node Node ID
53  */
54 static inline unsigned int txnic_address_node ( uint64_t addr ) {
55 
56  /* Node ID is in bits [45:44] of the hardcoded BAR address */
57  return ( ( addr >> 44 ) & 0x3 );
58 }
59 
60 /**
61  * Calculate BGX Ethernet interface index
62  *
63  * @v addr PCI BAR base address
64  * @ret index Index
65  */
66 static inline unsigned int txnic_address_bgx ( uint64_t addr ) {
67 
68  /* Index is in bit 24 of the hardcoded BAR address */
69  return ( ( addr >> 24 ) & 0x1 );
70 }
71 
72 /******************************************************************************
73  *
74  * Send queue
75  *
76  ******************************************************************************
77  */
78 
79 /** Send queue configuration */
80 #define TXNIC_QS_SQ_CFG(q) ( ( (q) << 18 ) | 0x010800 )
81 #define TXNIC_QS_SQ_CFG_ENA ( 1ULL << 19 )
82 #define TXNIC_QS_SQ_CFG_RESET ( 1ULL << 17 )
83 #define TXNIC_QS_SQ_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 8 )
84 #define TXNIC_QS_SQ_CFG_QSIZE_1K \
85  TXNIC_QS_SQ_CFG_QSIZE ( 0 )
86 
87 /** Send queue base address */
88 #define TXNIC_QS_SQ_BASE(q) ( ( (q) << 18 ) | 0x010820 )
89 
90 /** Send queue head pointer */
91 #define TXNIC_QS_SQ_HEAD(q) ( ( (q) << 18 ) | 0x010828 )
92 
93 /** Send queue tail pointer */
94 #define TXNIC_QS_SQ_TAIL(q) ( ( (q) << 18 ) | 0x010830 )
95 
96 /** Send queue doorbell */
97 #define TXNIC_QS_SQ_DOOR(q) ( ( (q) << 18 ) | 0x010838 )
98 
99 /** Send queue status */
100 #define TXNIC_QS_SQ_STATUS(q) ( ( (q) << 18 ) | 0x010840 )
101 #define TXNIC_QS_SQ_STATUS_STOPPED ( 1ULL << 21 )
102 
103 /** Maximum time to wait for a send queue to stop
104  *
105  * This is a policy decision.
106  */
107 #define TXNIC_SQ_STOP_MAX_WAIT_MS 100
108 
109 /** A send header subdescriptor */
111  /** Total length */
113  /** Unused */
115  /** Subdescriptor count */
117  /** Flags */
119  /** Unused */
121 } __attribute__ (( packed ));
122 
123 /** Flags for send header subdescriptor
124  *
125  * These comprise SUBDC=0x1 and PNC=0x1.
126  */
127 #define TXNIC_SEND_HDR_FLAGS 0x14
128 
129 /** A send gather subdescriptor */
131  /** Size */
133  /** Unused */
135  /** Flags */
137  /** Address */
139 } __attribute__ (( packed ));
140 
141 /** Flags for send gather subdescriptor
142  *
143  * These comprise SUBDC=0x4 and LD_TYPE=0x0.
144  */
145 #define TXNIC_SEND_GATHER_FLAGS 0x40
146 
147 /** A send queue entry
148  *
149  * Each send queue entry comprises a single send header subdescriptor
150  * and a single send gather subdescriptor.
151  */
152 struct txnic_sqe {
153  /** Send header descriptor */
155  /** Send gather descriptor */
157 } __attribute__ (( packed ));
158 
159 /** Number of subdescriptors per send queue entry */
160 #define TXNIC_SQE_SUBDESCS ( sizeof ( struct txnic_sqe ) / \
161  sizeof ( struct txnic_send_header ) )
162 
163 /** Number of send queue entries
164  *
165  * The minimum send queue size is 1024 entries.
166  */
167 #define TXNIC_SQES ( 1024 / TXNIC_SQE_SUBDESCS )
168 
169 /** Send queue maximum fill level
170  *
171  * This is a policy decision.
172  */
173 #define TXNIC_SQ_FILL 32
174 
175 /** Send queue alignment */
176 #define TXNIC_SQ_ALIGN TXNIC_LINE_SIZE
177 
178 /** Send queue stride */
179 #define TXNIC_SQ_STRIDE sizeof ( struct txnic_sqe )
180 
181 /** Send queue size */
182 #define TXNIC_SQ_SIZE ( TXNIC_SQES * TXNIC_SQ_STRIDE )
183 
184 /** A send queue */
185 struct txnic_sq {
186  /** Producer counter */
187  unsigned int prod;
188  /** Consumer counter */
189  unsigned int cons;
190  /** Send queue entries */
192 };
193 
194 /******************************************************************************
195  *
196  * Receive queue
197  *
198  ******************************************************************************
199  */
200 
201 /** Receive queue configuration */
202 #define TXNIC_QS_RQ_CFG(q) ( ( (q) << 18 ) | 0x010600 )
203 #define TXNIC_QS_RQ_CFG_ENA ( 1ULL << 1 )
204 
205 /** Maximum time to wait for a receive queue to disable
206  *
207  * This is a policy decision.
208  */
209 #define TXNIC_RQ_DISABLE_MAX_WAIT_MS 100
210 
211 /** Receive buffer descriptor ring configuration */
212 #define TXNIC_QS_RBDR_CFG(q) ( ( (q) << 18 ) | 0x010c00 )
213 #define TXNIC_QS_RBDR_CFG_ENA ( 1ULL << 44 )
214 #define TXNIC_QS_RBDR_CFG_RESET ( 1ULL << 43 )
215 #define TXNIC_QS_RBDR_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 32 )
216 #define TXNIC_QS_RBDR_CFG_QSIZE_8K \
217  TXNIC_QS_RBDR_CFG_QSIZE ( 0 )
218 #define TXNIC_QS_RBDR_CFG_LINES(sz) ( ( ( uint64_t ) (sz) ) << 0 )
219 
220 /** Receive buffer descriptor ring base address */
221 #define TXNIC_QS_RBDR_BASE(q) ( ( (q) << 18 ) | 0x010c20 )
222 
223 /** Receive buffer descriptor ring head pointer */
224 #define TXNIC_QS_RBDR_HEAD(q) ( ( (q) << 18 ) | 0x010c28 )
225 
226 /** Receive buffer descriptor ring tail pointer */
227 #define TXNIC_QS_RBDR_TAIL(q) ( ( (q) << 18 ) | 0x010c30 )
228 
229 /** Receive buffer descriptor ring doorbell */
230 #define TXNIC_QS_RBDR_DOOR(q) ( ( (q) << 18 ) | 0x010c38 )
231 
232 /** Receive buffer descriptor ring status 0 */
233 #define TXNIC_QS_RBDR_STATUS0(q) ( ( (q) << 18 ) | 0x010c40 )
234 
235 /** A receive buffer descriptor ring entry */
237  /** Address */
239 } __attribute__ (( packed ));
240 
241 /** A receive queue entry */
242 struct txnic_rqe {
243  /** Receive buffer descriptor ring entry */
245 } __attribute__ (( packed ));
246 
247 /** Number of receive queue entries
248  *
249  * The minimum receive queue size is 8192 entries.
250  */
251 #define TXNIC_RQES 8192
252 
253 /** Receive queue maximum fill level
254  *
255  * This is a policy decision. Must not exceed TXNIC_RQES.
256  */
257 #define TXNIC_RQ_FILL 32
258 
259 /** Receive queue entry size
260  *
261  * This is a policy decision.
262  */
263 #define TXNIC_RQE_SIZE ( ( ETH_DATA_ALIGN + ETH_FRAME_LEN + \
264  4 /* VLAN */ + TXNIC_LINE_SIZE - 1 ) \
265  & ~( TXNIC_LINE_SIZE - 1 ) )
266 
267 /** Receive queue alignment */
268 #define TXNIC_RQ_ALIGN TXNIC_LINE_SIZE
269 
270 /** Receive queue stride */
271 #define TXNIC_RQ_STRIDE sizeof ( struct txnic_rqe )
272 
273 /** Receive queue size */
274 #define TXNIC_RQ_SIZE ( TXNIC_RQES * TXNIC_RQ_STRIDE )
275 
276 /** A receive queue */
277 struct txnic_rq {
278  /** Producer counter */
279  unsigned int prod;
280  /** Consumer counter */
281  unsigned int cons;
282  /** Receive queue entries */
284  /** I/O buffers */
286 };
287 
288 /******************************************************************************
289  *
290  * Completion queue
291  *
292  ******************************************************************************
293  */
294 
295 /** Completion queue configuration */
296 #define TXNIC_QS_CQ_CFG(q) ( ( (q) << 18 ) | 0x010400 )
297 #define TXNIC_QS_CQ_CFG_ENA ( 1ULL << 42 )
298 #define TXNIC_QS_CQ_CFG_RESET ( 1ULL << 41 )
299 #define TXNIC_QS_CQ_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 32 )
300 #define TXNIC_QS_CQ_CFG_QSIZE_256 \
301  TXNIC_QS_CQ_CFG_QSIZE ( 7 )
302 
303 /** Maximum time to wait for a completion queue to disable
304  *
305  * This is a policy decision.
306  */
307 #define TXNIC_CQ_DISABLE_MAX_WAIT_MS 100
308 
309 /** Completion queue base address */
310 #define TXNIC_QS_CQ_BASE(q) ( ( (q) << 18 ) | 0x010420 )
311 
312 /** Completion queue head pointer */
313 #define TXNIC_QS_CQ_HEAD(q) ( ( (q) << 18 ) | 0x010428 )
314 
315 /** Completion queue tail pointer */
316 #define TXNIC_QS_CQ_TAIL(q) ( ( (q) << 18 ) | 0x010430 )
317 
318 /** Completion queue doorbell */
319 #define TXNIC_QS_CQ_DOOR(q) ( ( (q) << 18 ) | 0x010438 )
320 
321 /** Completion queue status */
322 #define TXNIC_QS_CQ_STATUS(q) ( ( (q) << 18 ) | 0x010440 )
323 #define TXNIC_QS_CQ_STATUS_QCOUNT(status) \
324  ( ( (status) >> 0 ) & 0xffff )
325 
326 /** Completion queue status 2 */
327 #define TXNIC_QS_CQ_STATUS2(q) ( ( (q) << 18 ) | 0x010448 )
328 
329 /** A send completion queue entry */
331  /** Status */
333  /** Unused */
335  /** Send queue entry pointer */
337  /** Type */
339 } __attribute__ (( packed ));
340 
341 /** Send completion queue entry type */
342 #define TXNIC_CQE_TYPE_SEND 0x80
343 
344 /** A receive completion queue entry */
345 struct txnic_cqe_rx {
346  /** Error opcode */
348  /** Unused */
350  /** Type */
352  /** Unused */
354  /** Padding */
356  /** Unused */
358  /** Length */
360 } __attribute__ (( packed ));
361 
362 /** Receive completion queue entry type */
363 #define TXNIC_CQE_TYPE_RX 0x20
364 
365 /** Applied padding */
366 #define TXNIC_CQE_RX_APAD_LEN( apad ) ( (apad) >> 5 )
367 
368 /** Completion queue entry common fields */
370  /** Unused */
372  /** Type */
374 } __attribute__ (( packed ));
375 
376 /** A completion queue entry */
377 union txnic_cqe {
378  /** Common fields */
380  /** Send completion */
382  /** Receive completion */
383  struct txnic_cqe_rx rx;
384 };
385 
386 /** Number of completion queue entries
387  *
388  * The minimum completion queue size is 256 entries.
389  */
390 #define TXNIC_CQES 256
391 
392 /** Completion queue alignment */
393 #define TXNIC_CQ_ALIGN 512
394 
395 /** Completion queue stride */
396 #define TXNIC_CQ_STRIDE 512
397 
398 /** Completion queue size */
399 #define TXNIC_CQ_SIZE ( TXNIC_CQES * TXNIC_CQ_STRIDE )
400 
401 /** A completion queue */
402 struct txnic_cq {
403  /** Consumer counter */
404  unsigned int cons;
405  /** Completion queue entries */
407 };
408 
409 /******************************************************************************
410  *
411  * Virtual NIC
412  *
413  ******************************************************************************
414  */
415 
416 /** A virtual NIC */
417 struct txnic {
418  /** Registers */
419  void *regs;
420  /** Device name (for debugging) */
421  const char *name;
422  /** Network device */
424 
425  /** Send queue */
426  struct txnic_sq sq;
427  /** Receive queue */
428  struct txnic_rq rq;
429  /** Completion queue */
430  struct txnic_cq cq;
431 };
432 
433 /******************************************************************************
434  *
435  * Physical function
436  *
437  ******************************************************************************
438  */
439 
440 /** Physical function configuration */
441 #define TXNIC_PF_CFG 0x000000
442 #define TXNIC_PF_CFG_ENA ( 1ULL << 0 )
443 
444 /** Backpressure configuration */
445 #define TXNIC_PF_BP_CFG 0x000080
446 #define TXNIC_PF_BP_CFG_BP_POLL_ENA ( 1ULL << 6 )
447 #define TXNIC_PF_BP_CFG_BP_POLL_DLY(dl) ( ( ( uint64_t ) (dl) ) << 0 )
448 #define TXNIC_PF_BP_CFG_BP_POLL_DLY_DEFAULT \
449  TXNIC_PF_BP_CFG_BP_POLL_DLY ( 3 )
450 
451 /** Interface send configuration */
452 #define TXNIC_PF_INTF_SEND_CFG(in) ( ( (in) << 8 ) | 0x000200 )
453 #define TXNIC_PF_INTF_SEND_CFG_BLOCK_BGX ( 1ULL << 3 )
454 #define TXNIC_PF_INTF_SEND_CFG_BLOCK(bl) ( ( ( uint64_t ) (bl) ) << 0 )
455 
456 /** Interface backpressure configuration */
457 #define TXNIC_PF_INTF_BP_CFG(in) ( ( (in) << 8 ) | 0x000208 )
458 #define TXNIC_PF_INTF_BP_CFG_BP_ENA ( 1ULL << 63 )
459 #define TXNIC_PF_INTF_BP_CFG_BP_ID_BGX ( 1ULL << 3 )
460 #define TXNIC_PF_INTF_BP_CFG_BP_ID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
461 
462 /** Port kind configuration */
463 #define TXNIC_PF_PKIND_CFG(pk) ( ( (pk) << 3 ) | 0x000600 )
464 #define TXNIC_PF_PKIND_CFG_LENERR_EN ( 1ULL << 33 )
465 #define TXNIC_PF_PKIND_CFG_MAXLEN(ct) ( ( ( uint64_t ) (ct) ) << 16 )
466 #define TXNIC_PF_PKIND_CFG_MAXLEN_DISABLE \
467  TXNIC_PF_PKIND_CFG_MAXLEN ( 0xffff )
468 #define TXNIC_PF_PKIND_CFG_MINLEN(ct) ( ( ( uint64_t ) (ct) ) << 0 )
469 #define TXNIC_PF_PKIND_CFG_MINLEN_DISABLE \
470  TXNIC_PF_PKIND_CFG_MINLEN ( 0x0000 )
471 
472 /** Match parse index configuration */
473 #define TXNIC_PF_MPI_CFG(ix) ( ( (ix) << 3 ) | 0x210000 )
474 #define TXNIC_PF_MPI_CFG_VNIC(vn) ( ( ( uint64_t ) (vn) ) << 24 )
475 #define TXNIC_PF_MPI_CFG_RSSI_BASE(ix) ( ( ( uint64_t ) (ix) ) << 0 )
476 
477 /** RSS indirection receive queue */
478 #define TXNIC_PF_RSSI_RQ(ix) ( ( (ix) << 3 ) | 0x220000 )
479 #define TXNIC_PF_RSSI_RQ_RQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 3 )
480 
481 /** LMAC registers */
482 #define TXNIC_PF_LMAC(lm) ( ( (lm) << 3 ) | 0x240000 )
483 
484 /** LMAC configuration */
485 #define TXNIC_PF_LMAC_CFG 0x000000
486 #define TXNIC_PF_LMAC_CFG_ADJUST(ad) ( ( ( uint64_t ) (ad) ) << 8 )
487 #define TXNIC_PF_LMAC_CFG_ADJUST_DEFAULT \
488  TXNIC_PF_LMAC_CFG_ADJUST ( 6 )
489 #define TXNIC_PF_LMAC_CFG_MIN_PKT_SIZE(sz) ( ( ( uint64_t ) (sz) ) << 0 )
490 
491 /** LMAC configuration 2 */
492 #define TXNIC_PF_LMAC_CFG2 0x000100
493 #define TXNIC_PF_LMAC_CFG2_MAX_PKT_SIZE(sz) ( ( ( uint64_t ) (sz) ) << 0 )
494 
495 /** LMAC credit */
496 #define TXNIC_PF_LMAC_CREDIT 0x004000
497 #define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT(ct) ( ( ( uint64_t ) (ct) ) << 12 )
498 #define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT_DEFAULT \
499  TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT ( 192 )
500 #define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT(ct) ( ( ( uint64_t ) (ct) ) << 2 )
501 #define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT_DEFAULT \
502  TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT ( 511 )
503 #define TXNIC_PF_LMAC_CREDIT_CC_ENABLE ( 1ULL << 1 )
504 
505 /** Channel registers */
506 #define TXNIC_PF_CHAN(ch) ( ( (ch) << 3 ) | 0x400000 )
507 
508 /** Channel transmit configuration */
509 #define TXNIC_PF_CHAN_TX_CFG 0x000000
510 #define TXNIC_PF_CHAN_TX_CFG_BP_ENA ( 1ULL << 0 )
511 
512 /** Channel receive configuration */
513 #define TXNIC_PF_CHAN_RX_CFG 0x020000
514 #define TXNIC_PF_CHAN_RX_CFG_CPI_BASE(ix) ( ( ( uint64_t ) (ix) ) << 48 )
515 
516 /** Channel receive backpressure configuration */
517 #define TXNIC_PF_CHAN_RX_BP_CFG 0x080000
518 #define TXNIC_PF_CHAN_RX_BP_CFG_ENA ( 1ULL << 63 )
519 #define TXNIC_PF_CHAN_RX_BP_CFG_BPID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
520 
521 /** Traffic limiter 2 configuration */
522 #define TXNIC_PF_TL2_CFG(tl) ( ( (tl) << 3 ) | 0x500000 )
523 #define TXNIC_PF_TL2_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
524 #define TXNIC_PF_TL2_CFG_RR_QUANTUM_DEFAULT \
525  TXNIC_PF_TL2_CFG_RR_QUANTUM ( 0x905 )
526 
527 /** Traffic limiter 3 configuration */
528 #define TXNIC_PF_TL3_CFG(tl) ( ( (tl) << 3 ) | 0x600000 )
529 #define TXNIC_PF_TL3_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
530 #define TXNIC_PF_TL3_CFG_RR_QUANTUM_DEFAULT \
531  TXNIC_PF_TL3_CFG_RR_QUANTUM ( 0x905 )
532 
533 /** Traffic limiter 3 channel mapping */
534 #define TXNIC_PF_TL3_CHAN(tl) ( ( (tl) << 3 ) | 0x620000 )
535 #define TXNIC_PF_TL3_CHAN_CHAN(ch) ( ( (ch) & 0x7f ) << 0 )
536 
537 /** Traffic limiter 4 configuration */
538 #define TXNIC_PF_TL4_CFG(tl) ( ( (tl) << 3 ) | 0x800000 )
539 #define TXNIC_PF_TL4_CFG_SQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 27 )
540 #define TXNIC_PF_TL4_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
541 #define TXNIC_PF_TL4_CFG_RR_QUANTUM_DEFAULT \
542  TXNIC_PF_TL4_CFG_RR_QUANTUM ( 0x905 )
543 
544 /** Queue set registers */
545 #define TXNIC_PF_QS(qs) ( ( (qs) << 21 ) | 0x20000000UL )
546 
547 /** Queue set configuration */
548 #define TXNIC_PF_QS_CFG 0x010000
549 #define TXNIC_PF_QS_CFG_ENA ( 1ULL << 31 )
550 #define TXNIC_PF_QS_CFG_VNIC(vn) ( ( ( uint64_t ) (vn) ) << 0 )
551 
552 /** Receive queue configuration */
553 #define TXNIC_PF_QS_RQ_CFG(q) ( ( (q) << 18 ) | 0x010400 )
554 #define TXNIC_PF_QS_RQ_CFG_CACHING(cx) ( ( ( uint64_t ) (cx) ) << 26 )
555 #define TXNIC_PF_QS_RQ_CFG_CACHING_ALL \
556  TXNIC_PF_QS_RQ_CFG_CACHING ( 1 )
557 #define TXNIC_PF_QS_RQ_CFG_CQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 19 )
558 #define TXNIC_PF_QS_RQ_CFG_RBDR_CONT_QS(qs) ( ( ( uint64_t ) (qs) ) << 9 )
559 #define TXNIC_PF_QS_RQ_CFG_RBDR_STRT_QS(qs) ( ( ( uint64_t ) (qs) ) << 1 )
560 
561 /** Receive queue drop configuration */
562 #define TXNIC_PF_QS_RQ_DROP_CFG(q) ( ( (q) << 18 ) | 0x010420 )
563 
564 /** Receive queue backpressure configuration */
565 #define TXNIC_PF_QS_RQ_BP_CFG(q) ( ( (q) << 18 ) | 0x010500 )
566 #define TXNIC_PF_QS_RQ_BP_CFG_RBDR_BP_ENA ( 1ULL << 63 )
567 #define TXNIC_PF_QS_RQ_BP_CFG_CQ_BP_ENA ( 1ULL << 62 )
568 #define TXNIC_PF_QS_RQ_BP_CFG_BPID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
569 
570 /** Send queue configuration */
571 #define TXNIC_PF_QS_SQ_CFG(q) ( ( (q) << 18 ) | 0x010c00 )
572 #define TXNIC_PF_QS_SQ_CFG_CQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 3 )
573 
574 /** Send queue configuration 2 */
575 #define TXNIC_PF_QS_SQ_CFG2(q) ( ( (q) << 18 ) | 0x010c08 )
576 #define TXNIC_PF_QS_SQ_CFG2_TL4(tl) ( ( ( uint64_t ) (tl) ) << 0 )
577 
578 /** A physical function */
579 struct txnic_pf {
580  /** Registers */
581  void *regs;
582  /** PCI device */
583  struct pci_device *pci;
584  /** Node ID */
585  unsigned int node;
586 
587  /** Virtual function BAR base */
588  unsigned long vf_membase;
589  /** Virtual function BAR stride */
590  unsigned long vf_stride;
591 
592  /** List of physical functions */
593  struct list_head list;
594  /** BGX Ethernet interfaces (if known) */
596 };
597 
598 /**
599  * Calculate virtual NIC index
600  *
601  * @v bgx_idx BGX Ethernet interface index
602  * @v lmac_idx Logical MAC index
603  * @ret vnic_idx Virtual NIC index
604  */
605 #define TXNIC_VNIC_IDX( bgx_idx, lmac_idx ) \
606  ( ( (bgx_idx) * TXNIC_NUM_LMAC ) + (lmac_idx) )
607 
608 /**
609  * Calculate BGX Ethernet interface index
610  *
611  * @v vnic_idx Virtual NIC index
612  * @ret bgx_idx BGX Ethernet interface index
613  */
614 #define TXNIC_BGX_IDX( vnic_idx ) ( (vnic_idx) / TXNIC_NUM_LMAC )
615 
616 /**
617  * Calculate logical MAC index
618  *
619  * @v vnic_idx Virtual NIC index
620  * @ret lmac_idx Logical MAC index
621  */
622 #define TXNIC_LMAC_IDX( vnic_idx ) ( (vnic_idx) % TXNIC_NUM_LMAC )
623 
624 /**
625  * Calculate traffic limiter 2 index
626  *
627  * @v vnic_idx Virtual NIC index
628  * @v tl2_idx Traffic limiter 2 index
629  */
630 #define TXNIC_TL2_IDX( vnic_idx ) ( (vnic_idx) << 3 )
631 
632 /**
633  * Calculate traffic limiter 3 index
634  *
635  * @v vnic_idx Virtual NIC index
636  * @v tl3_idx Traffic limiter 3 index
637  */
638 #define TXNIC_TL3_IDX( vnic_idx ) ( (vnic_idx) << 5 )
639 
640 /**
641  * Calculate traffic limiter 4 index
642  *
643  * @v vnic_idx Virtual NIC index
644  * @v tl4_idx Traffic limiter 4 index
645  */
646 #define TXNIC_TL4_IDX( vnic_idx ) ( (vnic_idx) << 7 )
647 
648 /**
649  * Calculate channel index
650  *
651  * @v vnic_idx Virtual NIC index
652  * @v chan_idx Channel index
653  */
654 #define TXNIC_CHAN_IDX( vnic_idx ) ( ( TXNIC_BGX_IDX (vnic_idx) << 7 ) | \
655  ( TXNIC_LMAC_IDX (vnic_idx) << 4 ) )
656 
657 /******************************************************************************
658  *
659  * BGX Ethernet interface
660  *
661  ******************************************************************************
662  */
663 
664 /** Per-LMAC registers */
665 #define BGX_LMAC(lm) ( ( (lm) << 20 ) | 0x00000000UL )
666 
667 /** CMR configuration */
668 #define BGX_CMR_CONFIG 0x000000
669 #define BGX_CMR_CONFIG_ENABLE ( 1ULL << 15 )
670 #define BGX_CMR_CONFIG_DATA_PKT_RX_EN ( 1ULL << 14 )
671 #define BGX_CMR_CONFIG_DATA_PKT_TX_EN ( 1ULL << 13 )
672 #define BGX_CMR_CONFIG_LMAC_TYPE_GET(config) \
673  ( ( (config) >> 8 ) & 0x7 )
674 #define BGX_CMR_CONFIG_LMAC_TYPE_SET(ty) ( ( ( uint64_t ) (ty) ) << 8 )
675 #define BGX_CMR_CONFIG_LANE_TO_SDS(ls) ( ( ( uint64_t ) (ls) ) << 0 )
676 
677 /** CMR global configuration */
678 #define BGX_CMR_GLOBAL_CONFIG 0x000008
679 #define BGX_CMR_GLOBAL_CONFIG_FCS_STRIP ( 1ULL << 6 )
680 
681 /** CMR receive statistics 0 */
682 #define BGX_CMR_RX_STAT0 0x000070
683 
684 /** CMR receive statistics 1 */
685 #define BGX_CMR_RX_STAT1 0x000078
686 
687 /** CMR receive statistics 2 */
688 #define BGX_CMR_RX_STAT2 0x000080
689 
690 /** CMR receive statistics 3 */
691 #define BGX_CMR_RX_STAT3 0x000088
692 
693 /** CMR receive statistics 4 */
694 #define BGX_CMR_RX_STAT4 0x000090
695 
696 /** CMR receive statistics 5 */
697 #define BGX_CMR_RX_STAT5 0x000098
698 
699 /** CMR receive statistics 6 */
700 #define BGX_CMR_RX_STAT6 0x0000a0
701 
702 /** CMR receive statistics 7 */
703 #define BGX_CMR_RX_STAT7 0x0000a8
704 
705 /** CMR receive statistics 8 */
706 #define BGX_CMR_RX_STAT8 0x0000b0
707 
708 /** CMR receive statistics 9 */
709 #define BGX_CMR_RX_STAT9 0x0000b8
710 
711 /** CMR receive statistics 10 */
712 #define BGX_CMR_RX_STAT10 0x0000c0
713 
714 /** CMR destination MAC control */
715 #define BGX_CMR_RX_DMAC_CTL 0x0000e8
716 #define BGX_CMR_RX_DMAC_CTL_MCST_MODE(md) ( ( ( uint64_t ) (md) ) << 1 )
717 #define BGX_CMR_RX_DMAC_CTL_MCST_MODE_ACCEPT \
718  BGX_CMR_RX_DMAC_CTL_MCST_MODE ( 1 )
719 #define BGX_CMR_RX_DMAC_CTL_BCST_ACCEPT ( 1ULL << 0 )
720 
721 /** CMR destination MAC CAM */
722 #define BGX_CMR_RX_DMAC_CAM(i) ( ( (i) << 3 ) | 0x000200 )
723 
724 /** CMR receive steering */
725 #define BGX_CMR_RX_STEERING(i) ( ( (i) << 3 ) | 0x000300 )
726 
727 /** CMR backpressure channel mask AND */
728 #define BGX_CMR_CHAN_MSK_AND 0x000450
729 #define BGX_CMR_CHAN_MSK_AND_ALL(count) \
730  ( 0xffffffffffffffffULL >> ( 16 * ( 4 - (count) ) ) )
731 
732 /** CMR transmit statistics 0 */
733 #define BGX_CMR_TX_STAT0 0x000600
734 
735 /** CMR transmit statistics 1 */
736 #define BGX_CMR_TX_STAT1 0x000608
737 
738 /** CMR transmit statistics 2 */
739 #define BGX_CMR_TX_STAT2 0x000610
740 
741 /** CMR transmit statistics 3 */
742 #define BGX_CMR_TX_STAT3 0x000618
743 
744 /** CMR transmit statistics 4 */
745 #define BGX_CMR_TX_STAT4 0x000620
746 
747 /** CMR transmit statistics 5 */
748 #define BGX_CMR_TX_STAT5 0x000628
749 
750 /** CMR transmit statistics 6 */
751 #define BGX_CMR_TX_STAT6 0x000630
752 
753 /** CMR transmit statistics 7 */
754 #define BGX_CMR_TX_STAT7 0x000638
755 
756 /** CMR transmit statistics 8 */
757 #define BGX_CMR_TX_STAT8 0x000640
758 
759 /** CMR transmit statistics 9 */
760 #define BGX_CMR_TX_STAT9 0x000648
761 
762 /** CMR transmit statistics 10 */
763 #define BGX_CMR_TX_STAT10 0x000650
764 
765 /** CMR transmit statistics 11 */
766 #define BGX_CMR_TX_STAT11 0x000658
767 
768 /** CMR transmit statistics 12 */
769 #define BGX_CMR_TX_STAT12 0x000660
770 
771 /** CMR transmit statistics 13 */
772 #define BGX_CMR_TX_STAT13 0x000668
773 
774 /** CMR transmit statistics 14 */
775 #define BGX_CMR_TX_STAT14 0x000670
776 
777 /** CMR transmit statistics 15 */
778 #define BGX_CMR_TX_STAT15 0x000678
779 
780 /** CMR transmit statistics 16 */
781 #define BGX_CMR_TX_STAT16 0x000680
782 
783 /** CMR transmit statistics 17 */
784 #define BGX_CMR_TX_STAT17 0x000688
785 
786 /** CMR receive logical MACs */
787 #define BGX_CMR_RX_LMACS 0x000468
788 #define BGX_CMR_RX_LMACS_LMACS_GET(lmacs) \
789  ( ( (lmacs) >> 0 ) & 0x7 )
790 #define BGX_CMR_RX_LMACS_LMACS_SET(ct) ( ( ( uint64_t ) (ct) ) << 0 )
791 
792 /** CMR transmit logical MACs */
793 #define BGX_CMR_TX_LMACS 0x001000
794 #define BGX_CMR_TX_LMACS_LMACS_GET(lmacs) \
795  ( ( (lmacs) >> 0 ) & 0x7 )
796 #define BGX_CMR_TX_LMACS_LMACS_SET(ct) ( ( ( uint64_t ) (ct) ) << 0 )
797 
798 /** SPU control 1 */
799 #define BGX_SPU_CONTROL1 0x010000
800 #define BGX_SPU_CONTROL1_RESET ( 1ULL << 15 )
801 #define BGX_SPU_CONTROL1_LO_PWR ( 1ULL << 11 )
802 
803 /** SPU reset delay */
804 #define BGX_SPU_RESET_DELAY_MS 10
805 
806 /** SPU status 1 */
807 #define BGX_SPU_STATUS1 0x010008
808 #define BGX_SPU_STATUS1_FLT ( 1ULL << 7 )
809 #define BGX_SPU_STATUS1_RCV_LNK ( 1ULL << 2 )
810 
811 /** SPU status 2 */
812 #define BGX_SPU_STATUS2 0x010020
813 #define BGX_SPU_STATUS2_RCVFLT ( 1ULL << 10 )
814 
815 /** SPU BASE-R status 1 */
816 #define BGX_SPU_BR_STATUS1 0x010030
817 #define BGX_SPU_BR_STATUS1_RCV_LNK ( 1ULL << 12 )
818 #define BGX_SPU_BR_STATUS1_HI_BER ( 1ULL << 1 )
819 #define BGX_SPU_BR_STATUS1_BLK_LOCK ( 1ULL << 0 )
820 
821 /** SPU BASE-R status 2 */
822 #define BGX_SPU_BR_STATUS2 0x010038
823 #define BGX_SPU_BR_STATUS2_LATCHED_LOCK ( 1ULL << 15 )
824 #define BGX_SPU_BR_STATUS2_LATCHED_BER ( 1ULL << 14 )
825 
826 /** SPU BASE-R alignment status */
827 #define BGX_SPU_BR_ALGN_STATUS 0x010050
828 #define BGX_SPU_BR_ALGN_STATUS_ALIGND ( 1ULL << 12 )
829 
830 /** SPU BASE-R link training control */
831 #define BGX_SPU_BR_PMD_CONTROL 0x010068
832 #define BGX_SPU_BR_PMD_CONTROL_TRAIN_EN ( 1ULL << 1 )
833 
834 /** SPU BASE-R link training status */
835 #define BGX_SPU_BR_PMD_STATUS 0x010070
836 
837 /** SPU link partner coefficient update */
838 #define BGX_SPU_BR_PMD_LP_CUP 0x010078
839 
840 /** SPU local device coefficient update */
841 #define BGX_SPU_BR_PMD_LD_CUP 0x010088
842 
843 /** SPU local device status report */
844 #define BGX_SPU_BR_PMD_LD_REP 0x010090
845 
846 /** SPU forward error correction control */
847 #define BGX_SPU_FEC_CONTROL 0x0100a0
848 
849 /** SPU autonegotation control */
850 #define BGX_SPU_AN_CONTROL 0x0100c8
851 
852 /** SPU autonegotiation status */
853 #define BGX_SPU_AN_STATUS 0x0100d0
854 #define BGX_SPU_AN_STATUS_XNP_STAT ( 1ULL << 7 )
855 #define BGX_SPU_AN_STATUS_PAGE_RX ( 1ULL << 6 )
856 #define BGX_SPU_AN_STATUS_AN_COMPLETE ( 1ULL << 5 )
857 #define BGX_SPU_AN_STATUS_LINK_STATUS ( 1ULL << 2 )
858 #define BGX_SPU_AN_STATUS_LP_AN_ABLE ( 1ULL << 0 )
859 
860 /** SPU interrupt */
861 #define BGX_SPU_INT 0x010220
862 #define BGX_SPU_INT_TRAINING_FAIL ( 1ULL << 14 )
863 #define BGX_SPU_INT_TRAINING_DONE ( 1ULL << 13 )
864 #define BGX_SPU_INT_AN_COMPLETE ( 1ULL << 12 )
865 #define BGX_SPU_INT_AN_LINK_GOOD ( 1ULL << 11 )
866 #define BGX_SPU_INT_AN_PAGE_RX ( 1ULL << 10 )
867 #define BGX_SPU_INT_FEC_UNCORR ( 1ULL << 9 )
868 #define BGX_SPU_INT_FEC_CORR ( 1ULL << 8 )
869 #define BGX_SPU_INT_BIP_ERR ( 1ULL << 7 )
870 #define BGX_SPU_INT_DBG_SYNC ( 1ULL << 6 )
871 #define BGX_SPU_INT_ALGNLOS ( 1ULL << 5 )
872 #define BGX_SPU_INT_SYNLOS ( 1ULL << 4 )
873 #define BGX_SPU_INT_BITLCKLS ( 1ULL << 3 )
874 #define BGX_SPU_INT_ERR_BLK ( 1ULL << 2 )
875 #define BGX_SPU_INT_RX_LINK_DOWN ( 1ULL << 1 )
876 #define BGX_SPU_INT_RX_LINK_UP ( 1ULL << 0 )
877 
878 /** LMAC types */
880  TXNIC_LMAC_SGMII = 0x0, /**< SGMII/1000BASE-X */
881  TXNIC_LMAC_XAUI = 0x1, /**< 10GBASE-X/XAUI or DXAUI */
882  TXNIC_LMAC_RXAUI = 0x2, /**< Reduced XAUI */
883  TXNIC_LMAC_10G_R = 0x3, /**< 10GBASE-R */
884  TXNIC_LMAC_40G_R = 0x4, /**< 40GBASE-R */
885 };
886 
887 /** An LMAC type */
889  /** Name */
890  const char *name;
891  /** Number of LMACs */
893  /** Lane-to-SDS mapping */
895 };
896 
897 /** An LMAC address */
899  struct {
902  } __attribute__ (( packed ));
904 };
905 
906 /** A Logical MAC (LMAC) */
907 struct txnic_lmac {
908  /** Registers */
909  void *regs;
910  /** Containing BGX Ethernet interface */
911  struct txnic_bgx *bgx;
912  /** Virtual NIC index */
913  unsigned int idx;
914 
915  /** MAC address */
917 
918  /** Virtual NIC (if applicable) */
919  struct txnic *vnic;
920 };
921 
922 /** A BGX Ethernet interface */
923 struct txnic_bgx {
924  /** Registers */
925  void *regs;
926  /** PCI device */
927  struct pci_device *pci;
928  /** Node ID */
929  unsigned int node;
930  /** BGX index */
931  unsigned int idx;
932 
933  /** LMAC type */
935  /** Number of LMACs */
936  unsigned int count;
937  /** Link training is in use */
938  int training;
939 
940  /** List of BGX Ethernet interfaces */
941  struct list_head list;
942  /** Physical function (if known) */
943  struct txnic_pf *pf;
944 
945  /** Logical MACs */
947 };
948 
949 #endif /* _THUNDERX_H */
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned int idx
BGX index.
Definition: thunderx.h:931
#define __attribute__(x)
Definition: compiler.h:10
uint8_t cqe_type
Type.
Definition: thunderx.h:351
A receive completion queue entry.
Definition: thunderx.h:345
struct txnic * vnic
Virtual NIC (if applicable)
Definition: thunderx.h:919
unsigned short uint16_t
Definition: stdint.h:11
40GBASE-R
Definition: thunderx.h:884
uint16_t sqe_ptr
Send queue entry pointer.
Definition: thunderx.h:336
A physical function.
Definition: thunderx.h:579
uint8_t flags
Flags.
Definition: thunderx.h:118
An LMAC address.
Definition: thunderx.h:898
unsigned int count
Number of LMACs.
Definition: thunderx.h:936
10GBASE-R
Definition: thunderx.h:883
uint8_t unused[4]
Unused.
Definition: thunderx.h:334
uint8_t unused_b[1]
Unused.
Definition: thunderx.h:353
uint8_t unused_c[4]
Unused.
Definition: thunderx.h:357
const char * name
Device name (for debugging)
Definition: thunderx.h:421
A Logical MAC (LMAC)
Definition: thunderx.h:907
A receive buffer descriptor ring entry.
Definition: thunderx.h:236
uint16_t size
Size.
Definition: thunderx.h:132
uint8_t unused_a[6]
Unused.
Definition: thunderx.h:349
#define TXNIC_NUM_BGX
Maximum number of BGX Ethernet interfaces (per node)
Definition: thunderx.h:37
A receive queue.
Definition: thunderx.h:277
uint8_t unused_a[7]
Unused.
Definition: thunderx.h:371
unsigned long long uint64_t
Definition: stdint.h:13
uint8_t errop
Error opcode.
Definition: thunderx.h:347
uint8_t flags
Flags.
Definition: thunderx.h:136
uint8_t unused_a[2]
Unused.
Definition: thunderx.h:114
unsigned long vf_stride
Virtual function BAR stride.
Definition: thunderx.h:590
struct txnic_rbdr_entry rbdre
Receive buffer descriptor ring entry.
Definition: thunderx.h:244
struct txnic_sq sq
Send queue.
Definition: thunderx.h:426
uint8_t send_status
Status.
Definition: thunderx.h:332
unsigned int cons
Consumer counter.
Definition: thunderx.h:281
unsigned int prod
Producer counter.
Definition: thunderx.h:279
Access to external ("user") memory.
uint32_t lane_to_sds
Lane-to-SDS mapping.
Definition: thunderx.h:894
A doubly-linked list entry (or list head)
Definition: list.h:18
void * regs
Registers.
Definition: thunderx.h:909
uint8_t cqe_type
Type.
Definition: thunderx.h:338
Completion queue entry common fields.
Definition: thunderx.h:369
An LMAC type.
Definition: thunderx.h:888
struct txnic_pf * pf
Physical function (if known)
Definition: thunderx.h:943
A receive queue entry.
Definition: thunderx.h:242
A send queue entry.
Definition: thunderx.h:152
unsigned int cons
Consumer counter.
Definition: thunderx.h:189
uint64_t addr
Address.
Definition: thunderx.h:138
unsigned int node
Node ID.
Definition: thunderx.h:929
struct pci_device * pci
PCI device.
Definition: thunderx.h:927
uint8_t unused_b[8]
Unused.
Definition: thunderx.h:120
unsigned int cons
Consumer counter.
Definition: thunderx.h:404
struct txnic_rq rq
Receive queue.
Definition: thunderx.h:428
Linked lists.
A send completion queue entry.
Definition: thunderx.h:330
struct list_head list
List of physical functions.
Definition: thunderx.h:593
void * regs
Registers.
Definition: thunderx.h:925
const char * name
Name.
Definition: thunderx.h:890
A send queue.
Definition: thunderx.h:185
A PCI device.
Definition: pci.h:187
A completion queue.
Definition: thunderx.h:402
struct txnic_bgx * bgx[TXNIC_NUM_BGX]
BGX Ethernet interfaces (if known)
Definition: thunderx.h:595
A virtual NIC.
Definition: thunderx.h:417
A network device.
Definition: netdevice.h:348
A send header subdescriptor.
Definition: thunderx.h:110
u32 addr
Definition: sky2.h:8
unsigned char uint8_t
Definition: stdint.h:10
userptr_t cqe
Completion queue entries.
Definition: thunderx.h:406
#define TXNIC_RQ_FILL
Receive queue maximum fill level.
Definition: thunderx.h:257
#define ETH_ALEN
Definition: if_ether.h:8
uint8_t raw[ETH_ALEN]
Definition: thunderx.h:901
A BGX Ethernet interface.
Definition: thunderx.h:923
unsigned int uint32_t
Definition: stdint.h:12
userptr_t sqe
Send queue entries.
Definition: thunderx.h:191
struct txnic_lmac_type * type
LMAC type.
Definition: thunderx.h:934
struct io_buffer * iobuf[TXNIC_RQ_FILL]
I/O buffers.
Definition: thunderx.h:285
txnic_lmac_types
LMAC types.
Definition: thunderx.h:879
struct txnic_send_header hdr
Send header descriptor.
Definition: thunderx.h:154
static unsigned int txnic_address_node(uint64_t addr)
Calculate node ID.
Definition: thunderx.h:54
void * regs
Registers.
Definition: thunderx.h:419
struct txnic_cqe_common common
Common fields.
Definition: thunderx.h:379
uint8_t unused[5]
Unused.
Definition: thunderx.h:134
A send gather subdescriptor.
Definition: thunderx.h:130
uint8_t count
Number of LMACs.
Definition: thunderx.h:892
10GBASE-X/XAUI or DXAUI
Definition: thunderx.h:881
Network device management.
struct txnic_lmac lmac[TXNIC_NUM_LMAC]
Logical MACs.
Definition: thunderx.h:946
unsigned int node
Node ID.
Definition: thunderx.h:585
uint8_t apad
Padding.
Definition: thunderx.h:355
uint8_t subdcnt
Subdescriptor count.
Definition: thunderx.h:116
struct txnic_send_gather gather
Send gather descriptor.
Definition: thunderx.h:156
unsigned long vf_membase
Virtual function BAR base.
Definition: thunderx.h:588
void * regs
Registers.
Definition: thunderx.h:581
struct pci_device * pci
PCI device.
Definition: thunderx.h:583
userptr_t rqe
Receive queue entries.
Definition: thunderx.h:283
uint8_t cqe_type
Type.
Definition: thunderx.h:373
uint16_t len
Length.
Definition: thunderx.h:359
struct txnic_cqe_send send
Send completion.
Definition: thunderx.h:381
SGMII/1000BASE-X.
Definition: thunderx.h:880
uint32_t total
Total length.
Definition: thunderx.h:112
unsigned int idx
Virtual NIC index.
Definition: thunderx.h:913
uint64_t addr
Address.
Definition: thunderx.h:238
#define TXNIC_NUM_LMAC
Maximum number of Logical MACs (per BGX)
Definition: thunderx.h:40
struct net_device * netdev
Network device.
Definition: thunderx.h:423
int training
Link training is in use.
Definition: thunderx.h:938
struct list_head list
List of BGX Ethernet interfaces.
Definition: thunderx.h:941
struct txnic_cq cq
Completion queue.
Definition: thunderx.h:430
A completion queue entry.
Definition: thunderx.h:377
unsigned int prod
Producer counter.
Definition: thunderx.h:187
union txnic_lmac_address mac
MAC address.
Definition: thunderx.h:916
struct txnic_bgx * bgx
Containing BGX Ethernet interface.
Definition: thunderx.h:911
Reduced XAUI.
Definition: thunderx.h:882
unsigned long userptr_t
A pointer to a user buffer.
Definition: uaccess.h:33
uint8_t pad[2]
Definition: thunderx.h:900
struct txnic_cqe_rx rx
Receive completion.
Definition: thunderx.h:383
A persistent I/O buffer.
Definition: iobuf.h:32
static unsigned int txnic_address_bgx(uint64_t addr)
Calculate BGX Ethernet interface index.
Definition: thunderx.h:66