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| #define | VMXNET3_MAX_TX_QUEUES 8 |
| | Maximum number of TX queues. More...
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| #define | VMXNET3_MAX_RX_QUEUES 16 |
| | Maximum number of RX queues. More...
|
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| #define | VMXNET3_MAX_INTRS 25 |
| | Maximum number of interrupts. More...
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| #define | VMXNET3_MAX_PACKET_LEN 0x4000 |
| | Maximum packet size. More...
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| #define | VMXNET3_PT_BAR PCI_BASE_ADDRESS_0 |
| | "PT" PCI BAR address More...
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| |
| #define | VMXNET3_PT_LEN 0x1000 |
| | "PT" PCI BAR size More...
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| #define | VMXNET3_PT_IMR 0x0 |
| | Interrupt Mask Register. More...
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| #define | VMXNET3_PT_TXPROD 0x600 |
| | Transmit producer index. More...
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| #define | VMXNET3_PT_RXPROD 0x800 |
| | Rx producer index for ring 1. More...
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| |
| #define | VMXNET3_PT_RXPROD2 0xa00 |
| | Rx producer index for ring 2. More...
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| |
| #define | VMXNET3_VD_BAR PCI_BASE_ADDRESS_1 |
| | "VD" PCI BAR address More...
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| |
| #define | VMXNET3_VD_LEN 0x1000 |
| | "VD" PCI BAR size More...
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| |
| #define | VMXNET3_VD_VRRS 0x0 |
| | vmxnet3 Revision Report Selection More...
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| |
| #define | VMXNET3_VD_UVRS 0x8 |
| | UPT Version Report Selection. More...
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| |
| #define | VMXNET3_VD_DSAL 0x10 |
| | Driver Shared Address Low. More...
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| |
| #define | VMXNET3_VD_DSAH 0x18 |
| | Driver Shared Address High. More...
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| |
| #define | VMXNET3_VD_CMD 0x20 |
| | Command. More...
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| |
| #define | VMXNET3_VD_MACL 0x28 |
| | MAC Address Low. More...
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| |
| #define | VMXNET3_VD_MACH 0x30 |
| | MAC Address High. More...
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| |
| #define | VMXNET3_VD_ICR 0x38 |
| | Interrupt Cause Register. More...
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| |
| #define | VMXNET3_VD_ECR 0x40 |
| | Event Cause Register. More...
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| |
| #define | VMXNET3_VERSION_MAGIC 0x69505845 |
| | Driver version magic. More...
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| |
| #define | VMXNET3_IC_DISABLE_ALL 0x1 |
| | Interrupt control - disable all interrupts. More...
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| |
| #define | VMXNET3_SHARED_ALIGN 8 |
| | Alignment of driver shared area. More...
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| |
| #define | VMXNET3_SHARED_MAGIC 0xbabefee1 |
| | Driver shared area magic. More...
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| |
| #define | VMXNET3_TXF_GEN 0x00004000UL |
| | Transmit generation flag. More...
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| |
| #define | VMXNET3_TXF_EOP 0x000001000UL |
| | Transmit end-of-packet flag. More...
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| |
| #define | VMXNET3_TXF_CQ 0x000002000UL |
| | Transmit completion request flag. More...
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| |
| #define | VMXNET3_TXCF_GEN 0x80000000UL |
| | Transmit completion generation flag. More...
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| |
| #define | VMXNET3_RXF_GEN 0x80000000UL |
| | Receive generation flag. More...
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| |
| #define | VMXNET3_RXCF_GEN 0x80000000UL |
| | Receive completion generation flag. More...
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| |
| #define | VMXNET3_QUEUES_ALIGN 128 |
| | Alignment of queue descriptor set. More...
|
| |
| #define | VMXNET3_RING_ALIGN 512 |
| | Alignment of rings. More...
|
| |
| #define | VMXNET3_NUM_TX_DESC 32 |
| | Number of TX descriptors. More...
|
| |
| #define | VMXNET3_NUM_TX_COMP 32 |
| | Number of TX completion descriptors. More...
|
| |
| #define | VMXNET3_NUM_RX_DESC 32 |
| | Number of RX descriptors. More...
|
| |
| #define | VMXNET3_NUM_RX_COMP 32 |
| | Number of RX completion descriptors. More...
|
| |
| #define | VMXNET3_DMA_ALIGN 512 |
| | DMA area alignment. More...
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| |
| #define | VMXNET3_VERSION_SELECT 1 |
| | vmxnet3 version that we support More...
|
| |
| #define | VMXNET3_UPT_VERSION_SELECT 1 |
| | UPT version that we support. More...
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| |
| #define | VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ ) |
| | MTU size. More...
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| |
| #define | VMXNET3_TX_FILL ( VMXNET3_NUM_TX_DESC - 1 ) |
| | Transmit ring maximum fill level. More...
|
| |
| #define | VMXNET3_RX_FILL 8 |
| | Receive ring maximum fill level. More...
|
| |
| #define | NET_IP_ALIGN 2 |
| | Received packet alignment padding. More...
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| |
