iPXE
efx_common.c
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00001 /**************************************************************************
00002  *
00003  * Driver datapath common code for Solarflare network cards
00004  *
00005  * Written by Shradha Shah <sshah@solarflare.com>
00006  *
00007  * Copyright Fen Systems Ltd. 2005
00008  * Copyright Level 5 Networks Inc. 2005
00009  * Copyright 2006-2017 Solarflare Communications Inc.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License as
00013  * published by the Free Software Foundation; either version 2 of the
00014  * License, or any later version.
00015  *
00016  * You can also choose to distribute this program under the terms of
00017  * the Unmodified Binary Distribution Licence (as given in the file
00018  * COPYING.UBDL), provided that you have satisfied its requirements.
00019  *
00020  ***************************************************************************/
00021 #include <stdint.h>
00022 #include <stdlib.h>
00023 #include <stdio.h>
00024 #include <unistd.h>
00025 #include <errno.h>
00026 #include <assert.h>
00027 #include <byteswap.h>
00028 #include <ipxe/io.h>
00029 #include <ipxe/pci.h>
00030 #include <ipxe/malloc.h>
00031 #include <ipxe/iobuf.h>
00032 #include <ipxe/netdevice.h>
00033 #include "efx_common.h"
00034 #include "efx_bitfield.h"
00035 #include "mc_driver_pcol.h"
00036 
00037 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00038 
00039 /*******************************************************************************
00040  *
00041  *
00042  * Low-level hardware access
00043  *
00044  *
00045  ******************************************************************************/
00046 
00047 void
00048 efx_writel(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
00049 {
00050         DBGCIO(efx, "Writing partial register %x with " EFX_DWORD_FMT "\n",
00051                reg, EFX_DWORD_VAL(*value));
00052         _efx_writel(efx, value->u32[0], reg);
00053 }
00054 
00055 void
00056 efx_readl(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
00057 {
00058         value->u32[0] = _efx_readl(efx, reg);
00059         DBGCIO(efx, "Read from register %x, got " EFX_DWORD_FMT "\n",
00060                reg, EFX_DWORD_VAL(*value));
00061 }
00062 
00063 /*******************************************************************************
00064  *
00065  *
00066  * Inititialization and Close
00067  *
00068  *
00069  ******************************************************************************/
00070 void efx_probe(struct net_device *netdev, enum efx_revision revision)
00071 {
00072         struct efx_nic *efx = netdev_priv(netdev);
00073         struct pci_device *pci = container_of(netdev->dev,
00074                                               struct pci_device, dev);
00075         unsigned int reg = PCI_BASE_ADDRESS_0;
00076         uint32_t bar_low;
00077 
00078         efx->netdev = netdev;
00079         efx->revision = revision;
00080 
00081         /* Find the memory bar to use */
00082         pci_read_config_dword(pci, reg, &bar_low);
00083         if ((bar_low & PCI_BASE_ADDRESS_IO_MASK) == PCI_BASE_ADDRESS_SPACE_IO)
00084                 reg = PCI_BASE_ADDRESS_2;
00085 
00086         efx->mmio_start = pci_bar_start(pci, reg);
00087         efx->mmio_len = pci_bar_size(pci, reg);
00088         efx->membase = ioremap(efx->mmio_start, efx->mmio_len);
00089 
00090         DBGCP(efx, "BAR of %lx bytes at phys %lx mapped at %p\n",
00091               efx->mmio_len, efx->mmio_start, efx->membase);
00092 
00093         /* Enable PCI access */
00094         adjust_pci_device(pci);
00095 }
00096 
00097 void efx_remove(struct net_device *netdev)
00098 {
00099         struct efx_nic *efx = netdev_priv(netdev);
00100 
00101         iounmap(efx->membase);
00102         efx->membase = NULL;
00103 }