iPXE
mac.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef MAC_H
00021 #define MAC_H
00022 
00023 FILE_LICENCE ( BSD2 );
00024 
00025 #include <unistd.h>
00026 
00027 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ?          \
00028                                 MS(ads->ds_rxstatus0, AR_RxRate) :      \
00029                                 (ads->ds_rxstatus3 >> 2) & 0xFF)
00030 
00031 #define set11nTries(_series, _index) \
00032         (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
00033 
00034 #define set11nRate(_series, _index) \
00035         (SM((_series)[_index].Rate, AR_XmitRate##_index))
00036 
00037 #define set11nPktDurRTSCTS(_series, _index)                             \
00038         (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |      \
00039          ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS   ?    \
00040           AR_RTSCTSQual##_index : 0))
00041 
00042 #define set11nRateFlags(_series, _index)                                \
00043         (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ?         \
00044           AR_2040_##_index : 0)                                         \
00045          |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ?      \
00046            AR_GI##_index : 0)                                           \
00047          |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ?        \
00048            AR_STBC##_index : 0)                                         \
00049          |SM((_series)[_index].ChSel, AR_ChainSel##_index))
00050 
00051 #define CCK_SIFS_TIME        10
00052 #define CCK_PREAMBLE_BITS   144
00053 #define CCK_PLCP_BITS        48
00054 
00055 #define OFDM_SIFS_TIME        16
00056 #define OFDM_PREAMBLE_TIME    20
00057 #define OFDM_PLCP_BITS        22
00058 #define OFDM_SYMBOL_TIME      4
00059 
00060 #define OFDM_SIFS_TIME_HALF     32
00061 #define OFDM_PREAMBLE_TIME_HALF 40
00062 #define OFDM_PLCP_BITS_HALF     22
00063 #define OFDM_SYMBOL_TIME_HALF   8
00064 
00065 #define OFDM_SIFS_TIME_QUARTER      64
00066 #define OFDM_PREAMBLE_TIME_QUARTER  80
00067 #define OFDM_PLCP_BITS_QUARTER      22
00068 #define OFDM_SYMBOL_TIME_QUARTER    16
00069 
00070 #define INIT_AIFS       2
00071 #define INIT_CWMIN      15
00072 #define INIT_CWMIN_11B  31
00073 #define INIT_CWMAX      1023
00074 #define INIT_SH_RETRY   10
00075 #define INIT_LG_RETRY   10
00076 #define INIT_SSH_RETRY  32
00077 #define INIT_SLG_RETRY  32
00078 
00079 #define ATH9K_SLOT_TIME_6 6
00080 #define ATH9K_SLOT_TIME_9 9
00081 #define ATH9K_SLOT_TIME_20 20
00082 
00083 #define ATH9K_TXERR_XRETRY         0x01
00084 #define ATH9K_TXERR_FILT           0x02
00085 #define ATH9K_TXERR_FIFO           0x04
00086 #define ATH9K_TXERR_XTXOP          0x08
00087 #define ATH9K_TXERR_TIMER_EXPIRED  0x10
00088 #define ATH9K_TX_ACKED             0x20
00089 #define ATH9K_TXERR_MASK                                                \
00090         (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO |     \
00091          ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
00092 
00093 #define ATH9K_TX_BA                0x01
00094 #define ATH9K_TX_PWRMGMT           0x02
00095 #define ATH9K_TX_DESC_CFG_ERR      0x04
00096 #define ATH9K_TX_DATA_UNDERRUN     0x08
00097 #define ATH9K_TX_DELIM_UNDERRUN    0x10
00098 #define ATH9K_TX_SW_FILTERED       0x80
00099 
00100 /* 64 bytes */
00101 #define MIN_TX_FIFO_THRESHOLD   0x1
00102 
00103 /*
00104  * Single stream device AR9285 and AR9271 require 2 KB
00105  * to work around a hardware issue, all other devices
00106  * have can use the max 4 KB limit.
00107  */
00108 #define MAX_TX_FIFO_THRESHOLD   ((4096 / 64) - 1)
00109 
00110 struct ath_tx_status {
00111         u32 ts_tstamp;
00112         u16 ts_seqnum;
00113         u8 ts_status;
00114         u8 ts_rateindex;
00115         int8_t ts_rssi;
00116         u8 ts_shortretry;
00117         u8 ts_longretry;
00118         u8 ts_virtcol;
00119         u8 ts_flags;
00120         int8_t ts_rssi_ctl0;
00121         int8_t ts_rssi_ctl1;
00122         int8_t ts_rssi_ctl2;
00123         int8_t ts_rssi_ext0;
00124         int8_t ts_rssi_ext1;
00125         int8_t ts_rssi_ext2;
00126         u8 qid;
00127         u16 desc_id;
00128         u8 tid;
00129         u32 ba_low;
00130         u32 ba_high;
00131         u32 evm0;
00132         u32 evm1;
00133         u32 evm2;
00134 };
00135 
00136 struct ath_rx_status {
00137         u32 rs_tstamp;
00138         u16 rs_datalen;
00139         u8 rs_status;
00140         u8 rs_phyerr;
00141         int8_t rs_rssi;
00142         u8 rs_keyix;
00143         u8 rs_rate;
00144         u8 rs_antenna;
00145         u8 rs_more;
00146         int8_t rs_rssi_ctl0;
00147         int8_t rs_rssi_ctl1;
00148         int8_t rs_rssi_ctl2;
00149         int8_t rs_rssi_ext0;
00150         int8_t rs_rssi_ext1;
00151         int8_t rs_rssi_ext2;
00152         u8 rs_isaggr;
00153         u8 rs_moreaggr;
00154         u8 rs_num_delims;
00155         u8 rs_flags;
00156         u32 evm0;
00157         u32 evm1;
00158         u32 evm2;
00159         u32 evm3;
00160         u32 evm4;
00161 };
00162 
00163 struct ath_htc_rx_status {
00164         uint64_t rs_tstamp;
00165         uint16_t rs_datalen;
00166         u8 rs_status;
00167         u8 rs_phyerr;
00168         int8_t rs_rssi;
00169         int8_t rs_rssi_ctl0;
00170         int8_t rs_rssi_ctl1;
00171         int8_t rs_rssi_ctl2;
00172         int8_t rs_rssi_ext0;
00173         int8_t rs_rssi_ext1;
00174         int8_t rs_rssi_ext2;
00175         u8 rs_keyix;
00176         u8 rs_rate;
00177         u8 rs_antenna;
00178         u8 rs_more;
00179         u8 rs_isaggr;
00180         u8 rs_moreaggr;
00181         u8 rs_num_delims;
00182         u8 rs_flags;
00183         u8 rs_dummy;
00184         uint32_t evm0;
00185         uint32_t evm1;
00186         uint32_t evm2;
00187 };
00188 
00189 #define ATH9K_RXERR_CRC           0x01
00190 #define ATH9K_RXERR_PHY           0x02
00191 #define ATH9K_RXERR_FIFO          0x04
00192 #define ATH9K_RXERR_DECRYPT       0x08
00193 #define ATH9K_RXERR_MIC           0x10
00194 
00195 #define ATH9K_RX_MORE             0x01
00196 #define ATH9K_RX_MORE_AGGR        0x02
00197 #define ATH9K_RX_GI               0x04
00198 #define ATH9K_RX_2040             0x08
00199 #define ATH9K_RX_DELIM_CRC_PRE    0x10
00200 #define ATH9K_RX_DELIM_CRC_POST   0x20
00201 #define ATH9K_RX_DECRYPT_BUSY     0x40
00202 
00203 #define ATH9K_RXKEYIX_INVALID   ((u8)-1)
00204 #define ATH9K_TXKEYIX_INVALID   ((u32)-1)
00205 
00206 enum ath9k_phyerr {
00207         ATH9K_PHYERR_UNDERRUN             = 0,  /* Transmit underrun */
00208         ATH9K_PHYERR_TIMING               = 1,  /* Timing error */
00209         ATH9K_PHYERR_PARITY               = 2,  /* Illegal parity */
00210         ATH9K_PHYERR_RATE                 = 3,  /* Illegal rate */
00211         ATH9K_PHYERR_LENGTH               = 4,  /* Illegal length */
00212         ATH9K_PHYERR_RADAR                = 5,  /* Radar detect */
00213         ATH9K_PHYERR_SERVICE              = 6,  /* Illegal service */
00214         ATH9K_PHYERR_TOR                  = 7,  /* Transmit override receive */
00215 
00216         ATH9K_PHYERR_OFDM_TIMING          = 17,
00217         ATH9K_PHYERR_OFDM_SIGNAL_PARITY   = 18,
00218         ATH9K_PHYERR_OFDM_RATE_ILLEGAL    = 19,
00219         ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL  = 20,
00220         ATH9K_PHYERR_OFDM_POWER_DROP      = 21,
00221         ATH9K_PHYERR_OFDM_SERVICE         = 22,
00222         ATH9K_PHYERR_OFDM_RESTART         = 23,
00223         ATH9K_PHYERR_FALSE_RADAR_EXT      = 24,
00224 
00225         ATH9K_PHYERR_CCK_TIMING           = 25,
00226         ATH9K_PHYERR_CCK_HEADER_CRC       = 26,
00227         ATH9K_PHYERR_CCK_RATE_ILLEGAL     = 27,
00228         ATH9K_PHYERR_CCK_SERVICE          = 30,
00229         ATH9K_PHYERR_CCK_RESTART          = 31,
00230         ATH9K_PHYERR_CCK_LENGTH_ILLEGAL   = 32,
00231         ATH9K_PHYERR_CCK_POWER_DROP       = 33,
00232 
00233         ATH9K_PHYERR_HT_CRC_ERROR         = 34,
00234         ATH9K_PHYERR_HT_LENGTH_ILLEGAL    = 35,
00235         ATH9K_PHYERR_HT_RATE_ILLEGAL      = 36,
00236 
00237         ATH9K_PHYERR_MAX                  = 37,
00238 };
00239 
00240 struct ath_desc {
00241         u32 ds_link;
00242         u32 ds_data;
00243         u32 ds_ctl0;
00244         u32 ds_ctl1;
00245         u32 ds_hw[20];
00246 //      void *ds_vdata;
00247 } __attribute__((packed, aligned(4)));
00248 
00249 #define ATH9K_TXDESC_NOACK              0x0002
00250 #define ATH9K_TXDESC_RTSENA             0x0004
00251 #define ATH9K_TXDESC_CTSENA             0x0008
00252 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
00253  * the descriptor its marked on.  We take a tx interrupt to reap
00254  * descriptors when the h/w hits an EOL condition or
00255  * when the descriptor is specifically marked to generate
00256  * an interrupt with this flag. Descriptors should be
00257  * marked periodically to insure timely replenishing of the
00258  * supply needed for sending frames. Defering interrupts
00259  * reduces system load and potentially allows more concurrent
00260  * work to be done but if done to aggressively can cause
00261  * senders to backup. When the hardware queue is left too
00262  * large rate control information may also be too out of
00263  * date. An Alternative for this is TX interrupt mitigation
00264  * but this needs more testing. */
00265 #define ATH9K_TXDESC_INTREQ             0x0010
00266 #define ATH9K_TXDESC_VEOL               0x0020
00267 #define ATH9K_TXDESC_EXT_ONLY           0x0040
00268 #define ATH9K_TXDESC_EXT_AND_CTL        0x0080
00269 #define ATH9K_TXDESC_VMF                0x0100
00270 #define ATH9K_TXDESC_FRAG_IS_ON         0x0200
00271 #define ATH9K_TXDESC_LOWRXCHAIN         0x0400
00272 #define ATH9K_TXDESC_LDPC               0x00010000
00273 
00274 #define ATH9K_RXDESC_INTREQ             0x0020
00275 
00276 struct ar5416_desc {
00277         u32 ds_link;
00278         u32 ds_data;
00279         u32 ds_ctl0;
00280         u32 ds_ctl1;
00281         union {
00282                 struct {
00283                         u32 ctl2;
00284                         u32 ctl3;
00285                         u32 ctl4;
00286                         u32 ctl5;
00287                         u32 ctl6;
00288                         u32 ctl7;
00289                         u32 ctl8;
00290                         u32 ctl9;
00291                         u32 ctl10;
00292                         u32 ctl11;
00293                         u32 status0;
00294                         u32 status1;
00295                         u32 status2;
00296                         u32 status3;
00297                         u32 status4;
00298                         u32 status5;
00299                         u32 status6;
00300                         u32 status7;
00301                         u32 status8;
00302                         u32 status9;
00303                 } tx;
00304                 struct {
00305                         u32 status0;
00306                         u32 status1;
00307                         u32 status2;
00308                         u32 status3;
00309                         u32 status4;
00310                         u32 status5;
00311                         u32 status6;
00312                         u32 status7;
00313                         u32 status8;
00314                 } rx;
00315         } u;
00316 } __attribute__((packed, aligned(4)));
00317 
00318 #define AR5416DESC(_ds)         ((struct ar5416_desc *)(_ds))
00319 #define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
00320 
00321 #define ds_ctl2     u.tx.ctl2
00322 #define ds_ctl3     u.tx.ctl3
00323 #define ds_ctl4     u.tx.ctl4
00324 #define ds_ctl5     u.tx.ctl5
00325 #define ds_ctl6     u.tx.ctl6
00326 #define ds_ctl7     u.tx.ctl7
00327 #define ds_ctl8     u.tx.ctl8
00328 #define ds_ctl9     u.tx.ctl9
00329 #define ds_ctl10    u.tx.ctl10
00330 #define ds_ctl11    u.tx.ctl11
00331 
00332 #define ds_txstatus0    u.tx.status0
00333 #define ds_txstatus1    u.tx.status1
00334 #define ds_txstatus2    u.tx.status2
00335 #define ds_txstatus3    u.tx.status3
00336 #define ds_txstatus4    u.tx.status4
00337 #define ds_txstatus5    u.tx.status5
00338 #define ds_txstatus6    u.tx.status6
00339 #define ds_txstatus7    u.tx.status7
00340 #define ds_txstatus8    u.tx.status8
00341 #define ds_txstatus9    u.tx.status9
00342 
00343 #define ds_rxstatus0    u.rx.status0
00344 #define ds_rxstatus1    u.rx.status1
00345 #define ds_rxstatus2    u.rx.status2
00346 #define ds_rxstatus3    u.rx.status3
00347 #define ds_rxstatus4    u.rx.status4
00348 #define ds_rxstatus5    u.rx.status5
00349 #define ds_rxstatus6    u.rx.status6
00350 #define ds_rxstatus7    u.rx.status7
00351 #define ds_rxstatus8    u.rx.status8
00352 
00353 #define AR_FrameLen         0x00000fff
00354 #define AR_VirtMoreFrag     0x00001000
00355 #define AR_TxCtlRsvd00      0x0000e000
00356 #define AR_XmitPower        0x003f0000
00357 #define AR_XmitPower_S      16
00358 #define AR_RTSEnable        0x00400000
00359 #define AR_VEOL             0x00800000
00360 #define AR_ClrDestMask      0x01000000
00361 #define AR_TxCtlRsvd01      0x1e000000
00362 #define AR_TxIntrReq        0x20000000
00363 #define AR_DestIdxValid     0x40000000
00364 #define AR_CTSEnable        0x80000000
00365 
00366 #define AR_TxMore           0x00001000
00367 #define AR_DestIdx          0x000fe000
00368 #define AR_DestIdx_S        13
00369 #define AR_FrameType        0x00f00000
00370 #define AR_FrameType_S      20
00371 #define AR_NoAck            0x01000000
00372 #define AR_InsertTS         0x02000000
00373 #define AR_CorruptFCS       0x04000000
00374 #define AR_ExtOnly          0x08000000
00375 #define AR_ExtAndCtl        0x10000000
00376 #define AR_MoreAggr         0x20000000
00377 #define AR_IsAggr           0x40000000
00378 
00379 #define AR_BurstDur         0x00007fff
00380 #define AR_BurstDur_S       0
00381 #define AR_DurUpdateEna     0x00008000
00382 #define AR_XmitDataTries0   0x000f0000
00383 #define AR_XmitDataTries0_S 16
00384 #define AR_XmitDataTries1   0x00f00000
00385 #define AR_XmitDataTries1_S 20
00386 #define AR_XmitDataTries2   0x0f000000
00387 #define AR_XmitDataTries2_S 24
00388 #define AR_XmitDataTries3   0xf0000000
00389 #define AR_XmitDataTries3_S 28
00390 
00391 #define AR_XmitRate0        0x000000ff
00392 #define AR_XmitRate0_S      0
00393 #define AR_XmitRate1        0x0000ff00
00394 #define AR_XmitRate1_S      8
00395 #define AR_XmitRate2        0x00ff0000
00396 #define AR_XmitRate2_S      16
00397 #define AR_XmitRate3        0xff000000
00398 #define AR_XmitRate3_S      24
00399 
00400 #define AR_PacketDur0       0x00007fff
00401 #define AR_PacketDur0_S     0
00402 #define AR_RTSCTSQual0      0x00008000
00403 #define AR_PacketDur1       0x7fff0000
00404 #define AR_PacketDur1_S     16
00405 #define AR_RTSCTSQual1      0x80000000
00406 
00407 #define AR_PacketDur2       0x00007fff
00408 #define AR_PacketDur2_S     0
00409 #define AR_RTSCTSQual2      0x00008000
00410 #define AR_PacketDur3       0x7fff0000
00411 #define AR_PacketDur3_S     16
00412 #define AR_RTSCTSQual3      0x80000000
00413 
00414 #define AR_AggrLen          0x0000ffff
00415 #define AR_AggrLen_S        0
00416 #define AR_TxCtlRsvd60      0x00030000
00417 #define AR_PadDelim         0x03fc0000
00418 #define AR_PadDelim_S       18
00419 #define AR_EncrType         0x0c000000
00420 #define AR_EncrType_S       26
00421 #define AR_TxCtlRsvd61      0xf0000000
00422 #define AR_LDPC             0x80000000
00423 
00424 #define AR_2040_0           0x00000001
00425 #define AR_GI0              0x00000002
00426 #define AR_ChainSel0        0x0000001c
00427 #define AR_ChainSel0_S      2
00428 #define AR_2040_1           0x00000020
00429 #define AR_GI1              0x00000040
00430 #define AR_ChainSel1        0x00000380
00431 #define AR_ChainSel1_S      7
00432 #define AR_2040_2           0x00000400
00433 #define AR_GI2              0x00000800
00434 #define AR_ChainSel2        0x00007000
00435 #define AR_ChainSel2_S      12
00436 #define AR_2040_3           0x00008000
00437 #define AR_GI3              0x00010000
00438 #define AR_ChainSel3        0x000e0000
00439 #define AR_ChainSel3_S      17
00440 #define AR_RTSCTSRate       0x0ff00000
00441 #define AR_RTSCTSRate_S     20
00442 #define AR_STBC0            0x10000000
00443 #define AR_STBC1            0x20000000
00444 #define AR_STBC2            0x40000000
00445 #define AR_STBC3            0x80000000
00446 
00447 #define AR_TxRSSIAnt00      0x000000ff
00448 #define AR_TxRSSIAnt00_S    0
00449 #define AR_TxRSSIAnt01      0x0000ff00
00450 #define AR_TxRSSIAnt01_S    8
00451 #define AR_TxRSSIAnt02      0x00ff0000
00452 #define AR_TxRSSIAnt02_S    16
00453 #define AR_TxStatusRsvd00   0x3f000000
00454 #define AR_TxBaStatus       0x40000000
00455 #define AR_TxStatusRsvd01   0x80000000
00456 
00457 /*
00458  * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
00459  * transmitted successfully. If clear, no ACK or BA was received to indicate
00460  * successful transmission when we were expecting an ACK or BA.
00461  */
00462 #define AR_FrmXmitOK            0x00000001
00463 #define AR_ExcessiveRetries     0x00000002
00464 #define AR_FIFOUnderrun         0x00000004
00465 #define AR_Filtered             0x00000008
00466 #define AR_RTSFailCnt           0x000000f0
00467 #define AR_RTSFailCnt_S         4
00468 #define AR_DataFailCnt          0x00000f00
00469 #define AR_DataFailCnt_S        8
00470 #define AR_VirtRetryCnt         0x0000f000
00471 #define AR_VirtRetryCnt_S       12
00472 #define AR_TxDelimUnderrun      0x00010000
00473 #define AR_TxDataUnderrun       0x00020000
00474 #define AR_DescCfgErr           0x00040000
00475 #define AR_TxTimerExpired       0x00080000
00476 #define AR_TxStatusRsvd10       0xfff00000
00477 
00478 #define AR_SendTimestamp    ds_txstatus2
00479 #define AR_BaBitmapLow      ds_txstatus3
00480 #define AR_BaBitmapHigh     ds_txstatus4
00481 
00482 #define AR_TxRSSIAnt10      0x000000ff
00483 #define AR_TxRSSIAnt10_S    0
00484 #define AR_TxRSSIAnt11      0x0000ff00
00485 #define AR_TxRSSIAnt11_S    8
00486 #define AR_TxRSSIAnt12      0x00ff0000
00487 #define AR_TxRSSIAnt12_S    16
00488 #define AR_TxRSSICombined   0xff000000
00489 #define AR_TxRSSICombined_S 24
00490 
00491 #define AR_TxTid        0xf0000000
00492 #define AR_TxTid_S      28
00493 
00494 #define AR_TxEVM0           ds_txstatus5
00495 #define AR_TxEVM1           ds_txstatus6
00496 #define AR_TxEVM2           ds_txstatus7
00497 
00498 #define AR_TxDone           0x00000001
00499 #define AR_SeqNum           0x00001ffe
00500 #define AR_SeqNum_S         1
00501 #define AR_TxStatusRsvd80   0x0001e000
00502 #define AR_TxOpExceeded     0x00020000
00503 #define AR_TxStatusRsvd81   0x001c0000
00504 #define AR_FinalTxIdx       0x00600000
00505 #define AR_FinalTxIdx_S     21
00506 #define AR_TxStatusRsvd82   0x01800000
00507 #define AR_PowerMgmt        0x02000000
00508 #define AR_TxStatusRsvd83   0xfc000000
00509 
00510 #define AR_RxCTLRsvd00  0xffffffff
00511 
00512 #define AR_RxCtlRsvd00  0x00001000
00513 #define AR_RxIntrReq    0x00002000
00514 #define AR_RxCtlRsvd01  0xffffc000
00515 
00516 #define AR_RxRSSIAnt00      0x000000ff
00517 #define AR_RxRSSIAnt00_S    0
00518 #define AR_RxRSSIAnt01      0x0000ff00
00519 #define AR_RxRSSIAnt01_S    8
00520 #define AR_RxRSSIAnt02      0x00ff0000
00521 #define AR_RxRSSIAnt02_S    16
00522 #define AR_RxRate           0xff000000
00523 #define AR_RxRate_S         24
00524 #define AR_RxStatusRsvd00   0xff000000
00525 
00526 #define AR_DataLen          0x00000fff
00527 #define AR_RxMore           0x00001000
00528 #define AR_NumDelim         0x003fc000
00529 #define AR_NumDelim_S       14
00530 #define AR_RxStatusRsvd10   0xff800000
00531 
00532 #define AR_RcvTimestamp     ds_rxstatus2
00533 
00534 #define AR_GI               0x00000001
00535 #define AR_2040             0x00000002
00536 #define AR_Parallel40       0x00000004
00537 #define AR_Parallel40_S     2
00538 #define AR_RxStatusRsvd30   0x000000f8
00539 #define AR_RxAntenna        0xffffff00
00540 #define AR_RxAntenna_S      8
00541 
00542 #define AR_RxRSSIAnt10            0x000000ff
00543 #define AR_RxRSSIAnt10_S          0
00544 #define AR_RxRSSIAnt11            0x0000ff00
00545 #define AR_RxRSSIAnt11_S          8
00546 #define AR_RxRSSIAnt12            0x00ff0000
00547 #define AR_RxRSSIAnt12_S          16
00548 #define AR_RxRSSICombined         0xff000000
00549 #define AR_RxRSSICombined_S       24
00550 
00551 #define AR_RxEVM0           ds_rxstatus4
00552 #define AR_RxEVM1           ds_rxstatus5
00553 #define AR_RxEVM2           ds_rxstatus6
00554 
00555 #define AR_RxDone           0x00000001
00556 #define AR_RxFrameOK        0x00000002
00557 #define AR_CRCErr           0x00000004
00558 #define AR_DecryptCRCErr    0x00000008
00559 #define AR_PHYErr           0x00000010
00560 #define AR_MichaelErr       0x00000020
00561 #define AR_PreDelimCRCErr   0x00000040
00562 #define AR_RxStatusRsvd70   0x00000080
00563 #define AR_RxKeyIdxValid    0x00000100
00564 #define AR_KeyIdx           0x0000fe00
00565 #define AR_KeyIdx_S         9
00566 #define AR_PHYErrCode       0x0000ff00
00567 #define AR_PHYErrCode_S     8
00568 #define AR_RxMoreAggr       0x00010000
00569 #define AR_RxAggr           0x00020000
00570 #define AR_PostDelimCRCErr  0x00040000
00571 #define AR_RxStatusRsvd71   0x3ff80000
00572 #define AR_DecryptBusyErr   0x40000000
00573 #define AR_KeyMiss          0x80000000
00574 
00575 enum ath9k_tx_queue {
00576         ATH9K_TX_QUEUE_INACTIVE = 0,
00577         ATH9K_TX_QUEUE_DATA,
00578 };
00579 
00580 #define ATH9K_NUM_TX_QUEUES 1
00581 
00582 /* Used as a queue subtype instead of a WMM AC */
00583 #define ATH9K_WME_UPSD  4
00584 
00585 enum ath9k_tx_queue_flags {
00586         TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
00587         TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
00588         TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
00589         TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
00590         TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
00591         TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
00592         TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
00593         TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
00594         TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
00595 };
00596 
00597 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
00598 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
00599 
00600 #define ATH9K_DECOMP_MASK_SIZE     128
00601 #define ATH9K_READY_TIME_LO_BOUND  50
00602 #define ATH9K_READY_TIME_HI_BOUND  96
00603 
00604 enum ath9k_pkt_type {
00605         ATH9K_PKT_TYPE_NORMAL = 0,
00606         ATH9K_PKT_TYPE_ATIM,
00607         ATH9K_PKT_TYPE_PSPOLL,
00608         ATH9K_PKT_TYPE_BEACON,
00609         ATH9K_PKT_TYPE_PROBE_RESP,
00610         ATH9K_PKT_TYPE_CHIRP,
00611         ATH9K_PKT_TYPE_GRP_POLL,
00612 };
00613 
00614 struct ath9k_tx_queue_info {
00615         u32 tqi_ver;
00616         enum ath9k_tx_queue tqi_type;
00617         int tqi_subtype;
00618         enum ath9k_tx_queue_flags tqi_qflags;
00619         u32 tqi_priority;
00620         u32 tqi_aifs;
00621         u32 tqi_cwmin;
00622         u32 tqi_cwmax;
00623         u16 tqi_shretry;
00624         u16 tqi_lgretry;
00625         u32 tqi_cbrPeriod;
00626         u32 tqi_cbrOverflowLimit;
00627         u32 tqi_burstTime;
00628         u32 tqi_readyTime;
00629         u32 tqi_physCompBuf;
00630         u32 tqi_intFlags;
00631 };
00632 
00633 enum ath9k_rx_filter {
00634         ATH9K_RX_FILTER_UCAST = 0x00000001,
00635         ATH9K_RX_FILTER_MCAST = 0x00000002,
00636         ATH9K_RX_FILTER_BCAST = 0x00000004,
00637         ATH9K_RX_FILTER_CONTROL = 0x00000008,
00638         ATH9K_RX_FILTER_BEACON = 0x00000010,
00639         ATH9K_RX_FILTER_PROM = 0x00000020,
00640         ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
00641         ATH9K_RX_FILTER_PHYERR = 0x00000100,
00642         ATH9K_RX_FILTER_MYBEACON = 0x00000200,
00643         ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
00644         ATH9K_RX_FILTER_COMP_BA = 0x00000800,
00645         ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
00646         ATH9K_RX_FILTER_PSPOLL = 0x00004000,
00647         ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
00648         ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
00649 };
00650 
00651 #define ATH9K_RATESERIES_RTS_CTS  0x0001
00652 #define ATH9K_RATESERIES_2040     0x0002
00653 #define ATH9K_RATESERIES_HALFGI   0x0004
00654 #define ATH9K_RATESERIES_STBC     0x0008
00655 
00656 struct ath9k_11n_rate_series {
00657         u32 Tries;
00658         u32 Rate;
00659         u32 PktDuration;
00660         u32 ChSel;
00661         u32 RateFlags;
00662 };
00663 
00664 enum ath9k_key_type {
00665         ATH9K_KEY_TYPE_CLEAR,
00666         ATH9K_KEY_TYPE_WEP,
00667         ATH9K_KEY_TYPE_AES,
00668         ATH9K_KEY_TYPE_TKIP,
00669 };
00670 
00671 struct ath_hw;
00672 struct ath9k_channel;
00673 
00674 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
00675 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
00676 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
00677 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
00678 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
00679 int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel);
00680 int ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
00681 void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
00682 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
00683 int ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
00684                             const struct ath9k_tx_queue_info *qinfo);
00685 int ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
00686                             struct ath9k_tx_queue_info *qinfo);
00687 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
00688                           const struct ath9k_tx_queue_info *qinfo);
00689 int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
00690 int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
00691 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
00692                         struct ath_rx_status *rs, u64 tsf);
00693 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
00694                           u32 size, u32 flags);
00695 int ath9k_hw_setrxabort(struct ath_hw *ah, int set);
00696 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
00697 void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning);
00698 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
00699 int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset);
00700 
00701 /* Interrupt Handling */
00702 int ath9k_hw_intrpend(struct ath_hw *ah);
00703 void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints);
00704 void ath9k_hw_enable_interrupts(struct ath_hw *ah);
00705 void ath9k_hw_disable_interrupts(struct ath_hw *ah);
00706 
00707 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
00708 
00709 #endif /* MAC_H */