iPXE
skge.h
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00001 /*
00002  * Definitions for the new Marvell Yukon / SysKonnect driver.
00003  */
00004 #ifndef _SKGE_H
00005 #define _SKGE_H
00006 
00007 FILE_LICENCE ( GPL2_ONLY );
00008 
00009 /* PCI config registers */
00010 #define PCI_DEV_REG1    0x40
00011 #define  PCI_PHY_COMA   0x8000000
00012 #define  PCI_VIO        0x2000000
00013 
00014 #define PCI_DEV_REG2    0x44
00015 #define  PCI_VPD_ROM_SZ 7L<<14  /* VPD ROM size 0=256, 1=512, ... */
00016 #define  PCI_REV_DESC   1<<2    /* Reverse Descriptor bytes */
00017 
00018 #define DRV_NAME                "skge"
00019 #define DRV_VERSION             "1.13"
00020 #define PFX                     DRV_NAME " "
00021 
00022 #define NUM_TX_DESC             8
00023 #define NUM_RX_DESC             8
00024 
00025 /* mdeck used a 16 byte alignment, but datasheet says 8 bytes is sufficient */
00026 #define SKGE_RING_ALIGN         8
00027 #define RX_BUF_SIZE             1536
00028 #define PHY_RETRIES             1000
00029 
00030 #define TX_RING_SIZE    ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )
00031 #define RX_RING_SIZE    ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )
00032 #define RING_SIZE       ( TX_RING_SIZE + RX_RING_SIZE )
00033 
00034 #define SKGE_REG_SIZE   0x4000
00035 
00036 #define SKGE_EEPROM_MAGIC       0x9933aabb
00037 
00038 /* Added for iPXE ------------------ */
00039 
00040 /* from ethtool.h */
00041 #define AUTONEG_DISABLE 0x00
00042 #define AUTONEG_ENABLE  0x01
00043 
00044 #define DUPLEX_HALF     0x00
00045 #define DUPLEX_FULL     0x01
00046 
00047 #define SPEED_10        10
00048 #define SPEED_100       100
00049 #define SPEED_1000      1000
00050 
00051 #define ADVERTISED_10baseT_Half         (1 << 0)
00052 #define ADVERTISED_10baseT_Full         (1 << 1)
00053 #define ADVERTISED_100baseT_Half        (1 << 2)
00054 #define ADVERTISED_100baseT_Full        (1 << 3)
00055 #define ADVERTISED_1000baseT_Half       (1 << 4)
00056 #define ADVERTISED_1000baseT_Full       (1 << 5)
00057 
00058 #define SUPPORTED_10baseT_Half          (1 << 0)
00059 #define SUPPORTED_10baseT_Full          (1 << 1)
00060 #define SUPPORTED_100baseT_Half         (1 << 2)
00061 #define SUPPORTED_100baseT_Full         (1 << 3)
00062 #define SUPPORTED_1000baseT_Half        (1 << 4)
00063 #define SUPPORTED_1000baseT_Full        (1 << 5)
00064 #define SUPPORTED_Autoneg               (1 << 6)
00065 #define SUPPORTED_TP                    (1 << 7)
00066 #define SUPPORTED_FIBRE                 (1 << 10)
00067 
00068 /* ----------------------------------- */
00069 
00070 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
00071                                PCI_STATUS_SIG_SYSTEM_ERROR | \
00072                                PCI_STATUS_REC_MASTER_ABORT | \
00073                                PCI_STATUS_REC_TARGET_ABORT | \
00074                                PCI_STATUS_PARITY)
00075 
00076 enum csr_regs {
00077         B0_RAP  = 0x0000,
00078         B0_CTST = 0x0004,
00079         B0_LED  = 0x0006,
00080         B0_POWER_CTRL   = 0x0007,
00081         B0_ISRC = 0x0008,
00082         B0_IMSK = 0x000c,
00083         B0_HWE_ISRC     = 0x0010,
00084         B0_HWE_IMSK     = 0x0014,
00085         B0_SP_ISRC      = 0x0018,
00086         B0_XM1_IMSK     = 0x0020,
00087         B0_XM1_ISRC     = 0x0028,
00088         B0_XM1_PHY_ADDR = 0x0030,
00089         B0_XM1_PHY_DATA = 0x0034,
00090         B0_XM2_IMSK     = 0x0040,
00091         B0_XM2_ISRC     = 0x0048,
00092         B0_XM2_PHY_ADDR = 0x0050,
00093         B0_XM2_PHY_DATA = 0x0054,
00094         B0_R1_CSR       = 0x0060,
00095         B0_R2_CSR       = 0x0064,
00096         B0_XS1_CSR      = 0x0068,
00097         B0_XA1_CSR      = 0x006c,
00098         B0_XS2_CSR      = 0x0070,
00099         B0_XA2_CSR      = 0x0074,
00100 
00101         B2_MAC_1        = 0x0100,
00102         B2_MAC_2        = 0x0108,
00103         B2_MAC_3        = 0x0110,
00104         B2_CONN_TYP     = 0x0118,
00105         B2_PMD_TYP      = 0x0119,
00106         B2_MAC_CFG      = 0x011a,
00107         B2_CHIP_ID      = 0x011b,
00108         B2_E_0          = 0x011c,
00109         B2_E_1          = 0x011d,
00110         B2_E_2          = 0x011e,
00111         B2_E_3          = 0x011f,
00112         B2_FAR          = 0x0120,
00113         B2_FDP          = 0x0124,
00114         B2_LD_CTRL      = 0x0128,
00115         B2_LD_TEST      = 0x0129,
00116         B2_TI_INI       = 0x0130,
00117         B2_TI_VAL       = 0x0134,
00118         B2_TI_CTRL      = 0x0138,
00119         B2_TI_TEST      = 0x0139,
00120         B2_IRQM_INI     = 0x0140,
00121         B2_IRQM_VAL     = 0x0144,
00122         B2_IRQM_CTRL    = 0x0148,
00123         B2_IRQM_TEST    = 0x0149,
00124         B2_IRQM_MSK     = 0x014c,
00125         B2_IRQM_HWE_MSK = 0x0150,
00126         B2_TST_CTRL1    = 0x0158,
00127         B2_TST_CTRL2    = 0x0159,
00128         B2_GP_IO        = 0x015c,
00129         B2_I2C_CTRL     = 0x0160,
00130         B2_I2C_DATA     = 0x0164,
00131         B2_I2C_IRQ      = 0x0168,
00132         B2_I2C_SW       = 0x016c,
00133         B2_BSC_INI      = 0x0170,
00134         B2_BSC_VAL      = 0x0174,
00135         B2_BSC_CTRL     = 0x0178,
00136         B2_BSC_STAT     = 0x0179,
00137         B2_BSC_TST      = 0x017a,
00138 
00139         B3_RAM_ADDR     = 0x0180,
00140         B3_RAM_DATA_LO  = 0x0184,
00141         B3_RAM_DATA_HI  = 0x0188,
00142         B3_RI_WTO_R1    = 0x0190,
00143         B3_RI_WTO_XA1   = 0x0191,
00144         B3_RI_WTO_XS1   = 0x0192,
00145         B3_RI_RTO_R1    = 0x0193,
00146         B3_RI_RTO_XA1   = 0x0194,
00147         B3_RI_RTO_XS1   = 0x0195,
00148         B3_RI_WTO_R2    = 0x0196,
00149         B3_RI_WTO_XA2   = 0x0197,
00150         B3_RI_WTO_XS2   = 0x0198,
00151         B3_RI_RTO_R2    = 0x0199,
00152         B3_RI_RTO_XA2   = 0x019a,
00153         B3_RI_RTO_XS2   = 0x019b,
00154         B3_RI_TO_VAL    = 0x019c,
00155         B3_RI_CTRL      = 0x01a0,
00156         B3_RI_TEST      = 0x01a2,
00157         B3_MA_TOINI_RX1 = 0x01b0,
00158         B3_MA_TOINI_RX2 = 0x01b1,
00159         B3_MA_TOINI_TX1 = 0x01b2,
00160         B3_MA_TOINI_TX2 = 0x01b3,
00161         B3_MA_TOVAL_RX1 = 0x01b4,
00162         B3_MA_TOVAL_RX2 = 0x01b5,
00163         B3_MA_TOVAL_TX1 = 0x01b6,
00164         B3_MA_TOVAL_TX2 = 0x01b7,
00165         B3_MA_TO_CTRL   = 0x01b8,
00166         B3_MA_TO_TEST   = 0x01ba,
00167         B3_MA_RCINI_RX1 = 0x01c0,
00168         B3_MA_RCINI_RX2 = 0x01c1,
00169         B3_MA_RCINI_TX1 = 0x01c2,
00170         B3_MA_RCINI_TX2 = 0x01c3,
00171         B3_MA_RCVAL_RX1 = 0x01c4,
00172         B3_MA_RCVAL_RX2 = 0x01c5,
00173         B3_MA_RCVAL_TX1 = 0x01c6,
00174         B3_MA_RCVAL_TX2 = 0x01c7,
00175         B3_MA_RC_CTRL   = 0x01c8,
00176         B3_MA_RC_TEST   = 0x01ca,
00177         B3_PA_TOINI_RX1 = 0x01d0,
00178         B3_PA_TOINI_RX2 = 0x01d4,
00179         B3_PA_TOINI_TX1 = 0x01d8,
00180         B3_PA_TOINI_TX2 = 0x01dc,
00181         B3_PA_TOVAL_RX1 = 0x01e0,
00182         B3_PA_TOVAL_RX2 = 0x01e4,
00183         B3_PA_TOVAL_TX1 = 0x01e8,
00184         B3_PA_TOVAL_TX2 = 0x01ec,
00185         B3_PA_CTRL      = 0x01f0,
00186         B3_PA_TEST      = 0x01f2,
00187 };
00188 
00189 /*      B0_CTST                 16 bit  Control/Status register */
00190 enum {
00191         CS_CLK_RUN_HOT  = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
00192         CS_CLK_RUN_RST  = 1<<12,/* CLK_RUN reset  (YUKON-Lite only) */
00193         CS_CLK_RUN_ENA  = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
00194         CS_VAUX_AVAIL   = 1<<10,/* VAUX available (YUKON only) */
00195         CS_BUS_CLOCK    = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
00196         CS_BUS_SLOT_SZ  = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
00197         CS_ST_SW_IRQ    = 1<<7, /* Set IRQ SW Request */
00198         CS_CL_SW_IRQ    = 1<<6, /* Clear IRQ SW Request */
00199         CS_STOP_DONE    = 1<<5, /* Stop Master is finished */
00200         CS_STOP_MAST    = 1<<4, /* Command Bit to stop the master */
00201         CS_MRST_CLR     = 1<<3, /* Clear Master reset   */
00202         CS_MRST_SET     = 1<<2, /* Set Master reset     */
00203         CS_RST_CLR      = 1<<1, /* Clear Software reset */
00204         CS_RST_SET      = 1,    /* Set   Software reset */
00205 
00206 /*      B0_LED                   8 Bit  LED register */
00207 /* Bit  7.. 2:  reserved */
00208         LED_STAT_ON     = 1<<1, /* Status LED on        */
00209         LED_STAT_OFF    = 1,            /* Status LED off       */
00210 
00211 /*      B0_POWER_CTRL    8 Bit  Power Control reg (YUKON only) */
00212         PC_VAUX_ENA     = 1<<7, /* Switch VAUX Enable  */
00213         PC_VAUX_DIS     = 1<<6, /* Switch VAUX Disable */
00214         PC_VCC_ENA      = 1<<5, /* Switch VCC Enable  */
00215         PC_VCC_DIS      = 1<<4, /* Switch VCC Disable */
00216         PC_VAUX_ON      = 1<<3, /* Switch VAUX On  */
00217         PC_VAUX_OFF     = 1<<2, /* Switch VAUX Off */
00218         PC_VCC_ON       = 1<<1, /* Switch VCC On  */
00219         PC_VCC_OFF      = 1<<0, /* Switch VCC Off */
00220 };
00221 
00222 /*      B2_IRQM_MSK     32 bit  IRQ Moderation Mask */
00223 enum {
00224         IS_ALL_MSK      = 0xbffffffful, /* All Interrupt bits */
00225         IS_HW_ERR       = 1<<31,        /* Interrupt HW Error */
00226                                         /* Bit 30:      reserved */
00227         IS_PA_TO_RX1    = 1<<29,        /* Packet Arb Timeout Rx1 */
00228         IS_PA_TO_RX2    = 1<<28,        /* Packet Arb Timeout Rx2 */
00229         IS_PA_TO_TX1    = 1<<27,        /* Packet Arb Timeout Tx1 */
00230         IS_PA_TO_TX2    = 1<<26,        /* Packet Arb Timeout Tx2 */
00231         IS_I2C_READY    = 1<<25,        /* IRQ on end of I2C Tx */
00232         IS_IRQ_SW       = 1<<24,        /* SW forced IRQ        */
00233         IS_EXT_REG      = 1<<23,        /* IRQ from LM80 or PHY (GENESIS only) */
00234                                         /* IRQ from PHY (YUKON only) */
00235         IS_TIMINT       = 1<<22,        /* IRQ from Timer       */
00236         IS_MAC1         = 1<<21,        /* IRQ from MAC 1       */
00237         IS_LNK_SYNC_M1  = 1<<20,        /* Link Sync Cnt wrap MAC 1 */
00238         IS_MAC2         = 1<<19,        /* IRQ from MAC 2       */
00239         IS_LNK_SYNC_M2  = 1<<18,        /* Link Sync Cnt wrap MAC 2 */
00240 /* Receive Queue 1 */
00241         IS_R1_B         = 1<<17,        /* Q_R1 End of Buffer */
00242         IS_R1_F         = 1<<16,        /* Q_R1 End of Frame */
00243         IS_R1_C         = 1<<15,        /* Q_R1 Encoding Error */
00244 /* Receive Queue 2 */
00245         IS_R2_B         = 1<<14,        /* Q_R2 End of Buffer */
00246         IS_R2_F         = 1<<13,        /* Q_R2 End of Frame */
00247         IS_R2_C         = 1<<12,        /* Q_R2 Encoding Error */
00248 /* Synchronous Transmit Queue 1 */
00249         IS_XS1_B        = 1<<11,        /* Q_XS1 End of Buffer */
00250         IS_XS1_F        = 1<<10,        /* Q_XS1 End of Frame */
00251         IS_XS1_C        = 1<<9,         /* Q_XS1 Encoding Error */
00252 /* Asynchronous Transmit Queue 1 */
00253         IS_XA1_B        = 1<<8,         /* Q_XA1 End of Buffer */
00254         IS_XA1_F        = 1<<7,         /* Q_XA1 End of Frame */
00255         IS_XA1_C        = 1<<6,         /* Q_XA1 Encoding Error */
00256 /* Synchronous Transmit Queue 2 */
00257         IS_XS2_B        = 1<<5,         /* Q_XS2 End of Buffer */
00258         IS_XS2_F        = 1<<4,         /* Q_XS2 End of Frame */
00259         IS_XS2_C        = 1<<3,         /* Q_XS2 Encoding Error */
00260 /* Asynchronous Transmit Queue 2 */
00261         IS_XA2_B        = 1<<2,         /* Q_XA2 End of Buffer */
00262         IS_XA2_F        = 1<<1,         /* Q_XA2 End of Frame */
00263         IS_XA2_C        = 1<<0,         /* Q_XA2 Encoding Error */
00264 
00265         IS_TO_PORT1     = IS_PA_TO_RX1 | IS_PA_TO_TX1,
00266         IS_TO_PORT2     = IS_PA_TO_RX2 | IS_PA_TO_TX2,
00267 
00268         IS_PORT_1       = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
00269         IS_PORT_2       = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
00270 };
00271 
00272 
00273 /*      B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
00274 enum {
00275         IS_IRQ_TIST_OV  = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
00276         IS_IRQ_SENSOR   = 1<<12, /* IRQ from Sensor (YUKON only) */
00277         IS_IRQ_MST_ERR  = 1<<11, /* IRQ master error detected */
00278         IS_IRQ_STAT     = 1<<10, /* IRQ status exception */
00279         IS_NO_STAT_M1   = 1<<9, /* No Rx Status from MAC 1 */
00280         IS_NO_STAT_M2   = 1<<8, /* No Rx Status from MAC 2 */
00281         IS_NO_TIST_M1   = 1<<7, /* No Time Stamp from MAC 1 */
00282         IS_NO_TIST_M2   = 1<<6, /* No Time Stamp from MAC 2 */
00283         IS_RAM_RD_PAR   = 1<<5, /* RAM Read  Parity Error */
00284         IS_RAM_WR_PAR   = 1<<4, /* RAM Write Parity Error */
00285         IS_M1_PAR_ERR   = 1<<3, /* MAC 1 Parity Error */
00286         IS_M2_PAR_ERR   = 1<<2, /* MAC 2 Parity Error */
00287         IS_R1_PAR_ERR   = 1<<1, /* Queue R1 Parity Error */
00288         IS_R2_PAR_ERR   = 1<<0, /* Queue R2 Parity Error */
00289 
00290         IS_ERR_MSK      = IS_IRQ_MST_ERR | IS_IRQ_STAT
00291                         | IS_RAM_RD_PAR | IS_RAM_WR_PAR
00292                         | IS_M1_PAR_ERR | IS_M2_PAR_ERR
00293                         | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
00294 };
00295 
00296 /*      B2_TST_CTRL1     8 bit  Test Control Register 1 */
00297 enum {
00298         TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
00299         TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
00300         TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
00301         TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
00302         TST_FRC_APERR_M  = 1<<3, /* force ADDRPERR on MST */
00303         TST_FRC_APERR_T  = 1<<2, /* force ADDRPERR on TRG */
00304         TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
00305         TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
00306 };
00307 
00308 /*      B2_MAC_CFG               8 bit  MAC Configuration / Chip Revision */
00309 enum {
00310         CFG_CHIP_R_MSK    = 0xf<<4,     /* Bit 7.. 4: Chip Revision */
00311                                         /* Bit 3.. 2:   reserved */
00312         CFG_DIS_M2_CLK    = 1<<1,       /* Disable Clock for 2nd MAC */
00313         CFG_SNG_MAC       = 1<<0,       /* MAC Config: 0=2 MACs / 1=1 MAC*/
00314 };
00315 
00316 /*      B2_CHIP_ID               8 bit  Chip Identification Number */
00317 enum {
00318         CHIP_ID_GENESIS    = 0x0a, /* Chip ID for GENESIS */
00319         CHIP_ID_YUKON      = 0xb0, /* Chip ID for YUKON */
00320         CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
00321         CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
00322         CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
00323         CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
00324         CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
00325 
00326         CHIP_REV_YU_LITE_A1  = 3,       /* Chip Rev. for YUKON-Lite A1,A2 */
00327         CHIP_REV_YU_LITE_A3  = 7,       /* Chip Rev. for YUKON-Lite A3 */
00328 };
00329 
00330 /*      B2_TI_CTRL               8 bit  Timer control */
00331 /*      B2_IRQM_CTRL     8 bit  IRQ Moderation Timer Control */
00332 enum {
00333         TIM_START       = 1<<2, /* Start Timer */
00334         TIM_STOP        = 1<<1, /* Stop  Timer */
00335         TIM_CLR_IRQ     = 1<<0, /* Clear Timer IRQ (!IRQM) */
00336 };
00337 
00338 /*      B2_TI_TEST               8 Bit  Timer Test */
00339 /*      B2_IRQM_TEST     8 bit  IRQ Moderation Timer Test */
00340 /*      B28_DPT_TST              8 bit  Descriptor Poll Timer Test Reg */
00341 enum {
00342         TIM_T_ON        = 1<<2, /* Test mode on */
00343         TIM_T_OFF       = 1<<1, /* Test mode off */
00344         TIM_T_STEP      = 1<<0, /* Test step */
00345 };
00346 
00347 /*      B2_GP_IO                32 bit  General Purpose I/O Register */
00348 enum {
00349         GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
00350         GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
00351         GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
00352         GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
00353         GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
00354         GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
00355         GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
00356         GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
00357         GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
00358         GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
00359 
00360         GP_IO_9 = 1<<9, /* IO_9 pin */
00361         GP_IO_8 = 1<<8, /* IO_8 pin */
00362         GP_IO_7 = 1<<7, /* IO_7 pin */
00363         GP_IO_6 = 1<<6, /* IO_6 pin */
00364         GP_IO_5 = 1<<5, /* IO_5 pin */
00365         GP_IO_4 = 1<<4, /* IO_4 pin */
00366         GP_IO_3 = 1<<3, /* IO_3 pin */
00367         GP_IO_2 = 1<<2, /* IO_2 pin */
00368         GP_IO_1 = 1<<1, /* IO_1 pin */
00369         GP_IO_0 = 1<<0, /* IO_0 pin */
00370 };
00371 
00372 /* Descriptor Bit Definition */
00373 /*      TxCtrl          Transmit Buffer Control Field */
00374 /*      RxCtrl          Receive  Buffer Control Field */
00375 enum {
00376         BMU_OWN         = 1<<31, /* OWN bit: 0=host/1=BMU */
00377         BMU_STF         = 1<<30, /* Start of Frame */
00378         BMU_EOF         = 1<<29, /* End of Frame */
00379         BMU_IRQ_EOB     = 1<<28, /* Req "End of Buffer" IRQ */
00380         BMU_IRQ_EOF     = 1<<27, /* Req "End of Frame" IRQ */
00381                                 /* TxCtrl specific bits */
00382         BMU_STFWD       = 1<<26, /* (Tx)        Store & Forward Frame */
00383         BMU_NO_FCS      = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
00384         BMU_SW  = 1<<24, /* (Tx)        1 bit res. for SW use */
00385                                 /* RxCtrl specific bits */
00386         BMU_DEV_0       = 1<<26, /* (Rx)        Transfer data to Dev0 */
00387         BMU_STAT_VAL    = 1<<25, /* (Rx)        Rx Status Valid */
00388         BMU_TIST_VAL    = 1<<24, /* (Rx)        Rx TimeStamp Valid */
00389                         /* Bit 23..16:  BMU Check Opcodes */
00390         BMU_CHECK       = 0x55<<16, /* Default BMU check */
00391         BMU_TCP_CHECK   = 0x56<<16, /* Descr with TCP ext */
00392         BMU_UDP_CHECK   = 0x57<<16, /* Descr with UDP ext (YUKON only) */
00393         BMU_BBC         = 0xffffL, /* Bit 15.. 0:       Buffer Byte Counter */
00394 };
00395 
00396 /*      B2_BSC_CTRL              8 bit  Blink Source Counter Control */
00397 enum {
00398          BSC_START      = 1<<1, /* Start Blink Source Counter */
00399          BSC_STOP       = 1<<0, /* Stop  Blink Source Counter */
00400 };
00401 
00402 /*      B2_BSC_STAT              8 bit  Blink Source Counter Status */
00403 enum {
00404         BSC_SRC         = 1<<0, /* Blink Source, 0=Off / 1=On */
00405 };
00406 
00407 /*      B2_BSC_TST              16 bit  Blink Source Counter Test Reg */
00408 enum {
00409         BSC_T_ON        = 1<<2, /* Test mode on */
00410         BSC_T_OFF       = 1<<1, /* Test mode off */
00411         BSC_T_STEP      = 1<<0, /* Test step */
00412 };
00413 
00414 /*      B3_RAM_ADDR             32 bit  RAM Address, to read or write */
00415                                         /* Bit 31..19:  reserved */
00416 #define RAM_ADR_RAN     0x0007ffffL     /* Bit 18.. 0:  RAM Address Range */
00417 /* RAM Interface Registers */
00418 
00419 /*      B3_RI_CTRL              16 bit  RAM Iface Control Register */
00420 enum {
00421         RI_CLR_RD_PERR  = 1<<9, /* Clear IRQ RAM Read Parity Err */
00422         RI_CLR_WR_PERR  = 1<<8, /* Clear IRQ RAM Write Parity Err*/
00423 
00424         RI_RST_CLR      = 1<<1, /* Clear RAM Interface Reset */
00425         RI_RST_SET      = 1<<0, /* Set   RAM Interface Reset */
00426 };
00427 
00428 /* MAC Arbiter Registers */
00429 /*      B3_MA_TO_CTRL   16 bit  MAC Arbiter Timeout Ctrl Reg */
00430 enum {
00431         MA_FOE_ON       = 1<<3, /* XMAC Fast Output Enable ON */
00432         MA_FOE_OFF      = 1<<2, /* XMAC Fast Output Enable OFF */
00433         MA_RST_CLR      = 1<<1, /* Clear MAC Arbiter Reset */
00434         MA_RST_SET      = 1<<0, /* Set   MAC Arbiter Reset */
00435 
00436 };
00437 
00438 /* Timeout values */
00439 #define SK_MAC_TO_53    72              /* MAC arbiter timeout */
00440 #define SK_PKT_TO_53    0x2000          /* Packet arbiter timeout */
00441 #define SK_PKT_TO_MAX   0xffff          /* Maximum value */
00442 #define SK_RI_TO_53     36              /* RAM interface timeout */
00443 
00444 /* Packet Arbiter Registers */
00445 /*      B3_PA_CTRL              16 bit  Packet Arbiter Ctrl Register */
00446 enum {
00447         PA_CLR_TO_TX2   = 1<<13,/* Clear IRQ Packet Timeout TX2 */
00448         PA_CLR_TO_TX1   = 1<<12,/* Clear IRQ Packet Timeout TX1 */
00449         PA_CLR_TO_RX2   = 1<<11,/* Clear IRQ Packet Timeout RX2 */
00450         PA_CLR_TO_RX1   = 1<<10,/* Clear IRQ Packet Timeout RX1 */
00451         PA_ENA_TO_TX2   = 1<<9, /* Enable  Timeout Timer TX2 */
00452         PA_DIS_TO_TX2   = 1<<8, /* Disable Timeout Timer TX2 */
00453         PA_ENA_TO_TX1   = 1<<7, /* Enable  Timeout Timer TX1 */
00454         PA_DIS_TO_TX1   = 1<<6, /* Disable Timeout Timer TX1 */
00455         PA_ENA_TO_RX2   = 1<<5, /* Enable  Timeout Timer RX2 */
00456         PA_DIS_TO_RX2   = 1<<4, /* Disable Timeout Timer RX2 */
00457         PA_ENA_TO_RX1   = 1<<3, /* Enable  Timeout Timer RX1 */
00458         PA_DIS_TO_RX1   = 1<<2, /* Disable Timeout Timer RX1 */
00459         PA_RST_CLR      = 1<<1, /* Clear MAC Arbiter Reset */
00460         PA_RST_SET      = 1<<0, /* Set   MAC Arbiter Reset */
00461 };
00462 
00463 #define PA_ENA_TO_ALL   (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
00464                                                 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
00465 
00466 
00467 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
00468 /*      TXA_ITI_INI             32 bit  Tx Arb Interval Timer Init Val */
00469 /*      TXA_ITI_VAL             32 bit  Tx Arb Interval Timer Value */
00470 /*      TXA_LIM_INI             32 bit  Tx Arb Limit Counter Init Val */
00471 /*      TXA_LIM_VAL             32 bit  Tx Arb Limit Counter Value */
00472 
00473 #define TXA_MAX_VAL     0x00ffffffUL    /* Bit 23.. 0:  Max TXA Timer/Cnt Val */
00474 
00475 /*      TXA_CTRL                 8 bit  Tx Arbiter Control Register */
00476 enum {
00477         TXA_ENA_FSYNC   = 1<<7, /* Enable  force of sync Tx queue */
00478         TXA_DIS_FSYNC   = 1<<6, /* Disable force of sync Tx queue */
00479         TXA_ENA_ALLOC   = 1<<5, /* Enable  alloc of free bandwidth */
00480         TXA_DIS_ALLOC   = 1<<4, /* Disable alloc of free bandwidth */
00481         TXA_START_RC    = 1<<3, /* Start sync Rate Control */
00482         TXA_STOP_RC     = 1<<2, /* Stop  sync Rate Control */
00483         TXA_ENA_ARB     = 1<<1, /* Enable  Tx Arbiter */
00484         TXA_DIS_ARB     = 1<<0, /* Disable Tx Arbiter */
00485 };
00486 
00487 /*
00488  *      Bank 4 - 5
00489  */
00490 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
00491 enum {
00492         TXA_ITI_INI     = 0x0200,/* 32 bit      Tx Arb Interval Timer Init Val*/
00493         TXA_ITI_VAL     = 0x0204,/* 32 bit      Tx Arb Interval Timer Value */
00494         TXA_LIM_INI     = 0x0208,/* 32 bit      Tx Arb Limit Counter Init Val */
00495         TXA_LIM_VAL     = 0x020c,/* 32 bit      Tx Arb Limit Counter Value */
00496         TXA_CTRL        = 0x0210,/*  8 bit      Tx Arbiter Control Register */
00497         TXA_TEST        = 0x0211,/*  8 bit      Tx Arbiter Test Register */
00498         TXA_STAT        = 0x0212,/*  8 bit      Tx Arbiter Status Register */
00499 };
00500 
00501 
00502 enum {
00503         B6_EXT_REG      = 0x0300,/* External registers (GENESIS only) */
00504         B7_CFG_SPC      = 0x0380,/* copy of the Configuration register */
00505         B8_RQ1_REGS     = 0x0400,/* Receive Queue 1 */
00506         B8_RQ2_REGS     = 0x0480,/* Receive Queue 2 */
00507         B8_TS1_REGS     = 0x0600,/* Transmit sync queue 1 */
00508         B8_TA1_REGS     = 0x0680,/* Transmit async queue 1 */
00509         B8_TS2_REGS     = 0x0700,/* Transmit sync queue 2 */
00510         B8_TA2_REGS     = 0x0780,/* Transmit sync queue 2 */
00511         B16_RAM_REGS    = 0x0800,/* RAM Buffer Registers */
00512 };
00513 
00514 /* Queue Register Offsets, use Q_ADDR() to access */
00515 enum {
00516         B8_Q_REGS = 0x0400, /* base of Queue registers */
00517         Q_D     = 0x00, /* 8*32 bit     Current Descriptor */
00518         Q_DA_L  = 0x20, /* 32 bit       Current Descriptor Address Low dWord */
00519         Q_DA_H  = 0x24, /* 32 bit       Current Descriptor Address High dWord */
00520         Q_AC_L  = 0x28, /* 32 bit       Current Address Counter Low dWord */
00521         Q_AC_H  = 0x2c, /* 32 bit       Current Address Counter High dWord */
00522         Q_BC    = 0x30, /* 32 bit       Current Byte Counter */
00523         Q_CSR   = 0x34, /* 32 bit       BMU Control/Status Register */
00524         Q_F     = 0x38, /* 32 bit       Flag Register */
00525         Q_T1    = 0x3c, /* 32 bit       Test Register 1 */
00526         Q_T1_TR = 0x3c, /*  8 bit       Test Register 1 Transfer SM */
00527         Q_T1_WR = 0x3d, /*  8 bit       Test Register 1 Write Descriptor SM */
00528         Q_T1_RD = 0x3e, /*  8 bit       Test Register 1 Read Descriptor SM */
00529         Q_T1_SV = 0x3f, /*  8 bit       Test Register 1 Supervisor SM */
00530         Q_T2    = 0x40, /* 32 bit       Test Register 2 */
00531         Q_T3    = 0x44, /* 32 bit       Test Register 3 */
00532 
00533 };
00534 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
00535 
00536 /* RAM Buffer Register Offsets */
00537 enum {
00538 
00539         RB_START= 0x00,/* 32 bit        RAM Buffer Start Address */
00540         RB_END  = 0x04,/* 32 bit        RAM Buffer End Address */
00541         RB_WP   = 0x08,/* 32 bit        RAM Buffer Write Pointer */
00542         RB_RP   = 0x0c,/* 32 bit        RAM Buffer Read Pointer */
00543         RB_RX_UTPP= 0x10,/* 32 bit      Rx Upper Threshold, Pause Packet */
00544         RB_RX_LTPP= 0x14,/* 32 bit      Rx Lower Threshold, Pause Packet */
00545         RB_RX_UTHP= 0x18,/* 32 bit      Rx Upper Threshold, High Prio */
00546         RB_RX_LTHP= 0x1c,/* 32 bit      Rx Lower Threshold, High Prio */
00547         /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
00548         RB_PC   = 0x20,/* 32 bit        RAM Buffer Packet Counter */
00549         RB_LEV  = 0x24,/* 32 bit        RAM Buffer Level Register */
00550         RB_CTRL = 0x28,/* 32 bit        RAM Buffer Control Register */
00551         RB_TST1 = 0x29,/*  8 bit        RAM Buffer Test Register 1 */
00552         RB_TST2 = 0x2a,/*  8 bit        RAM Buffer Test Register 2 */
00553 };
00554 
00555 /* Receive and Transmit Queues */
00556 enum {
00557         Q_R1    = 0x0000,       /* Receive Queue 1 */
00558         Q_R2    = 0x0080,       /* Receive Queue 2 */
00559         Q_XS1   = 0x0200,       /* Synchronous Transmit Queue 1 */
00560         Q_XA1   = 0x0280,       /* Asynchronous Transmit Queue 1 */
00561         Q_XS2   = 0x0300,       /* Synchronous Transmit Queue 2 */
00562         Q_XA2   = 0x0380,       /* Asynchronous Transmit Queue 2 */
00563 };
00564 
00565 /* Different MAC Types */
00566 enum {
00567         SK_MAC_XMAC =   0,      /* Xaqti XMAC II */
00568         SK_MAC_GMAC =   1,      /* Marvell GMAC */
00569 };
00570 
00571 /* Different PHY Types */
00572 enum {
00573         SK_PHY_XMAC     = 0,/* integrated in XMAC II */
00574         SK_PHY_BCOM     = 1,/* Broadcom BCM5400 */
00575         SK_PHY_LONE     = 2,/* Level One LXT1000  [not supported]*/
00576         SK_PHY_NAT      = 3,/* National DP83891  [not supported] */
00577         SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
00578         SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
00579 };
00580 
00581 /* PHY addresses (bits 12..8 of PHY address reg) */
00582 enum {
00583         PHY_ADDR_XMAC   = 0<<8,
00584         PHY_ADDR_BCOM   = 1<<8,
00585 
00586 /* GPHY address (bits 15..11 of SMI control reg) */
00587         PHY_ADDR_MARV   = 0,
00588 };
00589 
00590 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
00591 
00592 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
00593 enum {
00594         RX_MFF_EA       = 0x0c00,/* 32 bit      Receive MAC FIFO End Address */
00595         RX_MFF_WP       = 0x0c04,/* 32 bit      Receive MAC FIFO Write Pointer */
00596 
00597         RX_MFF_RP       = 0x0c0c,/* 32 bit      Receive MAC FIFO Read Pointer */
00598         RX_MFF_PC       = 0x0c10,/* 32 bit      Receive MAC FIFO Packet Cnt */
00599         RX_MFF_LEV      = 0x0c14,/* 32 bit      Receive MAC FIFO Level */
00600         RX_MFF_CTRL1    = 0x0c18,/* 16 bit      Receive MAC FIFO Control Reg 1*/
00601         RX_MFF_STAT_TO  = 0x0c1a,/*  8 bit      Receive MAC Status Timeout */
00602         RX_MFF_TIST_TO  = 0x0c1b,/*  8 bit      Receive MAC Time Stamp Timeout */
00603         RX_MFF_CTRL2    = 0x0c1c,/*  8 bit      Receive MAC FIFO Control Reg 2*/
00604         RX_MFF_TST1     = 0x0c1d,/*  8 bit      Receive MAC FIFO Test Reg 1 */
00605         RX_MFF_TST2     = 0x0c1e,/*  8 bit      Receive MAC FIFO Test Reg 2 */
00606 
00607         RX_LED_INI      = 0x0c20,/* 32 bit      Receive LED Cnt Init Value */
00608         RX_LED_VAL      = 0x0c24,/* 32 bit      Receive LED Cnt Current Value */
00609         RX_LED_CTRL     = 0x0c28,/*  8 bit      Receive LED Cnt Control Reg */
00610         RX_LED_TST      = 0x0c29,/*  8 bit      Receive LED Cnt Test Register */
00611 
00612         LNK_SYNC_INI    = 0x0c30,/* 32 bit      Link Sync Cnt Init Value */
00613         LNK_SYNC_VAL    = 0x0c34,/* 32 bit      Link Sync Cnt Current Value */
00614         LNK_SYNC_CTRL   = 0x0c38,/*  8 bit      Link Sync Cnt Control Register */
00615         LNK_SYNC_TST    = 0x0c39,/*  8 bit      Link Sync Cnt Test Register */
00616         LNK_LED_REG     = 0x0c3c,/*  8 bit      Link LED Register */
00617 };
00618 
00619 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
00620 /*      RX_MFF_CTRL1    16 bit  Receive MAC FIFO Control Reg 1 */
00621 enum {
00622         MFF_ENA_RDY_PAT = 1<<13,        /* Enable  Ready Patch */
00623         MFF_DIS_RDY_PAT = 1<<12,        /* Disable Ready Patch */
00624         MFF_ENA_TIM_PAT = 1<<11,        /* Enable  Timing Patch */
00625         MFF_DIS_TIM_PAT = 1<<10,        /* Disable Timing Patch */
00626         MFF_ENA_ALM_FUL = 1<<9, /* Enable  AlmostFull Sign */
00627         MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
00628         MFF_ENA_PAUSE   = 1<<7, /* Enable  Pause Signaling */
00629         MFF_DIS_PAUSE   = 1<<6, /* Disable Pause Signaling */
00630         MFF_ENA_FLUSH   = 1<<5, /* Enable  Frame Flushing */
00631         MFF_DIS_FLUSH   = 1<<4, /* Disable Frame Flushing */
00632         MFF_ENA_TIST    = 1<<3, /* Enable  Time Stamp Gener */
00633         MFF_DIS_TIST    = 1<<2, /* Disable Time Stamp Gener */
00634         MFF_CLR_INTIST  = 1<<1, /* Clear IRQ No Time Stamp */
00635         MFF_CLR_INSTAT  = 1<<0, /* Clear IRQ No Status */
00636         MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
00637 };
00638 
00639 /*      TX_MFF_CTRL1    16 bit  Transmit MAC FIFO Control Reg 1 */
00640 enum {
00641         MFF_CLR_PERR    = 1<<15, /* Clear Parity Error IRQ */
00642 
00643         MFF_ENA_PKT_REC = 1<<13, /* Enable  Packet Recovery */
00644         MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
00645 
00646         MFF_ENA_W4E     = 1<<7, /* Enable  Wait for Empty */
00647         MFF_DIS_W4E     = 1<<6, /* Disable Wait for Empty */
00648 
00649         MFF_ENA_LOOPB   = 1<<3, /* Enable  Loopback */
00650         MFF_DIS_LOOPB   = 1<<2, /* Disable Loopback */
00651         MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
00652         MFF_SET_MAC_RST = 1<<0, /* Set   XMAC Reset */
00653 
00654         MFF_TX_CTRL_DEF  = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
00655 };
00656 
00657 
00658 /*      RX_MFF_TST2              8 bit  Receive MAC FIFO Test Register 2 */
00659 /*      TX_MFF_TST2              8 bit  Transmit MAC FIFO Test Register 2 */
00660 enum {
00661         MFF_WSP_T_ON    = 1<<6, /* Tx: Write Shadow Ptr TestOn */
00662         MFF_WSP_T_OFF   = 1<<5, /* Tx: Write Shadow Ptr TstOff */
00663         MFF_WSP_INC     = 1<<4, /* Tx: Write Shadow Ptr Increment */
00664         MFF_PC_DEC      = 1<<3, /* Packet Counter Decrement */
00665         MFF_PC_T_ON     = 1<<2, /* Packet Counter Test On */
00666         MFF_PC_T_OFF    = 1<<1, /* Packet Counter Test Off */
00667         MFF_PC_INC      = 1<<0, /* Packet Counter Increment */
00668 };
00669 
00670 /*      RX_MFF_TST1              8 bit  Receive MAC FIFO Test Register 1 */
00671 /*      TX_MFF_TST1              8 bit  Transmit MAC FIFO Test Register 1 */
00672 enum {
00673         MFF_WP_T_ON     = 1<<6, /* Write Pointer Test On */
00674         MFF_WP_T_OFF    = 1<<5, /* Write Pointer Test Off */
00675         MFF_WP_INC      = 1<<4, /* Write Pointer Increm */
00676 
00677         MFF_RP_T_ON     = 1<<2, /* Read Pointer Test On */
00678         MFF_RP_T_OFF    = 1<<1, /* Read Pointer Test Off */
00679         MFF_RP_DEC      = 1<<0, /* Read Pointer Decrement */
00680 };
00681 
00682 /*      RX_MFF_CTRL2     8 bit  Receive MAC FIFO Control Reg 2 */
00683 /*      TX_MFF_CTRL2     8 bit  Transmit MAC FIFO Control Reg 2 */
00684 enum {
00685         MFF_ENA_OP_MD   = 1<<3, /* Enable  Operation Mode */
00686         MFF_DIS_OP_MD   = 1<<2, /* Disable Operation Mode */
00687         MFF_RST_CLR     = 1<<1, /* Clear MAC FIFO Reset */
00688         MFF_RST_SET     = 1<<0, /* Set   MAC FIFO Reset */
00689 };
00690 
00691 
00692 /*      Link LED Counter Registers (GENESIS only) */
00693 
00694 /*      RX_LED_CTRL              8 bit  Receive LED Cnt Control Reg */
00695 /*      TX_LED_CTRL              8 bit  Transmit LED Cnt Control Reg */
00696 /*      LNK_SYNC_CTRL    8 bit  Link Sync Cnt Control Register */
00697 enum {
00698         LED_START       = 1<<2, /* Start Timer */
00699         LED_STOP        = 1<<1, /* Stop Timer */
00700         LED_STATE       = 1<<0, /* Rx/Tx: LED State, 1=LED on */
00701 };
00702 
00703 /*      RX_LED_TST               8 bit  Receive LED Cnt Test Register */
00704 /*      TX_LED_TST               8 bit  Transmit LED Cnt Test Register */
00705 /*      LNK_SYNC_TST     8 bit  Link Sync Cnt Test Register */
00706 enum {
00707         LED_T_ON        = 1<<2, /* LED Counter Test mode On */
00708         LED_T_OFF       = 1<<1, /* LED Counter Test mode Off */
00709         LED_T_STEP      = 1<<0, /* LED Counter Step */
00710 };
00711 
00712 /*      LNK_LED_REG              8 bit  Link LED Register */
00713 enum {
00714         LED_BLK_ON      = 1<<5, /* Link LED Blinking On */
00715         LED_BLK_OFF     = 1<<4, /* Link LED Blinking Off */
00716         LED_SYNC_ON     = 1<<3, /* Use Sync Wire to switch LED */
00717         LED_SYNC_OFF    = 1<<2, /* Disable Sync Wire Input */
00718         LED_ON  = 1<<1, /* switch LED on */
00719         LED_OFF = 1<<0, /* switch LED off */
00720 };
00721 
00722 /* Receive GMAC FIFO (YUKON) */
00723 enum {
00724         RX_GMF_EA       = 0x0c40,/* 32 bit      Rx GMAC FIFO End Address */
00725         RX_GMF_AF_THR   = 0x0c44,/* 32 bit      Rx GMAC FIFO Almost Full Thresh. */
00726         RX_GMF_CTRL_T   = 0x0c48,/* 32 bit      Rx GMAC FIFO Control/Test */
00727         RX_GMF_FL_MSK   = 0x0c4c,/* 32 bit      Rx GMAC FIFO Flush Mask */
00728         RX_GMF_FL_THR   = 0x0c50,/* 32 bit      Rx GMAC FIFO Flush Threshold */
00729         RX_GMF_WP       = 0x0c60,/* 32 bit      Rx GMAC FIFO Write Pointer */
00730         RX_GMF_WLEV     = 0x0c68,/* 32 bit      Rx GMAC FIFO Write Level */
00731         RX_GMF_RP       = 0x0c70,/* 32 bit      Rx GMAC FIFO Read Pointer */
00732         RX_GMF_RLEV     = 0x0c78,/* 32 bit      Rx GMAC FIFO Read Level */
00733 };
00734 
00735 
00736 /*      TXA_TEST                 8 bit  Tx Arbiter Test Register */
00737 enum {
00738         TXA_INT_T_ON    = 1<<5, /* Tx Arb Interval Timer Test On */
00739         TXA_INT_T_OFF   = 1<<4, /* Tx Arb Interval Timer Test Off */
00740         TXA_INT_T_STEP  = 1<<3, /* Tx Arb Interval Timer Step */
00741         TXA_LIM_T_ON    = 1<<2, /* Tx Arb Limit Timer Test On */
00742         TXA_LIM_T_OFF   = 1<<1, /* Tx Arb Limit Timer Test Off */
00743         TXA_LIM_T_STEP  = 1<<0, /* Tx Arb Limit Timer Step */
00744 };
00745 
00746 /*      TXA_STAT                 8 bit  Tx Arbiter Status Register */
00747 enum {
00748         TXA_PRIO_XS     = 1<<0, /* sync queue has prio to send */
00749 };
00750 
00751 
00752 /*      Q_BC                    32 bit  Current Byte Counter */
00753 
00754 /* BMU Control Status Registers */
00755 /*      B0_R1_CSR               32 bit  BMU Ctrl/Stat Rx Queue 1 */
00756 /*      B0_R2_CSR               32 bit  BMU Ctrl/Stat Rx Queue 2 */
00757 /*      B0_XA1_CSR              32 bit  BMU Ctrl/Stat Sync Tx Queue 1 */
00758 /*      B0_XS1_CSR              32 bit  BMU Ctrl/Stat Async Tx Queue 1 */
00759 /*      B0_XA2_CSR              32 bit  BMU Ctrl/Stat Sync Tx Queue 2 */
00760 /*      B0_XS2_CSR              32 bit  BMU Ctrl/Stat Async Tx Queue 2 */
00761 /*      Q_CSR                   32 bit  BMU Control/Status Register */
00762 
00763 enum {
00764         CSR_SV_IDLE     = 1<<24,        /* BMU SM Idle */
00765 
00766         CSR_DESC_CLR    = 1<<21,        /* Clear Reset for Descr */
00767         CSR_DESC_SET    = 1<<20,        /* Set   Reset for Descr */
00768         CSR_FIFO_CLR    = 1<<19,        /* Clear Reset for FIFO */
00769         CSR_FIFO_SET    = 1<<18,        /* Set   Reset for FIFO */
00770         CSR_HPI_RUN     = 1<<17,        /* Release HPI SM */
00771         CSR_HPI_RST     = 1<<16,        /* Reset   HPI SM to Idle */
00772         CSR_SV_RUN      = 1<<15,        /* Release Supervisor SM */
00773         CSR_SV_RST      = 1<<14,        /* Reset   Supervisor SM */
00774         CSR_DREAD_RUN   = 1<<13,        /* Release Descr Read SM */
00775         CSR_DREAD_RST   = 1<<12,        /* Reset   Descr Read SM */
00776         CSR_DWRITE_RUN  = 1<<11,        /* Release Descr Write SM */
00777         CSR_DWRITE_RST  = 1<<10,        /* Reset   Descr Write SM */
00778         CSR_TRANS_RUN   = 1<<9,         /* Release Transfer SM */
00779         CSR_TRANS_RST   = 1<<8,         /* Reset   Transfer SM */
00780         CSR_ENA_POL     = 1<<7,         /* Enable  Descr Polling */
00781         CSR_DIS_POL     = 1<<6,         /* Disable Descr Polling */
00782         CSR_STOP        = 1<<5,         /* Stop  Rx/Tx Queue */
00783         CSR_START       = 1<<4,         /* Start Rx/Tx Queue */
00784         CSR_IRQ_CL_P    = 1<<3,         /* (Rx) Clear Parity IRQ */
00785         CSR_IRQ_CL_B    = 1<<2,         /* Clear EOB IRQ */
00786         CSR_IRQ_CL_F    = 1<<1,         /* Clear EOF IRQ */
00787         CSR_IRQ_CL_C    = 1<<0,         /* Clear ERR IRQ */
00788 };
00789 
00790 #define CSR_SET_RESET   (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
00791                         CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
00792                         CSR_TRANS_RST)
00793 #define CSR_CLR_RESET   (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
00794                         CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
00795                         CSR_TRANS_RUN)
00796 
00797 /*      Q_F                             32 bit  Flag Register */
00798 enum {
00799         F_ALM_FULL      = 1<<27,        /* Rx FIFO: almost full */
00800         F_EMPTY         = 1<<27,        /* Tx FIFO: empty flag */
00801         F_FIFO_EOF      = 1<<26,        /* Tag (EOF Flag) bit in FIFO */
00802         F_WM_REACHED    = 1<<25,        /* Watermark reached */
00803 
00804         F_FIFO_LEVEL    = 0x1fL<<16,    /* Bit 23..16:  # of Qwords in FIFO */
00805         F_WATER_MARK    = 0x0007ffL,    /* Bit 10.. 0:  Watermark */
00806 };
00807 
00808 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
00809 /*      RB_START                32 bit  RAM Buffer Start Address */
00810 /*      RB_END                  32 bit  RAM Buffer End Address */
00811 /*      RB_WP                   32 bit  RAM Buffer Write Pointer */
00812 /*      RB_RP                   32 bit  RAM Buffer Read Pointer */
00813 /*      RB_RX_UTPP              32 bit  Rx Upper Threshold, Pause Pack */
00814 /*      RB_RX_LTPP              32 bit  Rx Lower Threshold, Pause Pack */
00815 /*      RB_RX_UTHP              32 bit  Rx Upper Threshold, High Prio */
00816 /*      RB_RX_LTHP              32 bit  Rx Lower Threshold, High Prio */
00817 /*      RB_PC                   32 bit  RAM Buffer Packet Counter */
00818 /*      RB_LEV                  32 bit  RAM Buffer Level Register */
00819 
00820 #define RB_MSK  0x0007ffff      /* Bit 18.. 0:  RAM Buffer Pointer Bits */
00821 /*      RB_TST2                  8 bit  RAM Buffer Test Register 2 */
00822 /*      RB_TST1                  8 bit  RAM Buffer Test Register 1 */
00823 
00824 /*      RB_CTRL                  8 bit  RAM Buffer Control Register */
00825 enum {
00826         RB_ENA_STFWD    = 1<<5, /* Enable  Store & Forward */
00827         RB_DIS_STFWD    = 1<<4, /* Disable Store & Forward */
00828         RB_ENA_OP_MD    = 1<<3, /* Enable  Operation Mode */
00829         RB_DIS_OP_MD    = 1<<2, /* Disable Operation Mode */
00830         RB_RST_CLR      = 1<<1, /* Clear RAM Buf STM Reset */
00831         RB_RST_SET      = 1<<0, /* Set   RAM Buf STM Reset */
00832 };
00833 
00834 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
00835 enum {
00836         TX_MFF_EA       = 0x0d00,/* 32 bit      Transmit MAC FIFO End Address */
00837         TX_MFF_WP       = 0x0d04,/* 32 bit      Transmit MAC FIFO WR Pointer */
00838         TX_MFF_WSP      = 0x0d08,/* 32 bit      Transmit MAC FIFO WR Shadow Ptr */
00839         TX_MFF_RP       = 0x0d0c,/* 32 bit      Transmit MAC FIFO RD Pointer */
00840         TX_MFF_PC       = 0x0d10,/* 32 bit      Transmit MAC FIFO Packet Cnt */
00841         TX_MFF_LEV      = 0x0d14,/* 32 bit      Transmit MAC FIFO Level */
00842         TX_MFF_CTRL1    = 0x0d18,/* 16 bit      Transmit MAC FIFO Ctrl Reg 1 */
00843         TX_MFF_WAF      = 0x0d1a,/*  8 bit      Transmit MAC Wait after flush */
00844 
00845         TX_MFF_CTRL2    = 0x0d1c,/*  8 bit      Transmit MAC FIFO Ctrl Reg 2 */
00846         TX_MFF_TST1     = 0x0d1d,/*  8 bit      Transmit MAC FIFO Test Reg 1 */
00847         TX_MFF_TST2     = 0x0d1e,/*  8 bit      Transmit MAC FIFO Test Reg 2 */
00848 
00849         TX_LED_INI      = 0x0d20,/* 32 bit      Transmit LED Cnt Init Value */
00850         TX_LED_VAL      = 0x0d24,/* 32 bit      Transmit LED Cnt Current Val */
00851         TX_LED_CTRL     = 0x0d28,/*  8 bit      Transmit LED Cnt Control Reg */
00852         TX_LED_TST      = 0x0d29,/*  8 bit      Transmit LED Cnt Test Reg */
00853 };
00854 
00855 /* Counter and Timer constants, for a host clock of 62.5 MHz */
00856 #define SK_XMIT_DUR             0x002faf08UL    /*  50 ms */
00857 #define SK_BLK_DUR              0x01dcd650UL    /* 500 ms */
00858 
00859 #define SK_DPOLL_DEF    0x00ee6b28UL    /* 250 ms at 62.5 MHz */
00860 
00861 #define SK_DPOLL_MAX    0x00ffffffUL    /* 268 ms at 62.5 MHz */
00862                                         /* 215 ms at 78.12 MHz */
00863 
00864 #define SK_FACT_62              100     /* is given in percent */
00865 #define SK_FACT_53               85     /* on GENESIS:  53.12 MHz */
00866 #define SK_FACT_78              125     /* on YUKON:    78.12 MHz */
00867 
00868 
00869 /* Transmit GMAC FIFO (YUKON only) */
00870 enum {
00871         TX_GMF_EA       = 0x0d40,/* 32 bit      Tx GMAC FIFO End Address */
00872         TX_GMF_AE_THR   = 0x0d44,/* 32 bit      Tx GMAC FIFO Almost Empty Thresh.*/
00873         TX_GMF_CTRL_T   = 0x0d48,/* 32 bit      Tx GMAC FIFO Control/Test */
00874 
00875         TX_GMF_WP       = 0x0d60,/* 32 bit      Tx GMAC FIFO Write Pointer */
00876         TX_GMF_WSP      = 0x0d64,/* 32 bit      Tx GMAC FIFO Write Shadow Ptr. */
00877         TX_GMF_WLEV     = 0x0d68,/* 32 bit      Tx GMAC FIFO Write Level */
00878 
00879         TX_GMF_RP       = 0x0d70,/* 32 bit      Tx GMAC FIFO Read Pointer */
00880         TX_GMF_RSTP     = 0x0d74,/* 32 bit      Tx GMAC FIFO Restart Pointer */
00881         TX_GMF_RLEV     = 0x0d78,/* 32 bit      Tx GMAC FIFO Read Level */
00882 
00883         /* Descriptor Poll Timer Registers */
00884         B28_DPT_INI     = 0x0e00,/* 24 bit      Descriptor Poll Timer Init Val */
00885         B28_DPT_VAL     = 0x0e04,/* 24 bit      Descriptor Poll Timer Curr Val */
00886         B28_DPT_CTRL    = 0x0e08,/*  8 bit      Descriptor Poll Timer Ctrl Reg */
00887 
00888         B28_DPT_TST     = 0x0e0a,/*  8 bit      Descriptor Poll Timer Test Reg */
00889 
00890         /* Time Stamp Timer Registers (YUKON only) */
00891         GMAC_TI_ST_VAL  = 0x0e14,/* 32 bit      Time Stamp Timer Curr Val */
00892         GMAC_TI_ST_CTRL = 0x0e18,/*  8 bit      Time Stamp Timer Ctrl Reg */
00893         GMAC_TI_ST_TST  = 0x0e1a,/*  8 bit      Time Stamp Timer Test Reg */
00894 };
00895 
00896 
00897 enum {
00898         LINKLED_OFF          = 0x01,
00899         LINKLED_ON           = 0x02,
00900         LINKLED_LINKSYNC_OFF = 0x04,
00901         LINKLED_LINKSYNC_ON  = 0x08,
00902         LINKLED_BLINK_OFF    = 0x10,
00903         LINKLED_BLINK_ON     = 0x20,
00904 };
00905 
00906 /* GMAC and GPHY Control Registers (YUKON only) */
00907 enum {
00908         GMAC_CTRL       = 0x0f00,/* 32 bit      GMAC Control Reg */
00909         GPHY_CTRL       = 0x0f04,/* 32 bit      GPHY Control Reg */
00910         GMAC_IRQ_SRC    = 0x0f08,/*  8 bit      GMAC Interrupt Source Reg */
00911         GMAC_IRQ_MSK    = 0x0f0c,/*  8 bit      GMAC Interrupt Mask Reg */
00912         GMAC_LINK_CTRL  = 0x0f10,/* 16 bit      Link Control Reg */
00913 
00914 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
00915 
00916         WOL_REG_OFFS    = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
00917 
00918         WOL_CTRL_STAT   = 0x0f20,/* 16 bit      WOL Control/Status Reg */
00919         WOL_MATCH_CTL   = 0x0f22,/*  8 bit      WOL Match Control Reg */
00920         WOL_MATCH_RES   = 0x0f23,/*  8 bit      WOL Match Result Reg */
00921         WOL_MAC_ADDR    = 0x0f24,/* 32 bit      WOL MAC Address */
00922         WOL_PATT_RPTR   = 0x0f2c,/*  8 bit      WOL Pattern Read Pointer */
00923 
00924 /* WOL Pattern Length Registers (YUKON only) */
00925 
00926         WOL_PATT_LEN_LO = 0x0f30,/* 32 bit      WOL Pattern Length 3..0 */
00927         WOL_PATT_LEN_HI = 0x0f34,/* 24 bit      WOL Pattern Length 6..4 */
00928 
00929 /* WOL Pattern Counter Registers (YUKON only) */
00930 
00931         WOL_PATT_CNT_0  = 0x0f38,/* 32 bit      WOL Pattern Counter 3..0 */
00932         WOL_PATT_CNT_4  = 0x0f3c,/* 24 bit      WOL Pattern Counter 6..4 */
00933 };
00934 #define WOL_REGS(port, x)       (x + (port)*0x80)
00935 
00936 enum {
00937         WOL_PATT_RAM_1  = 0x1000,/*  WOL Pattern RAM Link 1 */
00938         WOL_PATT_RAM_2  = 0x1400,/*  WOL Pattern RAM Link 2 */
00939 };
00940 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
00941 
00942 enum {
00943         BASE_XMAC_1     = 0x2000,/* XMAC 1 registers */
00944         BASE_GMAC_1     = 0x2800,/* GMAC 1 registers */
00945         BASE_XMAC_2     = 0x3000,/* XMAC 2 registers */
00946         BASE_GMAC_2     = 0x3800,/* GMAC 2 registers */
00947 };
00948 
00949 /*
00950  * Receive Frame Status Encoding
00951  */
00952 enum {
00953         XMR_FS_LEN      = 0x3fff<<18,   /* Bit 31..18:  Rx Frame Length */
00954         XMR_FS_LEN_SHIFT = 18,
00955         XMR_FS_2L_VLAN  = 1<<17, /* Bit 17:     tagged wh 2Lev VLAN ID*/
00956         XMR_FS_1_VLAN   = 1<<16, /* Bit 16:     tagged wh 1ev VLAN ID*/
00957         XMR_FS_BC       = 1<<15, /* Bit 15:     Broadcast Frame */
00958         XMR_FS_MC       = 1<<14, /* Bit 14:     Multicast Frame */
00959         XMR_FS_UC       = 1<<13, /* Bit 13:     Unicast Frame */
00960 
00961         XMR_FS_BURST    = 1<<11, /* Bit 11:     Burst Mode */
00962         XMR_FS_CEX_ERR  = 1<<10, /* Bit 10:     Carrier Ext. Error */
00963         XMR_FS_802_3    = 1<<9, /* Bit  9:      802.3 Frame */
00964         XMR_FS_COL_ERR  = 1<<8, /* Bit  8:      Collision Error */
00965         XMR_FS_CAR_ERR  = 1<<7, /* Bit  7:      Carrier Event Error */
00966         XMR_FS_LEN_ERR  = 1<<6, /* Bit  6:      In-Range Length Error */
00967         XMR_FS_FRA_ERR  = 1<<5, /* Bit  5:      Framing Error */
00968         XMR_FS_RUNT     = 1<<4, /* Bit  4:      Runt Frame */
00969         XMR_FS_LNG_ERR  = 1<<3, /* Bit  3:      Giant (Jumbo) Frame */
00970         XMR_FS_FCS_ERR  = 1<<2, /* Bit  2:      Frame Check Sequ Err */
00971         XMR_FS_ERR      = 1<<1, /* Bit  1:      Frame Error */
00972         XMR_FS_MCTRL    = 1<<0, /* Bit  0:      MAC Control Packet */
00973 
00974 /*
00975  * XMR_FS_ERR will be set if
00976  *      XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
00977  *      XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
00978  * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
00979  * XMR_FS_ERR unless the corresponding bit in the Receive Command
00980  * Register is set.
00981  */
00982 };
00983 
00984 /*
00985 ,* XMAC-PHY Registers, indirect addressed over the XMAC
00986  */
00987 enum {
00988         PHY_XMAC_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
00989         PHY_XMAC_STAT           = 0x01,/* 16 bit r/w    PHY Status Register */
00990         PHY_XMAC_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
00991         PHY_XMAC_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
00992         PHY_XMAC_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
00993         PHY_XMAC_AUNE_LP        = 0x05,/* 16 bit r/o    Link Partner Abi Reg */
00994         PHY_XMAC_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
00995         PHY_XMAC_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
00996         PHY_XMAC_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
00997 
00998         PHY_XMAC_EXT_STAT       = 0x0f,/* 16 bit r/o    Ext Status Register */
00999         PHY_XMAC_RES_ABI        = 0x10,/* 16 bit r/o    PHY Resolved Ability */
01000 };
01001 /*
01002  * Broadcom-PHY Registers, indirect addressed over XMAC
01003  */
01004 enum {
01005         PHY_BCOM_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
01006         PHY_BCOM_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
01007         PHY_BCOM_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
01008         PHY_BCOM_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
01009         PHY_BCOM_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
01010         PHY_BCOM_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
01011         PHY_BCOM_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
01012         PHY_BCOM_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
01013         PHY_BCOM_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
01014         /* Broadcom-specific registers */
01015         PHY_BCOM_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
01016         PHY_BCOM_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
01017         PHY_BCOM_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
01018         PHY_BCOM_P_EXT_CTRL     = 0x10,/* 16 bit r/w    PHY Extended Ctrl Reg */
01019         PHY_BCOM_P_EXT_STAT     = 0x11,/* 16 bit r/o    PHY Extended Stat Reg */
01020         PHY_BCOM_RE_CTR         = 0x12,/* 16 bit r/w    Receive Error Counter */
01021         PHY_BCOM_FC_CTR         = 0x13,/* 16 bit r/w    False Carrier Sense Cnt */
01022         PHY_BCOM_RNO_CTR        = 0x14,/* 16 bit r/w    Receiver NOT_OK Cnt */
01023 
01024         PHY_BCOM_AUX_CTRL       = 0x18,/* 16 bit r/w    Auxiliary Control Reg */
01025         PHY_BCOM_AUX_STAT       = 0x19,/* 16 bit r/o    Auxiliary Stat Summary */
01026         PHY_BCOM_INT_STAT       = 0x1a,/* 16 bit r/o    Interrupt Status Reg */
01027         PHY_BCOM_INT_MASK       = 0x1b,/* 16 bit r/w    Interrupt Mask Reg */
01028 };
01029 
01030 /*
01031  * Marvel-PHY Registers, indirect addressed over GMAC
01032  */
01033 enum {
01034         PHY_MARV_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
01035         PHY_MARV_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
01036         PHY_MARV_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
01037         PHY_MARV_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
01038         PHY_MARV_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
01039         PHY_MARV_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
01040         PHY_MARV_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
01041         PHY_MARV_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
01042         PHY_MARV_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
01043         /* Marvel-specific registers */
01044         PHY_MARV_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
01045         PHY_MARV_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
01046         PHY_MARV_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
01047         PHY_MARV_PHY_CTRL       = 0x10,/* 16 bit r/w    PHY Specific Ctrl Reg */
01048         PHY_MARV_PHY_STAT       = 0x11,/* 16 bit r/o    PHY Specific Stat Reg */
01049         PHY_MARV_INT_MASK       = 0x12,/* 16 bit r/w    Interrupt Mask Reg */
01050         PHY_MARV_INT_STAT       = 0x13,/* 16 bit r/o    Interrupt Status Reg */
01051         PHY_MARV_EXT_CTRL       = 0x14,/* 16 bit r/w    Ext. PHY Specific Ctrl */
01052         PHY_MARV_RXE_CNT        = 0x15,/* 16 bit r/w    Receive Error Counter */
01053         PHY_MARV_EXT_ADR        = 0x16,/* 16 bit r/w    Ext. Ad. for Cable Diag. */
01054         PHY_MARV_PORT_IRQ       = 0x17,/* 16 bit r/o    Port 0 IRQ (88E1111 only) */
01055         PHY_MARV_LED_CTRL       = 0x18,/* 16 bit r/w    LED Control Reg */
01056         PHY_MARV_LED_OVER       = 0x19,/* 16 bit r/w    Manual LED Override Reg */
01057         PHY_MARV_EXT_CTRL_2     = 0x1a,/* 16 bit r/w    Ext. PHY Specific Ctrl 2 */
01058         PHY_MARV_EXT_P_STAT     = 0x1b,/* 16 bit r/w    Ext. PHY Spec. Stat Reg */
01059         PHY_MARV_CABLE_DIAG     = 0x1c,/* 16 bit r/o    Cable Diagnostic Reg */
01060         PHY_MARV_PAGE_ADDR      = 0x1d,/* 16 bit r/w    Extended Page Address Reg */
01061         PHY_MARV_PAGE_DATA      = 0x1e,/* 16 bit r/w    Extended Page Data Reg */
01062 
01063 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
01064         PHY_MARV_FE_LED_PAR     = 0x16,/* 16 bit r/w    LED Parallel Select Reg. */
01065         PHY_MARV_FE_LED_SER     = 0x17,/* 16 bit r/w    LED Stream Select S. LED */
01066         PHY_MARV_FE_VCT_TX      = 0x1a,/* 16 bit r/w    VCT Reg. for TXP/N Pins */
01067         PHY_MARV_FE_VCT_RX      = 0x1b,/* 16 bit r/o    VCT Reg. for RXP/N Pins */
01068         PHY_MARV_FE_SPEC_2      = 0x1c,/* 16 bit r/w    Specific Control Reg. 2 */
01069 };
01070 
01071 enum {
01072         PHY_CT_RESET    = 1<<15, /* Bit 15: (sc)        clear all PHY related regs */
01073         PHY_CT_LOOP     = 1<<14, /* Bit 14:     enable Loopback over PHY */
01074         PHY_CT_SPS_LSB  = 1<<13, /* Bit 13:     Speed select, lower bit */
01075         PHY_CT_ANE      = 1<<12, /* Bit 12:     Auto-Negotiation Enabled */
01076         PHY_CT_PDOWN    = 1<<11, /* Bit 11:     Power Down Mode */
01077         PHY_CT_ISOL     = 1<<10, /* Bit 10:     Isolate Mode */
01078         PHY_CT_RE_CFG   = 1<<9, /* Bit  9:      (sc) Restart Auto-Negotiation */
01079         PHY_CT_DUP_MD   = 1<<8, /* Bit  8:      Duplex Mode */
01080         PHY_CT_COL_TST  = 1<<7, /* Bit  7:      Collision Test enabled */
01081         PHY_CT_SPS_MSB  = 1<<6, /* Bit  6:      Speed select, upper bit */
01082 };
01083 
01084 enum {
01085         PHY_CT_SP1000   = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
01086         PHY_CT_SP100    = PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
01087         PHY_CT_SP10     = 0,              /* enable speed of   10 Mbps */
01088 };
01089 
01090 enum {
01091         PHY_ST_EXT_ST   = 1<<8, /* Bit  8:      Extended Status Present */
01092 
01093         PHY_ST_PRE_SUP  = 1<<6, /* Bit  6:      Preamble Suppression */
01094         PHY_ST_AN_OVER  = 1<<5, /* Bit  5:      Auto-Negotiation Over */
01095         PHY_ST_REM_FLT  = 1<<4, /* Bit  4:      Remote Fault Condition Occurred */
01096         PHY_ST_AN_CAP   = 1<<3, /* Bit  3:      Auto-Negotiation Capability */
01097         PHY_ST_LSYNC    = 1<<2, /* Bit  2:      Link Synchronized */
01098         PHY_ST_JAB_DET  = 1<<1, /* Bit  1:      Jabber Detected */
01099         PHY_ST_EXT_REG  = 1<<0, /* Bit  0:      Extended Register available */
01100 };
01101 
01102 enum {
01103         PHY_I1_OUI_MSK  = 0x3f<<10, /* Bit 15..10:      Organization Unique ID */
01104         PHY_I1_MOD_NUM  = 0x3f<<4, /* Bit  9.. 4:       Model Number */
01105         PHY_I1_REV_MSK  = 0xf, /* Bit  3.. 0:   Revision Number */
01106 };
01107 
01108 /* different Broadcom PHY Ids */
01109 enum {
01110         PHY_BCOM_ID1_A1 = 0x6041,
01111         PHY_BCOM_ID1_B2 = 0x6043,
01112         PHY_BCOM_ID1_C0 = 0x6044,
01113         PHY_BCOM_ID1_C5 = 0x6047,
01114 };
01115 
01116 /* different Marvell PHY Ids */
01117 enum {
01118         PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
01119         PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
01120         PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
01121         PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
01122         PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
01123 };
01124 
01125 /* Advertisement register bits */
01126 enum {
01127         PHY_AN_NXT_PG   = 1<<15, /* Bit 15:     Request Next Page */
01128         PHY_AN_ACK      = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
01129         PHY_AN_RF       = 1<<13, /* Bit 13:     Remote Fault Bits */
01130 
01131         PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:    Try for asymmetric */
01132         PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:    Try for pause */
01133         PHY_AN_100BASE4 = 1<<9, /* Bit 9:       Try for 100mbps 4k packets */
01134         PHY_AN_100FULL  = 1<<8, /* Bit 8:       Try for 100mbps full-duplex */
01135         PHY_AN_100HALF  = 1<<7, /* Bit 7:       Try for 100mbps half-duplex */
01136         PHY_AN_10FULL   = 1<<6, /* Bit 6:       Try for 10mbps full-duplex */
01137         PHY_AN_10HALF   = 1<<5, /* Bit 5:       Try for 10mbps half-duplex */
01138         PHY_AN_CSMA     = 1<<0, /* Bit 0:       Only selector supported */
01139         PHY_AN_SEL      = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
01140         PHY_AN_FULL     = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
01141         PHY_AN_ALL      = PHY_AN_10HALF | PHY_AN_10FULL |
01142                           PHY_AN_100HALF | PHY_AN_100FULL,
01143 };
01144 
01145 /* Xmac Specific */
01146 enum {
01147         PHY_X_AN_NXT_PG = 1<<15, /* Bit 15:     Request Next Page */
01148         PHY_X_AN_ACK    = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
01149         PHY_X_AN_RFB    = 3<<12,/* Bit 13..12:  Remote Fault Bits */
01150 
01151         PHY_X_AN_PAUSE  = 3<<7,/* Bit  8.. 7:   Pause Bits */
01152         PHY_X_AN_HD     = 1<<6, /* Bit  6:      Half Duplex */
01153         PHY_X_AN_FD     = 1<<5, /* Bit  5:      Full Duplex */
01154 };
01155 
01156 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
01157 enum {
01158         PHY_X_P_NO_PAUSE= 0<<7,/* Bit  8..7:    no Pause Mode */
01159         PHY_X_P_SYM_MD  = 1<<7, /* Bit  8..7:   symmetric Pause Mode */
01160         PHY_X_P_ASYM_MD = 2<<7,/* Bit  8..7:    asymmetric Pause Mode */
01161         PHY_X_P_BOTH_MD = 3<<7,/* Bit  8..7:    both Pause Mode */
01162 };
01163 
01164 
01165 /*****  PHY_XMAC_EXT_STAT       16 bit r/w      Extended Status Register *****/
01166 enum {
01167         PHY_X_EX_FD     = 1<<15, /* Bit 15:     Device Supports Full Duplex */
01168         PHY_X_EX_HD     = 1<<14, /* Bit 14:     Device Supports Half Duplex */
01169 };
01170 
01171 /*****  PHY_XMAC_RES_ABI        16 bit r/o      PHY Resolved Ability *****/
01172 enum {
01173         PHY_X_RS_PAUSE  = 3<<7, /* Bit  8..7:   selected Pause Mode */
01174         PHY_X_RS_HD     = 1<<6, /* Bit  6:      Half Duplex Mode selected */
01175         PHY_X_RS_FD     = 1<<5, /* Bit  5:      Full Duplex Mode selected */
01176         PHY_X_RS_ABLMIS = 1<<4, /* Bit  4:      duplex or pause cap mismatch */
01177         PHY_X_RS_PAUMIS = 1<<3, /* Bit  3:      pause capability mismatch */
01178 };
01179 
01180 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
01181 enum {
01182         X_RFB_OK        = 0<<12,/* Bit 13..12   No errors, Link OK */
01183         X_RFB_LF        = 1<<12,/* Bit 13..12   Link Failure */
01184         X_RFB_OFF       = 2<<12,/* Bit 13..12   Offline */
01185         X_RFB_AN_ERR    = 3<<12,/* Bit 13..12   Auto-Negotiation Error */
01186 };
01187 
01188 /* Broadcom-Specific */
01189 /*****  PHY_BCOM_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
01190 enum {
01191         PHY_B_1000C_TEST        = 7<<13,/* Bit 15..13:  Test Modes */
01192         PHY_B_1000C_MSE = 1<<12, /* Bit 12:     Master/Slave Enable */
01193         PHY_B_1000C_MSC = 1<<11, /* Bit 11:     M/S Configuration */
01194         PHY_B_1000C_RD  = 1<<10, /* Bit 10:     Repeater/DTE */
01195         PHY_B_1000C_AFD = 1<<9, /* Bit  9:      Advertise Full Duplex */
01196         PHY_B_1000C_AHD = 1<<8, /* Bit  8:      Advertise Half Duplex */
01197 };
01198 
01199 /*****  PHY_BCOM_1000T_STAT     16 bit r/o      1000Base-T Status Reg *****/
01200 /*****  PHY_MARV_1000T_STAT     16 bit r/o      1000Base-T Status Reg *****/
01201 enum {
01202         PHY_B_1000S_MSF = 1<<15, /* Bit 15:     Master/Slave Fault */
01203         PHY_B_1000S_MSR = 1<<14, /* Bit 14:     Master/Slave Result */
01204         PHY_B_1000S_LRS = 1<<13, /* Bit 13:     Local Receiver Status */
01205         PHY_B_1000S_RRS = 1<<12, /* Bit 12:     Remote Receiver Status */
01206         PHY_B_1000S_LP_FD       = 1<<11, /* Bit 11:     Link Partner can FD */
01207         PHY_B_1000S_LP_HD       = 1<<10, /* Bit 10:     Link Partner can HD */
01208                                                                         /* Bit  9..8:   reserved */
01209         PHY_B_1000S_IEC = 0xff, /* Bit  7..0:   Idle Error Count */
01210 };
01211 
01212 /*****  PHY_BCOM_EXT_STAT       16 bit r/o      Extended Status Register *****/
01213 enum {
01214         PHY_B_ES_X_FD_CAP       = 1<<15, /* Bit 15:     1000Base-X FD capable */
01215         PHY_B_ES_X_HD_CAP       = 1<<14, /* Bit 14:     1000Base-X HD capable */
01216         PHY_B_ES_T_FD_CAP       = 1<<13, /* Bit 13:     1000Base-T FD capable */
01217         PHY_B_ES_T_HD_CAP       = 1<<12, /* Bit 12:     1000Base-T HD capable */
01218 };
01219 
01220 /*****  PHY_BCOM_P_EXT_CTRL     16 bit r/w      PHY Extended Control Reg *****/
01221 enum {
01222         PHY_B_PEC_MAC_PHY       = 1<<15, /* Bit 15:     10BIT/GMI-Interface */
01223         PHY_B_PEC_DIS_CROSS     = 1<<14, /* Bit 14:     Disable MDI Crossover */
01224         PHY_B_PEC_TX_DIS        = 1<<13, /* Bit 13:     Tx output Disabled */
01225         PHY_B_PEC_INT_DIS       = 1<<12, /* Bit 12:     Interrupts Disabled */
01226         PHY_B_PEC_F_INT = 1<<11, /* Bit 11:     Force Interrupt */
01227         PHY_B_PEC_BY_45 = 1<<10, /* Bit 10:     Bypass 4B5B-Decoder */
01228         PHY_B_PEC_BY_SCR        = 1<<9, /* Bit  9:      Bypass Scrambler */
01229         PHY_B_PEC_BY_MLT3       = 1<<8, /* Bit  8:      Bypass MLT3 Encoder */
01230         PHY_B_PEC_BY_RXA        = 1<<7, /* Bit  7:      Bypass Rx Alignm. */
01231         PHY_B_PEC_RES_SCR       = 1<<6, /* Bit  6:      Reset Scrambler */
01232         PHY_B_PEC_EN_LTR        = 1<<5, /* Bit  5:      Ena LED Traffic Mode */
01233         PHY_B_PEC_LED_ON        = 1<<4, /* Bit  4:      Force LED's on */
01234         PHY_B_PEC_LED_OFF       = 1<<3, /* Bit  3:      Force LED's off */
01235         PHY_B_PEC_EX_IPG        = 1<<2, /* Bit  2:      Extend Tx IPG Mode */
01236         PHY_B_PEC_3_LED = 1<<1, /* Bit  1:      Three Link LED mode */
01237         PHY_B_PEC_HIGH_LA       = 1<<0, /* Bit  0:      GMII FIFO Elasticy */
01238 };
01239 
01240 /*****  PHY_BCOM_P_EXT_STAT     16 bit r/o      PHY Extended Status Reg *****/
01241 enum {
01242         PHY_B_PES_CROSS_STAT    = 1<<13, /* Bit 13:     MDI Crossover Status */
01243         PHY_B_PES_INT_STAT      = 1<<12, /* Bit 12:     Interrupt Status */
01244         PHY_B_PES_RRS   = 1<<11, /* Bit 11:     Remote Receiver Stat. */
01245         PHY_B_PES_LRS   = 1<<10, /* Bit 10:     Local Receiver Stat. */
01246         PHY_B_PES_LOCKED        = 1<<9, /* Bit  9:      Locked */
01247         PHY_B_PES_LS    = 1<<8, /* Bit  8:      Link Status */
01248         PHY_B_PES_RF    = 1<<7, /* Bit  7:      Remote Fault */
01249         PHY_B_PES_CE_ER = 1<<6, /* Bit  6:      Carrier Ext Error */
01250         PHY_B_PES_BAD_SSD       = 1<<5, /* Bit  5:      Bad SSD */
01251         PHY_B_PES_BAD_ESD       = 1<<4, /* Bit  4:      Bad ESD */
01252         PHY_B_PES_RX_ER = 1<<3, /* Bit  3:      Receive Error */
01253         PHY_B_PES_TX_ER = 1<<2, /* Bit  2:      Transmit Error */
01254         PHY_B_PES_LOCK_ER       = 1<<1, /* Bit  1:      Lock Error */
01255         PHY_B_PES_MLT3_ER       = 1<<0, /* Bit  0:      MLT3 code Error */
01256 };
01257 
01258 /*  PHY_BCOM_AUNE_ADV   16 bit r/w      Auto-Negotiation Advertisement *****/
01259 /*  PHY_BCOM_AUNE_LP    16 bit r/o      Link Partner Ability Reg *****/
01260 enum {
01261         PHY_B_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
01262 
01263         PHY_B_AN_ASP    = 1<<11, /* Bit 11:     Asymmetric Pause */
01264         PHY_B_AN_PC     = 1<<10, /* Bit 10:     Pause Capable */
01265 };
01266 
01267 
01268 /*****  PHY_BCOM_FC_CTR         16 bit r/w      False Carrier Counter *****/
01269 enum {
01270         PHY_B_FC_CTR    = 0xff, /* Bit  7..0:   False Carrier Counter */
01271 
01272 /*****  PHY_BCOM_RNO_CTR        16 bit r/w      Receive NOT_OK Counter *****/
01273         PHY_B_RC_LOC_MSK        = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
01274         PHY_B_RC_REM_MSK        = 0x00ff, /* Bit  7..0: Remote Rx NOT_OK cnt */
01275 
01276 /*****  PHY_BCOM_AUX_CTRL       16 bit r/w      Auxiliary Control Reg *****/
01277         PHY_B_AC_L_SQE          = 1<<15, /* Bit 15:     Low Squelch */
01278         PHY_B_AC_LONG_PACK      = 1<<14, /* Bit 14:     Rx Long Packets */
01279         PHY_B_AC_ER_CTRL        = 3<<12,/* Bit 13..12:  Edgerate Control */
01280                                                                         /* Bit 11:      reserved */
01281         PHY_B_AC_TX_TST = 1<<10, /* Bit 10:     Tx test bit, always 1 */
01282                                                                         /* Bit  9.. 8:  reserved */
01283         PHY_B_AC_DIS_PRF        = 1<<7, /* Bit  7:      dis part resp filter */
01284                                                                         /* Bit  6:      reserved */
01285         PHY_B_AC_DIS_PM = 1<<5, /* Bit  5:      dis power management */
01286                                                                         /* Bit  4:      reserved */
01287         PHY_B_AC_DIAG   = 1<<3, /* Bit  3:      Diagnostic Mode */
01288 };
01289 
01290 /*****  PHY_BCOM_AUX_STAT       16 bit r/o      Auxiliary Status Reg *****/
01291 enum {
01292         PHY_B_AS_AN_C   = 1<<15, /* Bit 15:     AutoNeg complete */
01293         PHY_B_AS_AN_CA  = 1<<14, /* Bit 14:     AN Complete Ack */
01294         PHY_B_AS_ANACK_D        = 1<<13, /* Bit 13:     AN Ack Detect */
01295         PHY_B_AS_ANAB_D = 1<<12, /* Bit 12:     AN Ability Detect */
01296         PHY_B_AS_NPW    = 1<<11, /* Bit 11:     AN Next Page Wait */
01297         PHY_B_AS_AN_RES_MSK     = 7<<8,/* Bit 10..8:    AN HDC */
01298         PHY_B_AS_PDF    = 1<<7, /* Bit  7:      Parallel Detect. Fault */
01299         PHY_B_AS_RF     = 1<<6, /* Bit  6:      Remote Fault */
01300         PHY_B_AS_ANP_R  = 1<<5, /* Bit  5:      AN Page Received */
01301         PHY_B_AS_LP_ANAB        = 1<<4, /* Bit  4:      LP AN Ability */
01302         PHY_B_AS_LP_NPAB        = 1<<3, /* Bit  3:      LP Next Page Ability */
01303         PHY_B_AS_LS     = 1<<2, /* Bit  2:      Link Status */
01304         PHY_B_AS_PRR    = 1<<1, /* Bit  1:      Pause Resolution-Rx */
01305         PHY_B_AS_PRT    = 1<<0, /* Bit  0:      Pause Resolution-Tx */
01306 };
01307 #define PHY_B_AS_PAUSE_MSK      (PHY_B_AS_PRR | PHY_B_AS_PRT)
01308 
01309 /*****  PHY_BCOM_INT_STAT       16 bit r/o      Interrupt Status Reg *****/
01310 /*****  PHY_BCOM_INT_MASK       16 bit r/w      Interrupt Mask Reg *****/
01311 enum {
01312         PHY_B_IS_PSE    = 1<<14, /* Bit 14:     Pair Swap Error */
01313         PHY_B_IS_MDXI_SC        = 1<<13, /* Bit 13:     MDIX Status Change */
01314         PHY_B_IS_HCT    = 1<<12, /* Bit 12:     counter above 32k */
01315         PHY_B_IS_LCT    = 1<<11, /* Bit 11:     counter above 128 */
01316         PHY_B_IS_AN_PR  = 1<<10, /* Bit 10:     Page Received */
01317         PHY_B_IS_NO_HDCL        = 1<<9, /* Bit  9:      No HCD Link */
01318         PHY_B_IS_NO_HDC = 1<<8, /* Bit  8:      No HCD */
01319         PHY_B_IS_NEG_USHDC      = 1<<7, /* Bit  7:      Negotiated Unsup. HCD */
01320         PHY_B_IS_SCR_S_ER       = 1<<6, /* Bit  6:      Scrambler Sync Error */
01321         PHY_B_IS_RRS_CHANGE     = 1<<5, /* Bit  5:      Remote Rx Stat Change */
01322         PHY_B_IS_LRS_CHANGE     = 1<<4, /* Bit  4:      Local Rx Stat Change */
01323         PHY_B_IS_DUP_CHANGE     = 1<<3, /* Bit  3:      Duplex Mode Change */
01324         PHY_B_IS_LSP_CHANGE     = 1<<2, /* Bit  2:      Link Speed Change */
01325         PHY_B_IS_LST_CHANGE     = 1<<1, /* Bit  1:      Link Status Changed */
01326         PHY_B_IS_CRC_ER = 1<<0, /* Bit  0:      CRC Error */
01327 };
01328 #define PHY_B_DEF_MSK   \
01329         (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
01330             PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
01331 
01332 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
01333 enum {
01334         PHY_B_P_NO_PAUSE        = 0<<10,/* Bit 11..10:  no Pause Mode */
01335         PHY_B_P_SYM_MD  = 1<<10, /* Bit 11..10: symmetric Pause Mode */
01336         PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10:  asymmetric Pause Mode */
01337         PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10:  both Pause Mode */
01338 };
01339 /*
01340  * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
01341  */
01342 enum {
01343         PHY_B_RES_1000FD        = 7<<8,/* Bit 10..8:    1000Base-T Full Dup. */
01344         PHY_B_RES_1000HD        = 6<<8,/* Bit 10..8:    1000Base-T Half Dup. */
01345 };
01346 
01347 /** Marvell-Specific */
01348 enum {
01349         PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
01350         PHY_M_AN_ACK    = 1<<14, /* (ro)        Acknowledge Received */
01351         PHY_M_AN_RF     = 1<<13, /* Remote Fault */
01352 
01353         PHY_M_AN_ASP    = 1<<11, /* Asymmetric Pause */
01354         PHY_M_AN_PC     = 1<<10, /* MAC Pause implemented */
01355         PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
01356         PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
01357         PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
01358         PHY_M_AN_10_FD  = 1<<6, /* Advertise 10Base-TX Full Duplex */
01359         PHY_M_AN_10_HD  = 1<<5, /* Advertise 10Base-TX Half Duplex */
01360         PHY_M_AN_SEL_MSK =0x1f<<4,      /* Bit  4.. 0: Selector Field Mask */
01361 };
01362 
01363 /* special defines for FIBER (88E1011S only) */
01364 enum {
01365         PHY_M_AN_ASP_X          = 1<<8, /* Asymmetric Pause */
01366         PHY_M_AN_PC_X           = 1<<7, /* MAC Pause implemented */
01367         PHY_M_AN_1000X_AHD      = 1<<6, /* Advertise 10000Base-X Half Duplex */
01368         PHY_M_AN_1000X_AFD      = 1<<5, /* Advertise 10000Base-X Full Duplex */
01369 };
01370 
01371 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
01372 enum {
01373         PHY_M_P_NO_PAUSE_X      = 0<<7,/* Bit  8.. 7:   no Pause Mode */
01374         PHY_M_P_SYM_MD_X        = 1<<7, /* Bit  8.. 7:  symmetric Pause Mode */
01375         PHY_M_P_ASYM_MD_X       = 2<<7,/* Bit  8.. 7:   asymmetric Pause Mode */
01376         PHY_M_P_BOTH_MD_X       = 3<<7,/* Bit  8.. 7:   both Pause Mode */
01377 };
01378 
01379 /*****  PHY_MARV_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
01380 enum {
01381         PHY_M_1000C_TEST= 7<<13,/* Bit 15..13:  Test Modes */
01382         PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
01383         PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
01384         PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
01385         PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
01386         PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
01387 };
01388 
01389 /*****  PHY_MARV_PHY_CTRL       16 bit r/w      PHY Specific Ctrl Reg *****/
01390 enum {
01391         PHY_M_PC_TX_FFD_MSK     = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
01392         PHY_M_PC_RX_FFD_MSK     = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
01393         PHY_M_PC_ASS_CRS_TX     = 1<<11, /* Assert CRS on Transmit */
01394         PHY_M_PC_FL_GOOD        = 1<<10, /* Force Link Good */
01395         PHY_M_PC_EN_DET_MSK     = 3<<8,/* Bit  9.. 8: Energy Detect Mask */
01396         PHY_M_PC_ENA_EXT_D      = 1<<7, /* Enable Ext. Distance (10BT) */
01397         PHY_M_PC_MDIX_MSK       = 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
01398         PHY_M_PC_DIS_125CLK     = 1<<4, /* Disable 125 CLK */
01399         PHY_M_PC_MAC_POW_UP     = 1<<3, /* MAC Power up */
01400         PHY_M_PC_SQE_T_ENA      = 1<<2, /* SQE Test Enabled */
01401         PHY_M_PC_POL_R_DIS      = 1<<1, /* Polarity Reversal Disabled */
01402         PHY_M_PC_DIS_JABBER     = 1<<0, /* Disable Jabber */
01403 };
01404 
01405 enum {
01406         PHY_M_PC_EN_DET         = 2<<8, /* Energy Detect (Mode 1) */
01407         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
01408 };
01409 
01410 enum {
01411         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
01412         PHY_M_PC_MAN_MDIX       = 1, /* 01 = Manual MDIX configuration */
01413         PHY_M_PC_ENA_AUTO       = 3, /* 11 = Enable Automatic Crossover */
01414 };
01415 
01416 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
01417 enum {
01418         PHY_M_PC_ENA_DTE_DT     = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
01419         PHY_M_PC_ENA_ENE_DT     = 1<<14, /* Enable Energy Detect (sense & pulse) */
01420         PHY_M_PC_DIS_NLP_CK     = 1<<13, /* Disable Normal Link Puls (NLP) Check */
01421         PHY_M_PC_ENA_LIP_NP     = 1<<12, /* Enable Link Partner Next Page Reg. */
01422         PHY_M_PC_DIS_NLP_GN     = 1<<11, /* Disable Normal Link Puls Generation */
01423 
01424         PHY_M_PC_DIS_SCRAMB     = 1<<9, /* Disable Scrambler */
01425         PHY_M_PC_DIS_FEFI       = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
01426 
01427         PHY_M_PC_SH_TP_SEL      = 1<<6, /* Shielded Twisted Pair Select */
01428         PHY_M_PC_RX_FD_MSK      = 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
01429 };
01430 
01431 /*****  PHY_MARV_PHY_STAT       16 bit r/o      PHY Specific Status Reg *****/
01432 enum {
01433         PHY_M_PS_SPEED_MSK      = 3<<14, /* Bit 15..14: Speed Mask */
01434         PHY_M_PS_SPEED_1000     = 1<<15, /*             10 = 1000 Mbps */
01435         PHY_M_PS_SPEED_100      = 1<<14, /*             01 =  100 Mbps */
01436         PHY_M_PS_SPEED_10       = 0,     /*             00 =   10 Mbps */
01437         PHY_M_PS_FULL_DUP       = 1<<13, /* Full Duplex */
01438         PHY_M_PS_PAGE_REC       = 1<<12, /* Page Received */
01439         PHY_M_PS_SPDUP_RES      = 1<<11, /* Speed & Duplex Resolved */
01440         PHY_M_PS_LINK_UP        = 1<<10, /* Link Up */
01441         PHY_M_PS_CABLE_MSK      = 7<<7,  /* Bit  9.. 7: Cable Length Mask */
01442         PHY_M_PS_MDI_X_STAT     = 1<<6,  /* MDI Crossover Stat (1=MDIX) */
01443         PHY_M_PS_DOWNS_STAT     = 1<<5,  /* Downshift Status (1=downsh.) */
01444         PHY_M_PS_ENDET_STAT     = 1<<4,  /* Energy Detect Status (1=act) */
01445         PHY_M_PS_TX_P_EN        = 1<<3,  /* Tx Pause Enabled */
01446         PHY_M_PS_RX_P_EN        = 1<<2,  /* Rx Pause Enabled */
01447         PHY_M_PS_POL_REV        = 1<<1,  /* Polarity Reversed */
01448         PHY_M_PS_JABBER         = 1<<0,  /* Jabber */
01449 };
01450 
01451 #define PHY_M_PS_PAUSE_MSK      (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
01452 
01453 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
01454 enum {
01455         PHY_M_PS_DTE_DETECT     = 1<<15, /* Data Terminal Equipment (DTE) Detected */
01456         PHY_M_PS_RES_SPEED      = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
01457 };
01458 
01459 enum {
01460         PHY_M_IS_AN_ERROR       = 1<<15, /* Auto-Negotiation Error */
01461         PHY_M_IS_LSP_CHANGE     = 1<<14, /* Link Speed Changed */
01462         PHY_M_IS_DUP_CHANGE     = 1<<13, /* Duplex Mode Changed */
01463         PHY_M_IS_AN_PR          = 1<<12, /* Page Received */
01464         PHY_M_IS_AN_COMPL       = 1<<11, /* Auto-Negotiation Completed */
01465         PHY_M_IS_LST_CHANGE     = 1<<10, /* Link Status Changed */
01466         PHY_M_IS_SYMB_ERROR     = 1<<9, /* Symbol Error */
01467         PHY_M_IS_FALSE_CARR     = 1<<8, /* False Carrier */
01468         PHY_M_IS_FIFO_ERROR     = 1<<7, /* FIFO Overflow/Underrun Error */
01469         PHY_M_IS_MDI_CHANGE     = 1<<6, /* MDI Crossover Changed */
01470         PHY_M_IS_DOWNSH_DET     = 1<<5, /* Downshift Detected */
01471         PHY_M_IS_END_CHANGE     = 1<<4, /* Energy Detect Changed */
01472 
01473         PHY_M_IS_DTE_CHANGE     = 1<<2, /* DTE Power Det. Status Changed */
01474         PHY_M_IS_POL_CHANGE     = 1<<1, /* Polarity Changed */
01475         PHY_M_IS_JABBER         = 1<<0, /* Jabber */
01476 
01477         PHY_M_IS_DEF_MSK        = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
01478                                   PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
01479 
01480         PHY_M_IS_AN_MSK         = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
01481 };
01482 
01483 /*****  PHY_MARV_EXT_CTRL       16 bit r/w      Ext. PHY Specific Ctrl *****/
01484 enum {
01485         PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
01486         PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
01487 
01488         PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
01489         PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:     Master Downshift Counter */
01490                                         /* (88E1011 only) */
01491         PHY_M_EC_S_DSC_MSK  = 3<<8,  /* Bit  9.. 8:     Slave  Downshift Counter */
01492                                        /* (88E1011 only) */
01493         PHY_M_EC_M_DSC_MSK2  = 7<<9, /* Bit 11.. 9:     Master Downshift Counter */
01494                                         /* (88E1111 only) */
01495         PHY_M_EC_DOWN_S_ENA  = 1<<8, /* Downshift Enable (88E1111 only) */
01496                                         /* !!! Errata in spec. (1 = disable) */
01497         PHY_M_EC_RX_TIM_CT   = 1<<7, /* RGMII Rx Timing Control*/
01498         PHY_M_EC_MAC_S_MSK   = 7<<4, /* Bit  6.. 4:     Def. MAC interface speed */
01499         PHY_M_EC_FIB_AN_ENA  = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
01500         PHY_M_EC_DTE_D_ENA   = 1<<2, /* DTE Detect Enable (88E1111 only) */
01501         PHY_M_EC_TX_TIM_CT   = 1<<1, /* RGMII Tx Timing Control */
01502         PHY_M_EC_TRANS_DIS   = 1<<0, /* Transmitter Disable (88E1111 only) */};
01503 
01504 #define PHY_M_EC_M_DSC(x)       ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
01505 #define PHY_M_EC_S_DSC(x)       ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
01506 #define PHY_M_EC_MAC_S(x)       ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
01507 
01508 #define PHY_M_EC_M_DSC_2(x)     ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
01509                                                                                         /* 100=5x; 101=6x; 110=7x; 111=8x */
01510 enum {
01511         MAC_TX_CLK_0_MHZ        = 2,
01512         MAC_TX_CLK_2_5_MHZ      = 6,
01513         MAC_TX_CLK_25_MHZ       = 7,
01514 };
01515 
01516 /*****  PHY_MARV_LED_CTRL       16 bit r/w      LED Control Reg *****/
01517 enum {
01518         PHY_M_LEDC_DIS_LED      = 1<<15, /* Disable LED */
01519         PHY_M_LEDC_PULS_MSK     = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
01520         PHY_M_LEDC_F_INT        = 1<<11, /* Force Interrupt */
01521         PHY_M_LEDC_BL_R_MSK     = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
01522         PHY_M_LEDC_DP_C_LSB     = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
01523         PHY_M_LEDC_TX_C_LSB     = 1<<6, /* Tx Control (LSB, 88E1111 only) */
01524         PHY_M_LEDC_LK_C_MSK     = 7<<3,/* Bit  5.. 3: Link Control Mask */
01525                                         /* (88E1111 only) */
01526 };
01527 #define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
01528 #define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
01529 
01530 enum {
01531         PHY_M_LEDC_LINK_MSK     = 3<<3, /* Bit  4.. 3: Link Control Mask */
01532                                         /* (88E1011 only) */
01533         PHY_M_LEDC_DP_CTRL      = 1<<2, /* Duplex Control */
01534         PHY_M_LEDC_DP_C_MSB     = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
01535         PHY_M_LEDC_RX_CTRL      = 1<<1, /* Rx Activity / Link */
01536         PHY_M_LEDC_TX_CTRL      = 1<<0, /* Tx Activity / Link */
01537         PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
01538 };
01539 
01540 enum {
01541         PULS_NO_STR     = 0, /* no pulse stretching */
01542         PULS_21MS       = 1, /* 21 ms to 42 ms */
01543         PULS_42MS       = 2, /* 42 ms to 84 ms */
01544         PULS_84MS       = 3, /* 84 ms to 170 ms */
01545         PULS_170MS      = 4, /* 170 ms to 340 ms */
01546         PULS_340MS      = 5, /* 340 ms to 670 ms */
01547         PULS_670MS      = 6, /* 670 ms to 1.3 s */
01548         PULS_1300MS     = 7, /* 1.3 s to 2.7 s */
01549 };
01550 
01551 
01552 enum {
01553         BLINK_42MS      = 0, /* 42 ms */
01554         BLINK_84MS      = 1, /* 84 ms */
01555         BLINK_170MS     = 2, /* 170 ms */
01556         BLINK_340MS     = 3, /* 340 ms */
01557         BLINK_670MS     = 4, /* 670 ms */
01558 };
01559 
01560 /*****  PHY_MARV_LED_OVER       16 bit r/w      Manual LED Override Reg *****/
01561 #define PHY_M_LED_MO_SGMII(x)   ((x)<<14) /* Bit 15..14:  SGMII AN Timer */
01562                                                                                 /* Bit 13..12:  reserved */
01563 #define PHY_M_LED_MO_DUP(x)     ((x)<<10) /* Bit 11..10:  Duplex */
01564 #define PHY_M_LED_MO_10(x)      ((x)<<8) /* Bit  9.. 8:  Link 10 */
01565 #define PHY_M_LED_MO_100(x)     ((x)<<6) /* Bit  7.. 6:  Link 100 */
01566 #define PHY_M_LED_MO_1000(x)    ((x)<<4) /* Bit  5.. 4:  Link 1000 */
01567 #define PHY_M_LED_MO_RX(x)      ((x)<<2) /* Bit  3.. 2:  Rx */
01568 #define PHY_M_LED_MO_TX(x)      ((x)<<0) /* Bit  1.. 0:  Tx */
01569 
01570 enum {
01571         MO_LED_NORM     = 0,
01572         MO_LED_BLINK    = 1,
01573         MO_LED_OFF      = 2,
01574         MO_LED_ON       = 3,
01575 };
01576 
01577 /*****  PHY_MARV_EXT_CTRL_2     16 bit r/w      Ext. PHY Specific Ctrl 2 *****/
01578 enum {
01579         PHY_M_EC2_FI_IMPED      = 1<<6, /* Fiber Input  Impedance */
01580         PHY_M_EC2_FO_IMPED      = 1<<5, /* Fiber Output Impedance */
01581         PHY_M_EC2_FO_M_CLK      = 1<<4, /* Fiber Mode Clock Enable */
01582         PHY_M_EC2_FO_BOOST      = 1<<3, /* Fiber Output Boost */
01583         PHY_M_EC2_FO_AM_MSK     = 7, /* Bit  2.. 0:     Fiber Output Amplitude */
01584 };
01585 
01586 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
01587 enum {
01588         PHY_M_FC_AUTO_SEL       = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
01589         PHY_M_FC_AN_REG_ACC     = 1<<14, /* Fiber/Copper AN Reg. Access */
01590         PHY_M_FC_RESOLUTION     = 1<<13, /* Fiber/Copper Resolution */
01591         PHY_M_SER_IF_AN_BP      = 1<<12, /* Ser. IF AN Bypass Enable */
01592         PHY_M_SER_IF_BP_ST      = 1<<11, /* Ser. IF AN Bypass Status */
01593         PHY_M_IRQ_POLARITY      = 1<<10, /* IRQ polarity */
01594         PHY_M_DIS_AUT_MED       = 1<<9, /* Disable Aut. Medium Reg. Selection */
01595                                                                         /* (88E1111 only) */
01596                                                                 /* Bit  9.. 4: reserved (88E1011 only) */
01597         PHY_M_UNDOC1    = 1<<7, /* undocumented bit !! */
01598         PHY_M_DTE_POW_STAT      = 1<<4, /* DTE Power Status (88E1111 only) */
01599         PHY_M_MODE_MASK = 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
01600 };
01601 
01602 /*****  PHY_MARV_CABLE_DIAG     16 bit r/o      Cable Diagnostic Reg *****/
01603 enum {
01604         PHY_M_CABD_ENA_TEST     = 1<<15, /* Enable Test (Page 0) */
01605         PHY_M_CABD_DIS_WAIT     = 1<<15, /* Disable Waiting Period (Page 1) */
01606                                         /* (88E1111 only) */
01607         PHY_M_CABD_STAT_MSK     = 3<<13, /* Bit 14..13: Status Mask */
01608         PHY_M_CABD_AMPL_MSK     = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
01609                                         /* (88E1111 only) */
01610         PHY_M_CABD_DIST_MSK     = 0xff, /* Bit  7.. 0: Distance Mask */
01611 };
01612 
01613 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
01614 enum {
01615         CABD_STAT_NORMAL= 0,
01616         CABD_STAT_SHORT = 1,
01617         CABD_STAT_OPEN  = 2,
01618         CABD_STAT_FAIL  = 3,
01619 };
01620 
01621 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
01622 /*****  PHY_MARV_FE_LED_PAR             16 bit r/w      LED Parallel Select Reg. *****/
01623                                                                         /* Bit 15..12: reserved (used internally) */
01624 enum {
01625         PHY_M_FELP_LED2_MSK = 0xf<<8,   /* Bit 11.. 8: LED2 Mask (LINK) */
01626         PHY_M_FELP_LED1_MSK = 0xf<<4,   /* Bit  7.. 4: LED1 Mask (ACT) */
01627         PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
01628 };
01629 
01630 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
01631 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
01632 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
01633 
01634 enum {
01635         LED_PAR_CTRL_COLX       = 0x00,
01636         LED_PAR_CTRL_ERROR      = 0x01,
01637         LED_PAR_CTRL_DUPLEX     = 0x02,
01638         LED_PAR_CTRL_DP_COL     = 0x03,
01639         LED_PAR_CTRL_SPEED      = 0x04,
01640         LED_PAR_CTRL_LINK       = 0x05,
01641         LED_PAR_CTRL_TX         = 0x06,
01642         LED_PAR_CTRL_RX         = 0x07,
01643         LED_PAR_CTRL_ACT        = 0x08,
01644         LED_PAR_CTRL_LNK_RX     = 0x09,
01645         LED_PAR_CTRL_LNK_AC     = 0x0a,
01646         LED_PAR_CTRL_ACT_BL     = 0x0b,
01647         LED_PAR_CTRL_TX_BL      = 0x0c,
01648         LED_PAR_CTRL_RX_BL      = 0x0d,
01649         LED_PAR_CTRL_COL_BL     = 0x0e,
01650         LED_PAR_CTRL_INACT      = 0x0f
01651 };
01652 
01653 /*****,PHY_MARV_FE_SPEC_2               16 bit r/w      Specific Control Reg. 2 *****/
01654 enum {
01655         PHY_M_FESC_DIS_WAIT     = 1<<2, /* Disable TDR Waiting Period */
01656         PHY_M_FESC_ENA_MCLK     = 1<<1, /* Enable MAC Rx Clock in sleep mode */
01657         PHY_M_FESC_SEL_CL_A     = 1<<0, /* Select Class A driver (100B-TX) */
01658 };
01659 
01660 
01661 /*****  PHY_MARV_PHY_CTRL (page 3)              16 bit r/w      LED Control Reg. *****/
01662 enum {
01663         PHY_M_LEDC_LOS_MSK      = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
01664         PHY_M_LEDC_INIT_MSK     = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
01665         PHY_M_LEDC_STA1_MSK     = 0xf<<4, /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
01666         PHY_M_LEDC_STA0_MSK     = 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
01667 };
01668 
01669 #define PHY_M_LEDC_LOS_CTRL(x)  (((x)<<12) & PHY_M_LEDC_LOS_MSK)
01670 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
01671 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
01672 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
01673 
01674 /* GMAC registers  */
01675 /* Port Registers */
01676 enum {
01677         GM_GP_STAT      = 0x0000,       /* 16 bit r/o   General Purpose Status */
01678         GM_GP_CTRL      = 0x0004,       /* 16 bit r/w   General Purpose Control */
01679         GM_TX_CTRL      = 0x0008,       /* 16 bit r/w   Transmit Control Reg. */
01680         GM_RX_CTRL      = 0x000c,       /* 16 bit r/w   Receive Control Reg. */
01681         GM_TX_FLOW_CTRL = 0x0010,       /* 16 bit r/w   Transmit Flow-Control */
01682         GM_TX_PARAM     = 0x0014,       /* 16 bit r/w   Transmit Parameter Reg. */
01683         GM_SERIAL_MODE  = 0x0018,       /* 16 bit r/w   Serial Mode Register */
01684 /* Source Address Registers */
01685         GM_SRC_ADDR_1L  = 0x001c,       /* 16 bit r/w   Source Address 1 (low) */
01686         GM_SRC_ADDR_1M  = 0x0020,       /* 16 bit r/w   Source Address 1 (middle) */
01687         GM_SRC_ADDR_1H  = 0x0024,       /* 16 bit r/w   Source Address 1 (high) */
01688         GM_SRC_ADDR_2L  = 0x0028,       /* 16 bit r/w   Source Address 2 (low) */
01689         GM_SRC_ADDR_2M  = 0x002c,       /* 16 bit r/w   Source Address 2 (middle) */
01690         GM_SRC_ADDR_2H  = 0x0030,       /* 16 bit r/w   Source Address 2 (high) */
01691 
01692 /* Multicast Address Hash Registers */
01693         GM_MC_ADDR_H1   = 0x0034,       /* 16 bit r/w   Multicast Address Hash 1 */
01694         GM_MC_ADDR_H2   = 0x0038,       /* 16 bit r/w   Multicast Address Hash 2 */
01695         GM_MC_ADDR_H3   = 0x003c,       /* 16 bit r/w   Multicast Address Hash 3 */
01696         GM_MC_ADDR_H4   = 0x0040,       /* 16 bit r/w   Multicast Address Hash 4 */
01697 
01698 /* Interrupt Source Registers */
01699         GM_TX_IRQ_SRC   = 0x0044,       /* 16 bit r/o   Tx Overflow IRQ Source */
01700         GM_RX_IRQ_SRC   = 0x0048,       /* 16 bit r/o   Rx Overflow IRQ Source */
01701         GM_TR_IRQ_SRC   = 0x004c,       /* 16 bit r/o   Tx/Rx Over. IRQ Source */
01702 
01703 /* Interrupt Mask Registers */
01704         GM_TX_IRQ_MSK   = 0x0050,       /* 16 bit r/w   Tx Overflow IRQ Mask */
01705         GM_RX_IRQ_MSK   = 0x0054,       /* 16 bit r/w   Rx Overflow IRQ Mask */
01706         GM_TR_IRQ_MSK   = 0x0058,       /* 16 bit r/w   Tx/Rx Over. IRQ Mask */
01707 
01708 /* Serial Management Interface (SMI) Registers */
01709         GM_SMI_CTRL     = 0x0080,       /* 16 bit r/w   SMI Control Register */
01710         GM_SMI_DATA     = 0x0084,       /* 16 bit r/w   SMI Data Register */
01711         GM_PHY_ADDR     = 0x0088,       /* 16 bit r/w   GPHY Address Register */
01712 };
01713 
01714 /* MIB Counters */
01715 #define GM_MIB_CNT_BASE 0x0100          /* Base Address of MIB Counters */
01716 #define GM_MIB_CNT_SIZE 44              /* Number of MIB Counters */
01717 
01718 /*
01719  * MIB Counters base address definitions (low word) -
01720  * use offset 4 for access to high word (32 bit r/o)
01721  */
01722 enum {
01723         GM_RXF_UC_OK  = GM_MIB_CNT_BASE + 0,    /* Unicast Frames Received OK */
01724         GM_RXF_BC_OK    = GM_MIB_CNT_BASE + 8,  /* Broadcast Frames Received OK */
01725         GM_RXF_MPAUSE   = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
01726         GM_RXF_MC_OK    = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
01727         GM_RXF_FCS_ERR  = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
01728         /* GM_MIB_CNT_BASE + 40:        reserved */
01729         GM_RXO_OK_LO    = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
01730         GM_RXO_OK_HI    = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
01731         GM_RXO_ERR_LO   = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
01732         GM_RXO_ERR_HI   = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
01733         GM_RXF_SHT      = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
01734         GM_RXE_FRAG     = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
01735         GM_RXF_64B      = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
01736         GM_RXF_127B     = GM_MIB_CNT_BASE + 104,        /* 65-127 Byte Rx Frame */
01737         GM_RXF_255B     = GM_MIB_CNT_BASE + 112,        /* 128-255 Byte Rx Frame */
01738         GM_RXF_511B     = GM_MIB_CNT_BASE + 120,        /* 256-511 Byte Rx Frame */
01739         GM_RXF_1023B    = GM_MIB_CNT_BASE + 128,        /* 512-1023 Byte Rx Frame */
01740         GM_RXF_1518B    = GM_MIB_CNT_BASE + 136,        /* 1024-1518 Byte Rx Frame */
01741         GM_RXF_MAX_SZ   = GM_MIB_CNT_BASE + 144,        /* 1519-MaxSize Byte Rx Frame */
01742         GM_RXF_LNG_ERR  = GM_MIB_CNT_BASE + 152,        /* Rx Frame too Long Error */
01743         GM_RXF_JAB_PKT  = GM_MIB_CNT_BASE + 160,        /* Rx Jabber Packet Frame */
01744         /* GM_MIB_CNT_BASE + 168:       reserved */
01745         GM_RXE_FIFO_OV  = GM_MIB_CNT_BASE + 176,        /* Rx FIFO overflow Event */
01746         /* GM_MIB_CNT_BASE + 184:       reserved */
01747         GM_TXF_UC_OK    = GM_MIB_CNT_BASE + 192,        /* Unicast Frames Xmitted OK */
01748         GM_TXF_BC_OK    = GM_MIB_CNT_BASE + 200,        /* Broadcast Frames Xmitted OK */
01749         GM_TXF_MPAUSE   = GM_MIB_CNT_BASE + 208,        /* Pause MAC Ctrl Frames Xmitted */
01750         GM_TXF_MC_OK    = GM_MIB_CNT_BASE + 216,        /* Multicast Frames Xmitted OK */
01751         GM_TXO_OK_LO    = GM_MIB_CNT_BASE + 224,        /* Octets Transmitted OK Low */
01752         GM_TXO_OK_HI    = GM_MIB_CNT_BASE + 232,        /* Octets Transmitted OK High */
01753         GM_TXF_64B      = GM_MIB_CNT_BASE + 240,        /* 64 Byte Tx Frame */
01754         GM_TXF_127B     = GM_MIB_CNT_BASE + 248,        /* 65-127 Byte Tx Frame */
01755         GM_TXF_255B     = GM_MIB_CNT_BASE + 256,        /* 128-255 Byte Tx Frame */
01756         GM_TXF_511B     = GM_MIB_CNT_BASE + 264,        /* 256-511 Byte Tx Frame */
01757         GM_TXF_1023B    = GM_MIB_CNT_BASE + 272,        /* 512-1023 Byte Tx Frame */
01758         GM_TXF_1518B    = GM_MIB_CNT_BASE + 280,        /* 1024-1518 Byte Tx Frame */
01759         GM_TXF_MAX_SZ   = GM_MIB_CNT_BASE + 288,        /* 1519-MaxSize Byte Tx Frame */
01760 
01761         GM_TXF_COL      = GM_MIB_CNT_BASE + 304,        /* Tx Collision */
01762         GM_TXF_LAT_COL  = GM_MIB_CNT_BASE + 312,        /* Tx Late Collision */
01763         GM_TXF_ABO_COL  = GM_MIB_CNT_BASE + 320,        /* Tx aborted due to Exces. Col. */
01764         GM_TXF_MUL_COL  = GM_MIB_CNT_BASE + 328,        /* Tx Multiple Collision */
01765         GM_TXF_SNG_COL  = GM_MIB_CNT_BASE + 336,        /* Tx Single Collision */
01766         GM_TXE_FIFO_UR  = GM_MIB_CNT_BASE + 344,        /* Tx FIFO Underrun Event */
01767 };
01768 
01769 /* GMAC Bit Definitions */
01770 /*      GM_GP_STAT      16 bit r/o      General Purpose Status Register */
01771 enum {
01772         GM_GPSR_SPEED           = 1<<15, /* Bit 15:     Port Speed (1 = 100 Mbps) */
01773         GM_GPSR_DUPLEX          = 1<<14, /* Bit 14:     Duplex Mode (1 = Full) */
01774         GM_GPSR_FC_TX_DIS       = 1<<13, /* Bit 13:     Tx Flow-Control Mode Disabled */
01775         GM_GPSR_LINK_UP         = 1<<12, /* Bit 12:     Link Up Status */
01776         GM_GPSR_PAUSE           = 1<<11, /* Bit 11:     Pause State */
01777         GM_GPSR_TX_ACTIVE       = 1<<10, /* Bit 10:     Tx in Progress */
01778         GM_GPSR_EXC_COL         = 1<<9, /* Bit  9:      Excessive Collisions Occurred */
01779         GM_GPSR_LAT_COL         = 1<<8, /* Bit  8:      Late Collisions Occurred */
01780 
01781         GM_GPSR_PHY_ST_CH       = 1<<5, /* Bit  5:      PHY Status Change */
01782         GM_GPSR_GIG_SPEED       = 1<<4, /* Bit  4:      Gigabit Speed (1 = 1000 Mbps) */
01783         GM_GPSR_PART_MODE       = 1<<3, /* Bit  3:      Partition mode */
01784         GM_GPSR_FC_RX_DIS       = 1<<2, /* Bit  2:      Rx Flow-Control Mode Disabled */
01785         GM_GPSR_PROM_EN         = 1<<1, /* Bit  1:      Promiscuous Mode Enabled */
01786 };
01787 
01788 /*      GM_GP_CTRL      16 bit r/w      General Purpose Control Register */
01789 enum {
01790         GM_GPCR_PROM_ENA        = 1<<14,        /* Bit 14:      Enable Promiscuous Mode */
01791         GM_GPCR_FC_TX_DIS       = 1<<13, /* Bit 13:     Disable Tx Flow-Control Mode */
01792         GM_GPCR_TX_ENA          = 1<<12, /* Bit 12:     Enable Transmit */
01793         GM_GPCR_RX_ENA          = 1<<11, /* Bit 11:     Enable Receive */
01794         GM_GPCR_BURST_ENA       = 1<<10, /* Bit 10:     Enable Burst Mode */
01795         GM_GPCR_LOOP_ENA        = 1<<9, /* Bit  9:      Enable MAC Loopback Mode */
01796         GM_GPCR_PART_ENA        = 1<<8, /* Bit  8:      Enable Partition Mode */
01797         GM_GPCR_GIGS_ENA        = 1<<7, /* Bit  7:      Gigabit Speed (1000 Mbps) */
01798         GM_GPCR_FL_PASS         = 1<<6, /* Bit  6:      Force Link Pass */
01799         GM_GPCR_DUP_FULL        = 1<<5, /* Bit  5:      Full Duplex Mode */
01800         GM_GPCR_FC_RX_DIS       = 1<<4, /* Bit  4:      Disable Rx Flow-Control Mode */
01801         GM_GPCR_SPEED_100       = 1<<3,   /* Bit  3:    Port Speed 100 Mbps */
01802         GM_GPCR_AU_DUP_DIS      = 1<<2, /* Bit  2:      Disable Auto-Update Duplex */
01803         GM_GPCR_AU_FCT_DIS      = 1<<1, /* Bit  1:      Disable Auto-Update Flow-C. */
01804         GM_GPCR_AU_SPD_DIS      = 1<<0, /* Bit  0:      Disable Auto-Update Speed */
01805 };
01806 
01807 #define GM_GPCR_SPEED_1000      (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
01808 #define GM_GPCR_AU_ALL_DIS      (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
01809 
01810 /*      GM_TX_CTRL                      16 bit r/w      Transmit Control Register */
01811 enum {
01812         GM_TXCR_FORCE_JAM       = 1<<15, /* Bit 15:     Force Jam / Flow-Control */
01813         GM_TXCR_CRC_DIS         = 1<<14, /* Bit 14:     Disable insertion of CRC */
01814         GM_TXCR_PAD_DIS         = 1<<13, /* Bit 13:     Disable padding of packets */
01815         GM_TXCR_COL_THR_MSK     = 7<<10, /* Bit 12..10: Collision Threshold */
01816 };
01817 
01818 #define TX_COL_THR(x)           (((x)<<10) & GM_TXCR_COL_THR_MSK)
01819 #define TX_COL_DEF              0x04    /* late collision after 64 byte */
01820 
01821 /*      GM_RX_CTRL                      16 bit r/w      Receive Control Register */
01822 enum {
01823         GM_RXCR_UCF_ENA = 1<<15, /* Bit 15:     Enable Unicast filtering */
01824         GM_RXCR_MCF_ENA = 1<<14, /* Bit 14:     Enable Multicast filtering */
01825         GM_RXCR_CRC_DIS = 1<<13, /* Bit 13:     Remove 4-byte CRC */
01826         GM_RXCR_PASS_FC = 1<<12, /* Bit 12:     Pass FC packets to FIFO */
01827 };
01828 
01829 /*      GM_TX_PARAM             16 bit r/w      Transmit Parameter Register */
01830 enum {
01831         GM_TXPA_JAMLEN_MSK      = 0x03<<14,     /* Bit 15..14:  Jam Length */
01832         GM_TXPA_JAMIPG_MSK      = 0x1f<<9,      /* Bit 13..9:   Jam IPG */
01833         GM_TXPA_JAMDAT_MSK      = 0x1f<<4,      /* Bit  8..4:   IPG Jam to Data */
01834 
01835         TX_JAM_LEN_DEF          = 0x03,
01836         TX_JAM_IPG_DEF          = 0x0b,
01837         TX_IPG_JAM_DEF          = 0x1c,
01838 };
01839 
01840 #define TX_JAM_LEN_VAL(x)       (((x)<<14) & GM_TXPA_JAMLEN_MSK)
01841 #define TX_JAM_IPG_VAL(x)       (((x)<<9)  & GM_TXPA_JAMIPG_MSK)
01842 #define TX_IPG_JAM_DATA(x)      (((x)<<4)  & GM_TXPA_JAMDAT_MSK)
01843 
01844 
01845 /*      GM_SERIAL_MODE                  16 bit r/w      Serial Mode Register */
01846 enum {
01847         GM_SMOD_DATABL_MSK      = 0x1f<<11, /* Bit 15..11:      Data Blinder (r/o) */
01848         GM_SMOD_LIMIT_4         = 1<<10, /* Bit 10:     4 consecutive Tx trials */
01849         GM_SMOD_VLAN_ENA        = 1<<9, /* Bit  9:      Enable VLAN  (Max. Frame Len) */
01850         GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
01851          GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
01852 };
01853 
01854 #define DATA_BLIND_VAL(x)       (((x)<<11) & GM_SMOD_DATABL_MSK)
01855 #define DATA_BLIND_DEF          0x04
01856 
01857 #define IPG_DATA_VAL(x)         (x & GM_SMOD_IPG_MSK)
01858 #define IPG_DATA_DEF            0x1e
01859 
01860 /*      GM_SMI_CTRL                     16 bit r/w      SMI Control Register */
01861 enum {
01862         GM_SMI_CT_PHY_A_MSK     = 0x1f<<11, /* Bit 15..11:      PHY Device Address */
01863         GM_SMI_CT_REG_A_MSK     = 0x1f<<6, /* Bit 10.. 6:       PHY Register Address */
01864         GM_SMI_CT_OP_RD         = 1<<5, /* Bit  5:      OpCode Read (0=Write)*/
01865         GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
01866         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
01867 };
01868 
01869 #define GM_SMI_CT_PHY_AD(x)     (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
01870 #define GM_SMI_CT_REG_AD(x)     (((x)<<6) & GM_SMI_CT_REG_A_MSK)
01871 
01872 /*      GM_PHY_ADDR                             16 bit r/w      GPHY Address Register */
01873 enum {
01874         GM_PAR_MIB_CLR  = 1<<5, /* Bit  5:      Set MIB Clear Counter Mode */
01875         GM_PAR_MIB_TST  = 1<<4, /* Bit  4:      MIB Load Counter (Test Mode) */
01876 };
01877 
01878 /* Receive Frame Status Encoding */
01879 enum {
01880         GMR_FS_LEN      = 0xffff<<16, /* Bit 31..16:    Rx Frame Length */
01881         GMR_FS_LEN_SHIFT = 16,
01882         GMR_FS_VLAN     = 1<<13, /* Bit 13:     VLAN Packet */
01883         GMR_FS_JABBER   = 1<<12, /* Bit 12:     Jabber Packet */
01884         GMR_FS_UN_SIZE  = 1<<11, /* Bit 11:     Undersize Packet */
01885         GMR_FS_MC       = 1<<10, /* Bit 10:     Multicast Packet */
01886         GMR_FS_BC       = 1<<9, /* Bit  9:      Broadcast Packet */
01887         GMR_FS_RX_OK    = 1<<8, /* Bit  8:      Receive OK (Good Packet) */
01888         GMR_FS_GOOD_FC  = 1<<7, /* Bit  7:      Good Flow-Control Packet */
01889         GMR_FS_BAD_FC   = 1<<6, /* Bit  6:      Bad  Flow-Control Packet */
01890         GMR_FS_MII_ERR  = 1<<5, /* Bit  5:      MII Error */
01891         GMR_FS_LONG_ERR = 1<<4, /* Bit  4:      Too Long Packet */
01892         GMR_FS_FRAGMENT = 1<<3, /* Bit  3:      Fragment */
01893 
01894         GMR_FS_CRC_ERR  = 1<<1, /* Bit  1:      CRC Error */
01895         GMR_FS_RX_FF_OV = 1<<0, /* Bit  0:      Rx FIFO Overflow */
01896 
01897 /*
01898  * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
01899  */
01900         GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
01901                           GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
01902                           GMR_FS_JABBER,
01903 /* Rx GMAC FIFO Flush Mask (default) */
01904         RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
01905                            GMR_FS_BAD_FC |  GMR_FS_UN_SIZE | GMR_FS_JABBER,
01906 };
01907 
01908 /*      RX_GMF_CTRL_T   32 bit  Rx GMAC FIFO Control/Test */
01909 enum {
01910         GMF_WP_TST_ON   = 1<<14,        /* Write Pointer Test On */
01911         GMF_WP_TST_OFF  = 1<<13,        /* Write Pointer Test Off */
01912         GMF_WP_STEP     = 1<<12,        /* Write Pointer Step/Increment */
01913 
01914         GMF_RP_TST_ON   = 1<<10,        /* Read Pointer Test On */
01915         GMF_RP_TST_OFF  = 1<<9,         /* Read Pointer Test Off */
01916         GMF_RP_STEP     = 1<<8,         /* Read Pointer Step/Increment */
01917         GMF_RX_F_FL_ON  = 1<<7,         /* Rx FIFO Flush Mode On */
01918         GMF_RX_F_FL_OFF = 1<<6,         /* Rx FIFO Flush Mode Off */
01919         GMF_CLI_RX_FO   = 1<<5,         /* Clear IRQ Rx FIFO Overrun */
01920         GMF_CLI_RX_FC   = 1<<4,         /* Clear IRQ Rx Frame Complete */
01921         GMF_OPER_ON     = 1<<3,         /* Operational Mode On */
01922         GMF_OPER_OFF    = 1<<2,         /* Operational Mode Off */
01923         GMF_RST_CLR     = 1<<1,         /* Clear GMAC FIFO Reset */
01924         GMF_RST_SET     = 1<<0,         /* Set   GMAC FIFO Reset */
01925 
01926         RX_GMF_FL_THR_DEF = 0xa,        /* flush threshold (default) */
01927 };
01928 
01929 
01930 /*      TX_GMF_CTRL_T   32 bit  Tx GMAC FIFO Control/Test */
01931 enum {
01932         GMF_WSP_TST_ON  = 1<<18, /* Write Shadow Pointer Test On */
01933         GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
01934         GMF_WSP_STEP    = 1<<16, /* Write Shadow Pointer Step/Increment */
01935 
01936         GMF_CLI_TX_FU   = 1<<6, /* Clear IRQ Tx FIFO Underrun */
01937         GMF_CLI_TX_FC   = 1<<5, /* Clear IRQ Tx Frame Complete */
01938         GMF_CLI_TX_PE   = 1<<4, /* Clear IRQ Tx Parity Error */
01939 };
01940 
01941 /*      GMAC_TI_ST_CTRL  8 bit  Time Stamp Timer Ctrl Reg (YUKON only) */
01942 enum {
01943         GMT_ST_START    = 1<<2, /* Start Time Stamp Timer */
01944         GMT_ST_STOP     = 1<<1, /* Stop  Time Stamp Timer */
01945         GMT_ST_CLR_IRQ  = 1<<0, /* Clear Time Stamp Timer IRQ */
01946 };
01947 
01948 /*      GMAC_CTRL               32 bit  GMAC Control Reg (YUKON only) */
01949 enum {
01950         GMC_H_BURST_ON  = 1<<7, /* Half Duplex Burst Mode On */
01951         GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
01952         GMC_F_LOOPB_ON  = 1<<5, /* FIFO Loopback On */
01953         GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
01954         GMC_PAUSE_ON    = 1<<3, /* Pause On */
01955         GMC_PAUSE_OFF   = 1<<2, /* Pause Off */
01956         GMC_RST_CLR     = 1<<1, /* Clear GMAC Reset */
01957         GMC_RST_SET     = 1<<0, /* Set   GMAC Reset */
01958 };
01959 
01960 /*      GPHY_CTRL               32 bit  GPHY Control Reg (YUKON only) */
01961 enum {
01962         GPC_SEL_BDT     = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
01963         GPC_INT_POL_HI  = 1<<27, /* IRQ Polarity is Active HIGH */
01964         GPC_75_OHM      = 1<<26, /* Use 75 Ohm Termination instead of 50 */
01965         GPC_DIS_FC      = 1<<25, /* Disable Automatic Fiber/Copper Detection */
01966         GPC_DIS_SLEEP   = 1<<24, /* Disable Energy Detect */
01967         GPC_HWCFG_M_3   = 1<<23, /* HWCFG_MODE[3] */
01968         GPC_HWCFG_M_2   = 1<<22, /* HWCFG_MODE[2] */
01969         GPC_HWCFG_M_1   = 1<<21, /* HWCFG_MODE[1] */
01970         GPC_HWCFG_M_0   = 1<<20, /* HWCFG_MODE[0] */
01971         GPC_ANEG_0      = 1<<19, /* ANEG[0] */
01972         GPC_ENA_XC      = 1<<18, /* Enable MDI crossover */
01973         GPC_DIS_125     = 1<<17, /* Disable 125 MHz clock */
01974         GPC_ANEG_3      = 1<<16, /* ANEG[3] */
01975         GPC_ANEG_2      = 1<<15, /* ANEG[2] */
01976         GPC_ANEG_1      = 1<<14, /* ANEG[1] */
01977         GPC_ENA_PAUSE   = 1<<13, /* Enable Pause (SYM_OR_REM) */
01978         GPC_PHYADDR_4   = 1<<12, /* Bit 4 of Phy Addr */
01979         GPC_PHYADDR_3   = 1<<11, /* Bit 3 of Phy Addr */
01980         GPC_PHYADDR_2   = 1<<10, /* Bit 2 of Phy Addr */
01981         GPC_PHYADDR_1   = 1<<9,  /* Bit 1 of Phy Addr */
01982         GPC_PHYADDR_0   = 1<<8,  /* Bit 0 of Phy Addr */
01983                                                 /* Bits  7..2:  reserved */
01984         GPC_RST_CLR     = 1<<1, /* Clear GPHY Reset */
01985         GPC_RST_SET     = 1<<0, /* Set   GPHY Reset */
01986 };
01987 
01988 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
01989 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
01990 #define GPC_ANEG_ADV_ALL_M  (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
01991 
01992 /* forced speed and duplex mode (don't mix with other ANEG bits) */
01993 #define GPC_FRC10MBIT_HALF      0
01994 #define GPC_FRC10MBIT_FULL      GPC_ANEG_0
01995 #define GPC_FRC100MBIT_HALF     GPC_ANEG_1
01996 #define GPC_FRC100MBIT_FULL     (GPC_ANEG_0 | GPC_ANEG_1)
01997 
01998 /* auto-negotiation with limited advertised speeds */
01999 /* mix only with master/slave settings (for copper) */
02000 #define GPC_ADV_1000_HALF       GPC_ANEG_2
02001 #define GPC_ADV_1000_FULL       GPC_ANEG_3
02002 #define GPC_ADV_ALL             (GPC_ANEG_2 | GPC_ANEG_3)
02003 
02004 /* master/slave settings */
02005 /* only for copper with 1000 Mbps */
02006 #define GPC_FORCE_MASTER        0
02007 #define GPC_FORCE_SLAVE         GPC_ANEG_0
02008 #define GPC_PREF_MASTER         GPC_ANEG_1
02009 #define GPC_PREF_SLAVE          (GPC_ANEG_1 | GPC_ANEG_0)
02010 
02011 /*      GMAC_IRQ_SRC     8 bit  GMAC Interrupt Source Reg (YUKON only) */
02012 /*      GMAC_IRQ_MSK     8 bit  GMAC Interrupt Mask   Reg (YUKON only) */
02013 enum {
02014         GM_IS_TX_CO_OV  = 1<<5, /* Transmit Counter Overflow IRQ */
02015         GM_IS_RX_CO_OV  = 1<<4, /* Receive Counter Overflow IRQ */
02016         GM_IS_TX_FF_UR  = 1<<3, /* Transmit FIFO Underrun */
02017         GM_IS_TX_COMPL  = 1<<2, /* Frame Transmission Complete */
02018         GM_IS_RX_FF_OR  = 1<<1, /* Receive FIFO Overrun */
02019         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
02020 
02021 #define GMAC_DEF_MSK    (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
02022 
02023 /*      GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
02024                                                 /* Bits 15.. 2: reserved */
02025         GMLC_RST_CLR    = 1<<1, /* Clear GMAC Link Reset */
02026         GMLC_RST_SET    = 1<<0, /* Set   GMAC Link Reset */
02027 
02028 
02029 /*      WOL_CTRL_STAT   16 bit  WOL Control/Status Reg */
02030         WOL_CTL_LINK_CHG_OCC            = 1<<15,
02031         WOL_CTL_MAGIC_PKT_OCC           = 1<<14,
02032         WOL_CTL_PATTERN_OCC             = 1<<13,
02033         WOL_CTL_CLEAR_RESULT            = 1<<12,
02034         WOL_CTL_ENA_PME_ON_LINK_CHG     = 1<<11,
02035         WOL_CTL_DIS_PME_ON_LINK_CHG     = 1<<10,
02036         WOL_CTL_ENA_PME_ON_MAGIC_PKT    = 1<<9,
02037         WOL_CTL_DIS_PME_ON_MAGIC_PKT    = 1<<8,
02038         WOL_CTL_ENA_PME_ON_PATTERN      = 1<<7,
02039         WOL_CTL_DIS_PME_ON_PATTERN      = 1<<6,
02040         WOL_CTL_ENA_LINK_CHG_UNIT       = 1<<5,
02041         WOL_CTL_DIS_LINK_CHG_UNIT       = 1<<4,
02042         WOL_CTL_ENA_MAGIC_PKT_UNIT      = 1<<3,
02043         WOL_CTL_DIS_MAGIC_PKT_UNIT      = 1<<2,
02044         WOL_CTL_ENA_PATTERN_UNIT        = 1<<1,
02045         WOL_CTL_DIS_PATTERN_UNIT        = 1<<0,
02046 };
02047 
02048 #define WOL_CTL_DEFAULT                         \
02049         (WOL_CTL_DIS_PME_ON_LINK_CHG |  \
02050         WOL_CTL_DIS_PME_ON_PATTERN |    \
02051         WOL_CTL_DIS_PME_ON_MAGIC_PKT |  \
02052         WOL_CTL_DIS_LINK_CHG_UNIT |             \
02053         WOL_CTL_DIS_PATTERN_UNIT |              \
02054         WOL_CTL_DIS_MAGIC_PKT_UNIT)
02055 
02056 /*      WOL_MATCH_CTL    8 bit  WOL Match Control Reg */
02057 #define WOL_CTL_PATT_ENA(x)     (1 << (x))
02058 
02059 
02060 /* XMAC II registers                                  */
02061 enum {
02062         XM_MMU_CMD      = 0x0000, /* 16 bit r/w MMU Command Register */
02063         XM_POFF         = 0x0008, /* 32 bit r/w Packet Offset Register */
02064         XM_BURST        = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
02065         XM_1L_VLAN_TAG  = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
02066         XM_2L_VLAN_TAG  = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
02067         XM_TX_CMD       = 0x0020, /* 16 bit r/w Transmit Command Register */
02068         XM_TX_RT_LIM    = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
02069         XM_TX_STIME     = 0x0028, /* 16 bit r/w Transmit Slottime Register */
02070         XM_TX_IPG       = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
02071         XM_RX_CMD       = 0x0030, /* 16 bit r/w Receive Command Register */
02072         XM_PHY_ADDR     = 0x0034, /* 16 bit r/w PHY Address Register */
02073         XM_PHY_DATA     = 0x0038, /* 16 bit r/w PHY Data Register */
02074         XM_GP_PORT      = 0x0040, /* 32 bit r/w General Purpose Port Register */
02075         XM_IMSK         = 0x0044, /* 16 bit r/w Interrupt Mask Register */
02076         XM_ISRC         = 0x0048, /* 16 bit r/o Interrupt Status Register */
02077         XM_HW_CFG       = 0x004c, /* 16 bit r/w Hardware Config Register */
02078         XM_TX_LO_WM     = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
02079         XM_TX_HI_WM     = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
02080         XM_TX_THR       = 0x0064, /* 16 bit r/w Tx Request Threshold */
02081         XM_HT_THR       = 0x0066, /* 16 bit r/w Host Request Threshold */
02082         XM_PAUSE_DA     = 0x0068, /* NA reg r/w Pause Destination Address */
02083         XM_CTL_PARA     = 0x0070, /* 32 bit r/w Control Parameter Register */
02084         XM_MAC_OPCODE   = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
02085         XM_MAC_PTIME    = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
02086         XM_TX_STAT      = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
02087 
02088         XM_EXM_START    = 0x0080, /* r/w        Start Address of the EXM Regs */
02089 #define XM_EXM(reg)     (XM_EXM_START + ((reg) << 3))
02090 };
02091 
02092 enum {
02093         XM_SRC_CHK      = 0x0100, /* NA reg r/w Source Check Address Register */
02094         XM_SA           = 0x0108, /* NA reg r/w Station Address Register */
02095         XM_HSM          = 0x0110, /* 64 bit r/w Hash Match Address Registers */
02096         XM_RX_LO_WM     = 0x0118, /* 16 bit r/w Receive Low Water Mark */
02097         XM_RX_HI_WM     = 0x011a, /* 16 bit r/w Receive High Water Mark */
02098         XM_RX_THR       = 0x011c, /* 32 bit r/w Receive Request Threshold */
02099         XM_DEV_ID       = 0x0120, /* 32 bit r/o Device ID Register */
02100         XM_MODE         = 0x0124, /* 32 bit r/w Mode Register */
02101         XM_LSA          = 0x0128, /* NA reg r/o Last Source Register */
02102         XM_TS_READ      = 0x0130, /* 32 bit r/o Time Stamp Read Register */
02103         XM_TS_LOAD      = 0x0134, /* 32 bit r/o Time Stamp Load Value */
02104         XM_STAT_CMD     = 0x0200, /* 16 bit r/w Statistics Command Register */
02105         XM_RX_CNT_EV    = 0x0204, /* 32 bit r/o Rx Counter Event Register */
02106         XM_TX_CNT_EV    = 0x0208, /* 32 bit r/o Tx Counter Event Register */
02107         XM_RX_EV_MSK    = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
02108         XM_TX_EV_MSK    = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
02109         XM_TXF_OK       = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
02110         XM_TXO_OK_HI    = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
02111         XM_TXO_OK_LO    = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
02112         XM_TXF_BC_OK    = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
02113         XM_TXF_MC_OK    = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
02114         XM_TXF_UC_OK    = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
02115         XM_TXF_LONG     = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
02116         XM_TXE_BURST    = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
02117         XM_TXF_MPAUSE   = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
02118         XM_TXF_MCTRL    = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
02119         XM_TXF_SNG_COL  = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
02120         XM_TXF_MUL_COL  = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
02121         XM_TXF_ABO_COL  = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
02122         XM_TXF_LAT_COL  = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
02123         XM_TXF_DEF      = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
02124         XM_TXF_EX_DEF   = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
02125         XM_TXE_FIFO_UR  = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
02126         XM_TXE_CS_ERR   = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
02127         XM_TXP_UTIL     = 0x02c8, /* 32 bit r/o Tx Utilization in % */
02128         XM_TXF_64B      = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
02129         XM_TXF_127B     = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
02130         XM_TXF_255B     = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
02131         XM_TXF_511B     = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
02132         XM_TXF_1023B    = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
02133         XM_TXF_MAX_SZ   = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
02134         XM_RXF_OK       = 0x0300, /* 32 bit r/o Frames Received OK */
02135         XM_RXO_OK_HI    = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
02136         XM_RXO_OK_LO    = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
02137         XM_RXF_BC_OK    = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
02138         XM_RXF_MC_OK    = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
02139         XM_RXF_UC_OK    = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
02140         XM_RXF_MPAUSE   = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
02141         XM_RXF_MCTRL    = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
02142         XM_RXF_INV_MP   = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
02143         XM_RXF_INV_MOC  = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
02144         XM_RXE_BURST    = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
02145         XM_RXE_FMISS    = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
02146         XM_RXF_FRA_ERR  = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
02147         XM_RXE_FIFO_OV  = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
02148         XM_RXF_JAB_PKT  = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
02149         XM_RXE_CAR_ERR  = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
02150         XM_RXF_LEN_ERR  = 0x0340, /* 32 bit r/o Rx in Range Length Error */
02151         XM_RXE_SYM_ERR  = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
02152         XM_RXE_SHT_ERR  = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
02153         XM_RXE_RUNT     = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
02154         XM_RXF_LNG_ERR  = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
02155         XM_RXF_FCS_ERR  = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
02156         XM_RXF_CEX_ERR  = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
02157         XM_RXP_UTIL     = 0x0360, /* 32 bit r/o Rx Utilization in % */
02158         XM_RXF_64B      = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
02159         XM_RXF_127B     = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
02160         XM_RXF_255B     = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
02161         XM_RXF_511B     = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
02162         XM_RXF_1023B    = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
02163         XM_RXF_MAX_SZ   = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
02164 };
02165 
02166 /*      XM_MMU_CMD      16 bit r/w      MMU Command Register */
02167 enum {
02168         XM_MMU_PHY_RDY  = 1<<12, /* Bit 12:     PHY Read Ready */
02169         XM_MMU_PHY_BUSY = 1<<11, /* Bit 11:     PHY Busy */
02170         XM_MMU_IGN_PF   = 1<<10, /* Bit 10:     Ignore Pause Frame */
02171         XM_MMU_MAC_LB   = 1<<9,  /* Bit  9:     Enable MAC Loopback */
02172         XM_MMU_FRC_COL  = 1<<7,  /* Bit  7:     Force Collision */
02173         XM_MMU_SIM_COL  = 1<<6,  /* Bit  6:     Simulate Collision */
02174         XM_MMU_NO_PRE   = 1<<5,  /* Bit  5:     No MDIO Preamble */
02175         XM_MMU_GMII_FD  = 1<<4,  /* Bit  4:     GMII uses Full Duplex */
02176         XM_MMU_RAT_CTRL = 1<<3,  /* Bit  3:     Enable Rate Control */
02177         XM_MMU_GMII_LOOP= 1<<2,  /* Bit  2:     PHY is in Loopback Mode */
02178         XM_MMU_ENA_RX   = 1<<1,  /* Bit  1:     Enable Receiver */
02179         XM_MMU_ENA_TX   = 1<<0,  /* Bit  0:     Enable Transmitter */
02180 };
02181 
02182 
02183 /*      XM_TX_CMD       16 bit r/w      Transmit Command Register */
02184 enum {
02185         XM_TX_BK2BK     = 1<<6, /* Bit  6:      Ignor Carrier Sense (Tx Bk2Bk)*/
02186         XM_TX_ENC_BYP   = 1<<5, /* Bit  5:      Set Encoder in Bypass Mode */
02187         XM_TX_SAM_LINE  = 1<<4, /* Bit  4: (sc) Start utilization calculation */
02188         XM_TX_NO_GIG_MD = 1<<3, /* Bit  3:      Disable Carrier Extension */
02189         XM_TX_NO_PRE    = 1<<2, /* Bit  2:      Disable Preamble Generation */
02190         XM_TX_NO_CRC    = 1<<1, /* Bit  1:      Disable CRC Generation */
02191         XM_TX_AUTO_PAD  = 1<<0, /* Bit  0:      Enable Automatic Padding */
02192 };
02193 
02194 /*      XM_TX_RT_LIM    16 bit r/w      Transmit Retry Limit Register */
02195 #define XM_RT_LIM_MSK   0x1f    /* Bit  4..0:   Tx Retry Limit */
02196 
02197 
02198 /*      XM_TX_STIME     16 bit r/w      Transmit Slottime Register */
02199 #define XM_STIME_MSK    0x7f    /* Bit  6..0:   Tx Slottime bits */
02200 
02201 
02202 /*      XM_TX_IPG       16 bit r/w      Transmit Inter Packet Gap */
02203 #define XM_IPG_MSK              0xff    /* Bit  7..0:   IPG value bits */
02204 
02205 
02206 /*      XM_RX_CMD       16 bit r/w      Receive Command Register */
02207 enum {
02208         XM_RX_LENERR_OK = 1<<8, /* Bit  8       don't set Rx Err bit for */
02209                                 /*              inrange error packets */
02210         XM_RX_BIG_PK_OK = 1<<7, /* Bit  7       don't set Rx Err bit for */
02211                                 /*              jumbo packets */
02212         XM_RX_IPG_CAP   = 1<<6, /* Bit  6       repl. type field with IPG */
02213         XM_RX_TP_MD     = 1<<5, /* Bit  5:      Enable transparent Mode */
02214         XM_RX_STRIP_FCS = 1<<4, /* Bit  4:      Enable FCS Stripping */
02215         XM_RX_SELF_RX   = 1<<3, /* Bit  3:      Enable Rx of own packets */
02216         XM_RX_SAM_LINE  = 1<<2, /* Bit  2: (sc) Start utilization calculation */
02217         XM_RX_STRIP_PAD = 1<<1, /* Bit  1:      Strip pad bytes of Rx frames */
02218         XM_RX_DIS_CEXT  = 1<<0, /* Bit  0:      Disable carrier ext. check */
02219 };
02220 
02221 
02222 /*      XM_GP_PORT      32 bit r/w      General Purpose Port Register */
02223 enum {
02224         XM_GP_ANIP      = 1<<6, /* Bit  6: (ro) Auto-Neg. in progress */
02225         XM_GP_FRC_INT   = 1<<5, /* Bit  5: (sc) Force Interrupt */
02226         XM_GP_RES_MAC   = 1<<3, /* Bit  3: (sc) Reset MAC and FIFOs */
02227         XM_GP_RES_STAT  = 1<<2, /* Bit  2: (sc) Reset the statistics module */
02228         XM_GP_INP_ASS   = 1<<0, /* Bit  0: (ro) GP Input Pin asserted */
02229 };
02230 
02231 
02232 /*      XM_IMSK         16 bit r/w      Interrupt Mask Register */
02233 /*      XM_ISRC         16 bit r/o      Interrupt Status Register */
02234 enum {
02235         XM_IS_LNK_AE    = 1<<14, /* Bit 14:     Link Asynchronous Event */
02236         XM_IS_TX_ABORT  = 1<<13, /* Bit 13:     Transmit Abort, late Col. etc */
02237         XM_IS_FRC_INT   = 1<<12, /* Bit 12:     Force INT bit set in GP */
02238         XM_IS_INP_ASS   = 1<<11, /* Bit 11:     Input Asserted, GP bit 0 set */
02239         XM_IS_LIPA_RC   = 1<<10, /* Bit 10:     Link Partner requests config */
02240         XM_IS_RX_PAGE   = 1<<9, /* Bit  9:      Page Received */
02241         XM_IS_TX_PAGE   = 1<<8, /* Bit  8:      Next Page Loaded for Transmit */
02242         XM_IS_AND       = 1<<7, /* Bit  7:      Auto-Negotiation Done */
02243         XM_IS_TSC_OV    = 1<<6, /* Bit  6:      Time Stamp Counter Overflow */
02244         XM_IS_RXC_OV    = 1<<5, /* Bit  5:      Rx Counter Event Overflow */
02245         XM_IS_TXC_OV    = 1<<4, /* Bit  4:      Tx Counter Event Overflow */
02246         XM_IS_RXF_OV    = 1<<3, /* Bit  3:      Receive FIFO Overflow */
02247         XM_IS_TXF_UR    = 1<<2, /* Bit  2:      Transmit FIFO Underrun */
02248         XM_IS_TX_COMP   = 1<<1, /* Bit  1:      Frame Tx Complete */
02249         XM_IS_RX_COMP   = 1<<0, /* Bit  0:      Frame Rx Complete */
02250 
02251         XM_IMSK_DISABLE = 0xffff,
02252 };
02253 
02254 /*      XM_HW_CFG       16 bit r/w      Hardware Config Register */
02255 enum {
02256         XM_HW_GEN_EOP   = 1<<3, /* Bit  3:      generate End of Packet pulse */
02257         XM_HW_COM4SIG   = 1<<2, /* Bit  2:      use Comma Detect for Sig. Det.*/
02258         XM_HW_GMII_MD   = 1<<0, /* Bit  0:      GMII Interface selected */
02259 };
02260 
02261 
02262 /*      XM_TX_LO_WM     16 bit r/w      Tx FIFO Low Water Mark */
02263 /*      XM_TX_HI_WM     16 bit r/w      Tx FIFO High Water Mark */
02264 #define XM_TX_WM_MSK    0x01ff  /* Bit  9.. 0   Tx FIFO Watermark bits */
02265 
02266 /*      XM_TX_THR       16 bit r/w      Tx Request Threshold */
02267 /*      XM_HT_THR       16 bit r/w      Host Request Threshold */
02268 /*      XM_RX_THR       16 bit r/w      Rx Request Threshold */
02269 #define XM_THR_MSK              0x03ff  /* Bit 10.. 0   Rx/Tx Request Threshold bits */
02270 
02271 
02272 /*      XM_TX_STAT      32 bit r/o      Tx Status LIFO Register */
02273 enum {
02274         XM_ST_VALID     = (1UL<<31),    /* Bit 31:      Status Valid */
02275         XM_ST_BYTE_CNT  = (0x3fffL<<17),        /* Bit 30..17:  Tx frame Length */
02276         XM_ST_RETRY_CNT = (0x1fL<<12),  /* Bit 16..12:  Retry Count */
02277         XM_ST_EX_COL    = 1<<11,        /* Bit 11:      Excessive Collisions */
02278         XM_ST_EX_DEF    = 1<<10,        /* Bit 10:      Excessive Deferral */
02279         XM_ST_BURST     = 1<<9,         /* Bit  9:      p. xmitted in burst md*/
02280         XM_ST_DEFER     = 1<<8,         /* Bit  8:      packet was defered */
02281         XM_ST_BC        = 1<<7,         /* Bit  7:      Broadcast packet */
02282         XM_ST_MC        = 1<<6,         /* Bit  6:      Multicast packet */
02283         XM_ST_UC        = 1<<5,         /* Bit  5:      Unicast packet */
02284         XM_ST_TX_UR     = 1<<4,         /* Bit  4:      FIFO Underrun occurred */
02285         XM_ST_CS_ERR    = 1<<3,         /* Bit  3:      Carrier Sense Error */
02286         XM_ST_LAT_COL   = 1<<2,         /* Bit  2:      Late Collision Error */
02287         XM_ST_MUL_COL   = 1<<1,         /* Bit  1:      Multiple Collisions */
02288         XM_ST_SGN_COL   = 1<<0,         /* Bit  0:      Single Collision */
02289 };
02290 
02291 /*      XM_RX_LO_WM     16 bit r/w      Receive Low Water Mark */
02292 /*      XM_RX_HI_WM     16 bit r/w      Receive High Water Mark */
02293 #define XM_RX_WM_MSK    0x03ff          /* Bit 11.. 0:  Rx FIFO Watermark bits */
02294 
02295 
02296 /*      XM_DEV_ID       32 bit r/o      Device ID Register */
02297 #define XM_DEV_OUI      (0x00ffffffUL<<8)       /* Bit 31..8:   Device OUI */
02298 #define XM_DEV_REV      (0x07L << 5)            /* Bit  7..5:   Chip Rev Num */
02299 
02300 
02301 /*      XM_MODE         32 bit r/w      Mode Register */
02302 enum {
02303         XM_MD_ENA_REJ   = 1<<26, /* Bit 26:     Enable Frame Reject */
02304         XM_MD_SPOE_E    = 1<<25, /* Bit 25:     Send Pause on Edge */
02305                                                                         /*              extern generated */
02306         XM_MD_TX_REP    = 1<<24, /* Bit 24:     Transmit Repeater Mode */
02307         XM_MD_SPOFF_I   = 1<<23, /* Bit 23:     Send Pause on FIFO full */
02308                                                                         /*              intern generated */
02309         XM_MD_LE_STW    = 1<<22, /* Bit 22:     Rx Stat Word in Little Endian */
02310         XM_MD_TX_CONT   = 1<<21, /* Bit 21:     Send Continuous */
02311         XM_MD_TX_PAUSE  = 1<<20, /* Bit 20: (sc)        Send Pause Frame */
02312         XM_MD_ATS       = 1<<19, /* Bit 19:     Append Time Stamp */
02313         XM_MD_SPOL_I    = 1<<18, /* Bit 18:     Send Pause on Low */
02314                                                                         /*              intern generated */
02315         XM_MD_SPOH_I    = 1<<17, /* Bit 17:     Send Pause on High */
02316                                                                         /*              intern generated */
02317         XM_MD_CAP       = 1<<16, /* Bit 16:     Check Address Pair */
02318         XM_MD_ENA_HASH  = 1<<15, /* Bit 15:     Enable Hashing */
02319         XM_MD_CSA       = 1<<14, /* Bit 14:     Check Station Address */
02320         XM_MD_CAA       = 1<<13, /* Bit 13:     Check Address Array */
02321         XM_MD_RX_MCTRL  = 1<<12, /* Bit 12:     Rx MAC Control Frame */
02322         XM_MD_RX_RUNT   = 1<<11, /* Bit 11:     Rx Runt Frames */
02323         XM_MD_RX_IRLE   = 1<<10, /* Bit 10:     Rx in Range Len Err Frame */
02324         XM_MD_RX_LONG   = 1<<9,  /* Bit  9:     Rx Long Frame */
02325         XM_MD_RX_CRCE   = 1<<8,  /* Bit  8:     Rx CRC Error Frame */
02326         XM_MD_RX_ERR    = 1<<7,  /* Bit  7:     Rx Error Frame */
02327         XM_MD_DIS_UC    = 1<<6,  /* Bit  6:     Disable Rx Unicast */
02328         XM_MD_DIS_MC    = 1<<5,  /* Bit  5:     Disable Rx Multicast */
02329         XM_MD_DIS_BC    = 1<<4,  /* Bit  4:     Disable Rx Broadcast */
02330         XM_MD_ENA_PROM  = 1<<3,  /* Bit  3:     Enable Promiscuous */
02331         XM_MD_ENA_BE    = 1<<2,  /* Bit  2:     Enable Big Endian */
02332         XM_MD_FTF       = 1<<1,  /* Bit  1: (sc)        Flush Tx FIFO */
02333         XM_MD_FRF       = 1<<0,  /* Bit  0: (sc)        Flush Rx FIFO */
02334 };
02335 
02336 #define XM_PAUSE_MODE   (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
02337 #define XM_DEF_MODE     (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
02338                          XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
02339 
02340 /*      XM_STAT_CMD     16 bit r/w      Statistics Command Register */
02341 enum {
02342         XM_SC_SNP_RXC   = 1<<5, /* Bit  5: (sc) Snap Rx Counters */
02343         XM_SC_SNP_TXC   = 1<<4, /* Bit  4: (sc) Snap Tx Counters */
02344         XM_SC_CP_RXC    = 1<<3, /* Bit  3:      Copy Rx Counters Continuously */
02345         XM_SC_CP_TXC    = 1<<2, /* Bit  2:      Copy Tx Counters Continuously */
02346         XM_SC_CLR_RXC   = 1<<1, /* Bit  1: (sc) Clear Rx Counters */
02347         XM_SC_CLR_TXC   = 1<<0, /* Bit  0: (sc) Clear Tx Counters */
02348 };
02349 
02350 
02351 /*      XM_RX_CNT_EV    32 bit r/o      Rx Counter Event Register */
02352 /*      XM_RX_EV_MSK    32 bit r/w      Rx Counter Event Mask */
02353 enum {
02354         XMR_MAX_SZ_OV   = 1<<31, /* Bit 31:     1024-MaxSize Rx Cnt Ov*/
02355         XMR_1023B_OV    = 1<<30, /* Bit 30:     512-1023Byte Rx Cnt Ov*/
02356         XMR_511B_OV     = 1<<29, /* Bit 29:     256-511 Byte Rx Cnt Ov*/
02357         XMR_255B_OV     = 1<<28, /* Bit 28:     128-255 Byte Rx Cnt Ov*/
02358         XMR_127B_OV     = 1<<27, /* Bit 27:     65-127 Byte Rx Cnt Ov */
02359         XMR_64B_OV      = 1<<26, /* Bit 26:     64 Byte Rx Cnt Ov */
02360         XMR_UTIL_OV     = 1<<25, /* Bit 25:     Rx Util Cnt Overflow */
02361         XMR_UTIL_UR     = 1<<24, /* Bit 24:     Rx Util Cnt Underrun */
02362         XMR_CEX_ERR_OV  = 1<<23, /* Bit 23:     CEXT Err Cnt Ov */
02363         XMR_FCS_ERR_OV  = 1<<21, /* Bit 21:     Rx FCS Error Cnt Ov */
02364         XMR_LNG_ERR_OV  = 1<<20, /* Bit 20:     Rx too Long Err Cnt Ov*/
02365         XMR_RUNT_OV     = 1<<19, /* Bit 19:     Runt Event Cnt Ov */
02366         XMR_SHT_ERR_OV  = 1<<18, /* Bit 18:     Rx Short Ev Err Cnt Ov*/
02367         XMR_SYM_ERR_OV  = 1<<17, /* Bit 17:     Rx Sym Err Cnt Ov */
02368         XMR_CAR_ERR_OV  = 1<<15, /* Bit 15:     Rx Carr Ev Err Cnt Ov */
02369         XMR_JAB_PKT_OV  = 1<<14, /* Bit 14:     Rx Jabb Packet Cnt Ov */
02370         XMR_FIFO_OV     = 1<<13, /* Bit 13:     Rx FIFO Ov Ev Cnt Ov */
02371         XMR_FRA_ERR_OV  = 1<<12, /* Bit 12:     Rx Framing Err Cnt Ov */
02372         XMR_FMISS_OV    = 1<<11, /* Bit 11:     Rx Missed Ev Cnt Ov */
02373         XMR_BURST       = 1<<10, /* Bit 10:     Rx Burst Event Cnt Ov */
02374         XMR_INV_MOC     = 1<<9,  /* Bit  9:     Rx with inv. MAC OC Ov*/
02375         XMR_INV_MP      = 1<<8,  /* Bit  8:     Rx inv Pause Frame Ov */
02376         XMR_MCTRL_OV    = 1<<7,  /* Bit  7:     Rx MAC Ctrl-F Cnt Ov */
02377         XMR_MPAUSE_OV   = 1<<6,  /* Bit  6:     Rx Pause MAC Ctrl-F Ov*/
02378         XMR_UC_OK_OV    = 1<<5,  /* Bit  5:     Rx Unicast Frame CntOv*/
02379         XMR_MC_OK_OV    = 1<<4,  /* Bit  4:     Rx Multicast Cnt Ov */
02380         XMR_BC_OK_OV    = 1<<3,  /* Bit  3:     Rx Broadcast Cnt Ov */
02381         XMR_OK_LO_OV    = 1<<2,  /* Bit  2:     Octets Rx OK Low CntOv*/
02382         XMR_OK_HI_OV    = 1<<1,  /* Bit  1:     Octets Rx OK Hi Cnt Ov*/
02383         XMR_OK_OV       = 1<<0,  /* Bit  0:     Frames Received Ok Ov */
02384 };
02385 
02386 #define XMR_DEF_MSK             (XMR_OK_LO_OV | XMR_OK_HI_OV)
02387 
02388 /*      XM_TX_CNT_EV    32 bit r/o      Tx Counter Event Register */
02389 /*      XM_TX_EV_MSK    32 bit r/w      Tx Counter Event Mask */
02390 enum {
02391         XMT_MAX_SZ_OV   = 1<<25,        /* Bit 25:      1024-MaxSize Tx Cnt Ov*/
02392         XMT_1023B_OV    = 1<<24,        /* Bit 24:      512-1023Byte Tx Cnt Ov*/
02393         XMT_511B_OV     = 1<<23,        /* Bit 23:      256-511 Byte Tx Cnt Ov*/
02394         XMT_255B_OV     = 1<<22,        /* Bit 22:      128-255 Byte Tx Cnt Ov*/
02395         XMT_127B_OV     = 1<<21,        /* Bit 21:      65-127 Byte Tx Cnt Ov */
02396         XMT_64B_OV      = 1<<20,        /* Bit 20:      64 Byte Tx Cnt Ov */
02397         XMT_UTIL_OV     = 1<<19,        /* Bit 19:      Tx Util Cnt Overflow */
02398         XMT_UTIL_UR     = 1<<18,        /* Bit 18:      Tx Util Cnt Underrun */
02399         XMT_CS_ERR_OV   = 1<<17,        /* Bit 17:      Tx Carr Sen Err Cnt Ov*/
02400         XMT_FIFO_UR_OV  = 1<<16,        /* Bit 16:      Tx FIFO Ur Ev Cnt Ov */
02401         XMT_EX_DEF_OV   = 1<<15,        /* Bit 15:      Tx Ex Deferall Cnt Ov */
02402         XMT_DEF = 1<<14,        /* Bit 14:      Tx Deferred Cnt Ov */
02403         XMT_LAT_COL_OV  = 1<<13,        /* Bit 13:      Tx Late Col Cnt Ov */
02404         XMT_ABO_COL_OV  = 1<<12,        /* Bit 12:      Tx abo dueto Ex Col Ov*/
02405         XMT_MUL_COL_OV  = 1<<11,        /* Bit 11:      Tx Mult Col Cnt Ov */
02406         XMT_SNG_COL     = 1<<10,        /* Bit 10:      Tx Single Col Cnt Ov */
02407         XMT_MCTRL_OV    = 1<<9,         /* Bit  9:      Tx MAC Ctrl Counter Ov*/
02408         XMT_MPAUSE      = 1<<8,         /* Bit  8:      Tx Pause MAC Ctrl-F Ov*/
02409         XMT_BURST       = 1<<7,         /* Bit  7:      Tx Burst Event Cnt Ov */
02410         XMT_LONG        = 1<<6,         /* Bit  6:      Tx Long Frame Cnt Ov */
02411         XMT_UC_OK_OV    = 1<<5,         /* Bit  5:      Tx Unicast Cnt Ov */
02412         XMT_MC_OK_OV    = 1<<4,         /* Bit  4:      Tx Multicast Cnt Ov */
02413         XMT_BC_OK_OV    = 1<<3,         /* Bit  3:      Tx Broadcast Cnt Ov */
02414         XMT_OK_LO_OV    = 1<<2,         /* Bit  2:      Octets Tx OK Low CntOv*/
02415         XMT_OK_HI_OV    = 1<<1,         /* Bit  1:      Octets Tx OK Hi Cnt Ov*/
02416         XMT_OK_OV       = 1<<0,         /* Bit  0:      Frames Tx Ok Ov */
02417 };
02418 
02419 
02420 #define XMT_DEF_MSK             (XMT_OK_LO_OV | XMT_OK_HI_OV)
02421 
02422 struct skge_rx_desc {
02423         u32             control;
02424         u32             next_offset;
02425         u32             dma_lo;
02426         u32             dma_hi;
02427         u32             status;
02428         u32             timestamp;
02429         u16             csum2;
02430         u16             csum1;
02431         u16             csum2_start;
02432         u16             csum1_start;
02433 };
02434 
02435 struct skge_tx_desc {
02436         u32             control;
02437         u32             next_offset;
02438         u32             dma_lo;
02439         u32             dma_hi;
02440         u32             status;
02441         u32             csum_offs;
02442         u16             csum_write;
02443         u16             csum_start;
02444         u32             rsvd;
02445 };
02446 
02447 struct skge_element {
02448         struct skge_element     *next;
02449         void                    *desc;
02450         struct io_buffer        *iob;
02451 };
02452 
02453 struct skge_ring {
02454         struct skge_element *to_clean;
02455         struct skge_element *to_use;
02456         struct skge_element *start;
02457 };
02458 
02459 
02460 struct skge_hw {
02461         unsigned long        regs;
02462         struct pci_device    *pdev;
02463         u32                  intr_mask;
02464         struct net_device    *dev[2];
02465 
02466         u8                   chip_id;
02467         u8                   chip_rev;
02468         u8                   copper;
02469         u8                   ports;
02470         u8                   phy_type;
02471 
02472         u32                  ram_size;
02473         u32                  ram_offset;
02474         u16                  phy_addr;
02475 };
02476 
02477 enum pause_control {
02478         FLOW_MODE_NONE          = 1, /* No Flow-Control */
02479         FLOW_MODE_LOC_SEND      = 2, /* Local station sends PAUSE */
02480         FLOW_MODE_SYMMETRIC     = 3, /* Both stations may send PAUSE */
02481         FLOW_MODE_SYM_OR_REM    = 4, /* Both stations may send PAUSE or
02482                                       * just the remote station may send PAUSE
02483                                       */
02484 };
02485 
02486 enum pause_status {
02487         FLOW_STAT_INDETERMINATED=0,     /* indeterminated */
02488         FLOW_STAT_NONE,                 /* No Flow Control */
02489         FLOW_STAT_REM_SEND,             /* Remote Station sends PAUSE */
02490         FLOW_STAT_LOC_SEND,             /* Local station sends PAUSE */
02491         FLOW_STAT_SYMMETRIC,            /* Both station may send PAUSE */
02492 };
02493 
02494 
02495 struct skge_port {
02496         struct skge_hw       *hw;
02497         struct net_device    *netdev;
02498         int                  port;
02499 
02500         struct skge_ring     tx_ring;
02501         struct skge_ring     rx_ring;
02502 
02503         enum pause_control   flow_control;
02504         enum pause_status    flow_status;
02505         u8                   autoneg;   /* AUTONEG_ENABLE, AUTONEG_DISABLE */
02506         u8                   duplex;    /* DUPLEX_HALF, DUPLEX_FULL */
02507         u16                  speed;     /* SPEED_1000, SPEED_100, ... */
02508         u32                  advertising;
02509 
02510         void                 *mem;      /* PCI memory for rings */
02511         u32                  dma;
02512         int                  use_xm_link_timer;
02513 };
02514 
02515 
02516 /* Register accessor for memory mapped device */
02517 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
02518 {
02519         return readl(hw->regs + reg);
02520 }
02521 
02522 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
02523 {
02524         return readw(hw->regs + reg);
02525 }
02526 
02527 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
02528 {
02529         return readb(hw->regs + reg);
02530 }
02531 
02532 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
02533 {
02534         writel(val, hw->regs + reg);
02535 }
02536 
02537 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
02538 {
02539         writew(val, hw->regs + reg);
02540 }
02541 
02542 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
02543 {
02544         writeb(val, hw->regs + reg);
02545 }
02546 
02547 /* MAC Related Registers inside the device. */
02548 #define SK_REG(port,reg)        (((port)<<7)+(u16)(reg))
02549 #define SK_XMAC_REG(port, reg) \
02550         ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
02551 
02552 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
02553 {
02554         u32 v;
02555         v = skge_read16(hw, SK_XMAC_REG(port, reg));
02556         v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
02557         return v;
02558 }
02559 
02560 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
02561 {
02562         return skge_read16(hw, SK_XMAC_REG(port,reg));
02563 }
02564 
02565 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
02566 {
02567         skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
02568         skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
02569 }
02570 
02571 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
02572 {
02573         skge_write16(hw, SK_XMAC_REG(port,r), v);
02574 }
02575 
02576 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
02577                                    const u8 *hash)
02578 {
02579         xm_write16(hw, port, reg,   (u16)hash[0] | ((u16)hash[1] << 8));
02580         xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
02581         xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
02582         xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
02583 }
02584 
02585 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
02586                                    const u8 *addr)
02587 {
02588         xm_write16(hw, port, reg,   (u16)addr[0] | ((u16)addr[1] << 8));
02589         xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
02590         xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
02591 }
02592 
02593 #define SK_GMAC_REG(port,reg) \
02594         (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
02595 
02596 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
02597 {
02598         return skge_read16(hw, SK_GMAC_REG(port,reg));
02599 }
02600 
02601 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
02602 {
02603         return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
02604                 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
02605 }
02606 
02607 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
02608 {
02609         skge_write16(hw, SK_GMAC_REG(port,r), v);
02610 }
02611 
02612 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
02613                                     const u8 *addr)
02614 {
02615         gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
02616         gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
02617         gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
02618 }
02619 
02620 #endif