iPXE
ath5k_qcu.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4  *
5  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  */
20 
21 FILE_LICENCE ( MIT );
22 
23 /********************************************\
24 Queue Control Unit, DFS Control Unit Functions
25 \********************************************/
26 
27 #include "ath5k.h"
28 #include "reg.h"
29 #include "base.h"
30 
31 /*
32  * Set properties for a transmit queue
33  */
35  const struct ath5k_txq_info *queue_info)
36 {
37  if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
38  return -EIO;
39 
40  memcpy(&ah->ah_txq, queue_info, sizeof(struct ath5k_txq_info));
41 
42  /*XXX: Is this supported on 5210 ?*/
43  if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
44  ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
45  (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
46  queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
47  ah->ah_txq.tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
48 
49  return 0;
50 }
51 
52 /*
53  * Initialize a transmit queue
54  */
55 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
56  struct ath5k_txq_info *queue_info)
57 {
58  int ret;
59 
60  /*
61  * Setup internal queue structure
62  */
63  memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info));
64  ah->ah_txq.tqi_type = queue_type;
65 
66  if (queue_info != NULL) {
67  queue_info->tqi_type = queue_type;
68  ret = ath5k_hw_set_tx_queueprops(ah, queue_info);
69  if (ret)
70  return ret;
71  }
72 
73  /*
74  * We use ah_txq_status to hold a temp value for
75  * the Secondary interrupt mask registers on 5211+
76  * check out ath5k_hw_reset_tx_queue
77  */
78  AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0);
79 
80  return 0;
81 }
82 
83 /*
84  * Set a transmit queue inactive
85  */
87 {
88  /* This queue will be skipped in further operations */
89  ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE;
90  /*For SIMR setup*/
91  AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0);
92 }
93 
94 /*
95  * Set DFS properties for a transmit queue on DCU
96  */
98 {
99  u32 cw_min, cw_max, retry_lg, retry_sh;
100  struct ath5k_txq_info *tq = &ah->ah_txq;
101  const int queue = 0;
102 
103  tq = &ah->ah_txq;
104 
105  if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
106  return 0;
107 
108  if (ah->ah_version == AR5K_AR5210) {
109  /* Only handle data queues, others will be ignored */
110  if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
111  return 0;
112 
113  /* Set Slot time */
114  ath5k_hw_reg_write(ah, ah->ah_turbo ?
117  /* Set ACK_CTS timeout */
118  ath5k_hw_reg_write(ah, ah->ah_turbo ?
121  /* Set Transmit Latency */
122  ath5k_hw_reg_write(ah, ah->ah_turbo ?
125 
126  /* Set IFS0 */
127  if (ah->ah_turbo) {
129  (ah->ah_aifs + tq->tqi_aifs) *
132  AR5K_IFS0);
133  } else {
135  (ah->ah_aifs + tq->tqi_aifs) *
138  }
139 
140  /* Set IFS1 */
141  ath5k_hw_reg_write(ah, ah->ah_turbo ?
144  /* Set AR5K_PHY_SETTLING */
145  ath5k_hw_reg_write(ah, ah->ah_turbo ?
147  | 0x38 :
149  | 0x1C,
151  /* Set Frame Control Register */
152  ath5k_hw_reg_write(ah, ah->ah_turbo ?
154  AR5K_PHY_TURBO_SHORT | 0x2020) :
155  (AR5K_PHY_FRAME_CTL_INI | 0x1020),
157  }
158 
159  /*
160  * Calculate cwmin/max by channel mode
161  */
162  cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
163  cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
164  ah->ah_aifs = AR5K_TUNE_AIFS;
165  /*XR is only supported on 5212*/
166  if (IS_CHAN_XR(ah->ah_current_channel) &&
167  ah->ah_version == AR5K_AR5212) {
168  cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
169  cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
170  ah->ah_aifs = AR5K_TUNE_AIFS_XR;
171  /*B mode is not supported on 5210*/
172  } else if (IS_CHAN_B(ah->ah_current_channel) &&
173  ah->ah_version != AR5K_AR5210) {
174  cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
175  cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
176  ah->ah_aifs = AR5K_TUNE_AIFS_11B;
177  }
178 
179  cw_min = 1;
180  while (cw_min < ah->ah_cw_min)
181  cw_min = (cw_min << 1) | 1;
182 
183  cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
184  ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
185  cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
186  ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
187 
188  /*
189  * Calculate and set retry limits
190  */
191  if (ah->ah_software_retry) {
192  /* XXX Need to test this */
193  retry_lg = ah->ah_limit_tx_retries;
194  retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
195  AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
196  } else {
197  retry_lg = AR5K_INIT_LG_RETRY;
198  retry_sh = AR5K_INIT_SH_RETRY;
199  }
200 
201  /*No QCU/DCU [5210]*/
202  if (ah->ah_version == AR5K_AR5210) {
212  } else {
213  /*QCU/DCU [5211+]*/
222 
223  /*===Rest is also for QCU/DCU only [5211+]===*/
224 
225  /*
226  * Set initial content window (cw_min/cw_max)
227  * and arbitrated interframe space (aifs)...
228  */
232  AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
235 
236  /*
237  * Set misc registers
238  */
239  /* Enable DCU early termination for this queue */
242 
243  /* Enable DCU to wait for next fragment from QCU */
246 
247  /* On Maui and Spirit use the global seqnum on DCU */
248  if (ah->ah_mac_version < AR5K_SREV_AR5211)
251 
252  if (tq->tqi_cbr_period) {
260  if (tq->tqi_cbr_overflow_limit)
264  }
265 
266  if (tq->tqi_ready_time &&
267  (tq->tqi_type != AR5K_TX_QUEUE_CAB))
272 
273  if (tq->tqi_burst_time) {
278 
279  if (tq->tqi_flags
284  }
285 
289 
293 
294  /* TODO: Handle frame compression */
295 
296  /*
297  * Enable interrupts for this tx queue
298  * in the secondary interrupt mask registers
299  */
301  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
302 
304  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
305 
307  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
308 
310  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
311 
313  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
314 
316  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
317 
319  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
320 
322  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
323 
325  AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
326 
327  /* Update secondary interrupt mask registers */
328 
329  /* Filter out inactive queues */
330  ah->ah_txq_imr_txok &= ah->ah_txq_status;
331  ah->ah_txq_imr_txerr &= ah->ah_txq_status;
332  ah->ah_txq_imr_txurn &= ah->ah_txq_status;
333  ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
334  ah->ah_txq_imr_txeol &= ah->ah_txq_status;
335  ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
336  ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
337  ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
338  ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
339 
340  ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
342  AR5K_REG_SM(ah->ah_txq_imr_txdesc,
344  ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
346  AR5K_REG_SM(ah->ah_txq_imr_txeol,
348  /* Update simr2 but don't overwrite rest simr2 settings */
351  AR5K_REG_SM(ah->ah_txq_imr_txurn,
353  ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
355  AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
357  ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
359  /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
360  ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
362  /* No queue has TXNOFRM enabled, disable the interrupt
363  * by setting AR5K_TXNOFRM to zero */
364  if (ah->ah_txq_imr_nofrm == 0)
366 
367  /* Set QCU mask for this DCU to save power */
369  }
370 
371  return 0;
372 }
373 
374 /*
375  * Set slot time on DCU
376  */
377 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
378 {
379  if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
380  return -EINVAL;
381 
382  if (ah->ah_version == AR5K_AR5210)
384  ah->ah_turbo), AR5K_SLOT_TIME);
385  else
387 
388  return 0;
389 }
390 
#define AR5K_QCU_MISC_DCU_EARLY
Definition: reg.h:618
int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
Definition: ath5k_qcu.c:34
#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE
Definition: ath5k.h:496
#define AR5K_PHY_SETTLING
Definition: reg.h:1975
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_QCU_MISC_RDY_VEOL_POLICY
Definition: reg.h:616
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
Definition: ath5k.h:499
#define AR5K_QCU_RDYTIMECFG_INTVAL
Definition: reg.h:584
#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE
Definition: ath5k.h:493
#define AR5K_NODCU_RETRY_LMT_SLG_RETRY
Definition: reg.h:1212
#define AR5K_INIT_SLG_RETRY
Definition: ath5k.h:227
#define AR5K_SIMR3
Definition: reg.h:444
#define AR5K_INIT_PROTO_TIME_CNTRL
Definition: ath5k.h:238
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
#define AR5K_DCU_CHAN_TIME_ENABLE
Definition: reg.h:708
#define AR5K_TXQ_FLAG_TXERRINT_ENABLE
Definition: ath5k.h:489
#define AR5K_NODCU_RETRY_LMT_SSH_RETRY
Definition: reg.h:1210
#define AR5K_TUNE_CWMAX
Definition: ath5k.h:187
#define AR5K_Q_ENABLE_BITS(_reg, _queue)
Definition: ath5k.h:124
#define AR5K_SLOT_TIME_MAX
Definition: ath5k.h:625
#define AR5K_Q_DISABLE_BITS(_reg, _queue)
Definition: ath5k.h:128
#define AR5K_SIMR1_QCU_TXEOL
Definition: reg.h:427
#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS
Definition: reg.h:746
int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:97
#define AR5K_DCU_GBL_IFS_SLOT
Definition: reg.h:768
#define AR5K_INIT_ACK_CTS_TIMEOUT
Definition: ath5k.h:216
#define AR5K_NODCU_RETRY_LMT
Definition: reg.h:1205
#define AR5K_TUNE_CWMAX_XR
Definition: ath5k.h:189
#define AR5K_SIMR0_QCU_TXDESC
Definition: reg.h:421
#define AR5K_QUEUE_RDYTIMECFG(_q)
Definition: reg.h:587
int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
Definition: ath5k_qcu.c:55
#define AR5K_QUEUE_DFS_MISC(_q)
Definition: reg.h:750
#define AR5K_TUNE_CWMIN
Definition: ath5k.h:184
#define AR5K_QUEUE_CBRCFG(_q)
Definition: reg.h:578
#define AR5K_QUEUE_QCUMASK(_q)
Definition: reg.h:673
#define IS_CHAN_XR(_c)
Definition: ath5k.h:657
#define AR5K_QCU_MISC_FRSHED_CBR
Definition: reg.h:607
#define AR5K_INIT_SH_RETRY
Definition: ath5k.h:224
#define AR5K_DCU_MISC_SEQNUM_CTL
Definition: reg.h:749
#define AR5K_TUNE_CWMIN_XR
Definition: ath5k.h:186
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
#define AR5K_DCU_LCL_IFS_CW_MIN
Definition: reg.h:679
int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
Definition: ath5k_qcu.c:377
u32 tqi_burst_time
Definition: ath5k.h:515
#define AR5K_INIT_SSH_RETRY
Definition: ath5k.h:226
#define AR5K_USEC_5210
Definition: reg.h:1220
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE
Definition: ath5k.h:497
#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)
Definition: reg.h:709
#define AR5K_SIMR4
Definition: reg.h:450
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)
Definition: ath5k.h:121
#define AR5K_SIMR1_QCU_TXERR
Definition: reg.h:425
#define AR5K_INIT_TRANSMIT_LATENCY
Definition: ath5k.h:230
u32 tqi_cbr_period
Definition: ath5k.h:513
#define AR5K_DCU_LCL_IFS_AIFS
Definition: reg.h:683
static unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
Definition: ath5k.h:1197
#define AR5K_DCU_MISC_FRAG_WAIT
Definition: reg.h:730
#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE
Definition: ath5k.h:494
ath5k_tx_queue
enum ath5k_tx_queue - Queue types used to classify tx queues.
Definition: ath5k.h:444
#define AR5K_DCU_RETRY_LMT_SSH_RETRY
Definition: reg.h:696
#define AR5K_TXQ_FLAG_TXURNINT_ENABLE
Definition: ath5k.h:492
#define AR5K_PHY_TURBO_MODE
Definition: reg.h:1897
#define AR5K_QCU_CBRCFG_ORN_THRES
Definition: reg.h:576
#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)
Definition: reg.h:686
#define AR5K_DCU_LCL_IFS_CW_MAX
Definition: reg.h:681
#define AR5K_IFS0_DIFS_S
Definition: reg.h:1299
#define AR5K_INIT_LG_RETRY
Definition: ath5k.h:225
enum ath5k_tx_queue tqi_type
Definition: ath5k.h:507
u32 tqi_cbr_overflow_limit
Definition: ath5k.h:514
#define AR5K_DCU_RETRY_LMT_LG_RETRY
Definition: reg.h:694
enum ath5k_tx_queue_subtype tqi_subtype
Definition: ath5k.h:508
#define AR5K_NODCU_RETRY_LMT_LG_RETRY
Definition: reg.h:1208
#define AR5K_INIT_SLOT_TIME_TURBO
Definition: ath5k.h:215
#define AR5K_SIMR4_QTRIG
Definition: reg.h:451
#define AR5K_NODCU_RETRY_LMT_CW_MIN_S
Definition: reg.h:1215
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO
Definition: ath5k.h:242
#define AR5K_SIMR2
Definition: reg.h:430
u32 tqi_aifs
Definition: ath5k.h:510
#define AR5K_TXNOFRM
Definition: reg.h:235
s32 tqi_cw_max
Definition: ath5k.h:512
#define AR5K_SIMR3_QCBRURN
Definition: reg.h:447
#define AR5K_INIT_SIFS
Definition: ath5k.h:222
#define AR5K_DCU_RETRY_LMT_SH_RETRY
Definition: reg.h:692
#define AR5K_PHY_FRAME_CTL_INI
Definition: reg.h:2288
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE
Definition: ath5k.h:490
#define AR5K_SIMR1
Definition: reg.h:424
#define AR5K_INIT_SLOT_TIME
Definition: ath5k.h:214
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO
Definition: ath5k.h:234
#define AR5K_DCU_MISC_BACKOFF_FRAG
Definition: reg.h:731
#define AR5K_QUEUE_MISC(_q)
Definition: reg.h:620
#define AR5K_SIMR0
Definition: reg.h:418
void ath5k_hw_release_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:86
#define AR5K_TXNOFRM_QCU
Definition: reg.h:237
FILE_LICENCE(MIT)
#define AR5K_PHY_TURBO_SHORT
Definition: reg.h:1898
#define AR5K_TUNE_AIFS
Definition: ath5k.h:181
#define AR5K_QCU_MISC_CBR_THRES_ENABLE
Definition: reg.h:615
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:107
#define AR5K_PHY_FRAME_CTL_5210
Definition: reg.h:2271
#define AR5K_SIMR0_QCU_TXOK
Definition: reg.h:419
#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)
Definition: reg.h:700
#define EIO
Input/output error.
Definition: errno.h:433
#define AR5K_IFS1
Definition: reg.h:1304
u16 tqi_flags
Definition: ath5k.h:509
#define AR5K_TXQ_FLAG_TXOKINT_ENABLE
Definition: ath5k.h:488
#define AR5K_SIMR3_QCBRORN
Definition: reg.h:445
s32 tqi_cw_min
Definition: ath5k.h:511
#define AR5K_SLOT_TIME
Definition: reg.h:1168
#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO
Definition: ath5k.h:217
u32 tqi_ready_time
Definition: ath5k.h:516
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE
Definition: ath5k.h:491
#define AR5K_TUNE_AIFS_XR
Definition: ath5k.h:183
#define AR5K_NODCU_RETRY_LMT_SH_RETRY
Definition: reg.h:1206
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS
Definition: ath5k.h:500
#define AR5K_TUNE_CWMAX_11B
Definition: ath5k.h:188
#define AR5K_TUNE_AIFS_11B
Definition: ath5k.h:182
uint8_t ah
Definition: registers.h:85
#define AR5K_DCU_CHAN_TIME_DUR
Definition: reg.h:706
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
Definition: ath5k.h:498
#define AR5K_QCU_CBRCFG_INTVAL
Definition: reg.h:574
#define AR5K_SREV_AR5211
Definition: ath5k.h:292
#define AR5K_IFS0
Definition: reg.h:1295
uint16_t queue
Queue ID.
Definition: ena.h:22
#define AR5K_TUNE_CWMIN_11B
Definition: ath5k.h:185
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE
Definition: ath5k.h:495
#define AR5K_SIMR2_QCU_TXURN
Definition: reg.h:431
uint32_t u32
Definition: stdint.h:23
#define AR5K_DCU_RETRY_LMT_SLG_RETRY
Definition: reg.h:698
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104
#define AR5K_INIT_SIFS_TURBO
Definition: ath5k.h:223
void * memset(void *dest, int character, size_t len) __nonnull
#define AR5K_REG_SM(_val, _flags)
Definition: ath5k.h:84
#define AR5K_QCU_RDYTIMECFG_ENABLE
Definition: reg.h:586