64 ah->ah_txq.tqi_type = queue_type;
66 if (queue_info !=
NULL) {
99 u32 cw_min, cw_max, retry_lg, retry_sh;
180 while (cw_min < ah->ah_cw_min)
181 cw_min = (cw_min << 1) | 1;
191 if (
ah->ah_software_retry) {
193 retry_lg =
ah->ah_limit_tx_retries;
330 ah->ah_txq_imr_txok &=
ah->ah_txq_status;
331 ah->ah_txq_imr_txerr &=
ah->ah_txq_status;
332 ah->ah_txq_imr_txurn &=
ah->ah_txq_status;
333 ah->ah_txq_imr_txdesc &=
ah->ah_txq_status;
334 ah->ah_txq_imr_txeol &=
ah->ah_txq_status;
335 ah->ah_txq_imr_cbrorn &=
ah->ah_txq_status;
336 ah->ah_txq_imr_cbrurn &=
ah->ah_txq_status;
337 ah->ah_txq_imr_qtrig &=
ah->ah_txq_status;
338 ah->ah_txq_imr_nofrm &=
ah->ah_txq_status;
364 if (
ah->ah_txq_imr_nofrm == 0)
#define AR5K_QCU_MISC_DCU_EARLY
int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE
#define AR5K_PHY_SETTLING
#define EINVAL
Invalid argument.
#define AR5K_QCU_MISC_RDY_VEOL_POLICY
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
#define AR5K_QCU_RDYTIMECFG_INTVAL
#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE
#define AR5K_NODCU_RETRY_LMT_SLG_RETRY
#define AR5K_INIT_SLG_RETRY
#define AR5K_INIT_PROTO_TIME_CNTRL
#define AR5K_DCU_CHAN_TIME_ENABLE
#define AR5K_TXQ_FLAG_TXERRINT_ENABLE
#define AR5K_NODCU_RETRY_LMT_SSH_RETRY
#define AR5K_Q_ENABLE_BITS(_reg, _queue)
#define AR5K_SLOT_TIME_MAX
#define AR5K_Q_DISABLE_BITS(_reg, _queue)
#define AR5K_SIMR1_QCU_TXEOL
#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS
int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah)
#define AR5K_DCU_GBL_IFS_SLOT
#define AR5K_INIT_ACK_CTS_TIMEOUT
#define AR5K_NODCU_RETRY_LMT
#define AR5K_TUNE_CWMAX_XR
#define AR5K_SIMR0_QCU_TXDESC
#define AR5K_QUEUE_RDYTIMECFG(_q)
int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
#define AR5K_QUEUE_DFS_MISC(_q)
#define AR5K_QUEUE_CBRCFG(_q)
#define AR5K_QUEUE_QCUMASK(_q)
#define AR5K_QCU_MISC_FRSHED_CBR
#define AR5K_INIT_SH_RETRY
#define AR5K_DCU_MISC_SEQNUM_CTL
#define AR5K_TUNE_CWMIN_XR
ath5k_hw_get_isr - Get interrupt status
#define AR5K_DCU_LCL_IFS_CW_MIN
int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
#define AR5K_INIT_SSH_RETRY
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE
#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)
#define AR5K_SIMR1_QCU_TXERR
#define AR5K_INIT_TRANSMIT_LATENCY
#define AR5K_DCU_LCL_IFS_AIFS
static unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
#define AR5K_DCU_MISC_FRAG_WAIT
#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE
ath5k_tx_queue
enum ath5k_tx_queue - Queue types used to classify tx queues.
#define AR5K_DCU_RETRY_LMT_SSH_RETRY
#define AR5K_TXQ_FLAG_TXURNINT_ENABLE
#define AR5K_PHY_TURBO_MODE
#define AR5K_QCU_CBRCFG_ORN_THRES
#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)
#define AR5K_DCU_LCL_IFS_CW_MAX
#define AR5K_INIT_LG_RETRY
enum ath5k_tx_queue tqi_type
u32 tqi_cbr_overflow_limit
#define AR5K_DCU_RETRY_LMT_LG_RETRY
enum ath5k_tx_queue_subtype tqi_subtype
#define AR5K_NODCU_RETRY_LMT_LG_RETRY
#define AR5K_INIT_SLOT_TIME_TURBO
#define AR5K_NODCU_RETRY_LMT_CW_MIN_S
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO
#define AR5K_SIMR3_QCBRURN
#define AR5K_DCU_RETRY_LMT_SH_RETRY
#define AR5K_PHY_FRAME_CTL_INI
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE
#define AR5K_INIT_SLOT_TIME
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO
#define AR5K_DCU_MISC_BACKOFF_FRAG
#define AR5K_QUEUE_MISC(_q)
void ath5k_hw_release_tx_queue(struct ath5k_hw *ah)
#define AR5K_PHY_TURBO_SHORT
#define AR5K_QCU_MISC_CBR_THRES_ENABLE
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
#define AR5K_PHY_FRAME_CTL_5210
#define AR5K_SIMR0_QCU_TXOK
#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)
#define EIO
Input/output error.
#define AR5K_TXQ_FLAG_TXOKINT_ENABLE
#define AR5K_SIMR3_QCBRORN
#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE
#define AR5K_TUNE_AIFS_XR
#define AR5K_NODCU_RETRY_LMT_SH_RETRY
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS
#define AR5K_TUNE_CWMAX_11B
#define AR5K_TUNE_AIFS_11B
#define AR5K_DCU_CHAN_TIME_DUR
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
#define AR5K_QCU_CBRCFG_INTVAL
#define AR5K_TUNE_CWMIN_11B
#define NULL
NULL pointer (VOID *)
#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE
#define AR5K_SIMR2_QCU_TXURN
#define AR5K_DCU_RETRY_LMT_SLG_RETRY
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
#define AR5K_INIT_SIFS_TURBO
void * memset(void *dest, int character, size_t len) __nonnull
#define AR5K_REG_SM(_val, _flags)
#define AR5K_QCU_RDYTIMECFG_ENABLE