iPXE
ath_hw.c
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1 /*
2  * Copyright (c) 2009 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 FILE_SECBOOT ( FORBIDDEN );
21 
22 #include <ipxe/io.h>
23 
24 #include "ath.h"
25 #include "reg.h"
26 
27 #define REG_READ (common->ops->read)
28 #define REG_WRITE (common->ops->write)
29 
30 /**
31  * ath_hw_set_bssid_mask - filter out bssids we listen
32  *
33  * @common: the ath_common struct for the device.
34  *
35  * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
36  * which bits of the interface's MAC address should be looked at when trying
37  * to decide which packets to ACK. In station mode and AP mode with a single
38  * BSS every bit matters since we lock to only one BSS. In AP mode with
39  * multiple BSSes (virtual interfaces) not every bit matters because hw must
40  * accept frames for all BSSes and so we tweak some bits of our mac address
41  * in order to have multiple BSSes.
42  *
43  * NOTE: This is a simple filter and does *not* filter out all
44  * relevant frames. Some frames that are not for us might get ACKed from us
45  * by PCU because they just match the mask.
46  *
47  * When handling multiple BSSes you can get the BSSID mask by computing the
48  * set of ~ ( MAC XOR BSSID ) for all bssids we handle.
49  *
50  * When you do this you are essentially computing the common bits of all your
51  * BSSes. Later it is assumed the hardware will "and" (&) the BSSID mask with
52  * the MAC address to obtain the relevant bits and compare the result with
53  * (frame's BSSID & mask) to see if they match.
54  *
55  * Simple example: on your card you have have two BSSes you have created with
56  * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
57  * There is another BSSID-03 but you are not part of it. For simplicity's sake,
58  * assuming only 4 bits for a mac address and for BSSIDs you can then have:
59  *
60  * \
61  * MAC: 0001 |
62  * BSSID-01: 0100 | --> Belongs to us
63  * BSSID-02: 1001 |
64  * /
65  * -------------------
66  * BSSID-03: 0110 | --> External
67  * -------------------
68  *
69  * Our bssid_mask would then be:
70  *
71  * On loop iteration for BSSID-01:
72  * ~(0001 ^ 0100) -> ~(0101)
73  * -> 1010
74  * bssid_mask = 1010
75  *
76  * On loop iteration for BSSID-02:
77  * bssid_mask &= ~(0001 ^ 1001)
78  * bssid_mask = (1010) & ~(0001 ^ 1001)
79  * bssid_mask = (1010) & ~(1000)
80  * bssid_mask = (1010) & (0111)
81  * bssid_mask = 0010
82  *
83  * A bssid_mask of 0010 means "only pay attention to the second least
84  * significant bit". This is because its the only bit common
85  * amongst the MAC and all BSSIDs we support. To findout what the real
86  * common bit is we can simply "&" the bssid_mask now with any BSSID we have
87  * or our MAC address (we assume the hardware uses the MAC address).
88  *
89  * Now, suppose there's an incoming frame for BSSID-03:
90  *
91  * IFRAME-01: 0110
92  *
93  * An easy eye-inspeciton of this already should tell you that this frame
94  * will not pass our check. This is because the bssid_mask tells the
95  * hardware to only look at the second least significant bit and the
96  * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
97  * as 1, which does not match 0.
98  *
99  * So with IFRAME-01 we *assume* the hardware will do:
100  *
101  * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
102  * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
103  * --> allow = (0010) == 0000 ? 1 : 0;
104  * --> allow = 0
105  *
106  * Lets now test a frame that should work:
107  *
108  * IFRAME-02: 0001 (we should allow)
109  *
110  * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
111  * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
112  * --> allow = (0000) == (0000)
113  * --> allow = 1
114  *
115  * Other examples:
116  *
117  * IFRAME-03: 0100 --> allowed
118  * IFRAME-04: 1001 --> allowed
119  * IFRAME-05: 1101 --> allowed but its not for us!!!
120  *
121  */
123 {
124  void *ah = common->ah;
125 
127  REG_WRITE(ah, get_unaligned_le16(common->bssidmask + 4), AR_BSSMSKU);
128 }
129 
130 
131 /**
132  * ath_hw_cycle_counters_update - common function to update cycle counters
133  *
134  * @common: the ath_common struct for the device.
135  *
136  * This function is used to update all cycle counters in one place.
137  * It has to be called while holding common->cc_lock!
138  */
140 {
141  u32 cycles, busy, rx, tx;
142  void *ah = common->ah;
143 
144  /* freeze */
146 
147  /* read */
148  cycles = REG_READ(ah, AR_CCCNT);
149  busy = REG_READ(ah, AR_RCCNT);
150  rx = REG_READ(ah, AR_RFCNT);
151  tx = REG_READ(ah, AR_TFCNT);
152 
153  /* clear */
154  REG_WRITE(ah, 0, AR_CCCNT);
155  REG_WRITE(ah, 0, AR_RFCNT);
156  REG_WRITE(ah, 0, AR_RCCNT);
157  REG_WRITE(ah, 0, AR_TFCNT);
158 
159  /* unfreeze */
160  REG_WRITE(ah, 0, AR_MIBC);
161 
162  /* update all cycle counters here */
163  common->cc_ani.cycles += cycles;
164  common->cc_ani.rx_busy += busy;
165  common->cc_ani.rx_frame += rx;
166  common->cc_ani.tx_frame += tx;
167 
168  common->cc_survey.cycles += cycles;
169  common->cc_survey.rx_busy += busy;
170  common->cc_survey.rx_frame += rx;
171  common->cc_survey.tx_frame += tx;
172 }
173 
175 {
176  struct ath_cycle_counters *cc = &common->cc_ani;
177  int32_t listen_time;
178 
179  listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) /
180  (common->clockrate * 1000);
181 
182  memset(cc, 0, sizeof(*cc));
183 
184  return listen_time;
185 }
iPXE I/O API
#define AR_RCCNT
Definition: reg.h:41
#define AR_BSSMSKL
Definition: reg.h:36
int32_t ath_hw_get_listen_time(struct ath_common *common)
Definition: ath_hw.c:174
#define REG_WRITE
Definition: ath_hw.c:28
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:89
#define REG_READ
Definition: ath_hw.c:27
#define AR_TFCNT
Definition: reg.h:39
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:85
#define AR_CCCNT
Definition: reg.h:42
#define AR_BSSMSKU
Definition: reg.h:37
struct ib_cm_common common
Definition: ib_mad.h:12
signed int int32_t
Definition: stdint.h:17
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
void ath_hw_cycle_counters_update(struct ath_common *common)
ath_hw_cycle_counters_update - common function to update cycle counters
Definition: ath_hw.c:139
uint8_t ah
Definition: registers.h:85
#define AR_MIBC
Definition: reg.h:26
FILE_SECBOOT(FORBIDDEN)
void ath_hw_setbssidmask(struct ath_common *common)
ath_hw_set_bssid_mask - filter out bssids we listen
Definition: ath_hw.c:122
#define AR_MIBC_FMC
Definition: reg.h:28
#define AR_RFCNT
Definition: reg.h:40
uint32_t u32
Definition: stdint.h:24
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
void * memset(void *dest, int character, size_t len) __nonnull