iPXE
ath_hw.c
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1 /*
2  * Copyright (c) 2009 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/io.h>
21 
22 #include "ath.h"
23 #include "reg.h"
24 
25 #define REG_READ (common->ops->read)
26 #define REG_WRITE (common->ops->write)
27 
28 /**
29  * ath_hw_set_bssid_mask - filter out bssids we listen
30  *
31  * @common: the ath_common struct for the device.
32  *
33  * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
34  * which bits of the interface's MAC address should be looked at when trying
35  * to decide which packets to ACK. In station mode and AP mode with a single
36  * BSS every bit matters since we lock to only one BSS. In AP mode with
37  * multiple BSSes (virtual interfaces) not every bit matters because hw must
38  * accept frames for all BSSes and so we tweak some bits of our mac address
39  * in order to have multiple BSSes.
40  *
41  * NOTE: This is a simple filter and does *not* filter out all
42  * relevant frames. Some frames that are not for us might get ACKed from us
43  * by PCU because they just match the mask.
44  *
45  * When handling multiple BSSes you can get the BSSID mask by computing the
46  * set of ~ ( MAC XOR BSSID ) for all bssids we handle.
47  *
48  * When you do this you are essentially computing the common bits of all your
49  * BSSes. Later it is assumed the hardware will "and" (&) the BSSID mask with
50  * the MAC address to obtain the relevant bits and compare the result with
51  * (frame's BSSID & mask) to see if they match.
52  *
53  * Simple example: on your card you have have two BSSes you have created with
54  * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
55  * There is another BSSID-03 but you are not part of it. For simplicity's sake,
56  * assuming only 4 bits for a mac address and for BSSIDs you can then have:
57  *
58  * \
59  * MAC: 0001 |
60  * BSSID-01: 0100 | --> Belongs to us
61  * BSSID-02: 1001 |
62  * /
63  * -------------------
64  * BSSID-03: 0110 | --> External
65  * -------------------
66  *
67  * Our bssid_mask would then be:
68  *
69  * On loop iteration for BSSID-01:
70  * ~(0001 ^ 0100) -> ~(0101)
71  * -> 1010
72  * bssid_mask = 1010
73  *
74  * On loop iteration for BSSID-02:
75  * bssid_mask &= ~(0001 ^ 1001)
76  * bssid_mask = (1010) & ~(0001 ^ 1001)
77  * bssid_mask = (1010) & ~(1000)
78  * bssid_mask = (1010) & (0111)
79  * bssid_mask = 0010
80  *
81  * A bssid_mask of 0010 means "only pay attention to the second least
82  * significant bit". This is because its the only bit common
83  * amongst the MAC and all BSSIDs we support. To findout what the real
84  * common bit is we can simply "&" the bssid_mask now with any BSSID we have
85  * or our MAC address (we assume the hardware uses the MAC address).
86  *
87  * Now, suppose there's an incoming frame for BSSID-03:
88  *
89  * IFRAME-01: 0110
90  *
91  * An easy eye-inspeciton of this already should tell you that this frame
92  * will not pass our check. This is because the bssid_mask tells the
93  * hardware to only look at the second least significant bit and the
94  * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
95  * as 1, which does not match 0.
96  *
97  * So with IFRAME-01 we *assume* the hardware will do:
98  *
99  * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
100  * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
101  * --> allow = (0010) == 0000 ? 1 : 0;
102  * --> allow = 0
103  *
104  * Lets now test a frame that should work:
105  *
106  * IFRAME-02: 0001 (we should allow)
107  *
108  * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
109  * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
110  * --> allow = (0000) == (0000)
111  * --> allow = 1
112  *
113  * Other examples:
114  *
115  * IFRAME-03: 0100 --> allowed
116  * IFRAME-04: 1001 --> allowed
117  * IFRAME-05: 1101 --> allowed but its not for us!!!
118  *
119  */
121 {
122  void *ah = common->ah;
123 
125  REG_WRITE(ah, get_unaligned_le16(common->bssidmask + 4), AR_BSSMSKU);
126 }
127 
128 
129 /**
130  * ath_hw_cycle_counters_update - common function to update cycle counters
131  *
132  * @common: the ath_common struct for the device.
133  *
134  * This function is used to update all cycle counters in one place.
135  * It has to be called while holding common->cc_lock!
136  */
138 {
139  u32 cycles, busy, rx, tx;
140  void *ah = common->ah;
141 
142  /* freeze */
144 
145  /* read */
146  cycles = REG_READ(ah, AR_CCCNT);
147  busy = REG_READ(ah, AR_RCCNT);
148  rx = REG_READ(ah, AR_RFCNT);
149  tx = REG_READ(ah, AR_TFCNT);
150 
151  /* clear */
152  REG_WRITE(ah, 0, AR_CCCNT);
153  REG_WRITE(ah, 0, AR_RFCNT);
154  REG_WRITE(ah, 0, AR_RCCNT);
155  REG_WRITE(ah, 0, AR_TFCNT);
156 
157  /* unfreeze */
158  REG_WRITE(ah, 0, AR_MIBC);
159 
160  /* update all cycle counters here */
161  common->cc_ani.cycles += cycles;
162  common->cc_ani.rx_busy += busy;
163  common->cc_ani.rx_frame += rx;
164  common->cc_ani.tx_frame += tx;
165 
166  common->cc_survey.cycles += cycles;
167  common->cc_survey.rx_busy += busy;
168  common->cc_survey.rx_frame += rx;
169  common->cc_survey.tx_frame += tx;
170 }
171 
173 {
174  struct ath_cycle_counters *cc = &common->cc_ani;
175  int32_t listen_time;
176 
177  listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) /
178  (common->clockrate * 1000);
179 
180  memset(cc, 0, sizeof(*cc));
181 
182  return listen_time;
183 }
iPXE I/O API
#define AR_RCCNT
Definition: reg.h:40
#define AR_BSSMSKL
Definition: reg.h:35
int32_t ath_hw_get_listen_time(struct ath_common *common)
Definition: ath_hw.c:172
#define REG_WRITE
Definition: ath_hw.c:26
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:87
#define REG_READ
Definition: ath_hw.c:25
#define AR_TFCNT
Definition: reg.h:38
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:83
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
#define AR_CCCNT
Definition: reg.h:41
#define AR_BSSMSKU
Definition: reg.h:36
struct ib_cm_common common
Definition: ib_mad.h:11
signed int int32_t
Definition: stdint.h:17
void ath_hw_cycle_counters_update(struct ath_common *common)
ath_hw_cycle_counters_update - common function to update cycle counters
Definition: ath_hw.c:137
uint8_t ah
Definition: registers.h:85
#define AR_MIBC
Definition: reg.h:25
void ath_hw_setbssidmask(struct ath_common *common)
ath_hw_set_bssid_mask - filter out bssids we listen
Definition: ath_hw.c:120
#define AR_MIBC_FMC
Definition: reg.h:27
#define AR_RFCNT
Definition: reg.h:39
uint32_t u32
Definition: stdint.h:23
void * memset(void *dest, int character, size_t len) __nonnull