iPXE
Data Structures | Macros | Enumerations | Functions
intel.h File Reference

Intel 10/100/1000 network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/nvs.h>
#include <ipxe/dma.h>

Go to the source code of this file.

Data Structures

struct  intel_descriptor
 A packet descriptor. More...
 
union  intel_receive_address
 Receive address. More...
 
struct  intel_ring
 An Intel descriptor ring. More...
 
struct  intel_mailbox
 An Intel virtual function mailbox. More...
 
struct  intel_nic
 An Intel network card. More...
 

Macros

#define INTEL_BAR_SIZE   ( 128 * 1024 )
 Intel BAR size. More...
 
#define INTEL_DESC_FL_DTYP(dtyp)   ( (dtyp) << 4 )
 Descriptor type. More...
 
#define INTEL_DESC_FL_DTYP_DATA   INTEL_DESC_FL_DTYP ( 0x03 )
 
#define INTEL_DESC_CMD_DEXT   0x20
 Descriptor extension. More...
 
#define INTEL_DESC_CMD_RS   0x08
 Report status. More...
 
#define INTEL_DESC_CMD_IFCS   0x02
 Insert frame checksum (CRC) More...
 
#define INTEL_DESC_CMD_EOP   0x01
 End of packet. More...
 
#define INTEL_DESC_STATUS_DD   0x00000001UL
 Descriptor done. More...
 
#define INTEL_DESC_STATUS_RXE   0x00000100UL
 Receive error. More...
 
#define INTEL_DESC_STATUS_PAYLEN(len)   ( (len) << 14 )
 Payload length. More...
 
#define INTEL_CTRL   0x00000UL
 Device Control Register. More...
 
#define INTEL_CTRL_LRST   0x00000008UL
 Link reset. More...
 
#define INTEL_CTRL_ASDE   0x00000020UL
 Auto-speed detection. More...
 
#define INTEL_CTRL_SLU   0x00000040UL
 Set link up. More...
 
#define INTEL_CTRL_FRCSPD   0x00000800UL
 Force speed. More...
 
#define INTEL_CTRL_FRCDPLX   0x00001000UL
 Force duplex. More...
 
#define INTEL_CTRL_RST   0x04000000UL
 Device reset. More...
 
#define INTEL_CTRL_PHY_RST   0x80000000UL
 PHY reset. More...
 
#define INTEL_RESET_DELAY_MS   20
 Time to delay for device reset, in milliseconds. More...
 
#define INTEL_STATUS   0x00008UL
 Device Status Register. More...
 
#define INTEL_STATUS_LU   0x00000002UL
 Link up. More...
 
#define INTEL_EERD   0x00014UL
 EEPROM Read Register. More...
 
#define INTEL_EERD_START   0x00000001UL
 Start read. More...
 
#define INTEL_EERD_DONE_SMALL   0x00000010UL
 Read done (small EERD) More...
 
#define INTEL_EERD_DONE_LARGE   0x00000002UL
 Read done (large EERD) More...
 
#define INTEL_EERD_ADDR_SHIFT_SMALL   8
 Address shift (small) More...
 
#define INTEL_EERD_ADDR_SHIFT_LARGE   2
 Address shift (large) More...
 
#define INTEL_EERD_DATA(value)   ( (value) >> 16 )
 Read data. More...
 
#define INTEL_EEPROM_MAX_WAIT_MS   100
 Maximum time to wait for EEPROM read, in milliseconds. More...
 
#define INTEL_EEPROM_WORD_LEN_LOG2   1
 EEPROM word length. More...
 
#define INTEL_EEPROM_MIN_SIZE_WORDS   64
 Minimum EEPROM size, in words. More...
 
#define INTEL_EEPROM_MAC   0x00
 Offset of MAC address within EEPROM. More...
 
#define INTEL_ICR   0x000c0UL
 Interrupt Cause Read Register. More...
 
#define INTEL_IRQ_TXDW   0x00000001UL
 Transmit descriptor done. More...
 
#define INTEL_IRQ_TXQE   0x00000002UL
 Transmit queue empty. More...
 
#define INTEL_IRQ_LSC   0x00000004UL
 Link status change. More...
 
#define INTEL_IRQ_RXDMT0   0x00000010UL
 Receive queue low. More...
 
#define INTEL_IRQ_RXO   0x00000040UL
 Receive overrun. More...
 
#define INTEL_IRQ_RXT0   0x00000080UL
 Receive timer. More...
 
#define INTEL_IMS   0x000d0UL
 Interrupt Mask Set/Read Register. More...
 
#define INTEL_IMC   0x000d8UL
 Interrupt Mask Clear Register. More...
 
#define INTEL_RCTL   0x00100UL
 Receive Control Register. More...
 
#define INTEL_RCTL_EN   0x00000002UL
 Receive enable. More...
 
#define INTEL_RCTL_UPE   0x00000008UL
 Unicast promiscuous mode. More...
 
#define INTEL_RCTL_MPE   0x00000010UL
 Multicast promiscuous. More...
 
#define INTEL_RCTL_BAM   0x00008000UL
 Broadcast accept mode. More...
 
#define INTEL_RCTL_BSIZE_BSEX(bsex, bsize)   ( ( (bsize) << 16 ) | ( (bsex) << 25 ) )
 Buffer size. More...
 
#define INTEL_RCTL_BSIZE_2048   INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
 
#define INTEL_RCTL_BSIZE_BSEX_MASK   INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
 
#define INTEL_RCTL_SECRC   0x04000000UL
 Strip CRC. More...
 
#define INTEL_TCTL   0x00400UL
 Transmit Control Register. More...
 
#define INTEL_TCTL_EN   0x00000002UL
 Transmit enable. More...
 
#define INTEL_TCTL_PSP   0x00000008UL
 Pad short packets. More...
 
#define INTEL_TCTL_CT(x)   ( (x) << 4 )
 Collision threshold. More...
 
#define INTEL_TCTL_CT_DEFAULT   INTEL_TCTL_CT ( 0x0f )
 
#define INTEL_TCTL_CT_MASK   INTEL_TCTL_CT ( 0xff )
 
#define INTEL_TCTL_COLD(x)   ( (x) << 12 )
 Collision distance. More...
 
#define INTEL_TCTL_COLD_DEFAULT   INTEL_TCTL_COLD ( 0x040 )
 
#define INTEL_TCTL_COLD_MASK   INTEL_TCTL_COLD ( 0x3ff )
 
#define INTEL_PBA   0x01000UL
 Packet Buffer Allocation. More...
 
#define INTEL_PBS   0x01008UL
 Packet Buffer Size. More...
 
#define INTEL_RXPBS   0x02404UL
 Receive packet buffer size. More...
 
#define INTEL_RXPBS_I210   0x000000a2UL
 I210 power-up default. More...
 
#define INTEL_RD   0x02800UL
 Receive Descriptor register block. More...
 
#define INTEL_NUM_RX_DESC   16
 Number of receive descriptors. More...
 
#define INTEL_RX_FILL   8
 Receive descriptor ring fill level. More...
 
#define INTEL_RX_MAX_LEN   2048
 Receive buffer length. More...
 
#define INTEL_TXPBS   0x03404UL
 Transmit packet buffer size. More...
 
#define INTEL_TXPBS_I210   0x04000014UL
 I210 power-up default. More...
 
#define INTEL_TD   0x03800UL
 Transmit Descriptor register block. More...
 
#define INTEL_NUM_TX_DESC   16
 Number of transmit descriptors. More...
 
#define INTEL_TX_FILL   ( INTEL_NUM_TX_DESC - 1 )
 Transmit descriptor ring maximum fill level. More...
 
#define INTEL_xDBAL   0x00
 Receive/Transmit Descriptor Base Address Low (offset) More...
 
#define INTEL_xDBAH   0x04
 Receive/Transmit Descriptor Base Address High (offset) More...
 
#define INTEL_xDLEN   0x08
 Receive/Transmit Descriptor Length (offset) More...
 
#define INTEL_xDH   0x10
 Receive/Transmit Descriptor Head (offset) More...
 
#define INTEL_xDT   0x18
 Receive/Transmit Descriptor Tail (offset) More...
 
#define INTEL_xDCTL   0x28
 Receive/Transmit Descriptor Control (offset) More...
 
#define INTEL_xDCTL_ENABLE   0x02000000UL
 Queue enable. More...
 
#define INTEL_DISABLE_MAX_WAIT_MS   100
 Maximum time to wait for queue disable, in milliseconds. More...
 
#define INTEL_RAL0   0x05400UL
 Receive Address Low. More...
 
#define INTEL_RAH0   0x05404UL
 Receive Address High. More...
 
#define INTEL_RAH0_AV   0x80000000UL
 Address valid. More...
 
#define INTEL_FEXTNVM11   0x05bbcUL
 Future Extended NVM register 11. More...
 
#define INTEL_FEXTNVM11_WTF   0x00002000UL
 Don't ask. More...
 
#define INTEL_I219   ( INTEL_NO_PHY_RST | INTEL_RST_HANG )
 The i219 has a seriously broken reset mechanism. More...
 

Enumerations

enum  intel_flags {
  INTEL_PBS_ERRATA = 0x0001, INTEL_VMWARE = 0x0002, INTEL_NO_PHY_RST = 0x0004, INTEL_NO_ASDE = 0x0008,
  INTEL_RST_HANG = 0x0010, INTEL_PBSIZE_RST = 0x0020
}
 Driver flags. More...
 

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
 FILE_SECBOOT (PERMITTED)
 
static void intel_init_ring (struct intel_ring *ring, unsigned int count, unsigned int reg, void(*describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len))
 Initialise descriptor ring. More...
 
static void intel_init_mbox (struct intel_mailbox *mbox, unsigned int ctrl, unsigned int mem)
 Initialise mailbox. More...
 
static void intel_diag (struct intel_nic *intel)
 Dump diagnostic information. More...
 
void intel_describe_tx (struct intel_descriptor *tx, physaddr_t addr, size_t len)
 Populate transmit descriptor. More...
 
void intel_describe_tx_adv (struct intel_descriptor *tx, physaddr_t addr, size_t len)
 Populate advanced transmit descriptor. More...
 
void intel_describe_rx (struct intel_descriptor *rx, physaddr_t addr, size_t len)
 Populate receive descriptor. More...
 
void intel_reset_ring (struct intel_nic *intel, unsigned int reg)
 Reset descriptor ring. More...
 
int intel_create_ring (struct intel_nic *intel, struct intel_ring *ring)
 Create descriptor ring. More...
 
void intel_destroy_ring (struct intel_nic *intel, struct intel_ring *ring)
 Destroy descriptor ring. More...
 
void intel_refill_rx (struct intel_nic *intel)
 Refill receive descriptor ring. More...
 
void intel_empty_rx (struct intel_nic *intel)
 Discard unused receive I/O buffers. More...
 
int intel_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
void intel_poll_tx (struct net_device *netdev)
 Poll for completed packets. More...
 
void intel_poll_rx (struct net_device *netdev)
 Poll for received packets. More...
 

Detailed Description

Intel 10/100/1000 network card driver.

Definition in file intel.h.

Macro Definition Documentation

◆ INTEL_BAR_SIZE

#define INTEL_BAR_SIZE   ( 128 * 1024 )

Intel BAR size.

Definition at line 19 of file intel.h.

◆ INTEL_DESC_FL_DTYP

#define INTEL_DESC_FL_DTYP (   dtyp)    ( (dtyp) << 4 )

Descriptor type.

Definition at line 36 of file intel.h.

◆ INTEL_DESC_FL_DTYP_DATA

#define INTEL_DESC_FL_DTYP_DATA   INTEL_DESC_FL_DTYP ( 0x03 )

Definition at line 37 of file intel.h.

◆ INTEL_DESC_CMD_DEXT

#define INTEL_DESC_CMD_DEXT   0x20

Descriptor extension.

Definition at line 40 of file intel.h.

◆ INTEL_DESC_CMD_RS

#define INTEL_DESC_CMD_RS   0x08

Report status.

Definition at line 43 of file intel.h.

◆ INTEL_DESC_CMD_IFCS

#define INTEL_DESC_CMD_IFCS   0x02

Insert frame checksum (CRC)

Definition at line 46 of file intel.h.

◆ INTEL_DESC_CMD_EOP

#define INTEL_DESC_CMD_EOP   0x01

End of packet.

Definition at line 49 of file intel.h.

◆ INTEL_DESC_STATUS_DD

#define INTEL_DESC_STATUS_DD   0x00000001UL

Descriptor done.

Definition at line 52 of file intel.h.

◆ INTEL_DESC_STATUS_RXE

#define INTEL_DESC_STATUS_RXE   0x00000100UL

Receive error.

Definition at line 55 of file intel.h.

◆ INTEL_DESC_STATUS_PAYLEN

#define INTEL_DESC_STATUS_PAYLEN (   len)    ( (len) << 14 )

Payload length.

Definition at line 58 of file intel.h.

◆ INTEL_CTRL

#define INTEL_CTRL   0x00000UL

Device Control Register.

Definition at line 61 of file intel.h.

◆ INTEL_CTRL_LRST

#define INTEL_CTRL_LRST   0x00000008UL

Link reset.

Definition at line 62 of file intel.h.

◆ INTEL_CTRL_ASDE

#define INTEL_CTRL_ASDE   0x00000020UL

Auto-speed detection.

Definition at line 63 of file intel.h.

◆ INTEL_CTRL_SLU

#define INTEL_CTRL_SLU   0x00000040UL

Set link up.

Definition at line 64 of file intel.h.

◆ INTEL_CTRL_FRCSPD

#define INTEL_CTRL_FRCSPD   0x00000800UL

Force speed.

Definition at line 65 of file intel.h.

◆ INTEL_CTRL_FRCDPLX

#define INTEL_CTRL_FRCDPLX   0x00001000UL

Force duplex.

Definition at line 66 of file intel.h.

◆ INTEL_CTRL_RST

#define INTEL_CTRL_RST   0x04000000UL

Device reset.

Definition at line 67 of file intel.h.

◆ INTEL_CTRL_PHY_RST

#define INTEL_CTRL_PHY_RST   0x80000000UL

PHY reset.

Definition at line 68 of file intel.h.

◆ INTEL_RESET_DELAY_MS

#define INTEL_RESET_DELAY_MS   20

Time to delay for device reset, in milliseconds.

Definition at line 71 of file intel.h.

◆ INTEL_STATUS

#define INTEL_STATUS   0x00008UL

Device Status Register.

Definition at line 74 of file intel.h.

◆ INTEL_STATUS_LU

#define INTEL_STATUS_LU   0x00000002UL

Link up.

Definition at line 75 of file intel.h.

◆ INTEL_EERD

#define INTEL_EERD   0x00014UL

EEPROM Read Register.

Definition at line 78 of file intel.h.

◆ INTEL_EERD_START

#define INTEL_EERD_START   0x00000001UL

Start read.

Definition at line 79 of file intel.h.

◆ INTEL_EERD_DONE_SMALL

#define INTEL_EERD_DONE_SMALL   0x00000010UL

Read done (small EERD)

Definition at line 80 of file intel.h.

◆ INTEL_EERD_DONE_LARGE

#define INTEL_EERD_DONE_LARGE   0x00000002UL

Read done (large EERD)

Definition at line 81 of file intel.h.

◆ INTEL_EERD_ADDR_SHIFT_SMALL

#define INTEL_EERD_ADDR_SHIFT_SMALL   8

Address shift (small)

Definition at line 82 of file intel.h.

◆ INTEL_EERD_ADDR_SHIFT_LARGE

#define INTEL_EERD_ADDR_SHIFT_LARGE   2

Address shift (large)

Definition at line 83 of file intel.h.

◆ INTEL_EERD_DATA

#define INTEL_EERD_DATA (   value)    ( (value) >> 16 )

Read data.

Definition at line 84 of file intel.h.

◆ INTEL_EEPROM_MAX_WAIT_MS

#define INTEL_EEPROM_MAX_WAIT_MS   100

Maximum time to wait for EEPROM read, in milliseconds.

Definition at line 87 of file intel.h.

◆ INTEL_EEPROM_WORD_LEN_LOG2

#define INTEL_EEPROM_WORD_LEN_LOG2   1

EEPROM word length.

Definition at line 90 of file intel.h.

◆ INTEL_EEPROM_MIN_SIZE_WORDS

#define INTEL_EEPROM_MIN_SIZE_WORDS   64

Minimum EEPROM size, in words.

Definition at line 93 of file intel.h.

◆ INTEL_EEPROM_MAC

#define INTEL_EEPROM_MAC   0x00

Offset of MAC address within EEPROM.

Definition at line 96 of file intel.h.

◆ INTEL_ICR

#define INTEL_ICR   0x000c0UL

Interrupt Cause Read Register.

Definition at line 99 of file intel.h.

◆ INTEL_IRQ_TXDW

#define INTEL_IRQ_TXDW   0x00000001UL

Transmit descriptor done.

Definition at line 100 of file intel.h.

◆ INTEL_IRQ_TXQE

#define INTEL_IRQ_TXQE   0x00000002UL

Transmit queue empty.

Definition at line 101 of file intel.h.

◆ INTEL_IRQ_LSC

#define INTEL_IRQ_LSC   0x00000004UL

Link status change.

Definition at line 102 of file intel.h.

◆ INTEL_IRQ_RXDMT0

#define INTEL_IRQ_RXDMT0   0x00000010UL

Receive queue low.

Definition at line 103 of file intel.h.

◆ INTEL_IRQ_RXO

#define INTEL_IRQ_RXO   0x00000040UL

Receive overrun.

Definition at line 104 of file intel.h.

◆ INTEL_IRQ_RXT0

#define INTEL_IRQ_RXT0   0x00000080UL

Receive timer.

Definition at line 105 of file intel.h.

◆ INTEL_IMS

#define INTEL_IMS   0x000d0UL

Interrupt Mask Set/Read Register.

Definition at line 108 of file intel.h.

◆ INTEL_IMC

#define INTEL_IMC   0x000d8UL

Interrupt Mask Clear Register.

Definition at line 111 of file intel.h.

◆ INTEL_RCTL

#define INTEL_RCTL   0x00100UL

Receive Control Register.

Definition at line 114 of file intel.h.

◆ INTEL_RCTL_EN

#define INTEL_RCTL_EN   0x00000002UL

Receive enable.

Definition at line 115 of file intel.h.

◆ INTEL_RCTL_UPE

#define INTEL_RCTL_UPE   0x00000008UL

Unicast promiscuous mode.

Definition at line 116 of file intel.h.

◆ INTEL_RCTL_MPE

#define INTEL_RCTL_MPE   0x00000010UL

Multicast promiscuous.

Definition at line 117 of file intel.h.

◆ INTEL_RCTL_BAM

#define INTEL_RCTL_BAM   0x00008000UL

Broadcast accept mode.

Definition at line 118 of file intel.h.

◆ INTEL_RCTL_BSIZE_BSEX

#define INTEL_RCTL_BSIZE_BSEX (   bsex,
  bsize 
)    ( ( (bsize) << 16 ) | ( (bsex) << 25 ) )

Buffer size.

Definition at line 119 of file intel.h.

◆ INTEL_RCTL_BSIZE_2048

#define INTEL_RCTL_BSIZE_2048   INTEL_RCTL_BSIZE_BSEX ( 0, 0 )

Definition at line 122 of file intel.h.

◆ INTEL_RCTL_BSIZE_BSEX_MASK

#define INTEL_RCTL_BSIZE_BSEX_MASK   INTEL_RCTL_BSIZE_BSEX ( 1, 3 )

Definition at line 123 of file intel.h.

◆ INTEL_RCTL_SECRC

#define INTEL_RCTL_SECRC   0x04000000UL

Strip CRC.

Definition at line 124 of file intel.h.

◆ INTEL_TCTL

#define INTEL_TCTL   0x00400UL

Transmit Control Register.

Definition at line 127 of file intel.h.

◆ INTEL_TCTL_EN

#define INTEL_TCTL_EN   0x00000002UL

Transmit enable.

Definition at line 128 of file intel.h.

◆ INTEL_TCTL_PSP

#define INTEL_TCTL_PSP   0x00000008UL

Pad short packets.

Definition at line 129 of file intel.h.

◆ INTEL_TCTL_CT

#define INTEL_TCTL_CT (   x)    ( (x) << 4 )

Collision threshold.

Definition at line 130 of file intel.h.

◆ INTEL_TCTL_CT_DEFAULT

#define INTEL_TCTL_CT_DEFAULT   INTEL_TCTL_CT ( 0x0f )

Definition at line 131 of file intel.h.

◆ INTEL_TCTL_CT_MASK

#define INTEL_TCTL_CT_MASK   INTEL_TCTL_CT ( 0xff )

Definition at line 132 of file intel.h.

◆ INTEL_TCTL_COLD

#define INTEL_TCTL_COLD (   x)    ( (x) << 12 )

Collision distance.

Definition at line 133 of file intel.h.

◆ INTEL_TCTL_COLD_DEFAULT

#define INTEL_TCTL_COLD_DEFAULT   INTEL_TCTL_COLD ( 0x040 )

Definition at line 134 of file intel.h.

◆ INTEL_TCTL_COLD_MASK

#define INTEL_TCTL_COLD_MASK   INTEL_TCTL_COLD ( 0x3ff )

Definition at line 135 of file intel.h.

◆ INTEL_PBA

#define INTEL_PBA   0x01000UL

Packet Buffer Allocation.

Definition at line 138 of file intel.h.

◆ INTEL_PBS

#define INTEL_PBS   0x01008UL

Packet Buffer Size.

Definition at line 141 of file intel.h.

◆ INTEL_RXPBS

#define INTEL_RXPBS   0x02404UL

Receive packet buffer size.

Definition at line 144 of file intel.h.

◆ INTEL_RXPBS_I210

#define INTEL_RXPBS_I210   0x000000a2UL

I210 power-up default.

Definition at line 145 of file intel.h.

◆ INTEL_RD

#define INTEL_RD   0x02800UL

Receive Descriptor register block.

Definition at line 148 of file intel.h.

◆ INTEL_NUM_RX_DESC

#define INTEL_NUM_RX_DESC   16

Number of receive descriptors.

Minimum value is 8, since the descriptor ring length must be a multiple of 128.

Definition at line 155 of file intel.h.

◆ INTEL_RX_FILL

#define INTEL_RX_FILL   8

Receive descriptor ring fill level.

Definition at line 158 of file intel.h.

◆ INTEL_RX_MAX_LEN

#define INTEL_RX_MAX_LEN   2048

Receive buffer length.

Definition at line 161 of file intel.h.

◆ INTEL_TXPBS

#define INTEL_TXPBS   0x03404UL

Transmit packet buffer size.

Definition at line 164 of file intel.h.

◆ INTEL_TXPBS_I210

#define INTEL_TXPBS_I210   0x04000014UL

I210 power-up default.

Definition at line 165 of file intel.h.

◆ INTEL_TD

#define INTEL_TD   0x03800UL

Transmit Descriptor register block.

Definition at line 168 of file intel.h.

◆ INTEL_NUM_TX_DESC

#define INTEL_NUM_TX_DESC   16

Number of transmit descriptors.

Descriptor ring length must be a multiple of 16. ICH8/9/10 requires a minimum of 16 TX descriptors.

Definition at line 175 of file intel.h.

◆ INTEL_TX_FILL

#define INTEL_TX_FILL   ( INTEL_NUM_TX_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 178 of file intel.h.

◆ INTEL_xDBAL

#define INTEL_xDBAL   0x00

Receive/Transmit Descriptor Base Address Low (offset)

Definition at line 181 of file intel.h.

◆ INTEL_xDBAH

#define INTEL_xDBAH   0x04

Receive/Transmit Descriptor Base Address High (offset)

Definition at line 184 of file intel.h.

◆ INTEL_xDLEN

#define INTEL_xDLEN   0x08

Receive/Transmit Descriptor Length (offset)

Definition at line 187 of file intel.h.

◆ INTEL_xDH

#define INTEL_xDH   0x10

Receive/Transmit Descriptor Head (offset)

Definition at line 190 of file intel.h.

◆ INTEL_xDT

#define INTEL_xDT   0x18

Receive/Transmit Descriptor Tail (offset)

Definition at line 193 of file intel.h.

◆ INTEL_xDCTL

#define INTEL_xDCTL   0x28

Receive/Transmit Descriptor Control (offset)

Definition at line 196 of file intel.h.

◆ INTEL_xDCTL_ENABLE

#define INTEL_xDCTL_ENABLE   0x02000000UL

Queue enable.

Definition at line 197 of file intel.h.

◆ INTEL_DISABLE_MAX_WAIT_MS

#define INTEL_DISABLE_MAX_WAIT_MS   100

Maximum time to wait for queue disable, in milliseconds.

Definition at line 200 of file intel.h.

◆ INTEL_RAL0

#define INTEL_RAL0   0x05400UL

Receive Address Low.

Definition at line 203 of file intel.h.

◆ INTEL_RAH0

#define INTEL_RAH0   0x05404UL

Receive Address High.

Definition at line 206 of file intel.h.

◆ INTEL_RAH0_AV

#define INTEL_RAH0_AV   0x80000000UL

Address valid.

Definition at line 207 of file intel.h.

◆ INTEL_FEXTNVM11

#define INTEL_FEXTNVM11   0x05bbcUL

Future Extended NVM register 11.

Definition at line 210 of file intel.h.

◆ INTEL_FEXTNVM11_WTF

#define INTEL_FEXTNVM11_WTF   0x00002000UL

Don't ask.

Definition at line 211 of file intel.h.

◆ INTEL_I219

#define INTEL_I219   ( INTEL_NO_PHY_RST | INTEL_RST_HANG )

The i219 has a seriously broken reset mechanism.

Definition at line 337 of file intel.h.

Enumeration Type Documentation

◆ intel_flags

enum intel_flags

Driver flags.

Enumerator
INTEL_PBS_ERRATA 

PBS/PBA errata workaround required.

INTEL_VMWARE 

VMware missing interrupt workaround required.

INTEL_NO_PHY_RST 

PHY reset is broken.

INTEL_NO_ASDE 

ASDE is broken.

INTEL_RST_HANG 

Reset may cause a complete device hang.

INTEL_PBSIZE_RST 

PBSIZE registers must be explicitly reset.

Definition at line 321 of file intel.h.

343  {

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ FILE_SECBOOT()

FILE_SECBOOT ( PERMITTED  )

◆ intel_init_ring()

static void intel_init_ring ( struct intel_ring *  ring,
unsigned int  count,
unsigned int  reg,
void(*)(struct intel_descriptor *desc, physaddr_t addr, size_t len)  describe 
)
inlinestatic

Initialise descriptor ring.

Parameters
ringDescriptor ring
countNumber of descriptors
regDescriptor register block
describeMethod to populate descriptor

Definition at line 257 of file intel.h.

258  {
259 
260  ring->len = ( count * sizeof ( ring->desc[0] ) );
261  ring->reg = reg;
262  ring->describe = describe;
263 }
264 
reg
static unsigned int unsigned int reg
Definition: myson.h:162
intel_ring::len
size_t len
Length (in bytes)
Definition: intel.h:236
intel_ring::reg
unsigned int reg
Register block.
Definition: intel.h:234
count
static unsigned int count
Number of entries.
Definition: dwmac.h:225
intel_ring::describe
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:244
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225

References count, intel_ring::desc, intel_ring::describe, intel_ring::len, reg, and intel_ring::reg.

Referenced by intel_probe(), intelx_probe(), and intelxvf_probe().

◆ intel_init_mbox()

static void intel_init_mbox ( struct intel_mailbox *  mbox,
unsigned int  ctrl,
unsigned int  mem 
)
inlinestatic

Initialise mailbox.

Parameters
mboxMailbox
ctrlMailbox control register
memMailbox memory register base

Definition at line 282 of file intel.h.

282  {
283 
284  mbox->ctrl = ctrl;
285  mbox->mem = mem;
286 }
287 
mbox
Definition: golan.c:120
ctrl
uint8_t ctrl
Ring control.
Definition: dwmac.h:18

References ctrl.

Referenced by intelxvf_probe().

◆ intel_diag()

static void intel_diag ( struct intel_nic *  intel)
inlinestatic

Dump diagnostic information.

Parameters
intelIntel device

Definition at line 344 of file intel.h.

◆ intel_describe_tx()

void intel_describe_tx ( struct intel_descriptor *  tx,
physaddr_t  addr,
size_t  len 
)

Populate transmit descriptor.

Parameters
txTransmit descriptor
addrData buffer address
lenLength of data

Definition at line 396 of file intel.c.

397  {
398 
399  /* Populate transmit descriptor */
400  tx->address = cpu_to_le64 ( addr );
401  tx->length = cpu_to_le16 ( len );
402  tx->flags = 0;
403  tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
404  INTEL_DESC_CMD_EOP );
405  tx->status = 0;
406 }
cpu_to_le64
#define cpu_to_le64(value)
Definition: byteswap.h:109
len
ring len
Length.
Definition: dwmac.h:231
INTEL_DESC_CMD_IFCS
#define INTEL_DESC_CMD_IFCS
Insert frame checksum (CRC)
Definition: intel.h:46
addr
uint32_t addr
Buffer address.
Definition: dwmac.h:20
INTEL_DESC_CMD_EOP
#define INTEL_DESC_CMD_EOP
End of packet.
Definition: intel.h:49
cpu_to_le16
#define cpu_to_le16(value)
Definition: byteswap.h:107
INTEL_DESC_CMD_RS
#define INTEL_DESC_CMD_RS
Report status.
Definition: intel.h:43
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References addr, cpu_to_le16, cpu_to_le64, INTEL_DESC_CMD_EOP, INTEL_DESC_CMD_IFCS, INTEL_DESC_CMD_RS, len, and tx.

Referenced by intel_probe(), and intelx_probe().

◆ intel_describe_tx_adv()

void intel_describe_tx_adv ( struct intel_descriptor *  tx,
physaddr_t  addr,
size_t  len 
)

Populate advanced transmit descriptor.

Parameters
txTransmit descriptor
addrData buffer address
lenLength of data

Definition at line 415 of file intel.c.

416  {
417 
418  /* Populate advanced transmit descriptor */
419  tx->address = cpu_to_le64 ( addr );
420  tx->length = cpu_to_le16 ( len );
421  tx->flags = INTEL_DESC_FL_DTYP_DATA;
422  tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
423  INTEL_DESC_CMD_IFCS | INTEL_DESC_CMD_EOP );
424  tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
425 }
INTEL_DESC_STATUS_PAYLEN
#define INTEL_DESC_STATUS_PAYLEN(len)
Payload length.
Definition: intel.h:58
cpu_to_le64
#define cpu_to_le64(value)
Definition: byteswap.h:109
INTEL_DESC_FL_DTYP_DATA
#define INTEL_DESC_FL_DTYP_DATA
Definition: intel.h:37
len
ring len
Length.
Definition: dwmac.h:231
INTEL_DESC_CMD_IFCS
#define INTEL_DESC_CMD_IFCS
Insert frame checksum (CRC)
Definition: intel.h:46
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:108
addr
uint32_t addr
Buffer address.
Definition: dwmac.h:20
INTEL_DESC_CMD_DEXT
#define INTEL_DESC_CMD_DEXT
Descriptor extension.
Definition: intel.h:40
INTEL_DESC_CMD_EOP
#define INTEL_DESC_CMD_EOP
End of packet.
Definition: intel.h:49
cpu_to_le16
#define cpu_to_le16(value)
Definition: byteswap.h:107
INTEL_DESC_CMD_RS
#define INTEL_DESC_CMD_RS
Report status.
Definition: intel.h:43
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References addr, cpu_to_le16, cpu_to_le32, cpu_to_le64, INTEL_DESC_CMD_DEXT, INTEL_DESC_CMD_EOP, INTEL_DESC_CMD_IFCS, INTEL_DESC_CMD_RS, INTEL_DESC_FL_DTYP_DATA, INTEL_DESC_STATUS_PAYLEN, len, and tx.

Referenced by intelxvf_probe().

◆ intel_describe_rx()

void intel_describe_rx ( struct intel_descriptor *  rx,
physaddr_t  addr,
size_t len  __unused 
)

Populate receive descriptor.

Parameters
rxReceive descriptor
addrData buffer address
lenLength of data

Definition at line 434 of file intel.c.

435  {
436 
437  /* Populate transmit descriptor */
438  rx->address = cpu_to_le64 ( addr );
439  rx->length = 0;
440  rx->status = 0;
441 }
cpu_to_le64
#define cpu_to_le64(value)
Definition: byteswap.h:109
addr
uint32_t addr
Buffer address.
Definition: dwmac.h:20
rx
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234

References addr, cpu_to_le64, and rx.

Referenced by intel_probe(), intelx_probe(), and intelxvf_probe().

◆ intel_reset_ring()

void intel_reset_ring ( struct intel_nic *  intel,
unsigned int  reg 
)

Reset descriptor ring.

Parameters
intelIntel device
regRegister block
Return values
rcReturn status code

Definition at line 488 of file intel.c.

488  {
489 
490  /* Disable ring. Ignore errors and continue to reset the ring anyway */
491  intel_disable_ring ( intel, reg );
492 
493  /* Clear ring length */
494  writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
495 
496  /* Clear ring address */
497  writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
498  writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
499 
500  /* Reset head and tail pointers */
501  writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
502  writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
503 }
intel_nic::regs
void * regs
Registers.
Definition: intel.h:292
reg
static unsigned int unsigned int reg
Definition: myson.h:162
INTEL_xDT
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:193
INTEL_xDLEN
#define INTEL_xDLEN
Receive/Transmit Descriptor Length (offset)
Definition: intel.h:187
INTEL_xDH
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:190
INTEL_xDBAL
#define INTEL_xDBAL
Receive/Transmit Descriptor Base Address Low (offset)
Definition: intel.h:181
writel
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
intel_disable_ring
static int intel_disable_ring(struct intel_nic *intel, unsigned int reg)
Disable descriptor ring.
Definition: intel.c:457
INTEL_xDBAH
#define INTEL_xDBAH
Receive/Transmit Descriptor Base Address High (offset)
Definition: intel.h:184

References intel_disable_ring(), INTEL_xDBAH, INTEL_xDBAL, INTEL_xDH, INTEL_xDLEN, INTEL_xDT, reg, intel_nic::regs, and writel().

Referenced by intel_destroy_ring(), and intelxvf_open().

◆ intel_create_ring()

int intel_create_ring ( struct intel_nic *  intel,
struct intel_ring *  ring 
)

Create descriptor ring.

Parameters
intelIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 512 of file intel.c.

512  {
513  physaddr_t address;
514  uint32_t dctl;
515 
516  /* Allocate descriptor ring. Align ring on its own size to
517  * prevent any possible page-crossing errors due to hardware
518  * errata.
519  */
520  ring->desc = dma_alloc ( intel->dma, &ring->map, ring->len,
521  ring->len );
522  if ( ! ring->desc )
523  return -ENOMEM;
524 
525  /* Initialise descriptor ring */
526  memset ( ring->desc, 0, ring->len );
527 
528  /* Program ring address */
529  address = dma ( &ring->map, ring->desc );
530  writel ( ( address & 0xffffffffUL ),
531  ( intel->regs + ring->reg + INTEL_xDBAL ) );
532  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
533  writel ( ( ( ( uint64_t ) address ) >> 32 ),
534  ( intel->regs + ring->reg + INTEL_xDBAH ) );
535  } else {
536  writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
537  }
538 
539  /* Program ring length */
540  writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
541 
542  /* Reset head and tail pointers */
543  writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
544  writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
545 
546  /* Enable ring */
547  dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
548  dctl |= INTEL_xDCTL_ENABLE;
549  writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
550 
551  DBGC ( intel, "INTEL %p ring %05x is at [%08lx,%08lx)\n",
552  intel, ring->reg, virt_to_phys ( ring->desc ),
553  ( virt_to_phys ( ring->desc ) + ring->len ) );
554 
555  return 0;
556 }
intel_nic::regs
void * regs
Registers.
Definition: intel.h:292
intel_ring::map
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intel.h:227
INTEL_xDCTL
#define INTEL_xDCTL
Receive/Transmit Descriptor Control (offset)
Definition: intel.h:196
address
uint64_t address
Base address.
Definition: ena.h:24
readl
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
DBGC
#define DBGC(...)
Definition: compiler.h:505
INTEL_xDT
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:193
intel_ring::len
size_t len
Length (in bytes)
Definition: intel.h:236
uint64_t
unsigned long long uint64_t
Definition: stdint.h:13
INTEL_xDLEN
#define INTEL_xDLEN
Receive/Transmit Descriptor Length (offset)
Definition: intel.h:187
intel_ring::reg
unsigned int reg
Register block.
Definition: intel.h:234
INTEL_xDH
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:190
ENOMEM
#define ENOMEM
Not enough space.
Definition: errno.h:535
INTEL_xDBAL
#define INTEL_xDBAL
Receive/Transmit Descriptor Base Address Low (offset)
Definition: intel.h:181
writel
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
uint32_t
unsigned int uint32_t
Definition: stdint.h:12
dma_alloc
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
physaddr_t
unsigned long physaddr_t
Definition: stdint.h:20
intel_nic::dma
struct dma_device * dma
DMA device.
Definition: intel.h:294
INTEL_xDCTL_ENABLE
#define INTEL_xDCTL_ENABLE
Queue enable.
Definition: intel.h:197
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
INTEL_xDBAH
#define INTEL_xDBAH
Receive/Transmit Descriptor Base Address High (offset)
Definition: intel.h:184
dma
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
memset
void * memset(void *dest, int character, size_t len) __nonnull

References address, DBGC, intel_ring::desc, intel_nic::dma, dma(), dma_alloc(), ENOMEM, INTEL_xDBAH, INTEL_xDBAL, INTEL_xDCTL, INTEL_xDCTL_ENABLE, INTEL_xDH, INTEL_xDLEN, INTEL_xDT, intel_ring::len, intel_ring::map, memset(), readl(), intel_ring::reg, intel_nic::regs, and writel().

Referenced by intel_open(), intelx_open(), and intelxvf_open().

◆ intel_destroy_ring()

void intel_destroy_ring ( struct intel_nic *  intel,
struct intel_ring *  ring 
)

Destroy descriptor ring.

Parameters
intelIntel device
ringDescriptor ring

Definition at line 564 of file intel.c.

564  {
565 
566  /* Reset ring */
567  intel_reset_ring ( intel, ring->reg );
568 
569  /* Free descriptor ring */
570  dma_free ( &ring->map, ring->desc, ring->len );
571  ring->desc = NULL;
572  ring->prod = 0;
573  ring->cons = 0;
574 }
intel_reset_ring
void intel_reset_ring(struct intel_nic *intel, unsigned int reg)
Reset descriptor ring.
Definition: intel.c:488
intel_ring::map
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intel.h:227
intel_ring::len
size_t len
Length (in bytes)
Definition: intel.h:236
intel_ring::cons
unsigned int cons
Consumer index.
Definition: intel.h:231
intel_ring::reg
unsigned int reg
Register block.
Definition: intel.h:234
dma_free
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
intel_ring::prod
unsigned int prod
Producer index.
Definition: intel.h:229
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322

References intel_ring::cons, intel_ring::desc, dma_free(), intel_reset_ring(), intel_ring::len, intel_ring::map, NULL, intel_ring::prod, and intel_ring::reg.

Referenced by intel_close(), intel_open(), intelx_close(), intelx_open(), intelxvf_close(), and intelxvf_open().

◆ intel_refill_rx()

void intel_refill_rx ( struct intel_nic *  intel)

Refill receive descriptor ring.

Parameters
intelIntel device

Definition at line 581 of file intel.c.

581  {
582  struct intel_descriptor *rx;
583  struct io_buffer *iobuf;
584  unsigned int rx_idx;
585  unsigned int rx_tail;
586  unsigned int refilled = 0;
587 
588  /* Refill ring */
589  while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
590 
591  /* Allocate I/O buffer */
592  iobuf = alloc_rx_iob ( INTEL_RX_MAX_LEN, intel->dma );
593  if ( ! iobuf ) {
594  /* Wait for next refill */
595  break;
596  }
597 
598  /* Get next receive descriptor */
599  rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
600  rx = &intel->rx.desc[rx_idx];
601 
602  /* Populate receive descriptor */
603  intel->rx.describe ( rx, iob_dma ( iobuf ), 0 );
604 
605  /* Record I/O buffer */
606  assert ( intel->rx_iobuf[rx_idx] == NULL );
607  intel->rx_iobuf[rx_idx] = iobuf;
608 
609  DBGC2 ( intel, "INTEL %p RX %d is [%lx,%lx)\n",
610  intel, rx_idx, virt_to_phys ( iobuf->data ),
611  ( virt_to_phys ( iobuf->data ) + INTEL_RX_MAX_LEN ) );
612  refilled++;
613  }
614 
615  /* Push descriptors to card, if applicable */
616  if ( refilled ) {
617  wmb();
618  rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
619  profile_start ( &intel_vm_refill_profiler );
620  writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
621  profile_stop ( &intel_vm_refill_profiler );
622  profile_exclude ( &intel_vm_refill_profiler );
623  }
624 }
intel_nic::regs
void * regs
Registers.
Definition: intel.h:292
wmb
wmb()
INTEL_NUM_RX_DESC
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:155
intel_nic::rx
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:315
INTEL_xDT
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:193
profile_stop
static void profile_stop(struct profiler *profiler)
Stop profiling.
Definition: profile.h:174
intel_ring::cons
unsigned int cons
Consumer index.
Definition: intel.h:231
intel_ring::reg
unsigned int reg
Register block.
Definition: intel.h:234
assert
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
writel
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
iob_dma
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:268
intel_nic::rx_iobuf
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:317
profile_start
static void profile_start(struct profiler *profiler)
Start profiling.
Definition: profile.h:161
alloc_rx_iob
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:188
INTEL_RX_MAX_LEN
#define INTEL_RX_MAX_LEN
Receive buffer length.
Definition: intel.h:161
intel_ring::describe
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:244
intel_nic::dma
struct dma_device * dma
DMA device.
Definition: intel.h:294
intel_descriptor
A packet descriptor.
Definition: intel.h:22
DBGC2
#define DBGC2(...)
Definition: compiler.h:522
io_buffer::data
void * data
Start of data.
Definition: iobuf.h:53
intel_ring::prod
unsigned int prod
Producer index.
Definition: intel.h:229
rx
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
INTEL_RX_FILL
#define INTEL_RX_FILL
Receive descriptor ring fill level.
Definition: intel.h:158
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
profile_exclude
static void profile_exclude(struct profiler *profiler)
Exclude time from other ongoing profiling results.
Definition: profile.h:187
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
io_buffer
A persistent I/O buffer.
Definition: iobuf.h:38

References alloc_rx_iob(), assert(), intel_ring::cons, io_buffer::data, DBGC2, intel_ring::desc, intel_ring::describe, intel_nic::dma, INTEL_NUM_RX_DESC, INTEL_RX_FILL, INTEL_RX_MAX_LEN, INTEL_xDT, iob_dma(), NULL, intel_ring::prod, profile_exclude(), profile_start(), profile_stop(), intel_ring::reg, intel_nic::regs, rx, intel_nic::rx, intel_nic::rx_iobuf, wmb(), and writel().

Referenced by intel_open(), intel_poll(), intelx_open(), intelx_poll(), intelxvf_open(), and intelxvf_poll().

◆ intel_empty_rx()

void intel_empty_rx ( struct intel_nic *  intel)

Discard unused receive I/O buffers.

Parameters
intelIntel device

Definition at line 631 of file intel.c.

631  {
632  unsigned int i;
633 
634  /* Discard unused receive buffers */
635  for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
636  if ( intel->rx_iobuf[i] )
637  free_rx_iob ( intel->rx_iobuf[i] );
638  intel->rx_iobuf[i] = NULL;
639  }
640 }
INTEL_NUM_RX_DESC
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:155
intel_nic::rx_iobuf
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:317
free_rx_iob
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:215
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322

References free_rx_iob(), INTEL_NUM_RX_DESC, NULL, and intel_nic::rx_iobuf.

Referenced by intel_close(), intelx_close(), and intelxvf_close().

◆ intel_transmit()

int intel_transmit ( struct net_device *  netdev,
struct io_buffer *  iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 753 of file intel.c.

753  {
754  struct intel_nic *intel = netdev->priv;
755  struct intel_descriptor *tx;
756  unsigned int tx_idx;
757  unsigned int tx_tail;
758  size_t len;
759 
760  /* Get next transmit descriptor */
761  if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
762  DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
763  return -ENOBUFS;
764  }
765  tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
766  tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
767  tx = &intel->tx.desc[tx_idx];
768 
769  /* Populate transmit descriptor */
770  len = iob_len ( iobuf );
771  intel->tx.describe ( tx, iob_dma ( iobuf ), len );
772  wmb();
773 
774  /* Notify card that there are packets ready to transmit */
775  profile_start ( &intel_vm_tx_profiler );
776  writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
777  profile_stop ( &intel_vm_tx_profiler );
778  profile_exclude ( &intel_vm_tx_profiler );
779 
780  DBGC2 ( intel, "INTEL %p TX %d is [%lx,%lx)\n",
781  intel, tx_idx, virt_to_phys ( iobuf->data ),
782  ( virt_to_phys ( iobuf->data ) + len ) );
783 
784  return 0;
785 }
intel_nic::regs
void * regs
Registers.
Definition: intel.h:292
wmb
wmb()
INTEL_NUM_TX_DESC
#define INTEL_NUM_TX_DESC
Number of transmit descriptors.
Definition: intel.h:175
DBGC
#define DBGC(...)
Definition: compiler.h:505
INTEL_xDT
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:193
profile_stop
static void profile_stop(struct profiler *profiler)
Stop profiling.
Definition: profile.h:174
intel_ring::cons
unsigned int cons
Consumer index.
Definition: intel.h:231
intel_ring::reg
unsigned int reg
Register block.
Definition: intel.h:234
INTEL_TX_FILL
#define INTEL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intel.h:178
net_device::priv
void * priv
Driver private data.
Definition: netdevice.h:432
len
ring len
Length.
Definition: dwmac.h:231
writel
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
netdev
static struct net_device * netdev
Definition: gdbudp.c:52
iob_dma
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:268
profile_start
static void profile_start(struct profiler *profiler)
Start profiling.
Definition: profile.h:161
iob_len
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:160
intel_ring::describe
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:244
intel_descriptor
A packet descriptor.
Definition: intel.h:22
ENOBUFS
#define ENOBUFS
No buffer space available.
Definition: errno.h:499
DBGC2
#define DBGC2(...)
Definition: compiler.h:522
io_buffer::data
void * data
Start of data.
Definition: iobuf.h:53
intel_ring::prod
unsigned int prod
Producer index.
Definition: intel.h:229
intel_nic
An Intel network card.
Definition: intel.h:290
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
intel_nic::tx
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:313
profile_exclude
static void profile_exclude(struct profiler *profiler)
Exclude time from other ongoing profiling results.
Definition: profile.h:187
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intel_ring::cons, io_buffer::data, DBGC, DBGC2, intel_ring::desc, intel_ring::describe, ENOBUFS, INTEL_NUM_TX_DESC, INTEL_TX_FILL, INTEL_xDT, iob_dma(), iob_len(), len, netdev, net_device::priv, intel_ring::prod, profile_exclude(), profile_start(), profile_stop(), intel_ring::reg, intel_nic::regs, tx, intel_nic::tx, wmb(), and writel().

◆ intel_poll_tx()

void intel_poll_tx ( struct net_device *  netdev)

Poll for completed packets.

Parameters
netdevNetwork device

Definition at line 792 of file intel.c.

792  {
793  struct intel_nic *intel = netdev->priv;
794  struct intel_descriptor *tx;
795  unsigned int tx_idx;
796 
797  /* Check for completed packets */
798  while ( intel->tx.cons != intel->tx.prod ) {
799 
800  /* Get next transmit descriptor */
801  tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
802  tx = &intel->tx.desc[tx_idx];
803 
804  /* Stop if descriptor is still in use */
805  if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
806  return;
807 
808  DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
809 
810  /* Complete TX descriptor */
811  netdev_tx_complete_next ( netdev );
812  intel->tx.cons++;
813  }
814 }
INTEL_DESC_STATUS_DD
#define INTEL_DESC_STATUS_DD
Descriptor done.
Definition: intel.h:52
netdev_tx_complete_next
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:779
INTEL_NUM_TX_DESC
#define INTEL_NUM_TX_DESC
Number of transmit descriptors.
Definition: intel.h:175
intel_ring::cons
unsigned int cons
Consumer index.
Definition: intel.h:231
net_device::priv
void * priv
Driver private data.
Definition: netdevice.h:432
netdev
static struct net_device * netdev
Definition: gdbudp.c:52
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:108
intel_descriptor
A packet descriptor.
Definition: intel.h:22
DBGC2
#define DBGC2(...)
Definition: compiler.h:522
intel_ring::prod
unsigned int prod
Producer index.
Definition: intel.h:229
intel_nic
An Intel network card.
Definition: intel.h:290
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
intel_nic::tx
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:313
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intel_ring::cons, cpu_to_le32, DBGC2, intel_ring::desc, INTEL_DESC_STATUS_DD, INTEL_NUM_TX_DESC, netdev, netdev_tx_complete_next(), net_device::priv, intel_ring::prod, tx, and intel_nic::tx.

Referenced by intel_poll(), intelx_poll(), and intelxvf_poll().

◆ intel_poll_rx()

void intel_poll_rx ( struct net_device *  netdev)

Poll for received packets.

Parameters
netdevNetwork device

Definition at line 821 of file intel.c.

821  {
822  struct intel_nic *intel = netdev->priv;
823  struct intel_descriptor *rx;
824  struct io_buffer *iobuf;
825  unsigned int rx_idx;
826  size_t len;
827 
828  /* Check for received packets */
829  while ( intel->rx.cons != intel->rx.prod ) {
830 
831  /* Get next receive descriptor */
832  rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
833  rx = &intel->rx.desc[rx_idx];
834 
835  /* Stop if descriptor is still in use */
836  if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
837  return;
838 
839  /* Populate I/O buffer */
840  iobuf = intel->rx_iobuf[rx_idx];
841  intel->rx_iobuf[rx_idx] = NULL;
842  len = le16_to_cpu ( rx->length );
843  iob_put ( iobuf, len );
844 
845  /* Hand off to network stack */
846  if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
847  DBGC ( intel, "INTEL %p RX %d error (length %zd, "
848  "status %08x)\n", intel, rx_idx, len,
849  le32_to_cpu ( rx->status ) );
850  netdev_rx_err ( netdev, iobuf, -EIO );
851  } else {
852  DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
853  intel, rx_idx, len );
854  netdev_rx ( netdev, iobuf );
855  }
856  intel->rx.cons++;
857  }
858 }
INTEL_DESC_STATUS_DD
#define INTEL_DESC_STATUS_DD
Descriptor done.
Definition: intel.h:52
iob_put
#define iob_put(iobuf, len)
Definition: iobuf.h:125
INTEL_NUM_RX_DESC
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:155
netdev_rx_err
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:587
le32_to_cpu
#define le32_to_cpu(value)
Definition: byteswap.h:114
intel_nic::rx
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:315
DBGC
#define DBGC(...)
Definition: compiler.h:505
intel_ring::cons
unsigned int cons
Consumer index.
Definition: intel.h:231
net_device::priv
void * priv
Driver private data.
Definition: netdevice.h:432
len
ring len
Length.
Definition: dwmac.h:231
netdev
static struct net_device * netdev
Definition: gdbudp.c:52
intel_nic::rx_iobuf
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:317
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:108
le16_to_cpu
#define le16_to_cpu(value)
Definition: byteswap.h:113
netdev_rx
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:549
intel_descriptor
A packet descriptor.
Definition: intel.h:22
DBGC2
#define DBGC2(...)
Definition: compiler.h:522
intel_ring::prod
unsigned int prod
Producer index.
Definition: intel.h:229
EIO
#define EIO
Input/output error.
Definition: errno.h:434
rx
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
intel_nic
An Intel network card.
Definition: intel.h:290
intel_ring::desc
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:225
INTEL_DESC_STATUS_RXE
#define INTEL_DESC_STATUS_RXE
Receive error.
Definition: intel.h:55
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
io_buffer
A persistent I/O buffer.
Definition: iobuf.h:38

References intel_ring::cons, cpu_to_le32, DBGC, DBGC2, intel_ring::desc, EIO, INTEL_DESC_STATUS_DD, INTEL_DESC_STATUS_RXE, INTEL_NUM_RX_DESC, iob_put, le16_to_cpu, le32_to_cpu, len, netdev, netdev_rx(), netdev_rx_err(), NULL, net_device::priv, intel_ring::prod, rx, intel_nic::rx, and intel_nic::rx_iobuf.

Referenced by intel_poll(), intelx_poll(), and intelxvf_poll().

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