iPXE
Data Structures | Macros | Enumerations | Functions | Variables
intel.h File Reference

Intel 10/100/1000 network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/nvs.h>

Go to the source code of this file.

Data Structures

struct  intel_descriptor
 A packet descriptor. More...
 
union  intel_receive_address
 Receive address. More...
 
struct  intel_ring
 An Intel descriptor ring. More...
 
struct  intel_mailbox
 An Intel virtual function mailbox. More...
 
struct  intel_nic
 An Intel network card. More...
 

Macros

#define INTEL_BAR_SIZE   ( 128 * 1024 )
 Intel BAR size. More...
 
#define INTEL_DESC_FL_DTYP(dtyp)   ( (dtyp) << 4 )
 Descriptor type. More...
 
#define INTEL_DESC_FL_DTYP_DATA   INTEL_DESC_FL_DTYP ( 0x03 )
 
#define INTEL_DESC_CMD_DEXT   0x20
 Descriptor extension. More...
 
#define INTEL_DESC_CMD_RS   0x08
 Report status. More...
 
#define INTEL_DESC_CMD_IFCS   0x02
 Insert frame checksum (CRC) More...
 
#define INTEL_DESC_CMD_EOP   0x01
 End of packet. More...
 
#define INTEL_DESC_STATUS_DD   0x00000001UL
 Descriptor done. More...
 
#define INTEL_DESC_STATUS_RXE   0x00000100UL
 Receive error. More...
 
#define INTEL_DESC_STATUS_PAYLEN(len)   ( (len) << 14 )
 Payload length. More...
 
#define INTEL_CTRL   0x00000UL
 Device Control Register. More...
 
#define INTEL_CTRL_LRST   0x00000008UL
 Link reset. More...
 
#define INTEL_CTRL_ASDE   0x00000020UL
 Auto-speed detection. More...
 
#define INTEL_CTRL_SLU   0x00000040UL
 Set link up. More...
 
#define INTEL_CTRL_FRCSPD   0x00000800UL
 Force speed. More...
 
#define INTEL_CTRL_FRCDPLX   0x00001000UL
 Force duplex. More...
 
#define INTEL_CTRL_RST   0x04000000UL
 Device reset. More...
 
#define INTEL_CTRL_PHY_RST   0x80000000UL
 PHY reset. More...
 
#define INTEL_RESET_DELAY_MS   20
 Time to delay for device reset, in milliseconds. More...
 
#define INTEL_STATUS   0x00008UL
 Device Status Register. More...
 
#define INTEL_STATUS_LU   0x00000002UL
 Link up. More...
 
#define INTEL_EERD   0x00014UL
 EEPROM Read Register. More...
 
#define INTEL_EERD_START   0x00000001UL
 Start read. More...
 
#define INTEL_EERD_DONE_SMALL   0x00000010UL
 Read done (small EERD) More...
 
#define INTEL_EERD_DONE_LARGE   0x00000002UL
 Read done (large EERD) More...
 
#define INTEL_EERD_ADDR_SHIFT_SMALL   8
 Address shift (small) More...
 
#define INTEL_EERD_ADDR_SHIFT_LARGE   2
 Address shift (large) More...
 
#define INTEL_EERD_DATA(value)   ( (value) >> 16 )
 Read data. More...
 
#define INTEL_EEPROM_MAX_WAIT_MS   100
 Maximum time to wait for EEPROM read, in milliseconds. More...
 
#define INTEL_EEPROM_WORD_LEN_LOG2   1
 EEPROM word length. More...
 
#define INTEL_EEPROM_MIN_SIZE_WORDS   64
 Minimum EEPROM size, in words. More...
 
#define INTEL_EEPROM_MAC   0x00
 Offset of MAC address within EEPROM. More...
 
#define INTEL_ICR   0x000c0UL
 Interrupt Cause Read Register. More...
 
#define INTEL_IRQ_TXDW   0x00000001UL
 Transmit descriptor done. More...
 
#define INTEL_IRQ_TXQE   0x00000002UL
 Transmit queue empty. More...
 
#define INTEL_IRQ_LSC   0x00000004UL
 Link status change. More...
 
#define INTEL_IRQ_RXDMT0   0x00000010UL
 Receive queue low. More...
 
#define INTEL_IRQ_RXO   0x00000040UL
 Receive overrun. More...
 
#define INTEL_IRQ_RXT0   0x00000080UL
 Receive timer. More...
 
#define INTEL_IMS   0x000d0UL
 Interrupt Mask Set/Read Register. More...
 
#define INTEL_IMC   0x000d8UL
 Interrupt Mask Clear Register. More...
 
#define INTEL_RCTL   0x00100UL
 Receive Control Register. More...
 
#define INTEL_RCTL_EN   0x00000002UL
 Receive enable. More...
 
#define INTEL_RCTL_UPE   0x00000008UL
 Unicast promiscuous mode. More...
 
#define INTEL_RCTL_MPE   0x00000010UL
 Multicast promiscuous. More...
 
#define INTEL_RCTL_BAM   0x00008000UL
 Broadcast accept mode. More...
 
#define INTEL_RCTL_BSIZE_BSEX(bsex, bsize)   ( ( (bsize) << 16 ) | ( (bsex) << 25 ) )
 Buffer size. More...
 
#define INTEL_RCTL_BSIZE_2048   INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
 
#define INTEL_RCTL_BSIZE_BSEX_MASK   INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
 
#define INTEL_RCTL_SECRC   0x04000000UL
 Strip CRC. More...
 
#define INTEL_TCTL   0x00400UL
 Transmit Control Register. More...
 
#define INTEL_TCTL_EN   0x00000002UL
 Transmit enable. More...
 
#define INTEL_TCTL_PSP   0x00000008UL
 Pad short packets. More...
 
#define INTEL_TCTL_CT(x)   ( (x) << 4 )
 Collision threshold. More...
 
#define INTEL_TCTL_CT_DEFAULT   INTEL_TCTL_CT ( 0x0f )
 
#define INTEL_TCTL_CT_MASK   INTEL_TCTL_CT ( 0xff )
 
#define INTEL_TCTL_COLD(x)   ( (x) << 12 )
 Collision distance. More...
 
#define INTEL_TCTL_COLD_DEFAULT   INTEL_TCTL_COLD ( 0x040 )
 
#define INTEL_TCTL_COLD_MASK   INTEL_TCTL_COLD ( 0x3ff )
 
#define INTEL_PBA   0x01000UL
 Packet Buffer Allocation. More...
 
#define INTEL_PBS   0x01008UL
 Packet Buffer Size. More...
 
#define INTEL_RD   0x02800UL
 Receive Descriptor register block. More...
 
#define INTEL_NUM_RX_DESC   16
 Number of receive descriptors. More...
 
#define INTEL_RX_FILL   8
 Receive descriptor ring fill level. More...
 
#define INTEL_RX_MAX_LEN   2048
 Receive buffer length. More...
 
#define INTEL_TD   0x03800UL
 Transmit Descriptor register block. More...
 
#define INTEL_NUM_TX_DESC   16
 Number of transmit descriptors. More...
 
#define INTEL_TX_FILL   ( INTEL_NUM_TX_DESC - 1 )
 Transmit descriptor ring maximum fill level. More...
 
#define INTEL_xDBAL   0x00
 Receive/Transmit Descriptor Base Address Low (offset) More...
 
#define INTEL_xDBAH   0x04
 Receive/Transmit Descriptor Base Address High (offset) More...
 
#define INTEL_xDLEN   0x08
 Receive/Transmit Descriptor Length (offset) More...
 
#define INTEL_xDH   0x10
 Receive/Transmit Descriptor Head (offset) More...
 
#define INTEL_xDT   0x18
 Receive/Transmit Descriptor Tail (offset) More...
 
#define INTEL_xDCTL   0x28
 Receive/Transmit Descriptor Control (offset) More...
 
#define INTEL_xDCTL_ENABLE   0x02000000UL
 Queue enable. More...
 
#define INTEL_DISABLE_MAX_WAIT_MS   100
 Maximum time to wait for queue disable, in milliseconds. More...
 
#define INTEL_RAL0   0x05400UL
 Receive Address Low. More...
 
#define INTEL_RAH0   0x05404UL
 Receive Address High. More...
 
#define INTEL_RAH0_AV   0x80000000UL
 Address valid. More...
 
#define INTEL_FEXTNVM11   0x05bbcUL
 Future Extended NVM register 11. More...
 
#define INTEL_FEXTNVM11_WTF   0x00002000UL
 Don't ask. More...
 
#define INTEL_I219   ( INTEL_NO_PHY_RST | INTEL_RST_HANG )
 The i219 has a seriously broken reset mechanism. More...
 

Enumerations

enum  intel_flags {
  INTEL_PBS_ERRATA = 0x0001, INTEL_VMWARE = 0x0002, INTEL_NO_PHY_RST = 0x0004, INTEL_NO_ASDE = 0x0008,
  INTEL_RST_HANG = 0x0010
}
 Driver flags. More...
 

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
struct intel_descriptor __attribute__ ((packed))
 
static __attribute__ ((always_inline)) void intel_init_ring(struct intel_ring *ring
 Initialise descriptor ring. More...
 
static void intel_diag (struct intel_nic *intel)
 Dump diagnostic information. More...
 
void intel_describe_tx (struct intel_descriptor *tx, physaddr_t addr, size_t len)
 Populate transmit descriptor. More...
 
void intel_describe_tx_adv (struct intel_descriptor *tx, physaddr_t addr, size_t len)
 Populate advanced transmit descriptor. More...
 
void intel_describe_rx (struct intel_descriptor *rx, physaddr_t addr, size_t len)
 Populate receive descriptor. More...
 
void intel_reset_ring (struct intel_nic *intel, unsigned int reg)
 Reset descriptor ring. More...
 
int intel_create_ring (struct intel_nic *intel, struct intel_ring *ring)
 Create descriptor ring. More...
 
void intel_destroy_ring (struct intel_nic *intel, struct intel_ring *ring)
 Destroy descriptor ring. More...
 
void intel_refill_rx (struct intel_nic *intel)
 Refill receive descriptor ring. More...
 
void intel_empty_rx (struct intel_nic *intel)
 Discard unused receive I/O buffers. More...
 
int intel_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
void intel_poll_tx (struct net_device *netdev)
 Poll for completed packets. More...
 
void intel_poll_rx (struct net_device *netdev)
 Poll for received packets. More...
 

Variables

uint64_t address
 Buffer address. More...
 
uint16_t length
 Length. More...
 
uint8_t flags
 Flags. More...
 
uint8_t command
 Command. More...
 
uint32_t status
 Status. More...
 
uint32_t low
 Low 16 bits of address. More...
 
uint32_t high
 High 32 bits of address. More...
 
union intel_receive_address __attribute__
 
static unsigned int count
 
static unsigned int unsigned int reg = reg
 
static unsigned int unsigned int void(* describe )(struct intel_descriptor *desc, physaddr_t addr, size_t len))
 
static unsigned int ctrl
 
static unsigned int unsigned int mem
 

Detailed Description

Intel 10/100/1000 network card driver.

Definition in file intel.h.

Macro Definition Documentation

◆ INTEL_BAR_SIZE

#define INTEL_BAR_SIZE   ( 128 * 1024 )

Intel BAR size.

Definition at line 17 of file intel.h.

◆ INTEL_DESC_FL_DTYP

#define INTEL_DESC_FL_DTYP (   dtyp)    ( (dtyp) << 4 )

Descriptor type.

Definition at line 34 of file intel.h.

◆ INTEL_DESC_FL_DTYP_DATA

#define INTEL_DESC_FL_DTYP_DATA   INTEL_DESC_FL_DTYP ( 0x03 )

Definition at line 35 of file intel.h.

◆ INTEL_DESC_CMD_DEXT

#define INTEL_DESC_CMD_DEXT   0x20

Descriptor extension.

Definition at line 38 of file intel.h.

◆ INTEL_DESC_CMD_RS

#define INTEL_DESC_CMD_RS   0x08

Report status.

Definition at line 41 of file intel.h.

◆ INTEL_DESC_CMD_IFCS

#define INTEL_DESC_CMD_IFCS   0x02

Insert frame checksum (CRC)

Definition at line 44 of file intel.h.

◆ INTEL_DESC_CMD_EOP

#define INTEL_DESC_CMD_EOP   0x01

End of packet.

Definition at line 47 of file intel.h.

◆ INTEL_DESC_STATUS_DD

#define INTEL_DESC_STATUS_DD   0x00000001UL

Descriptor done.

Definition at line 50 of file intel.h.

◆ INTEL_DESC_STATUS_RXE

#define INTEL_DESC_STATUS_RXE   0x00000100UL

Receive error.

Definition at line 53 of file intel.h.

◆ INTEL_DESC_STATUS_PAYLEN

#define INTEL_DESC_STATUS_PAYLEN (   len)    ( (len) << 14 )

Payload length.

Definition at line 56 of file intel.h.

◆ INTEL_CTRL

#define INTEL_CTRL   0x00000UL

Device Control Register.

Definition at line 59 of file intel.h.

◆ INTEL_CTRL_LRST

#define INTEL_CTRL_LRST   0x00000008UL

Link reset.

Definition at line 60 of file intel.h.

◆ INTEL_CTRL_ASDE

#define INTEL_CTRL_ASDE   0x00000020UL

Auto-speed detection.

Definition at line 61 of file intel.h.

◆ INTEL_CTRL_SLU

#define INTEL_CTRL_SLU   0x00000040UL

Set link up.

Definition at line 62 of file intel.h.

◆ INTEL_CTRL_FRCSPD

#define INTEL_CTRL_FRCSPD   0x00000800UL

Force speed.

Definition at line 63 of file intel.h.

◆ INTEL_CTRL_FRCDPLX

#define INTEL_CTRL_FRCDPLX   0x00001000UL

Force duplex.

Definition at line 64 of file intel.h.

◆ INTEL_CTRL_RST

#define INTEL_CTRL_RST   0x04000000UL

Device reset.

Definition at line 65 of file intel.h.

◆ INTEL_CTRL_PHY_RST

#define INTEL_CTRL_PHY_RST   0x80000000UL

PHY reset.

Definition at line 66 of file intel.h.

◆ INTEL_RESET_DELAY_MS

#define INTEL_RESET_DELAY_MS   20

Time to delay for device reset, in milliseconds.

Definition at line 69 of file intel.h.

◆ INTEL_STATUS

#define INTEL_STATUS   0x00008UL

Device Status Register.

Definition at line 72 of file intel.h.

◆ INTEL_STATUS_LU

#define INTEL_STATUS_LU   0x00000002UL

Link up.

Definition at line 73 of file intel.h.

◆ INTEL_EERD

#define INTEL_EERD   0x00014UL

EEPROM Read Register.

Definition at line 76 of file intel.h.

◆ INTEL_EERD_START

#define INTEL_EERD_START   0x00000001UL

Start read.

Definition at line 77 of file intel.h.

◆ INTEL_EERD_DONE_SMALL

#define INTEL_EERD_DONE_SMALL   0x00000010UL

Read done (small EERD)

Definition at line 78 of file intel.h.

◆ INTEL_EERD_DONE_LARGE

#define INTEL_EERD_DONE_LARGE   0x00000002UL

Read done (large EERD)

Definition at line 79 of file intel.h.

◆ INTEL_EERD_ADDR_SHIFT_SMALL

#define INTEL_EERD_ADDR_SHIFT_SMALL   8

Address shift (small)

Definition at line 80 of file intel.h.

◆ INTEL_EERD_ADDR_SHIFT_LARGE

#define INTEL_EERD_ADDR_SHIFT_LARGE   2

Address shift (large)

Definition at line 81 of file intel.h.

◆ INTEL_EERD_DATA

#define INTEL_EERD_DATA (   value)    ( (value) >> 16 )

Read data.

Definition at line 82 of file intel.h.

◆ INTEL_EEPROM_MAX_WAIT_MS

#define INTEL_EEPROM_MAX_WAIT_MS   100

Maximum time to wait for EEPROM read, in milliseconds.

Definition at line 85 of file intel.h.

◆ INTEL_EEPROM_WORD_LEN_LOG2

#define INTEL_EEPROM_WORD_LEN_LOG2   1

EEPROM word length.

Definition at line 88 of file intel.h.

◆ INTEL_EEPROM_MIN_SIZE_WORDS

#define INTEL_EEPROM_MIN_SIZE_WORDS   64

Minimum EEPROM size, in words.

Definition at line 91 of file intel.h.

◆ INTEL_EEPROM_MAC

#define INTEL_EEPROM_MAC   0x00

Offset of MAC address within EEPROM.

Definition at line 94 of file intel.h.

◆ INTEL_ICR

#define INTEL_ICR   0x000c0UL

Interrupt Cause Read Register.

Definition at line 97 of file intel.h.

◆ INTEL_IRQ_TXDW

#define INTEL_IRQ_TXDW   0x00000001UL

Transmit descriptor done.

Definition at line 98 of file intel.h.

◆ INTEL_IRQ_TXQE

#define INTEL_IRQ_TXQE   0x00000002UL

Transmit queue empty.

Definition at line 99 of file intel.h.

◆ INTEL_IRQ_LSC

#define INTEL_IRQ_LSC   0x00000004UL

Link status change.

Definition at line 100 of file intel.h.

◆ INTEL_IRQ_RXDMT0

#define INTEL_IRQ_RXDMT0   0x00000010UL

Receive queue low.

Definition at line 101 of file intel.h.

◆ INTEL_IRQ_RXO

#define INTEL_IRQ_RXO   0x00000040UL

Receive overrun.

Definition at line 102 of file intel.h.

◆ INTEL_IRQ_RXT0

#define INTEL_IRQ_RXT0   0x00000080UL

Receive timer.

Definition at line 103 of file intel.h.

◆ INTEL_IMS

#define INTEL_IMS   0x000d0UL

Interrupt Mask Set/Read Register.

Definition at line 106 of file intel.h.

◆ INTEL_IMC

#define INTEL_IMC   0x000d8UL

Interrupt Mask Clear Register.

Definition at line 109 of file intel.h.

◆ INTEL_RCTL

#define INTEL_RCTL   0x00100UL

Receive Control Register.

Definition at line 112 of file intel.h.

◆ INTEL_RCTL_EN

#define INTEL_RCTL_EN   0x00000002UL

Receive enable.

Definition at line 113 of file intel.h.

◆ INTEL_RCTL_UPE

#define INTEL_RCTL_UPE   0x00000008UL

Unicast promiscuous mode.

Definition at line 114 of file intel.h.

◆ INTEL_RCTL_MPE

#define INTEL_RCTL_MPE   0x00000010UL

Multicast promiscuous.

Definition at line 115 of file intel.h.

◆ INTEL_RCTL_BAM

#define INTEL_RCTL_BAM   0x00008000UL

Broadcast accept mode.

Definition at line 116 of file intel.h.

◆ INTEL_RCTL_BSIZE_BSEX

#define INTEL_RCTL_BSIZE_BSEX (   bsex,
  bsize 
)    ( ( (bsize) << 16 ) | ( (bsex) << 25 ) )

Buffer size.

Definition at line 117 of file intel.h.

◆ INTEL_RCTL_BSIZE_2048

#define INTEL_RCTL_BSIZE_2048   INTEL_RCTL_BSIZE_BSEX ( 0, 0 )

Definition at line 120 of file intel.h.

◆ INTEL_RCTL_BSIZE_BSEX_MASK

#define INTEL_RCTL_BSIZE_BSEX_MASK   INTEL_RCTL_BSIZE_BSEX ( 1, 3 )

Definition at line 121 of file intel.h.

◆ INTEL_RCTL_SECRC

#define INTEL_RCTL_SECRC   0x04000000UL

Strip CRC.

Definition at line 122 of file intel.h.

◆ INTEL_TCTL

#define INTEL_TCTL   0x00400UL

Transmit Control Register.

Definition at line 125 of file intel.h.

◆ INTEL_TCTL_EN

#define INTEL_TCTL_EN   0x00000002UL

Transmit enable.

Definition at line 126 of file intel.h.

◆ INTEL_TCTL_PSP

#define INTEL_TCTL_PSP   0x00000008UL

Pad short packets.

Definition at line 127 of file intel.h.

◆ INTEL_TCTL_CT

#define INTEL_TCTL_CT (   x)    ( (x) << 4 )

Collision threshold.

Definition at line 128 of file intel.h.

◆ INTEL_TCTL_CT_DEFAULT

#define INTEL_TCTL_CT_DEFAULT   INTEL_TCTL_CT ( 0x0f )

Definition at line 129 of file intel.h.

◆ INTEL_TCTL_CT_MASK

#define INTEL_TCTL_CT_MASK   INTEL_TCTL_CT ( 0xff )

Definition at line 130 of file intel.h.

◆ INTEL_TCTL_COLD

#define INTEL_TCTL_COLD (   x)    ( (x) << 12 )

Collision distance.

Definition at line 131 of file intel.h.

◆ INTEL_TCTL_COLD_DEFAULT

#define INTEL_TCTL_COLD_DEFAULT   INTEL_TCTL_COLD ( 0x040 )

Definition at line 132 of file intel.h.

◆ INTEL_TCTL_COLD_MASK

#define INTEL_TCTL_COLD_MASK   INTEL_TCTL_COLD ( 0x3ff )

Definition at line 133 of file intel.h.

◆ INTEL_PBA

#define INTEL_PBA   0x01000UL

Packet Buffer Allocation.

Definition at line 136 of file intel.h.

◆ INTEL_PBS

#define INTEL_PBS   0x01008UL

Packet Buffer Size.

Definition at line 139 of file intel.h.

◆ INTEL_RD

#define INTEL_RD   0x02800UL

Receive Descriptor register block.

Definition at line 142 of file intel.h.

◆ INTEL_NUM_RX_DESC

#define INTEL_NUM_RX_DESC   16

Number of receive descriptors.

Minimum value is 8, since the descriptor ring length must be a multiple of 128.

Definition at line 149 of file intel.h.

◆ INTEL_RX_FILL

#define INTEL_RX_FILL   8

Receive descriptor ring fill level.

Definition at line 152 of file intel.h.

◆ INTEL_RX_MAX_LEN

#define INTEL_RX_MAX_LEN   2048

Receive buffer length.

Definition at line 155 of file intel.h.

◆ INTEL_TD

#define INTEL_TD   0x03800UL

Transmit Descriptor register block.

Definition at line 158 of file intel.h.

◆ INTEL_NUM_TX_DESC

#define INTEL_NUM_TX_DESC   16

Number of transmit descriptors.

Descriptor ring length must be a multiple of 16. ICH8/9/10 requires a minimum of 16 TX descriptors.

Definition at line 165 of file intel.h.

◆ INTEL_TX_FILL

#define INTEL_TX_FILL   ( INTEL_NUM_TX_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 168 of file intel.h.

◆ INTEL_xDBAL

#define INTEL_xDBAL   0x00

Receive/Transmit Descriptor Base Address Low (offset)

Definition at line 171 of file intel.h.

◆ INTEL_xDBAH

#define INTEL_xDBAH   0x04

Receive/Transmit Descriptor Base Address High (offset)

Definition at line 174 of file intel.h.

◆ INTEL_xDLEN

#define INTEL_xDLEN   0x08

Receive/Transmit Descriptor Length (offset)

Definition at line 177 of file intel.h.

◆ INTEL_xDH

#define INTEL_xDH   0x10

Receive/Transmit Descriptor Head (offset)

Definition at line 180 of file intel.h.

◆ INTEL_xDT

#define INTEL_xDT   0x18

Receive/Transmit Descriptor Tail (offset)

Definition at line 183 of file intel.h.

◆ INTEL_xDCTL

#define INTEL_xDCTL   0x28

Receive/Transmit Descriptor Control (offset)

Definition at line 186 of file intel.h.

◆ INTEL_xDCTL_ENABLE

#define INTEL_xDCTL_ENABLE   0x02000000UL

Queue enable.

Definition at line 187 of file intel.h.

◆ INTEL_DISABLE_MAX_WAIT_MS

#define INTEL_DISABLE_MAX_WAIT_MS   100

Maximum time to wait for queue disable, in milliseconds.

Definition at line 190 of file intel.h.

◆ INTEL_RAL0

#define INTEL_RAL0   0x05400UL

Receive Address Low.

Definition at line 193 of file intel.h.

◆ INTEL_RAH0

#define INTEL_RAH0   0x05404UL

Receive Address High.

Definition at line 196 of file intel.h.

◆ INTEL_RAH0_AV

#define INTEL_RAH0_AV   0x80000000UL

Address valid.

Definition at line 197 of file intel.h.

◆ INTEL_FEXTNVM11

#define INTEL_FEXTNVM11   0x05bbcUL

Future Extended NVM register 11.

Definition at line 200 of file intel.h.

◆ INTEL_FEXTNVM11_WTF

#define INTEL_FEXTNVM11_WTF   0x00002000UL

Don't ask.

Definition at line 201 of file intel.h.

◆ INTEL_I219

#define INTEL_I219   ( INTEL_NO_PHY_RST | INTEL_RST_HANG )

The i219 has a seriously broken reset mechanism.

Definition at line 321 of file intel.h.

Enumeration Type Documentation

◆ intel_flags

Driver flags.

Enumerator
INTEL_PBS_ERRATA 

PBS/PBA errata workaround required.

INTEL_VMWARE 

VMware missing interrupt workaround required.

INTEL_NO_PHY_RST 

PHY reset is broken.

INTEL_NO_ASDE 

ASDE is broken.

INTEL_RST_HANG 

Reset may cause a complete device hang.

Definition at line 307 of file intel.h.

327  {

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ __attribute__() [1/2]

struct intel_descriptor __attribute__ ( (packed)  )

◆ __attribute__() [2/2]

static __attribute__ ( (always_inline)  )
inlinestatic

Initialise descriptor ring.

Initialise mailbox.

Parameters
ringDescriptor ring
countNumber of descriptors
regDescriptor register block
describeMethod to populate descriptor
mboxMailbox
ctrlMailbox control register
memMailbox memory register base

◆ intel_diag()

static void intel_diag ( struct intel_nic intel)
inlinestatic

Dump diagnostic information.

Parameters
intelIntel device

Definition at line 328 of file intel.h.

◆ intel_describe_tx()

void intel_describe_tx ( struct intel_descriptor tx,
physaddr_t  addr,
size_t  len 
)

Populate transmit descriptor.

Parameters
txTransmit descriptor
addrData buffer address
lenLength of data

Definition at line 383 of file intel.c.

384  {
385 
386  /* Populate transmit descriptor */
387  tx->address = cpu_to_le64 ( addr );
388  tx->length = cpu_to_le16 ( len );
389  tx->flags = 0;
390  tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
392  tx->status = 0;
393 }
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define INTEL_DESC_CMD_IFCS
Insert frame checksum (CRC)
Definition: intel.h:44
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
u32 addr
Definition: sky2.h:8
uint32_t len
Length.
Definition: ena.h:14
#define INTEL_DESC_CMD_EOP
End of packet.
Definition: intel.h:47
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTEL_DESC_CMD_RS
Report status.
Definition: intel.h:41

References addr, cpu_to_le16, cpu_to_le64, INTEL_DESC_CMD_EOP, INTEL_DESC_CMD_IFCS, INTEL_DESC_CMD_RS, len, and tx.

Referenced by intel_probe(), and intelx_probe().

◆ intel_describe_tx_adv()

void intel_describe_tx_adv ( struct intel_descriptor tx,
physaddr_t  addr,
size_t  len 
)

Populate advanced transmit descriptor.

Parameters
txTransmit descriptor
addrData buffer address
lenLength of data

Definition at line 402 of file intel.c.

403  {
404 
405  /* Populate advanced transmit descriptor */
406  tx->address = cpu_to_le64 ( addr );
407  tx->length = cpu_to_le16 ( len );
408  tx->flags = INTEL_DESC_FL_DTYP_DATA;
409  tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
411  tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
412 }
#define INTEL_DESC_STATUS_PAYLEN(len)
Payload length.
Definition: intel.h:56
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define INTEL_DESC_FL_DTYP_DATA
Definition: intel.h:35
#define INTEL_DESC_CMD_IFCS
Insert frame checksum (CRC)
Definition: intel.h:44
#define cpu_to_le32(value)
Definition: byteswap.h:107
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
u32 addr
Definition: sky2.h:8
uint32_t len
Length.
Definition: ena.h:14
#define INTEL_DESC_CMD_DEXT
Descriptor extension.
Definition: intel.h:38
#define INTEL_DESC_CMD_EOP
End of packet.
Definition: intel.h:47
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTEL_DESC_CMD_RS
Report status.
Definition: intel.h:41

References addr, cpu_to_le16, cpu_to_le32, cpu_to_le64, INTEL_DESC_CMD_DEXT, INTEL_DESC_CMD_EOP, INTEL_DESC_CMD_IFCS, INTEL_DESC_CMD_RS, INTEL_DESC_FL_DTYP_DATA, INTEL_DESC_STATUS_PAYLEN, len, and tx.

Referenced by intelxvf_probe().

◆ intel_describe_rx()

void intel_describe_rx ( struct intel_descriptor rx,
physaddr_t  addr,
size_t len  __unused 
)

Populate receive descriptor.

Parameters
rxReceive descriptor
addrData buffer address
lenLength of data

Definition at line 421 of file intel.c.

422  {
423 
424  /* Populate transmit descriptor */
425  rx->address = cpu_to_le64 ( addr );
426  rx->length = 0;
427  rx->status = 0;
428 }
#define cpu_to_le64(value)
Definition: byteswap.h:108
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
u32 addr
Definition: sky2.h:8

References addr, cpu_to_le64, and rx.

Referenced by intel_probe(), intelx_probe(), and intelxvf_probe().

◆ intel_reset_ring()

void intel_reset_ring ( struct intel_nic intel,
unsigned int  reg 
)

Reset descriptor ring.

Parameters
intelIntel device
regRegister block
Return values
rcReturn status code

Definition at line 475 of file intel.c.

475  {
476 
477  /* Disable ring. Ignore errors and continue to reset the ring anyway */
478  intel_disable_ring ( intel, reg );
479 
480  /* Clear ring length */
481  writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
482 
483  /* Clear ring address */
484  writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
485  writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
486 
487  /* Reset head and tail pointers */
488  writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
489  writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
490 }
void * regs
Registers.
Definition: intel.h:280
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
#define INTEL_xDLEN
Receive/Transmit Descriptor Length (offset)
Definition: intel.h:177
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:180
#define INTEL_xDBAL
Receive/Transmit Descriptor Base Address Low (offset)
Definition: intel.h:171
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static unsigned int unsigned int reg
Definition: intel.h:245
static int intel_disable_ring(struct intel_nic *intel, unsigned int reg)
Disable descriptor ring.
Definition: intel.c:444
#define INTEL_xDBAH
Receive/Transmit Descriptor Base Address High (offset)
Definition: intel.h:174

References intel_disable_ring(), INTEL_xDBAH, INTEL_xDBAL, INTEL_xDH, INTEL_xDLEN, INTEL_xDT, reg, intel_nic::regs, and writel().

Referenced by intel_destroy_ring(), and intelxvf_open().

◆ intel_create_ring()

int intel_create_ring ( struct intel_nic intel,
struct intel_ring ring 
)

Create descriptor ring.

Parameters
intelIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 499 of file intel.c.

499  {
501  uint32_t dctl;
502 
503  /* Allocate descriptor ring. Align ring on its own size to
504  * prevent any possible page-crossing errors due to hardware
505  * errata.
506  */
507  ring->desc = malloc_dma ( ring->len, ring->len );
508  if ( ! ring->desc )
509  return -ENOMEM;
510 
511  /* Initialise descriptor ring */
512  memset ( ring->desc, 0, ring->len );
513 
514  /* Program ring address */
515  address = virt_to_bus ( ring->desc );
516  writel ( ( address & 0xffffffffUL ),
517  ( intel->regs + ring->reg + INTEL_xDBAL ) );
518  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
519  writel ( ( ( ( uint64_t ) address ) >> 32 ),
520  ( intel->regs + ring->reg + INTEL_xDBAH ) );
521  } else {
522  writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
523  }
524 
525  /* Program ring length */
526  writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
527 
528  /* Reset head and tail pointers */
529  writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
530  writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
531 
532  /* Enable ring */
533  dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
534  dctl |= INTEL_xDCTL_ENABLE;
535  writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
536 
537  DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
538  intel, ring->reg, ( ( unsigned long long ) address ),
539  ( ( unsigned long long ) address + ring->len ) );
540 
541  return 0;
542 }
void * regs
Registers.
Definition: intel.h:280
#define INTEL_xDCTL
Receive/Transmit Descriptor Control (offset)
Definition: intel.h:186
uint64_t address
Base address.
Definition: ena.h:24
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
size_t len
Length (in bytes)
Definition: intel.h:224
unsigned long long uint64_t
Definition: stdint.h:13
#define INTEL_xDLEN
Receive/Transmit Descriptor Length (offset)
Definition: intel.h:177
unsigned int reg
Register block.
Definition: intel.h:222
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:180
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define INTEL_xDBAL
Receive/Transmit Descriptor Base Address Low (offset)
Definition: intel.h:171
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
unsigned int uint32_t
Definition: stdint.h:12
unsigned long physaddr_t
Definition: stdint.h:20
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
#define INTEL_xDCTL_ENABLE
Queue enable.
Definition: intel.h:187
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
#define INTEL_xDBAH
Receive/Transmit Descriptor Base Address High (offset)
Definition: intel.h:174
void * memset(void *dest, int character, size_t len) __nonnull

References address, DBGC, intel_ring::desc, ENOMEM, INTEL_xDBAH, INTEL_xDBAL, INTEL_xDCTL, INTEL_xDCTL_ENABLE, INTEL_xDH, INTEL_xDLEN, INTEL_xDT, intel_ring::len, malloc_dma(), memset(), readl(), intel_ring::reg, intel_nic::regs, virt_to_bus(), and writel().

Referenced by intel_open(), intelx_open(), and intelxvf_open().

◆ intel_destroy_ring()

void intel_destroy_ring ( struct intel_nic intel,
struct intel_ring ring 
)

Destroy descriptor ring.

Parameters
intelIntel device
ringDescriptor ring

Definition at line 550 of file intel.c.

550  {
551 
552  /* Reset ring */
553  intel_reset_ring ( intel, ring->reg );
554 
555  /* Free descriptor ring */
556  free_dma ( ring->desc, ring->len );
557  ring->desc = NULL;
558  ring->prod = 0;
559  ring->cons = 0;
560 }
void intel_reset_ring(struct intel_nic *intel, unsigned int reg)
Reset descriptor ring.
Definition: intel.c:475
size_t len
Length (in bytes)
Definition: intel.h:224
unsigned int cons
Consumer index.
Definition: intel.h:219
unsigned int reg
Register block.
Definition: intel.h:222
unsigned int prod
Producer index.
Definition: intel.h:217
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References intel_ring::cons, intel_ring::desc, free_dma(), intel_reset_ring(), intel_ring::len, NULL, intel_ring::prod, and intel_ring::reg.

Referenced by intel_close(), intel_open(), intelx_close(), intelx_open(), intelxvf_close(), and intelxvf_open().

◆ intel_refill_rx()

void intel_refill_rx ( struct intel_nic intel)

Refill receive descriptor ring.

Parameters
intelIntel device

Definition at line 567 of file intel.c.

567  {
568  struct intel_descriptor *rx;
569  struct io_buffer *iobuf;
570  unsigned int rx_idx;
571  unsigned int rx_tail;
573  unsigned int refilled = 0;
574 
575  /* Refill ring */
576  while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
577 
578  /* Allocate I/O buffer */
579  iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
580  if ( ! iobuf ) {
581  /* Wait for next refill */
582  break;
583  }
584 
585  /* Get next receive descriptor */
586  rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
587  rx = &intel->rx.desc[rx_idx];
588 
589  /* Populate receive descriptor */
590  address = virt_to_bus ( iobuf->data );
591  intel->rx.describe ( rx, address, 0 );
592 
593  /* Record I/O buffer */
594  assert ( intel->rx_iobuf[rx_idx] == NULL );
595  intel->rx_iobuf[rx_idx] = iobuf;
596 
597  DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
598  ( ( unsigned long long ) address ),
599  ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
600  refilled++;
601  }
602 
603  /* Push descriptors to card, if applicable */
604  if ( refilled ) {
605  wmb();
606  rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
607  profile_start ( &intel_vm_refill_profiler );
608  writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
609  profile_stop ( &intel_vm_refill_profiler );
610  profile_exclude ( &intel_vm_refill_profiler );
611  }
612 }
void * regs
Registers.
Definition: intel.h:280
wmb()
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:149
uint64_t address
Base address.
Definition: ena.h:24
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:301
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
static void profile_stop(struct profiler *profiler)
Stop profiling.
Definition: profile.h:171
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
unsigned int cons
Consumer index.
Definition: intel.h:219
unsigned int reg
Register block.
Definition: intel.h:222
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:303
static void profile_start(struct profiler *profiler)
Start profiling.
Definition: profile.h:158
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
#define INTEL_RX_MAX_LEN
Receive buffer length.
Definition: intel.h:155
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:232
unsigned long physaddr_t
Definition: stdint.h:20
A packet descriptor.
Definition: intel.h:20
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:44
unsigned int prod
Producer index.
Definition: intel.h:217
#define INTEL_RX_FILL
Receive descriptor ring fill level.
Definition: intel.h:152
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
static void profile_exclude(struct profiler *profiler)
Exclude time from other ongoing profiling results.
Definition: profile.h:184
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
A persistent I/O buffer.
Definition: iobuf.h:32

References address, alloc_iob(), assert(), intel_ring::cons, io_buffer::data, DBGC2, intel_ring::desc, intel_ring::describe, INTEL_NUM_RX_DESC, INTEL_RX_FILL, INTEL_RX_MAX_LEN, INTEL_xDT, NULL, intel_ring::prod, profile_exclude(), profile_start(), profile_stop(), intel_ring::reg, intel_nic::regs, rx, intel_nic::rx, intel_nic::rx_iobuf, virt_to_bus(), wmb(), and writel().

Referenced by intel_open(), intel_poll(), intelx_open(), intelx_poll(), intelxvf_open(), and intelxvf_poll().

◆ intel_empty_rx()

void intel_empty_rx ( struct intel_nic intel)

Discard unused receive I/O buffers.

Parameters
intelIntel device

Definition at line 619 of file intel.c.

619  {
620  unsigned int i;
621 
622  for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
623  if ( intel->rx_iobuf[i] )
624  free_iob ( intel->rx_iobuf[i] );
625  intel->rx_iobuf[i] = NULL;
626  }
627 }
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:149
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:303
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References free_iob(), INTEL_NUM_RX_DESC, NULL, and intel_nic::rx_iobuf.

Referenced by intel_close(), intelx_close(), and intelxvf_close().

◆ intel_transmit()

int intel_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 740 of file intel.c.

740  {
741  struct intel_nic *intel = netdev->priv;
742  struct intel_descriptor *tx;
743  unsigned int tx_idx;
744  unsigned int tx_tail;
746  size_t len;
747 
748  /* Get next transmit descriptor */
749  if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
750  DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
751  return -ENOBUFS;
752  }
753  tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
754  tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
755  tx = &intel->tx.desc[tx_idx];
756 
757  /* Populate transmit descriptor */
758  address = virt_to_bus ( iobuf->data );
759  len = iob_len ( iobuf );
760  intel->tx.describe ( tx, address, len );
761  wmb();
762 
763  /* Notify card that there are packets ready to transmit */
764  profile_start ( &intel_vm_tx_profiler );
765  writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
766  profile_stop ( &intel_vm_tx_profiler );
767  profile_exclude ( &intel_vm_tx_profiler );
768 
769  DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
770  ( ( unsigned long long ) address ),
771  ( ( unsigned long long ) address + len ) );
772 
773  return 0;
774 }
void * regs
Registers.
Definition: intel.h:280
wmb()
#define INTEL_NUM_TX_DESC
Number of transmit descriptors.
Definition: intel.h:165
uint64_t address
Base address.
Definition: ena.h:24
#define DBGC(...)
Definition: compiler.h:505
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
static void profile_stop(struct profiler *profiler)
Stop profiling.
Definition: profile.h:171
unsigned int cons
Consumer index.
Definition: intel.h:219
unsigned int reg
Register block.
Definition: intel.h:222
#define INTEL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intel.h:168
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
void * priv
Driver private data.
Definition: netdevice.h:425
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
static void profile_start(struct profiler *profiler)
Start profiling.
Definition: profile.h:158
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:232
unsigned long physaddr_t
Definition: stdint.h:20
A packet descriptor.
Definition: intel.h:20
uint32_t len
Length.
Definition: ena.h:14
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:44
unsigned int prod
Producer index.
Definition: intel.h:217
An Intel network card.
Definition: intel.h:278
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:299
static void profile_exclude(struct profiler *profiler)
Exclude time from other ongoing profiling results.
Definition: profile.h:184

References address, intel_ring::cons, io_buffer::data, DBGC, DBGC2, intel_ring::desc, intel_ring::describe, ENOBUFS, INTEL_NUM_TX_DESC, INTEL_TX_FILL, INTEL_xDT, iob_len(), len, netdev, net_device::priv, intel_ring::prod, profile_exclude(), profile_start(), profile_stop(), intel_ring::reg, intel_nic::regs, tx, intel_nic::tx, virt_to_bus(), wmb(), and writel().

◆ intel_poll_tx()

void intel_poll_tx ( struct net_device netdev)

Poll for completed packets.

Parameters
netdevNetwork device

Definition at line 781 of file intel.c.

781  {
782  struct intel_nic *intel = netdev->priv;
783  struct intel_descriptor *tx;
784  unsigned int tx_idx;
785 
786  /* Check for completed packets */
787  while ( intel->tx.cons != intel->tx.prod ) {
788 
789  /* Get next transmit descriptor */
790  tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
791  tx = &intel->tx.desc[tx_idx];
792 
793  /* Stop if descriptor is still in use */
794  if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
795  return;
796 
797  DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
798 
799  /* Complete TX descriptor */
801  intel->tx.cons++;
802  }
803 }
#define INTEL_DESC_STATUS_DD
Descriptor done.
Definition: intel.h:50
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:758
#define INTEL_NUM_TX_DESC
Number of transmit descriptors.
Definition: intel.h:165
unsigned int cons
Consumer index.
Definition: intel.h:219
void * priv
Driver private data.
Definition: netdevice.h:425
static struct net_device * netdev
Definition: gdbudp.c:52
#define cpu_to_le32(value)
Definition: byteswap.h:107
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
A packet descriptor.
Definition: intel.h:20
#define DBGC2(...)
Definition: compiler.h:522
unsigned int prod
Producer index.
Definition: intel.h:217
An Intel network card.
Definition: intel.h:278
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:299

References intel_ring::cons, cpu_to_le32, DBGC2, intel_ring::desc, INTEL_DESC_STATUS_DD, INTEL_NUM_TX_DESC, netdev, netdev_tx_complete_next(), net_device::priv, intel_ring::prod, tx, and intel_nic::tx.

Referenced by intel_poll(), intelx_poll(), and intelxvf_poll().

◆ intel_poll_rx()

void intel_poll_rx ( struct net_device netdev)

Poll for received packets.

Parameters
netdevNetwork device

Definition at line 810 of file intel.c.

810  {
811  struct intel_nic *intel = netdev->priv;
812  struct intel_descriptor *rx;
813  struct io_buffer *iobuf;
814  unsigned int rx_idx;
815  size_t len;
816 
817  /* Check for received packets */
818  while ( intel->rx.cons != intel->rx.prod ) {
819 
820  /* Get next receive descriptor */
821  rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
822  rx = &intel->rx.desc[rx_idx];
823 
824  /* Stop if descriptor is still in use */
825  if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
826  return;
827 
828  /* Populate I/O buffer */
829  iobuf = intel->rx_iobuf[rx_idx];
830  intel->rx_iobuf[rx_idx] = NULL;
831  len = le16_to_cpu ( rx->length );
832  iob_put ( iobuf, len );
833 
834  /* Hand off to network stack */
835  if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
836  DBGC ( intel, "INTEL %p RX %d error (length %zd, "
837  "status %08x)\n", intel, rx_idx, len,
838  le32_to_cpu ( rx->status ) );
839  netdev_rx_err ( netdev, iobuf, -EIO );
840  } else {
841  DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
842  intel, rx_idx, len );
843  netdev_rx ( netdev, iobuf );
844  }
845  intel->rx.cons++;
846  }
847 }
#define INTEL_DESC_STATUS_DD
Descriptor done.
Definition: intel.h:50
#define iob_put(iobuf, len)
Definition: iobuf.h:116
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:149
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:501
#define le32_to_cpu(value)
Definition: byteswap.h:113
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:301
#define DBGC(...)
Definition: compiler.h:505
unsigned int cons
Consumer index.
Definition: intel.h:219
void * priv
Driver private data.
Definition: netdevice.h:425
static struct net_device * netdev
Definition: gdbudp.c:52
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:303
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define le16_to_cpu(value)
Definition: byteswap.h:112
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
A packet descriptor.
Definition: intel.h:20
uint32_t len
Length.
Definition: ena.h:14
#define DBGC2(...)
Definition: compiler.h:522
unsigned int prod
Producer index.
Definition: intel.h:217
#define EIO
Input/output error.
Definition: errno.h:433
An Intel network card.
Definition: intel.h:278
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
#define INTEL_DESC_STATUS_RXE
Receive error.
Definition: intel.h:53
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
A persistent I/O buffer.
Definition: iobuf.h:32

References intel_ring::cons, cpu_to_le32, DBGC, DBGC2, intel_ring::desc, EIO, INTEL_DESC_STATUS_DD, INTEL_DESC_STATUS_RXE, INTEL_NUM_RX_DESC, iob_put, le16_to_cpu, le32_to_cpu, len, netdev, netdev_rx(), netdev_rx_err(), NULL, net_device::priv, intel_ring::prod, rx, intel_nic::rx, and intel_nic::rx_iobuf.

Referenced by intel_poll(), intelx_poll(), and intelxvf_poll().

Variable Documentation

◆ address

uint64_t address

Buffer address.

Definition at line 12 of file intel.h.

◆ length

u16 length

◆ flags

uint8_t flags

Flags.

Definition at line 16 of file intel.h.

◆ command

◆ status

uint32_t status

Status.

Definition at line 20 of file intel.h.

◆ low

uint16_t low

◆ high

uint32_t high

◆ __attribute__

◆ count

unsigned int count

Definition at line 245 of file intel.h.

◆ reg

ring reg = reg

Definition at line 245 of file intel.h.

Referenced by __er32(), __ew32(), __gm_phy_read(), __mdio_read(), __mdio_write(), __vxge_hw_device_register_poll(), __xm_phy_read(), _efx_readl(), _efx_writel(), amd8111e_read_phy(), ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), ar9003_hw_drive_strength_apply(), ar9003_hw_prog_ini(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_write_rate_duration(), ath5k_setup_pwr_to_pdadc_table(), ath9k_hw_analog_shift_regwrite(), ath9k_hw_analog_shift_rmw(), ath9k_hw_check_alive(), ath9k_hw_setrxabort(), ath9k_hw_wait(), ath9k_init_band_txpower(), ath9k_regd_get_ctl(), ath_regd_get_band_ctl(), b44_phy_read(), b44_phy_write(), b44_wait_bit(), bcom_phy_init(), bflush(), bnx2_init_board(), bnx2_read_phy(), bnx2_reset_phy(), bnx2_write_phy(), bnxt_pci_base(), br32(), bw32(), efx_hunt_clear_interrupts(), efx_hunt_evq_read_ack(), efx_hunt_notify_rx_desc(), efx_hunt_notify_tx_desc(), efx_probe(), efx_readl(), efx_writel(), exanic_clear_base(), exanic_write_base(), falcon_clear_interrupts(), falcon_eventq_read_ack(), falcon_i2c_bit_read(), falcon_i2c_bit_write(), falcon_init_resources(), falcon_init_sram(), falcon_mask_status_intr(), falcon_mdio_read(), falcon_mdio_write(), falcon_notify_rx_desc(), falcon_notify_tx_desc(), falcon_pm8358_phy_init(), falcon_read(), falcon_read_sram(), falcon_readl(), falcon_reconfigure_mac_wrapper(), falcon_reconfigure_xmac(), falcon_reset_xaui(), falcon_reset_xmac(), falcon_setup_nic(), falcon_spi_rw(), falcon_spi_wait(), falcon_tenxpress_phy_init(), falcon_write(), falcon_write_sram(), falcon_writel(), falcon_xaui_link_ok(), falcon_xgmii_status(), forcedeth_map_regs(), genesis_reset(), genesis_stop(), gm_phy_read(), gm_phy_write(), gma_read16(), gma_read32(), gma_set_addr(), hfa384x_copy_from_bap(), hfa384x_docmd_wait(), hfa384x_getreg(), hfa384x_getreg_noswap(), hfa384x_prepare_bap(), hfa384x_setreg(), hfa384x_setreg_noswap(), hfa384x_wait_for_event(), icplus_mii_read_bit(), icplus_mii_write_bit(), intel_disable_ring(), intel_reset_ring(), is_yukon_lite_a0(), jme_mdio_read(), jme_mdio_write(), jread32(), jwrite32(), jwrite32f(), linda_ib_epb_mod_reg(), linda_set_serdes_param(), mdio_clause45_check_mmds(), mdio_read(), mdio_read_latched(), mdio_write(), mentormac_init(), mentormac_reset(), mii_bit_read(), mii_bit_rw(), mii_bit_write(), mii_read(), mii_rw(), mii_write(), natsemi_spi_read_bit(), natsemi_spi_write_bit(), pci_bar(), pci_bar_size(), pci_bar_start(), pci_read_bases(), pcnet32_mdio_read(), pcnet32_mdio_write(), phantom_crb_access_128m(), phantom_crb_access_2m(), phantom_crb_access_32m(), phantom_readl(), phantom_writel(), phy_init(), prism2_poll(), qib7322_ahb_mod_reg_all(), realtek_init_ring(), realtek_mii_read(), realtek_mii_write(), realtek_spi_read_bit(), realtek_spi_write_bit(), rhine_mii_read(), rhine_mii_write(), rtl818x_init_hw(), rtl818x_poll(), rtl818x_probe(), rtl818x_set_anaparam(), rtl818x_spi_read_bit(), rtl818x_spi_write_bit(), rtl818x_start(), rtl818x_stop(), rtl8225_read(), rtl8225_rf_set_tx_power(), rtl8225_rf_stop(), rtl8225_write(), sfe4001_init(), sis190_get_mac_addr(), sis190_get_mac_addr_from_apc(), sis190_mii_probe_88e1111_fixup(), sis190_read_eeprom(), sis190_set_rgmii(), sis630e_get_mac_addr(), skge_read16(), skge_read32(), skge_read8(), skge_reset(), skge_write16(), skge_write32(), skge_write8(), sky2_gmac_reset(), sky2_link_down(), sky2_link_up(), sky2_mac_init(), sky2_pci_read16(), sky2_pci_read32(), sky2_pci_write16(), sky2_pci_write32(), sky2_phy_init(), sky2_power_on(), sky2_read16(), sky2_read32(), sky2_read8(), sky2_set_multicast(), sky2_write16(), sky2_write32(), sky2_write8(), smscusb_mii_read(), smscusb_mii_write(), tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), tg3_phy_toggle_automdix(), tg3_phydsp_write(), tg3_readphy(), tg3_ump_link_report(), tg3_writephy(), TLan_MiiReadReg(), TLan_MiiWriteReg(), velocity_mii_read(), velocity_mii_write(), xhci_writeq(), xm_outaddr(), xm_outhash(), xm_phy_read(), xm_phy_write(), xm_read16(), xm_read32(), yukon_link_up(), and yukon_mac_init().

◆ describe

unsigned int unsigned int void( * describe) (struct intel_descriptor *desc, physaddr_t addr, size_t len))

Definition at line 246 of file intel.h.

246  {
247 
248  ring->len = ( count * sizeof ( ring->desc[0] ) );
249  ring->reg = reg;
250  ring->describe = describe;
251 }
252 
static unsigned int unsigned int void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len))
Definition: intel.h:246
static unsigned int count
Definition: intel.h:245
static unsigned int unsigned int reg
Definition: intel.h:245

◆ ctrl

uint32_t ctrl

◆ mem

mbox mem
Initial value:
{
mbox->ctrl = ctrl
Definition: golan.c:120
static unsigned int ctrl
Definition: intel.h:270

Definition at line 271 of file intel.h.

Referenced by ath5k_probe(), ath_pci_probe(), ath_pci_remove(), bzimage_parse_cmdline(), and ilog2().