iPXE
intel.c
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1 /*
2  * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  * You can also choose to distribute this program under the terms of
20  * the Unmodified Binary Distribution Licence (as given in the file
21  * COPYING.UBDL), provided that you have satisfied its requirements.
22  */
23 
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25 
26 #include <stdint.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include <errno.h>
30 #include <byteswap.h>
31 #include <ipxe/netdevice.h>
32 #include <ipxe/ethernet.h>
33 #include <ipxe/if_ether.h>
34 #include <ipxe/iobuf.h>
35 #include <ipxe/malloc.h>
36 #include <ipxe/pci.h>
37 #include <ipxe/profile.h>
38 #include "intel.h"
39 
40 /** @file
41  *
42  * Intel 10/100/1000 network card driver
43  *
44  */
45 
46 /** VM transmit profiler */
47 static struct profiler intel_vm_tx_profiler __profiler =
48  { .name = "intel.vm_tx" };
49 
50 /** VM receive refill profiler */
51 static struct profiler intel_vm_refill_profiler __profiler =
52  { .name = "intel.vm_refill" };
53 
54 /** VM poll profiler */
55 static struct profiler intel_vm_poll_profiler __profiler =
56  { .name = "intel.vm_poll" };
57 
58 /******************************************************************************
59  *
60  * EEPROM interface
61  *
62  ******************************************************************************
63  */
64 
65 /**
66  * Read data from EEPROM
67  *
68  * @v nvs NVS device
69  * @v address Address from which to read
70  * @v data Data buffer
71  * @v len Length of data buffer
72  * @ret rc Return status code
73  */
74 static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
75  void *data, size_t len ) {
76  struct intel_nic *intel =
77  container_of ( nvs, struct intel_nic, eeprom );
78  unsigned int i;
80  uint16_t *data_word = data;
81 
82  /* Sanity check. We advertise a blocksize of one word, so
83  * should only ever receive single-word requests.
84  */
85  assert ( len == sizeof ( *data_word ) );
86 
87  /* Initiate read */
88  writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
89  intel->regs + INTEL_EERD );
90 
91  /* Wait for read to complete */
92  for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
93 
94  /* If read is not complete, delay 1ms and retry */
95  value = readl ( intel->regs + INTEL_EERD );
96  if ( ! ( value & intel->eerd_done ) ) {
97  mdelay ( 1 );
98  continue;
99  }
100 
101  /* Extract data */
102  *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
103  return 0;
104  }
105 
106  DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
107  return -ETIMEDOUT;
108 }
109 
110 /**
111  * Write data to EEPROM
112  *
113  * @v nvs NVS device
114  * @v address Address to which to write
115  * @v data Data buffer
116  * @v len Length of data buffer
117  * @ret rc Return status code
118  */
119 static int intel_write_eeprom ( struct nvs_device *nvs,
120  unsigned int address __unused,
121  const void *data __unused,
122  size_t len __unused ) {
123  struct intel_nic *intel =
124  container_of ( nvs, struct intel_nic, eeprom );
125 
126  DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
127  return -ENOTSUP;
128 }
129 
130 /**
131  * Initialise EEPROM
132  *
133  * @v intel Intel device
134  * @ret rc Return status code
135  */
136 static int intel_init_eeprom ( struct intel_nic *intel ) {
137  unsigned int i;
138  uint32_t value;
139 
140  /* The NIC automatically detects the type of attached EEPROM.
141  * The EERD register provides access to only a single word at
142  * a time, so we pretend to have a single-word block size.
143  *
144  * The EEPROM size may be larger than the minimum size, but
145  * this doesn't matter to us since we access only the first
146  * few words.
147  */
150  intel->eeprom.block_size = 1;
151  intel->eeprom.read = intel_read_eeprom;
153 
154  /* The layout of the EERD register was changed at some point
155  * to accommodate larger EEPROMs. Read from address zero (for
156  * which the request layouts are compatible) to determine
157  * which type of register we have.
158  */
159  writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
160  for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
161  value = readl ( intel->regs + INTEL_EERD );
162  if ( value & INTEL_EERD_DONE_LARGE ) {
163  DBGC ( intel, "INTEL %p has large-format EERD\n",
164  intel );
167  return 0;
168  }
169  if ( value & INTEL_EERD_DONE_SMALL ) {
170  DBGC ( intel, "INTEL %p has small-format EERD\n",
171  intel );
174  return 0;
175  }
176  mdelay ( 1 );
177  }
178 
179  DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
180  "(value %08x)\n", intel, value );
181  return -ETIMEDOUT;
182 }
183 
184 /******************************************************************************
185  *
186  * MAC address
187  *
188  ******************************************************************************
189  */
190 
191 /**
192  * Fetch initial MAC address from EEPROM
193  *
194  * @v intel Intel device
195  * @v hw_addr Hardware address to fill in
196  * @ret rc Return status code
197  */
198 static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
199  uint8_t *hw_addr ) {
200  int rc;
201 
202  /* Initialise EEPROM */
203  if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
204  return rc;
205 
206  /* Read base MAC address from EEPROM */
207  if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
208  hw_addr, ETH_ALEN ) ) != 0 ) {
209  DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
210  "address: %s\n", intel, strerror ( rc ) );
211  return rc;
212  }
213 
214  /* Adjust MAC address for multi-port devices */
215  hw_addr[ETH_ALEN-1] ^= intel->port;
216 
217  DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
218  intel, eth_ntoa ( hw_addr ), intel->port );
219  return 0;
220 }
221 
222 /**
223  * Fetch initial MAC address
224  *
225  * @v intel Intel device
226  * @v hw_addr Hardware address to fill in
227  * @ret rc Return status code
228  */
229 static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
231  int rc;
232 
233  /* Read current address from RAL0/RAH0 */
234  mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
235  mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
236  DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
237  intel, eth_ntoa ( mac.raw ) );
238 
239  /* Use current address if valid */
240  if ( is_valid_ether_addr ( mac.raw ) ) {
241  memcpy ( hw_addr, mac.raw, ETH_ALEN );
242  return 0;
243  }
244 
245  /* Otherwise, try to read address from EEPROM */
246  if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
247  return 0;
248 
249  DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
250  return -ENOENT;
251 }
252 
253 /******************************************************************************
254  *
255  * Device reset
256  *
257  ******************************************************************************
258  */
259 
260 /**
261  * Reset hardware
262  *
263  * @v intel Intel device
264  * @ret rc Return status code
265  */
266 static int intel_reset ( struct intel_nic *intel ) {
267  uint32_t pbs;
268  uint32_t pba;
269  uint32_t ctrl;
271  uint32_t orig_ctrl;
272  uint32_t orig_status;
273 
274  /* Record initial control and status register values */
275  orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL );
276  orig_status = readl ( intel->regs + INTEL_STATUS );
277 
278  /* Force RX and TX packet buffer allocation, to work around an
279  * errata in ICH devices.
280  */
281  if ( intel->flags & INTEL_PBS_ERRATA ) {
282  DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
283  intel );
284  pbs = readl ( intel->regs + INTEL_PBS );
285  pba = readl ( intel->regs + INTEL_PBA );
286  writel ( 0x08, intel->regs + INTEL_PBA );
287  writel ( 0x10, intel->regs + INTEL_PBS );
288  DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
289  intel, pbs, readl ( intel->regs + INTEL_PBS ),
290  pba, readl ( intel->regs + INTEL_PBA ) );
291  }
292 
293  /* Always reset MAC. Required to reset the TX and RX rings. */
294  writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
296 
297  /* Set a sensible default configuration */
298  if ( ! ( intel->flags & INTEL_NO_ASDE ) )
300  ctrl |= INTEL_CTRL_SLU;
302  writel ( ctrl, intel->regs + INTEL_CTRL );
304 
305  /* On some models (notably ICH), the PHY reset mechanism
306  * appears to be broken. In particular, the PHY_CTRL register
307  * will be correctly loaded from NVM but the values will not
308  * be propagated to the "OEM bits" PHY register. This
309  * typically has the effect of dropping the link speed to
310  * 10Mbps.
311  *
312  * Work around this problem by skipping the PHY reset if
313  * either (a) the link is already up, or (b) this particular
314  * NIC is known to be broken.
315  */
316  status = readl ( intel->regs + INTEL_STATUS );
317  if ( ( intel->flags & INTEL_NO_PHY_RST ) ||
318  ( status & INTEL_STATUS_LU ) ) {
319  DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was "
320  "%08x/%08x)\n", intel,
321  ( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ),
322  ctrl, status, orig_ctrl, orig_status );
323  return 0;
324  }
325 
326  /* Reset PHY and MAC simultaneously */
328  intel->regs + INTEL_CTRL );
330 
331  /* PHY reset is not self-clearing on all models */
332  writel ( ctrl, intel->regs + INTEL_CTRL );
334  status = readl ( intel->regs + INTEL_STATUS );
335 
336  DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n",
337  intel, ctrl, status, orig_ctrl, orig_status );
338  return 0;
339 }
340 
341 /******************************************************************************
342  *
343  * Link state
344  *
345  ******************************************************************************
346  */
347 
348 /**
349  * Check link state
350  *
351  * @v netdev Network device
352  */
353 static void intel_check_link ( struct net_device *netdev ) {
354  struct intel_nic *intel = netdev->priv;
356 
357  /* Read link status */
358  status = readl ( intel->regs + INTEL_STATUS );
359  DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
360 
361  /* Update network device */
362  if ( status & INTEL_STATUS_LU ) {
364  } else {
366  }
367 }
368 
369 /******************************************************************************
370  *
371  * Descriptors
372  *
373  ******************************************************************************
374  */
375 
376 /**
377  * Populate transmit descriptor
378  *
379  * @v tx Transmit descriptor
380  * @v addr Data buffer address
381  * @v len Length of data
382  */
384  size_t len ) {
385 
386  /* Populate transmit descriptor */
387  tx->address = cpu_to_le64 ( addr );
388  tx->length = cpu_to_le16 ( len );
389  tx->flags = 0;
390  tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
392  tx->status = 0;
393 }
394 
395 /**
396  * Populate advanced transmit descriptor
397  *
398  * @v tx Transmit descriptor
399  * @v addr Data buffer address
400  * @v len Length of data
401  */
403  size_t len ) {
404 
405  /* Populate advanced transmit descriptor */
406  tx->address = cpu_to_le64 ( addr );
407  tx->length = cpu_to_le16 ( len );
408  tx->flags = INTEL_DESC_FL_DTYP_DATA;
409  tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
411  tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
412 }
413 
414 /**
415  * Populate receive descriptor
416  *
417  * @v rx Receive descriptor
418  * @v addr Data buffer address
419  * @v len Length of data
420  */
422  size_t len __unused ) {
423 
424  /* Populate transmit descriptor */
425  rx->address = cpu_to_le64 ( addr );
426  rx->length = 0;
427  rx->status = 0;
428 }
429 
430 /******************************************************************************
431  *
432  * Network device interface
433  *
434  ******************************************************************************
435  */
436 
437 /**
438  * Disable descriptor ring
439  *
440  * @v intel Intel device
441  * @v reg Register block
442  * @ret rc Return status code
443  */
444 static int intel_disable_ring ( struct intel_nic *intel, unsigned int reg ) {
445  uint32_t dctl;
446  unsigned int i;
447 
448  /* Disable ring */
449  writel ( 0, ( intel->regs + reg + INTEL_xDCTL ) );
450 
451  /* Wait for disable to complete */
452  for ( i = 0 ; i < INTEL_DISABLE_MAX_WAIT_MS ; i++ ) {
453 
454  /* Check if ring is disabled */
455  dctl = readl ( intel->regs + reg + INTEL_xDCTL );
456  if ( ! ( dctl & INTEL_xDCTL_ENABLE ) )
457  return 0;
458 
459  /* Delay */
460  mdelay ( 1 );
461  }
462 
463  DBGC ( intel, "INTEL %p ring %05x timed out waiting for disable "
464  "(dctl %08x)\n", intel, reg, dctl );
465  return -ETIMEDOUT;
466 }
467 
468 /**
469  * Reset descriptor ring
470  *
471  * @v intel Intel device
472  * @v reg Register block
473  * @ret rc Return status code
474  */
475 void intel_reset_ring ( struct intel_nic *intel, unsigned int reg ) {
476 
477  /* Disable ring. Ignore errors and continue to reset the ring anyway */
478  intel_disable_ring ( intel, reg );
479 
480  /* Clear ring length */
481  writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
482 
483  /* Clear ring address */
484  writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
485  writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
486 
487  /* Reset head and tail pointers */
488  writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
489  writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
490 }
491 
492 /**
493  * Create descriptor ring
494  *
495  * @v intel Intel device
496  * @v ring Descriptor ring
497  * @ret rc Return status code
498  */
499 int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
501  uint32_t dctl;
502 
503  /* Allocate descriptor ring. Align ring on its own size to
504  * prevent any possible page-crossing errors due to hardware
505  * errata.
506  */
507  ring->desc = malloc_dma ( ring->len, ring->len );
508  if ( ! ring->desc )
509  return -ENOMEM;
510 
511  /* Initialise descriptor ring */
512  memset ( ring->desc, 0, ring->len );
513 
514  /* Program ring address */
515  address = virt_to_bus ( ring->desc );
516  writel ( ( address & 0xffffffffUL ),
517  ( intel->regs + ring->reg + INTEL_xDBAL ) );
518  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
519  writel ( ( ( ( uint64_t ) address ) >> 32 ),
520  ( intel->regs + ring->reg + INTEL_xDBAH ) );
521  } else {
522  writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
523  }
524 
525  /* Program ring length */
526  writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
527 
528  /* Reset head and tail pointers */
529  writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
530  writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
531 
532  /* Enable ring */
533  dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
534  dctl |= INTEL_xDCTL_ENABLE;
535  writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
536 
537  DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
538  intel, ring->reg, ( ( unsigned long long ) address ),
539  ( ( unsigned long long ) address + ring->len ) );
540 
541  return 0;
542 }
543 
544 /**
545  * Destroy descriptor ring
546  *
547  * @v intel Intel device
548  * @v ring Descriptor ring
549  */
550 void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
551 
552  /* Reset ring */
553  intel_reset_ring ( intel, ring->reg );
554 
555  /* Free descriptor ring */
556  free_dma ( ring->desc, ring->len );
557  ring->desc = NULL;
558  ring->prod = 0;
559  ring->cons = 0;
560 }
561 
562 /**
563  * Refill receive descriptor ring
564  *
565  * @v intel Intel device
566  */
567 void intel_refill_rx ( struct intel_nic *intel ) {
568  struct intel_descriptor *rx;
569  struct io_buffer *iobuf;
570  unsigned int rx_idx;
571  unsigned int rx_tail;
573  unsigned int refilled = 0;
574 
575  /* Refill ring */
576  while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
577 
578  /* Allocate I/O buffer */
579  iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
580  if ( ! iobuf ) {
581  /* Wait for next refill */
582  break;
583  }
584 
585  /* Get next receive descriptor */
586  rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
587  rx = &intel->rx.desc[rx_idx];
588 
589  /* Populate receive descriptor */
590  address = virt_to_bus ( iobuf->data );
591  intel->rx.describe ( rx, address, 0 );
592 
593  /* Record I/O buffer */
594  assert ( intel->rx_iobuf[rx_idx] == NULL );
595  intel->rx_iobuf[rx_idx] = iobuf;
596 
597  DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
598  ( ( unsigned long long ) address ),
599  ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
600  refilled++;
601  }
602 
603  /* Push descriptors to card, if applicable */
604  if ( refilled ) {
605  wmb();
606  rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
607  profile_start ( &intel_vm_refill_profiler );
608  writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
609  profile_stop ( &intel_vm_refill_profiler );
610  profile_exclude ( &intel_vm_refill_profiler );
611  }
612 }
613 
614 /**
615  * Discard unused receive I/O buffers
616  *
617  * @v intel Intel device
618  */
619 void intel_empty_rx ( struct intel_nic *intel ) {
620  unsigned int i;
621 
622  for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
623  if ( intel->rx_iobuf[i] )
624  free_iob ( intel->rx_iobuf[i] );
625  intel->rx_iobuf[i] = NULL;
626  }
627 }
628 
629 /**
630  * Open network device
631  *
632  * @v netdev Network device
633  * @ret rc Return status code
634  */
635 static int intel_open ( struct net_device *netdev ) {
636  struct intel_nic *intel = netdev->priv;
638  uint32_t fextnvm11;
639  uint32_t tctl;
640  uint32_t rctl;
641  int rc;
642 
643  /* Set undocumented bit in FEXTNVM11 to work around an errata
644  * in i219 devices that will otherwise cause a complete
645  * datapath hang at the next device reset.
646  */
647  if ( intel->flags & INTEL_RST_HANG ) {
648  DBGC ( intel, "INTEL %p WARNING: applying reset hang "
649  "workaround\n", intel );
650  fextnvm11 = readl ( intel->regs + INTEL_FEXTNVM11 );
651  fextnvm11 |= INTEL_FEXTNVM11_WTF;
652  writel ( fextnvm11, intel->regs + INTEL_FEXTNVM11 );
653  }
654 
655  /* Create transmit descriptor ring */
656  if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
657  goto err_create_tx;
658 
659  /* Create receive descriptor ring */
660  if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
661  goto err_create_rx;
662 
663  /* Program MAC address */
664  memset ( &mac, 0, sizeof ( mac ) );
665  memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
666  writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
667  writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
668  intel->regs + INTEL_RAH0 );
669 
670  /* Enable transmitter */
671  tctl = readl ( intel->regs + INTEL_TCTL );
675  writel ( tctl, intel->regs + INTEL_TCTL );
676 
677  /* Enable receiver */
678  rctl = readl ( intel->regs + INTEL_RCTL );
679  rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
682  writel ( rctl, intel->regs + INTEL_RCTL );
683 
684  /* Fill receive ring */
685  intel_refill_rx ( intel );
686 
687  /* Update link state */
689 
690  /* Apply required errata */
691  if ( intel->flags & INTEL_VMWARE ) {
692  DBGC ( intel, "INTEL %p applying VMware errata workaround\n",
693  intel );
694  intel->force_icr = INTEL_IRQ_RXT0;
695  }
696 
697  return 0;
698 
699  intel_destroy_ring ( intel, &intel->rx );
700  err_create_rx:
701  intel_destroy_ring ( intel, &intel->tx );
702  err_create_tx:
703  return rc;
704 }
705 
706 /**
707  * Close network device
708  *
709  * @v netdev Network device
710  */
711 static void intel_close ( struct net_device *netdev ) {
712  struct intel_nic *intel = netdev->priv;
713 
714  /* Disable receiver */
715  writel ( 0, intel->regs + INTEL_RCTL );
716 
717  /* Disable transmitter */
718  writel ( 0, intel->regs + INTEL_TCTL );
719 
720  /* Destroy receive descriptor ring */
721  intel_destroy_ring ( intel, &intel->rx );
722 
723  /* Discard any unused receive buffers */
724  intel_empty_rx ( intel );
725 
726  /* Destroy transmit descriptor ring */
727  intel_destroy_ring ( intel, &intel->tx );
728 
729  /* Reset the NIC, to flush the transmit and receive FIFOs */
730  intel_reset ( intel );
731 }
732 
733 /**
734  * Transmit packet
735  *
736  * @v netdev Network device
737  * @v iobuf I/O buffer
738  * @ret rc Return status code
739  */
740 int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
741  struct intel_nic *intel = netdev->priv;
742  struct intel_descriptor *tx;
743  unsigned int tx_idx;
744  unsigned int tx_tail;
746  size_t len;
747 
748  /* Get next transmit descriptor */
749  if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
750  DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
751  return -ENOBUFS;
752  }
753  tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
754  tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
755  tx = &intel->tx.desc[tx_idx];
756 
757  /* Populate transmit descriptor */
758  address = virt_to_bus ( iobuf->data );
759  len = iob_len ( iobuf );
760  intel->tx.describe ( tx, address, len );
761  wmb();
762 
763  /* Notify card that there are packets ready to transmit */
764  profile_start ( &intel_vm_tx_profiler );
765  writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
766  profile_stop ( &intel_vm_tx_profiler );
767  profile_exclude ( &intel_vm_tx_profiler );
768 
769  DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
770  ( ( unsigned long long ) address ),
771  ( ( unsigned long long ) address + len ) );
772 
773  return 0;
774 }
775 
776 /**
777  * Poll for completed packets
778  *
779  * @v netdev Network device
780  */
781 void intel_poll_tx ( struct net_device *netdev ) {
782  struct intel_nic *intel = netdev->priv;
783  struct intel_descriptor *tx;
784  unsigned int tx_idx;
785 
786  /* Check for completed packets */
787  while ( intel->tx.cons != intel->tx.prod ) {
788 
789  /* Get next transmit descriptor */
790  tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
791  tx = &intel->tx.desc[tx_idx];
792 
793  /* Stop if descriptor is still in use */
794  if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
795  return;
796 
797  DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
798 
799  /* Complete TX descriptor */
801  intel->tx.cons++;
802  }
803 }
804 
805 /**
806  * Poll for received packets
807  *
808  * @v netdev Network device
809  */
810 void intel_poll_rx ( struct net_device *netdev ) {
811  struct intel_nic *intel = netdev->priv;
812  struct intel_descriptor *rx;
813  struct io_buffer *iobuf;
814  unsigned int rx_idx;
815  size_t len;
816 
817  /* Check for received packets */
818  while ( intel->rx.cons != intel->rx.prod ) {
819 
820  /* Get next receive descriptor */
821  rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
822  rx = &intel->rx.desc[rx_idx];
823 
824  /* Stop if descriptor is still in use */
825  if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
826  return;
827 
828  /* Populate I/O buffer */
829  iobuf = intel->rx_iobuf[rx_idx];
830  intel->rx_iobuf[rx_idx] = NULL;
831  len = le16_to_cpu ( rx->length );
832  iob_put ( iobuf, len );
833 
834  /* Hand off to network stack */
835  if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
836  DBGC ( intel, "INTEL %p RX %d error (length %zd, "
837  "status %08x)\n", intel, rx_idx, len,
838  le32_to_cpu ( rx->status ) );
839  netdev_rx_err ( netdev, iobuf, -EIO );
840  } else {
841  DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
842  intel, rx_idx, len );
843  netdev_rx ( netdev, iobuf );
844  }
845  intel->rx.cons++;
846  }
847 }
848 
849 /**
850  * Poll for completed and received packets
851  *
852  * @v netdev Network device
853  */
854 static void intel_poll ( struct net_device *netdev ) {
855  struct intel_nic *intel = netdev->priv;
856  uint32_t icr;
857 
858  /* Check for and acknowledge interrupts */
859  profile_start ( &intel_vm_poll_profiler );
860  icr = readl ( intel->regs + INTEL_ICR );
861  profile_stop ( &intel_vm_poll_profiler );
862  profile_exclude ( &intel_vm_poll_profiler );
863  icr |= intel->force_icr;
864  if ( ! icr )
865  return;
866 
867  /* Poll for TX completions, if applicable */
868  if ( icr & INTEL_IRQ_TXDW )
869  intel_poll_tx ( netdev );
870 
871  /* Poll for RX completions, if applicable */
872  if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
873  intel_poll_rx ( netdev );
874 
875  /* Report receive overruns */
876  if ( icr & INTEL_IRQ_RXO )
878 
879  /* Check link state, if applicable */
880  if ( icr & INTEL_IRQ_LSC )
882 
883  /* Check for unexpected interrupts */
884  if ( icr & ~( INTEL_IRQ_TXDW | INTEL_IRQ_TXQE | INTEL_IRQ_LSC |
886  DBGC ( intel, "INTEL %p unexpected ICR %08x\n", intel, icr );
887  /* Report as a TX error */
889  }
890 
891  /* Refill RX ring */
892  intel_refill_rx ( intel );
893 }
894 
895 /**
896  * Enable or disable interrupts
897  *
898  * @v netdev Network device
899  * @v enable Interrupts should be enabled
900  */
901 static void intel_irq ( struct net_device *netdev, int enable ) {
902  struct intel_nic *intel = netdev->priv;
903  uint32_t mask;
904 
906  if ( enable ) {
907  writel ( mask, intel->regs + INTEL_IMS );
908  } else {
909  writel ( mask, intel->regs + INTEL_IMC );
910  }
911 }
912 
913 /** Intel network device operations */
915  .open = intel_open,
916  .close = intel_close,
917  .transmit = intel_transmit,
918  .poll = intel_poll,
919  .irq = intel_irq,
920 };
921 
922 /******************************************************************************
923  *
924  * PCI interface
925  *
926  ******************************************************************************
927  */
928 
929 /**
930  * Probe PCI device
931  *
932  * @v pci PCI device
933  * @ret rc Return status code
934  */
935 static int intel_probe ( struct pci_device *pci ) {
936  struct net_device *netdev;
937  struct intel_nic *intel;
938  int rc;
939 
940  /* Allocate and initialise net device */
941  netdev = alloc_etherdev ( sizeof ( *intel ) );
942  if ( ! netdev ) {
943  rc = -ENOMEM;
944  goto err_alloc;
945  }
947  intel = netdev->priv;
948  pci_set_drvdata ( pci, netdev );
949  netdev->dev = &pci->dev;
950  memset ( intel, 0, sizeof ( *intel ) );
951  intel->port = PCI_FUNC ( pci->busdevfn );
952  intel->flags = pci->id->driver_data;
953  intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD,
955  intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD,
957 
958  /* Fix up PCI device */
959  adjust_pci_device ( pci );
960 
961  /* Map registers */
962  intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
963  if ( ! intel->regs ) {
964  rc = -ENODEV;
965  goto err_ioremap;
966  }
967 
968  /* Reset the NIC */
969  if ( ( rc = intel_reset ( intel ) ) != 0 )
970  goto err_reset;
971 
972  /* Fetch MAC address */
973  if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
974  goto err_fetch_mac;
975 
976  /* Register network device */
977  if ( ( rc = register_netdev ( netdev ) ) != 0 )
978  goto err_register_netdev;
979 
980  /* Set initial link state */
982 
983  return 0;
984 
986  err_register_netdev:
987  err_fetch_mac:
988  intel_reset ( intel );
989  err_reset:
990  iounmap ( intel->regs );
991  err_ioremap:
993  netdev_put ( netdev );
994  err_alloc:
995  return rc;
996 }
997 
998 /**
999  * Remove PCI device
1000  *
1001  * @v pci PCI device
1002  */
1003 static void intel_remove ( struct pci_device *pci ) {
1004  struct net_device *netdev = pci_get_drvdata ( pci );
1005  struct intel_nic *intel = netdev->priv;
1006 
1007  /* Unregister network device */
1009 
1010  /* Reset the NIC */
1011  intel_reset ( intel );
1012 
1013  /* Free network device */
1014  iounmap ( intel->regs );
1015  netdev_nullify ( netdev );
1016  netdev_put ( netdev );
1017 }
1018 
1019 /** Intel PCI device IDs */
1020 static struct pci_device_id intel_nics[] = {
1021  PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
1022  PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
1023  PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
1024  PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
1025  PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
1026  PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
1027  PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
1028  PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
1029  PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
1030  PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
1031  PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
1032  PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
1033  PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", INTEL_VMWARE ),
1034  PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
1035  PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
1036  PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
1037  PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
1038  PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
1039  PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
1040  PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
1041  PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
1042  PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
1043  PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
1044  PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
1045  PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
1046  PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
1047  PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
1048  PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
1049  PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
1050  PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
1051  PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
1052  PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
1053  PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
1054  PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
1055  PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
1056  PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
1057  PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
1058  PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
1059  PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
1060  PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
1061  PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
1062  PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
1063  PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
1064  PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
1065  PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
1066  PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
1067  PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
1068  PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
1069  PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
1070  PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
1071  PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
1072  PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
1073  PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
1074  PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
1075  PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
1076  PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
1077  PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
1078  PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
1079  PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
1080  PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
1081  PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
1082  PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
1083  PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
1084  PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
1085  PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
1086  PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
1087  PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
1088  PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
1089  PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
1090  PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
1091  PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
1092  PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
1093  PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
1094  PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
1095  PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
1096  PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
1097  PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
1098  PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
1099  PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
1100  PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
1101  PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
1102  PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
1103  PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
1104  PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
1105  PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
1106  PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
1107  PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
1108  PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
1109  PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
1110  PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
1111  PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
1112  PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
1113  PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
1114  PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
1115  PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", INTEL_NO_PHY_RST ),
1116  PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
1117  PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
1118  PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
1119  PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
1120  PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
1121  PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
1122  PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
1123  PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
1124  PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
1125  PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
1126  PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
1127  PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
1128  PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", INTEL_NO_ASDE ),
1129  PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
1130  PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
1131  PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
1132  PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
1133  PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
1134  PCI_ROM ( 0x8086, 0x1539, "i211", "I211", 0 ),
1135  PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", INTEL_NO_PHY_RST ),
1136  PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
1137  PCI_ROM ( 0x8086, 0x1559, "i218v", "I218-V", 0),
1138  PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218-LM", 0),
1139  PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", INTEL_I219 ),
1140  PCI_ROM ( 0x8086, 0x1570, "i219v", "I219-V", INTEL_I219 ),
1141  PCI_ROM ( 0x8086, 0x157b, "i210-2", "I210", 0 ),
1142  PCI_ROM ( 0x8086, 0x15a0, "i218lm-2", "I218-LM", INTEL_NO_PHY_RST ),
1143  PCI_ROM ( 0x8086, 0x15a1, "i218v-2", "I218-V", 0 ),
1144  PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", INTEL_NO_PHY_RST ),
1145  PCI_ROM ( 0x8086, 0x15a3, "i218v-3", "I218-V", INTEL_NO_PHY_RST ),
1146  PCI_ROM ( 0x8086, 0x15b7, "i219lm-2", "I219-LM (2)", INTEL_I219 ),
1147  PCI_ROM ( 0x8086, 0x15b8, "i219v-2", "I219-V (2)", INTEL_I219 ),
1148  PCI_ROM ( 0x8086, 0x15b9, "i219lm-3", "I219-LM (3)", INTEL_I219 ),
1149  PCI_ROM ( 0x8086, 0x15bb, "i219lm-7", "I219-LM (7)", INTEL_I219 ),
1150  PCI_ROM ( 0x8086, 0x15bc, "i219v-7", "I219-V (7)", INTEL_I219 ),
1151  PCI_ROM ( 0x8086, 0x15bd, "i219lm-6", "I219-LM (6)", INTEL_I219 ),
1152  PCI_ROM ( 0x8086, 0x15be, "i219v-6", "I219-V (6)", INTEL_I219 ),
1153  PCI_ROM ( 0x8086, 0x15d6, "i219v-5", "I219-V (5)", INTEL_I219 ),
1154  PCI_ROM ( 0x8086, 0x15d7, "i219lm-4", "I219-LM (4)", INTEL_I219 ),
1155  PCI_ROM ( 0x8086, 0x15d8, "i219v-4", "I219-V (4)", INTEL_I219 ),
1156  PCI_ROM ( 0x8086, 0x15df, "i219lm-8", "I219-LM (8)", INTEL_I219 ),
1157  PCI_ROM ( 0x8086, 0x15e0, "i219v-8", "I219-V (8)", INTEL_I219 ),
1158  PCI_ROM ( 0x8086, 0x15e1, "i219lm-9", "I219-LM (9)", INTEL_I219 ),
1159  PCI_ROM ( 0x8086, 0x15e2, "i219v-9", "I219-V (9)", INTEL_I219 ),
1160  PCI_ROM ( 0x8086, 0x15e3, "i219lm-5", "I219-LM (5)", INTEL_I219 ),
1161  PCI_ROM ( 0x8086, 0x1f41, "i354", "I354", INTEL_NO_ASDE ),
1162  PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
1163  PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
1164 };
1165 
1166 /** Intel PCI driver */
1167 struct pci_driver intel_driver __pci_driver = {
1168  .ids = intel_nics,
1169  .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
1170  .probe = intel_probe,
1171  .remove = intel_remove,
1172 };
unsigned int force_icr
Forced interrupts.
Definition: intel.h:286
void * regs
Registers.
Definition: intel.h:280
#define PCI_FUNC(busdevfn)
Definition: pci.h:258
PHY reset is broken.
Definition: intel.h:313
int(* write)(struct nvs_device *nvs, unsigned int address, const void *data, size_t len)
Write data to device.
Definition: nvs.h:59
unsigned long membase
Memory base.
Definition: pci.h:194
#define INTEL_RCTL_BSIZE_2048
Definition: intel.h:120
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
unsigned int word_len_log2
Word length.
Definition: nvs.h:22
#define INTEL_ICR
Interrupt Cause Read Register.
Definition: intel.h:97
#define INTEL_DESC_STATUS_DD
Descriptor done.
Definition: intel.h:50
#define iob_put(iobuf, len)
Definition: iobuf.h:116
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:149
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:501
#define INTEL_IRQ_RXDMT0
Receive queue low.
Definition: intel.h:101
#define INTEL_PBA
Packet Buffer Allocation.
Definition: intel.h:136
#define INTEL_EERD
EEPROM Read Register.
Definition: intel.h:76
void intel_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intel.c:810
A PCI driver.
Definition: pci.h:224
void intel_reset_ring(struct intel_nic *intel, unsigned int reg)
Reset descriptor ring.
Definition: intel.c:475
#define INTEL_DESC_STATUS_PAYLEN(len)
Payload length.
Definition: intel.h:56
static int intel_fetch_mac_eeprom(struct intel_nic *intel, uint8_t *hw_addr)
Fetch initial MAC address from EEPROM.
Definition: intel.c:198
ASDE is broken.
Definition: intel.h:315
static struct profiler intel_vm_tx_profiler __profiler
VM transmit profiler.
Definition: intel.c:47
#define INTEL_IRQ_RXT0
Receive timer.
Definition: intel.h:103
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
void netdev_tx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard transmitted packet.
Definition: netdevice.c:369
#define INTEL_EERD_DONE_SMALL
Read done (small EERD)
Definition: intel.h:78
Error codes.
static int intel_fetch_mac(struct intel_nic *intel, uint8_t *hw_addr)
Fetch initial MAC address.
Definition: intel.c:229
VMware missing interrupt workaround required.
Definition: intel.h:311
#define INTEL_xDCTL
Receive/Transmit Descriptor Control (offset)
Definition: intel.h:186
static int intel_open(struct net_device *netdev)
Open network device.
Definition: intel.c:635
#define INTEL_RD
Receive Descriptor register block.
Definition: intel.h:142
unsigned long driver_data
Arbitrary driver data.
Definition: pci.h:159
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:758
I/O buffers.
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
A non-volatile storage device.
Definition: nvs.h:15
#define INTEL_NUM_TX_DESC
Number of transmit descriptors.
Definition: intel.h:165
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:226
void intel_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intel.c:781
uint64_t address
Base address.
Definition: ena.h:24
static void intel_irq(struct net_device *netdev, int enable)
Enable or disable interrupts.
Definition: intel.c:901
#define INTEL_RCTL_BSIZE_BSEX_MASK
Definition: intel.h:121
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:301
#define INTEL_TCTL_EN
Transmit enable.
Definition: intel.h:126
#define DBGC(...)
Definition: compiler.h:505
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
int intel_create_ring(struct intel_nic *intel, struct intel_ring *ring)
Create descriptor ring.
Definition: intel.c:499
void intel_empty_rx(struct intel_nic *intel)
Discard unused receive I/O buffers.
Definition: intel.c:619
#define ENOENT
No such file or directory.
Definition: errno.h:514
size_t len
Length (in bytes)
Definition: intel.h:224
unsigned long long uint64_t
Definition: stdint.h:13
void intel_describe_tx(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate transmit descriptor.
Definition: intel.c:383
#define INTEL_PBS
Packet Buffer Size.
Definition: intel.h:139
#define cpu_to_le64(value)
Definition: byteswap.h:108
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
PBS/PBA errata workaround required.
Definition: intel.h:309
#define INTEL_IRQ_TXDW
Transmit descriptor done.
Definition: intel.h:98
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
A data structure for storing profiling information.
Definition: profile.h:26
An Intel descriptor ring.
Definition: intel.h:213
#define INTEL_BAR_SIZE
Intel BAR size.
Definition: intel.h:17
static void profile_stop(struct profiler *profiler)
Stop profiling.
Definition: profile.h:171
#define INTEL_DESC_FL_DTYP_DATA
Definition: intel.h:35
#define INTEL_RCTL_SECRC
Strip CRC.
Definition: intel.h:122
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
unsigned int cons
Consumer index.
Definition: intel.h:219
#define INTEL_xDLEN
Receive/Transmit Descriptor Length (offset)
Definition: intel.h:177
struct device dev
Generic device.
Definition: pci.h:189
unsigned int reg
Register block.
Definition: intel.h:222
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
void intel_refill_rx(struct intel_nic *intel)
Refill receive descriptor ring.
Definition: intel.c:567
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
Dynamic memory allocation.
eeprom
Definition: 3c90x.h:232
static void intel_check_link(struct net_device *netdev)
Check link state.
Definition: intel.c:353
uint8_t status
Status.
Definition: ena.h:16
unsigned int port
Port number (for multi-port devices)
Definition: intel.h:282
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:498
#define INTEL_CTRL_FRCDPLX
Force duplex.
Definition: intel.h:64
#define INTEL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intel.h:168
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:180
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:338
#define INTEL_TCTL_CT_MASK
Definition: intel.h:130
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define INTEL_xDBAL
Receive/Transmit Descriptor Base Address Low (offset)
Definition: intel.h:171
void * memcpy(void *dest, const void *src, size_t len) __nonnull
const char * name
Name.
Definition: profile.h:28
#define INTEL_FEXTNVM11
Future Extended NVM register 11.
Definition: intel.h:200
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
unsigned int block_size
Data block size (in words)
Definition: nvs.h:36
#define INTEL_EEPROM_MAC
Offset of MAC address within EEPROM.
Definition: intel.h:94
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:555
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
Ethernet protocol.
static int intel_reset(struct intel_nic *intel)
Reset hardware.
Definition: intel.c:266
#define INTEL_CTRL_ASDE
Auto-speed detection.
Definition: intel.h:61
void * priv
Driver private data.
Definition: netdevice.h:425
void intel_describe_rx(struct intel_descriptor *rx, physaddr_t addr, size_t len __unused)
Populate receive descriptor.
Definition: intel.c:421
#define INTEL_FEXTNVM11_WTF
Don't ask.
Definition: intel.h:201
#define INTEL_EERD_DATA(value)
Read data.
Definition: intel.h:82
Intel 10/100/1000 network card driver.
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:768
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTEL_CTRL_LRST
Link reset.
Definition: intel.h:60
uint32_t eerd_done
EEPROM done flag.
Definition: intel.h:291
#define INTEL_EEPROM_WORD_LEN_LOG2
EEPROM word length.
Definition: intel.h:88
static struct net_device * netdev
Definition: gdbudp.c:52
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:303
#define INTEL_EERD_ADDR_SHIFT_SMALL
Address shift (small)
Definition: intel.h:80
#define INTEL_IMS
Interrupt Mask Set/Read Register.
Definition: intel.h:106
static void profile_start(struct profiler *profiler)
Start profiling.
Definition: profile.h:158
Profiling.
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:844
#define INTEL_DESC_CMD_IFCS
Insert frame checksum (CRC)
Definition: intel.h:44
int(* read)(struct nvs_device *nvs, unsigned int address, void *data, size_t len)
Read data from device.
Definition: nvs.h:47
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define INTEL_CTRL_RST
Device reset.
Definition: intel.h:65
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
static int intel_probe(struct pci_device *pci)
Probe PCI device.
Definition: intel.c:935
static struct net_device_operations intel_operations
Intel network device operations.
Definition: intel.c:914
static void intel_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intel.c:854
static struct pci_device_id intel_nics[]
Intel PCI device IDs.
Definition: intel.c:1020
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
#define INTEL_I219
The i219 has a seriously broken reset mechanism.
Definition: intel.h:321
#define INTEL_STATUS_LU
Link up.
Definition: intel.h:73
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
static unsigned int unsigned int reg
Definition: intel.h:245
PCI bus.
A PCI device.
Definition: pci.h:187
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:667
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
A network device.
Definition: netdevice.h:348
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:511
u32 addr
Definition: sky2.h:8
unsigned char uint8_t
Definition: stdint.h:10
static int intel_write_eeprom(struct nvs_device *nvs, unsigned int address __unused, const void *data __unused, size_t len __unused)
Write data to EEPROM.
Definition: intel.c:119
#define INTEL_RX_MAX_LEN
Receive buffer length.
Definition: intel.h:155
#define INTEL_EEPROM_MAX_WAIT_MS
Maximum time to wait for EEPROM read, in milliseconds.
Definition: intel.h:85
#define ETH_ALEN
Definition: if_ether.h:8
#define INTEL_TCTL_CT_DEFAULT
Definition: intel.h:129
A PCI device ID list entry.
Definition: pci.h:151
#define INTEL_DISABLE_MAX_WAIT_MS
Maximum time to wait for queue disable, in milliseconds.
Definition: intel.h:190
struct pci_driver intel_driver __pci_driver
Intel PCI driver.
Definition: intel.c:1167
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define INTEL_RCTL_BAM
Broadcast accept mode.
Definition: intel.h:116
unsigned int uint32_t
Definition: stdint.h:12
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:232
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static void intel_remove(struct pci_device *pci)
Remove PCI device.
Definition: intel.c:1003
Network device operations.
Definition: netdevice.h:213
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
Network device management.
#define INTEL_CTRL
Device Control Register.
Definition: intel.h:59
unsigned long physaddr_t
Definition: stdint.h:20
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:348
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define INTEL_RCTL_UPE
Unicast promiscuous mode.
Definition: intel.h:114
#define INTEL_RCTL
Receive Control Register.
Definition: intel.h:112
uint32_t busdevfn
Segment, bus, device, and function (bus:dev.fn) number.
Definition: pci.h:210
A packet descriptor.
Definition: intel.h:20
#define INTEL_TCTL
Transmit Control Register.
Definition: intel.h:125
uint32_t len
Length.
Definition: ena.h:14
static unsigned int ctrl
Definition: intel.h:270
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
static int intel_disable_ring(struct intel_nic *intel, unsigned int reg)
Disable descriptor ring.
Definition: intel.c:444
#define DBGC2(...)
Definition: compiler.h:522
#define INTEL_CTRL_PHY_RST
PHY reset.
Definition: intel.h:66
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:237
#define INTEL_EERD_DONE_LARGE
Read done (large EERD)
Definition: intel.h:79
int intel_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intel.c:740
void * data
Start of data.
Definition: iobuf.h:44
#define INTEL_EERD_ADDR_SHIFT_LARGE
Address shift (large)
Definition: intel.h:81
unsigned int prod
Producer index.
Definition: intel.h:217
void intel_destroy_ring(struct intel_nic *intel, struct intel_ring *ring)
Destroy descriptor ring.
Definition: intel.c:550
#define INTEL_RESET_DELAY_MS
Time to delay for device reset, in milliseconds.
Definition: intel.h:69
#define EIO
Input/output error.
Definition: errno.h:433
#define INTEL_DESC_CMD_DEXT
Descriptor extension.
Definition: intel.h:38
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
#define INTEL_CTRL_SLU
Set link up.
Definition: intel.h:62
void intel_describe_tx_adv(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate advanced transmit descriptor.
Definition: intel.c:402
#define INTEL_DESC_CMD_EOP
End of packet.
Definition: intel.h:47
#define cpu_to_le16(value)
Definition: byteswap.h:106
An Intel network card.
Definition: intel.h:278
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define INTEL_RX_FILL
Receive descriptor ring fill level.
Definition: intel.h:152
#define INTEL_xDCTL_ENABLE
Queue enable.
Definition: intel.h:187
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
int nvs_read(struct nvs_device *nvs, unsigned int address, void *data, size_t len)
Read from non-volatile storage device.
Definition: nvs.c:75
static int intel_read_eeprom(struct nvs_device *nvs, unsigned int address, void *data, size_t len)
Read data from EEPROM.
Definition: intel.c:74
#define INTEL_TCTL_PSP
Pad short packets.
Definition: intel.h:127
static int intel_init_eeprom(struct intel_nic *intel)
Initialise EEPROM.
Definition: intel.c:136
#define INTEL_STATUS
Device Status Register.
Definition: intel.h:72
#define INTEL_EERD_START
Start read.
Definition: intel.h:77
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:299
Receive address.
Definition: intel.h:204
Reset may cause a complete device hang.
Definition: intel.h:317
#define INTEL_RCTL_EN
Receive enable.
Definition: intel.h:113
#define INTEL_RAH0_AV
Address valid.
Definition: intel.h:197
#define INTEL_IRQ_TXQE
Transmit queue empty.
Definition: intel.h:99
unsigned int eerd_addr_shift
EEPROM address shift.
Definition: intel.h:293
#define INTEL_DESC_STATUS_RXE
Receive error.
Definition: intel.h:53
#define INTEL_RAL0
Receive Address Low.
Definition: intel.h:193
#define INTEL_IRQ_LSC
Link status change.
Definition: intel.h:100
#define INTEL_EEPROM_MIN_SIZE_WORDS
Minimum EEPROM size, in words.
Definition: intel.h:91
#define INTEL_RAH0
Receive Address High.
Definition: intel.h:196
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
static void profile_exclude(struct profiler *profiler)
Exclude time from other ongoing profiling results.
Definition: profile.h:184
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:381
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
#define INTEL_TCTL_COLD_MASK
Definition: intel.h:133
#define INTEL_DESC_CMD_RS
Report status.
Definition: intel.h:41
#define INTEL_TCTL_COLD_DEFAULT
Definition: intel.h:132
unsigned int flags
Flags.
Definition: intel.h:284
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
static void intel_close(struct net_device *netdev)
Close network device.
Definition: intel.c:711
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:375
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct nvs_device eeprom
EEPROM.
Definition: intel.h:289
#define INTEL_xDBAH
Receive/Transmit Descriptor Base Address High (offset)
Definition: intel.h:174
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
String functions.
#define INTEL_IMC
Interrupt Mask Clear Register.
Definition: intel.h:109
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define INTEL_RCTL_MPE
Multicast promiscuous.
Definition: intel.h:115
unsigned int size
Device size (in words)
Definition: nvs.h:24
#define INTEL_IRQ_RXO
Receive overrun.
Definition: intel.h:102
#define INTEL_TD
Transmit Descriptor register block.
Definition: intel.h:158
#define INTEL_CTRL_FRCSPD
Force speed.
Definition: intel.h:63
void * memset(void *dest, int character, size_t len) __nonnull
A persistent I/O buffer.
Definition: iobuf.h:32