iPXE
mac.h
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef MAC_H
21 #define MAC_H
22 
23 FILE_LICENCE ( BSD2 );
24 
25 #include <unistd.h>
26 
27 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
28  MS(ads->ds_rxstatus0, AR_RxRate) : \
29  (ads->ds_rxstatus3 >> 2) & 0xFF)
30 
31 #define set11nTries(_series, _index) \
32  (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
33 
34 #define set11nRate(_series, _index) \
35  (SM((_series)[_index].Rate, AR_XmitRate##_index))
36 
37 #define set11nPktDurRTSCTS(_series, _index) \
38  (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
39  ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
40  AR_RTSCTSQual##_index : 0))
41 
42 #define set11nRateFlags(_series, _index) \
43  (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
44  AR_2040_##_index : 0) \
45  |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
46  AR_GI##_index : 0) \
47  |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
48  AR_STBC##_index : 0) \
49  |SM((_series)[_index].ChSel, AR_ChainSel##_index))
50 
51 #define CCK_SIFS_TIME 10
52 #define CCK_PREAMBLE_BITS 144
53 #define CCK_PLCP_BITS 48
54 
55 #define OFDM_SIFS_TIME 16
56 #define OFDM_PREAMBLE_TIME 20
57 #define OFDM_PLCP_BITS 22
58 #define OFDM_SYMBOL_TIME 4
59 
60 #define OFDM_SIFS_TIME_HALF 32
61 #define OFDM_PREAMBLE_TIME_HALF 40
62 #define OFDM_PLCP_BITS_HALF 22
63 #define OFDM_SYMBOL_TIME_HALF 8
64 
65 #define OFDM_SIFS_TIME_QUARTER 64
66 #define OFDM_PREAMBLE_TIME_QUARTER 80
67 #define OFDM_PLCP_BITS_QUARTER 22
68 #define OFDM_SYMBOL_TIME_QUARTER 16
69 
70 #define INIT_AIFS 2
71 #define INIT_CWMIN 15
72 #define INIT_CWMIN_11B 31
73 #define INIT_CWMAX 1023
74 #define INIT_SH_RETRY 10
75 #define INIT_LG_RETRY 10
76 #define INIT_SSH_RETRY 32
77 #define INIT_SLG_RETRY 32
78 
79 #define ATH9K_SLOT_TIME_6 6
80 #define ATH9K_SLOT_TIME_9 9
81 #define ATH9K_SLOT_TIME_20 20
82 
83 #define ATH9K_TXERR_XRETRY 0x01
84 #define ATH9K_TXERR_FILT 0x02
85 #define ATH9K_TXERR_FIFO 0x04
86 #define ATH9K_TXERR_XTXOP 0x08
87 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
88 #define ATH9K_TX_ACKED 0x20
89 #define ATH9K_TXERR_MASK \
90  (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
91  ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
92 
93 #define ATH9K_TX_BA 0x01
94 #define ATH9K_TX_PWRMGMT 0x02
95 #define ATH9K_TX_DESC_CFG_ERR 0x04
96 #define ATH9K_TX_DATA_UNDERRUN 0x08
97 #define ATH9K_TX_DELIM_UNDERRUN 0x10
98 #define ATH9K_TX_SW_FILTERED 0x80
99 
100 /* 64 bytes */
101 #define MIN_TX_FIFO_THRESHOLD 0x1
102 
103 /*
104  * Single stream device AR9285 and AR9271 require 2 KB
105  * to work around a hardware issue, all other devices
106  * have can use the max 4 KB limit.
107  */
108 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
109 
134 };
135 
161 };
162 
187 };
188 
189 #define ATH9K_RXERR_CRC 0x01
190 #define ATH9K_RXERR_PHY 0x02
191 #define ATH9K_RXERR_FIFO 0x04
192 #define ATH9K_RXERR_DECRYPT 0x08
193 #define ATH9K_RXERR_MIC 0x10
194 
195 #define ATH9K_RX_MORE 0x01
196 #define ATH9K_RX_MORE_AGGR 0x02
197 #define ATH9K_RX_GI 0x04
198 #define ATH9K_RX_2040 0x08
199 #define ATH9K_RX_DELIM_CRC_PRE 0x10
200 #define ATH9K_RX_DELIM_CRC_POST 0x20
201 #define ATH9K_RX_DECRYPT_BUSY 0x40
202 
203 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
204 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
205 
207  ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
208  ATH9K_PHYERR_TIMING = 1, /* Timing error */
209  ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
210  ATH9K_PHYERR_RATE = 3, /* Illegal rate */
211  ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
212  ATH9K_PHYERR_RADAR = 5, /* Radar detect */
213  ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
214  ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
215 
224 
232 
236 
238 };
239 
240 struct ath_desc {
245  u32 ds_hw[20];
246 // void *ds_vdata;
247 } __attribute__((packed, aligned(4)));
248 
249 #define ATH9K_TXDESC_NOACK 0x0002
250 #define ATH9K_TXDESC_RTSENA 0x0004
251 #define ATH9K_TXDESC_CTSENA 0x0008
252 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
253  * the descriptor its marked on. We take a tx interrupt to reap
254  * descriptors when the h/w hits an EOL condition or
255  * when the descriptor is specifically marked to generate
256  * an interrupt with this flag. Descriptors should be
257  * marked periodically to insure timely replenishing of the
258  * supply needed for sending frames. Defering interrupts
259  * reduces system load and potentially allows more concurrent
260  * work to be done but if done to aggressively can cause
261  * senders to backup. When the hardware queue is left too
262  * large rate control information may also be too out of
263  * date. An Alternative for this is TX interrupt mitigation
264  * but this needs more testing. */
265 #define ATH9K_TXDESC_INTREQ 0x0010
266 #define ATH9K_TXDESC_VEOL 0x0020
267 #define ATH9K_TXDESC_EXT_ONLY 0x0040
268 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
269 #define ATH9K_TXDESC_VMF 0x0100
270 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
271 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400
272 #define ATH9K_TXDESC_LDPC 0x00010000
273 
274 #define ATH9K_RXDESC_INTREQ 0x0020
275 
276 struct ar5416_desc {
281  union {
282  struct {
303  } tx;
304  struct {
305  u32 status0;
306  u32 status1;
307  u32 status2;
308  u32 status3;
309  u32 status4;
310  u32 status5;
311  u32 status6;
312  u32 status7;
313  u32 status8;
314  } rx;
315  } u;
316 } __attribute__((packed, aligned(4)));
317 
318 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
319 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
320 
321 #define ds_ctl2 u.tx.ctl2
322 #define ds_ctl3 u.tx.ctl3
323 #define ds_ctl4 u.tx.ctl4
324 #define ds_ctl5 u.tx.ctl5
325 #define ds_ctl6 u.tx.ctl6
326 #define ds_ctl7 u.tx.ctl7
327 #define ds_ctl8 u.tx.ctl8
328 #define ds_ctl9 u.tx.ctl9
329 #define ds_ctl10 u.tx.ctl10
330 #define ds_ctl11 u.tx.ctl11
331 
332 #define ds_txstatus0 u.tx.status0
333 #define ds_txstatus1 u.tx.status1
334 #define ds_txstatus2 u.tx.status2
335 #define ds_txstatus3 u.tx.status3
336 #define ds_txstatus4 u.tx.status4
337 #define ds_txstatus5 u.tx.status5
338 #define ds_txstatus6 u.tx.status6
339 #define ds_txstatus7 u.tx.status7
340 #define ds_txstatus8 u.tx.status8
341 #define ds_txstatus9 u.tx.status9
342 
343 #define ds_rxstatus0 u.rx.status0
344 #define ds_rxstatus1 u.rx.status1
345 #define ds_rxstatus2 u.rx.status2
346 #define ds_rxstatus3 u.rx.status3
347 #define ds_rxstatus4 u.rx.status4
348 #define ds_rxstatus5 u.rx.status5
349 #define ds_rxstatus6 u.rx.status6
350 #define ds_rxstatus7 u.rx.status7
351 #define ds_rxstatus8 u.rx.status8
352 
353 #define AR_FrameLen 0x00000fff
354 #define AR_VirtMoreFrag 0x00001000
355 #define AR_TxCtlRsvd00 0x0000e000
356 #define AR_XmitPower 0x003f0000
357 #define AR_XmitPower_S 16
358 #define AR_RTSEnable 0x00400000
359 #define AR_VEOL 0x00800000
360 #define AR_ClrDestMask 0x01000000
361 #define AR_TxCtlRsvd01 0x1e000000
362 #define AR_TxIntrReq 0x20000000
363 #define AR_DestIdxValid 0x40000000
364 #define AR_CTSEnable 0x80000000
365 
366 #define AR_TxMore 0x00001000
367 #define AR_DestIdx 0x000fe000
368 #define AR_DestIdx_S 13
369 #define AR_FrameType 0x00f00000
370 #define AR_FrameType_S 20
371 #define AR_NoAck 0x01000000
372 #define AR_InsertTS 0x02000000
373 #define AR_CorruptFCS 0x04000000
374 #define AR_ExtOnly 0x08000000
375 #define AR_ExtAndCtl 0x10000000
376 #define AR_MoreAggr 0x20000000
377 #define AR_IsAggr 0x40000000
378 
379 #define AR_BurstDur 0x00007fff
380 #define AR_BurstDur_S 0
381 #define AR_DurUpdateEna 0x00008000
382 #define AR_XmitDataTries0 0x000f0000
383 #define AR_XmitDataTries0_S 16
384 #define AR_XmitDataTries1 0x00f00000
385 #define AR_XmitDataTries1_S 20
386 #define AR_XmitDataTries2 0x0f000000
387 #define AR_XmitDataTries2_S 24
388 #define AR_XmitDataTries3 0xf0000000
389 #define AR_XmitDataTries3_S 28
390 
391 #define AR_XmitRate0 0x000000ff
392 #define AR_XmitRate0_S 0
393 #define AR_XmitRate1 0x0000ff00
394 #define AR_XmitRate1_S 8
395 #define AR_XmitRate2 0x00ff0000
396 #define AR_XmitRate2_S 16
397 #define AR_XmitRate3 0xff000000
398 #define AR_XmitRate3_S 24
399 
400 #define AR_PacketDur0 0x00007fff
401 #define AR_PacketDur0_S 0
402 #define AR_RTSCTSQual0 0x00008000
403 #define AR_PacketDur1 0x7fff0000
404 #define AR_PacketDur1_S 16
405 #define AR_RTSCTSQual1 0x80000000
406 
407 #define AR_PacketDur2 0x00007fff
408 #define AR_PacketDur2_S 0
409 #define AR_RTSCTSQual2 0x00008000
410 #define AR_PacketDur3 0x7fff0000
411 #define AR_PacketDur3_S 16
412 #define AR_RTSCTSQual3 0x80000000
413 
414 #define AR_AggrLen 0x0000ffff
415 #define AR_AggrLen_S 0
416 #define AR_TxCtlRsvd60 0x00030000
417 #define AR_PadDelim 0x03fc0000
418 #define AR_PadDelim_S 18
419 #define AR_EncrType 0x0c000000
420 #define AR_EncrType_S 26
421 #define AR_TxCtlRsvd61 0xf0000000
422 #define AR_LDPC 0x80000000
423 
424 #define AR_2040_0 0x00000001
425 #define AR_GI0 0x00000002
426 #define AR_ChainSel0 0x0000001c
427 #define AR_ChainSel0_S 2
428 #define AR_2040_1 0x00000020
429 #define AR_GI1 0x00000040
430 #define AR_ChainSel1 0x00000380
431 #define AR_ChainSel1_S 7
432 #define AR_2040_2 0x00000400
433 #define AR_GI2 0x00000800
434 #define AR_ChainSel2 0x00007000
435 #define AR_ChainSel2_S 12
436 #define AR_2040_3 0x00008000
437 #define AR_GI3 0x00010000
438 #define AR_ChainSel3 0x000e0000
439 #define AR_ChainSel3_S 17
440 #define AR_RTSCTSRate 0x0ff00000
441 #define AR_RTSCTSRate_S 20
442 #define AR_STBC0 0x10000000
443 #define AR_STBC1 0x20000000
444 #define AR_STBC2 0x40000000
445 #define AR_STBC3 0x80000000
446 
447 #define AR_TxRSSIAnt00 0x000000ff
448 #define AR_TxRSSIAnt00_S 0
449 #define AR_TxRSSIAnt01 0x0000ff00
450 #define AR_TxRSSIAnt01_S 8
451 #define AR_TxRSSIAnt02 0x00ff0000
452 #define AR_TxRSSIAnt02_S 16
453 #define AR_TxStatusRsvd00 0x3f000000
454 #define AR_TxBaStatus 0x40000000
455 #define AR_TxStatusRsvd01 0x80000000
456 
457 /*
458  * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
459  * transmitted successfully. If clear, no ACK or BA was received to indicate
460  * successful transmission when we were expecting an ACK or BA.
461  */
462 #define AR_FrmXmitOK 0x00000001
463 #define AR_ExcessiveRetries 0x00000002
464 #define AR_FIFOUnderrun 0x00000004
465 #define AR_Filtered 0x00000008
466 #define AR_RTSFailCnt 0x000000f0
467 #define AR_RTSFailCnt_S 4
468 #define AR_DataFailCnt 0x00000f00
469 #define AR_DataFailCnt_S 8
470 #define AR_VirtRetryCnt 0x0000f000
471 #define AR_VirtRetryCnt_S 12
472 #define AR_TxDelimUnderrun 0x00010000
473 #define AR_TxDataUnderrun 0x00020000
474 #define AR_DescCfgErr 0x00040000
475 #define AR_TxTimerExpired 0x00080000
476 #define AR_TxStatusRsvd10 0xfff00000
477 
478 #define AR_SendTimestamp ds_txstatus2
479 #define AR_BaBitmapLow ds_txstatus3
480 #define AR_BaBitmapHigh ds_txstatus4
481 
482 #define AR_TxRSSIAnt10 0x000000ff
483 #define AR_TxRSSIAnt10_S 0
484 #define AR_TxRSSIAnt11 0x0000ff00
485 #define AR_TxRSSIAnt11_S 8
486 #define AR_TxRSSIAnt12 0x00ff0000
487 #define AR_TxRSSIAnt12_S 16
488 #define AR_TxRSSICombined 0xff000000
489 #define AR_TxRSSICombined_S 24
490 
491 #define AR_TxTid 0xf0000000
492 #define AR_TxTid_S 28
493 
494 #define AR_TxEVM0 ds_txstatus5
495 #define AR_TxEVM1 ds_txstatus6
496 #define AR_TxEVM2 ds_txstatus7
497 
498 #define AR_TxDone 0x00000001
499 #define AR_SeqNum 0x00001ffe
500 #define AR_SeqNum_S 1
501 #define AR_TxStatusRsvd80 0x0001e000
502 #define AR_TxOpExceeded 0x00020000
503 #define AR_TxStatusRsvd81 0x001c0000
504 #define AR_FinalTxIdx 0x00600000
505 #define AR_FinalTxIdx_S 21
506 #define AR_TxStatusRsvd82 0x01800000
507 #define AR_PowerMgmt 0x02000000
508 #define AR_TxStatusRsvd83 0xfc000000
509 
510 #define AR_RxCTLRsvd00 0xffffffff
511 
512 #define AR_RxCtlRsvd00 0x00001000
513 #define AR_RxIntrReq 0x00002000
514 #define AR_RxCtlRsvd01 0xffffc000
515 
516 #define AR_RxRSSIAnt00 0x000000ff
517 #define AR_RxRSSIAnt00_S 0
518 #define AR_RxRSSIAnt01 0x0000ff00
519 #define AR_RxRSSIAnt01_S 8
520 #define AR_RxRSSIAnt02 0x00ff0000
521 #define AR_RxRSSIAnt02_S 16
522 #define AR_RxRate 0xff000000
523 #define AR_RxRate_S 24
524 #define AR_RxStatusRsvd00 0xff000000
525 
526 #define AR_DataLen 0x00000fff
527 #define AR_RxMore 0x00001000
528 #define AR_NumDelim 0x003fc000
529 #define AR_NumDelim_S 14
530 #define AR_RxStatusRsvd10 0xff800000
531 
532 #define AR_RcvTimestamp ds_rxstatus2
533 
534 #define AR_GI 0x00000001
535 #define AR_2040 0x00000002
536 #define AR_Parallel40 0x00000004
537 #define AR_Parallel40_S 2
538 #define AR_RxStatusRsvd30 0x000000f8
539 #define AR_RxAntenna 0xffffff00
540 #define AR_RxAntenna_S 8
541 
542 #define AR_RxRSSIAnt10 0x000000ff
543 #define AR_RxRSSIAnt10_S 0
544 #define AR_RxRSSIAnt11 0x0000ff00
545 #define AR_RxRSSIAnt11_S 8
546 #define AR_RxRSSIAnt12 0x00ff0000
547 #define AR_RxRSSIAnt12_S 16
548 #define AR_RxRSSICombined 0xff000000
549 #define AR_RxRSSICombined_S 24
550 
551 #define AR_RxEVM0 ds_rxstatus4
552 #define AR_RxEVM1 ds_rxstatus5
553 #define AR_RxEVM2 ds_rxstatus6
554 
555 #define AR_RxDone 0x00000001
556 #define AR_RxFrameOK 0x00000002
557 #define AR_CRCErr 0x00000004
558 #define AR_DecryptCRCErr 0x00000008
559 #define AR_PHYErr 0x00000010
560 #define AR_MichaelErr 0x00000020
561 #define AR_PreDelimCRCErr 0x00000040
562 #define AR_RxStatusRsvd70 0x00000080
563 #define AR_RxKeyIdxValid 0x00000100
564 #define AR_KeyIdx 0x0000fe00
565 #define AR_KeyIdx_S 9
566 #define AR_PHYErrCode 0x0000ff00
567 #define AR_PHYErrCode_S 8
568 #define AR_RxMoreAggr 0x00010000
569 #define AR_RxAggr 0x00020000
570 #define AR_PostDelimCRCErr 0x00040000
571 #define AR_RxStatusRsvd71 0x3ff80000
572 #define AR_DecryptBusyErr 0x40000000
573 #define AR_KeyMiss 0x80000000
574 
578 };
579 
580 #define ATH9K_NUM_TX_QUEUES 1
581 
582 /* Used as a queue subtype instead of a WMM AC */
583 #define ATH9K_WME_UPSD 4
584 
595 };
596 
597 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
598 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
599 
600 #define ATH9K_DECOMP_MASK_SIZE 128
601 #define ATH9K_READY_TIME_LO_BOUND 50
602 #define ATH9K_READY_TIME_HI_BOUND 96
603 
612 };
613 
631 };
632 
634  ATH9K_RX_FILTER_UCAST = 0x00000001,
635  ATH9K_RX_FILTER_MCAST = 0x00000002,
636  ATH9K_RX_FILTER_BCAST = 0x00000004,
639  ATH9K_RX_FILTER_PROM = 0x00000020,
649 };
650 
651 #define ATH9K_RATESERIES_RTS_CTS 0x0001
652 #define ATH9K_RATESERIES_2040 0x0002
653 #define ATH9K_RATESERIES_HALFGI 0x0004
654 #define ATH9K_RATESERIES_STBC 0x0008
655 
662 };
663 
669 };
670 
671 struct ath_hw;
672 struct ath9k_channel;
673 
674 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
675 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
676 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
677 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
679 int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel);
680 int ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
681 void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
682 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
683 int ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
684  const struct ath9k_tx_queue_info *qinfo);
685 int ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
686  struct ath9k_tx_queue_info *qinfo);
688  const struct ath9k_tx_queue_info *qinfo);
689 int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
690 int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
691 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
692  struct ath_rx_status *rs, u64 tsf);
693 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
694  u32 size, u32 flags);
695 int ath9k_hw_setrxabort(struct ath_hw *ah, int set);
696 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
697 void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning);
698 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
699 int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset);
700 
701 /* Interrupt Handling */
702 int ath9k_hw_intrpend(struct ath_hw *ah);
703 void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints);
704 void ath9k_hw_enable_interrupts(struct ath_hw *ah);
706 
707 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
708 
709 #endif /* MAC_H */
u8 ts_flags
Definition: mac.h:119
u8 ts_longretry
Definition: mac.h:117
u32 ctl4
Definition: mac.h:285
uint16_t u16
Definition: stdint.h:21
#define __attribute__(x)
Definition: compiler.h:10
u8 rs_moreaggr
Definition: mac.h:153
int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, struct ath_rx_status *rs, u64 tsf)
Definition: ath9k_mac.c:394
void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:55
int8_t ts_rssi_ext1
Definition: mac.h:124
int8_t rs_rssi_ext0
Definition: mac.h:149
ath9k_tx_queue
Definition: mac.h:575
unsigned short uint16_t
Definition: stdint.h:11
u32 ds_ctl0
Definition: mac.h:279
Definition: hw.h:656
u8 rs_more
Definition: mac.h:145
u32 ctl7
Definition: mac.h:288
u8 rs_flags
Definition: mac.h:155
u32 ds_link
Definition: mac.h:241
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo)
Definition: ath9k_mac.c:216
u32 evm0
Definition: mac.h:131
u32 ctl9
Definition: mac.h:290
int8_t rs_rssi_ctl0
Definition: mac.h:146
int8_t ts_rssi_ctl1
Definition: mac.h:121
int8_t ts_rssi
Definition: mac.h:115
u32 tqi_intFlags
Definition: mac.h:630
u32 rs_tstamp
Definition: mac.h:137
u32 tqi_priority
Definition: mac.h:619
u8 rs_rate
Definition: mac.h:143
u8 ts_status
Definition: mac.h:113
int8_t rs_rssi_ctl2
Definition: mac.h:171
uint8_t type
Type.
Definition: ena.h:16
int ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo)
Definition: ath9k_mac.c:162
int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:259
int ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
u32 status7
Definition: mac.h:300
unsigned long long uint64_t
Definition: stdint.h:13
u32 ctl11
Definition: mac.h:292
int8_t rs_rssi_ext1
Definition: mac.h:150
u16 ts_seqnum
Definition: mac.h:112
void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
Definition: ath9k_mac.c:129
u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
u32 status0
Definition: mac.h:293
int8_t rs_rssi_ext1
Definition: mac.h:173
Definition: mac.h:240
int8_t rs_rssi_ctl0
Definition: mac.h:169
FILE_LICENCE(BSD2)
int8_t rs_rssi_ext2
Definition: mac.h:151
u32 ds_data
Definition: mac.h:242
u32 ds_link
Definition: mac.h:277
u32 status3
Definition: mac.h:296
u32 ds_ctl0
Definition: mac.h:243
u8 ts_rateindex
Definition: mac.h:114
u16 rs_datalen
Definition: mac.h:138
u8 tid
Definition: mac.h:128
void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning)
Definition: ath9k_mac.c:524
int ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo)
u32 ctl5
Definition: mac.h:286
u32 ds_hw[20]
Definition: mac.h:245
u8 rs_antenna
Definition: mac.h:144
ath9k_key_type
Definition: mac.h:664
enum ath9k_tx_queue_flags tqi_qflags
Definition: mac.h:618
int8_t ts_rssi_ext0
Definition: mac.h:123
uint32_t evm1
Definition: mac.h:185
u32 evm4
Definition: mac.h:160
u32 tqi_cbrPeriod
Definition: mac.h:625
int8_t ts_rssi_ctl0
Definition: mac.h:120
uint64_t u64
Definition: stdint.h:25
int8_t rs_rssi_ext2
Definition: mac.h:174
uint16_t rs_datalen
Definition: mac.h:165
u32 ds_ctl1
Definition: mac.h:280
u8 rs_status
Definition: mac.h:139
signed char int8_t
Definition: stdint.h:15
u32 ba_high
Definition: mac.h:130
void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
u32 tqi_readyTime
Definition: mac.h:628
u8 rs_num_delims
Definition: mac.h:181
u32 evm3
Definition: mac.h:159
ath9k_tx_queue_flags
Definition: mac.h:585
u32 status1
Definition: mac.h:294
u32 tqi_cbrOverflowLimit
Definition: mac.h:626
int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:283
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags)
u8 ts_shortretry
Definition: mac.h:116
int8_t rs_rssi_ext0
Definition: mac.h:172
u32 evm2
Definition: mac.h:133
u32 ctl10
Definition: mac.h:291
u32 status4
Definition: mac.h:297
u32 status6
Definition: mac.h:299
u32 ts_tstamp
Definition: mac.h:111
u32 ctl6
Definition: mac.h:287
u8 rs_num_delims
Definition: mac.h:154
void ath9k_hw_enable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:616
u32 evm2
Definition: mac.h:158
ath9k_rx_filter
Definition: mac.h:633
int8_t rs_rssi
Definition: mac.h:141
Definition: sis900.h:30
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:62
unsigned int uint32_t
Definition: stdint.h:12
u32 tqi_physCompBuf
Definition: mac.h:629
u32 status8
Definition: mac.h:301
int8_t rs_rssi
Definition: mac.h:168
int ath9k_hw_setrxabort(struct ath_hw *ah, int set)
Definition: ath9k_mac.c:490
u8 rs_keyix
Definition: mac.h:142
uint32_t ds
Definition: librm.h:254
void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
Definition: ath9k_mac.c:641
void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
Definition: ath9k_mac.c:156
u32 ctl2
Definition: mac.h:283
static fd_set * set
Definition: posix_io.h:48
int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
Definition: ath9k_mac.c:101
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
u32 status5
Definition: mac.h:298
struct ar5416_desc::@32::@34 rx
ath9k_phyerr
Definition: mac.h:206
int8_t ts_rssi_ext2
Definition: mac.h:125
u32 evm0
Definition: mac.h:156
uint64_t rs_tstamp
Definition: mac.h:164
uint32_t evm0
Definition: mac.h:184
enum ath9k_tx_queue tqi_type
Definition: mac.h:616
u32 evm1
Definition: mac.h:157
u32 evm1
Definition: mac.h:132
u8 rs_isaggr
Definition: mac.h:152
u32 ctl8
Definition: mac.h:289
u32 ctl3
Definition: mac.h:284
int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset)
Definition: ath9k_mac.c:536
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
int8_t rs_rssi_ctl1
Definition: mac.h:147
Definition: sis900.h:32
void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
uint8_t ah
Definition: registers.h:85
int8_t rs_rssi_ctl1
Definition: mac.h:170
u8 qid
Definition: mac.h:126
int8_t ts_rssi_ctl2
Definition: mac.h:122
void ath9k_hw_abortpcurecv(struct ath_hw *ah)
Definition: ath9k_mac.c:531
u32 tqi_burstTime
Definition: mac.h:627
struct ar5416_desc::@32::@33 tx
ath9k_pkt_type
Definition: mac.h:604
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
Definition: ath9k_mac.c:519
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
Definition: ath9k_mac.c:50
int ath9k_hw_intrpend(struct ath_hw *ah)
Definition: ath9k_mac.c:583
u32 ds_data
Definition: mac.h:278
u32 status2
Definition: mac.h:295
int8_t rs_rssi_ctl2
Definition: mac.h:148
union ar5416_desc::@32 u
u32 ba_low
Definition: mac.h:129
uint8_t u8
Definition: stdint.h:19
u8 ts_virtcol
Definition: mac.h:118
u32 ds_ctl1
Definition: mac.h:244
uint32_t u32
Definition: stdint.h:23
uint32_t evm2
Definition: mac.h:186
u8 rs_moreaggr
Definition: mac.h:180
u16 desc_id
Definition: mac.h:127
u32 status9
Definition: mac.h:302
u8 rs_phyerr
Definition: mac.h:140
uint8_t flags
Flags.
Definition: ena.h:18