iPXE
ath9k_mac.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/io.h>
21 
22 #include "hw.h"
23 #include "hw-ops.h"
24 
26  struct ath9k_tx_queue_info *qi __unused)
27 {
28  DBG2("ath9k: "
29  "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
30  ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
31  ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
32  ah->txurn_interrupt_mask);
33 
35 
37  SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
38  | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
40  SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
41  | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
42 
43  ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
44  ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
45  REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
46 
48 }
49 
51 {
52  REG_WRITE(ah, AR_QTXDP(q), txdp);
53 }
54 
55 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
56 {
57  DBG2("ath9k: "
58  "Enable TXE on queue: %d\n", q);
59  REG_WRITE(ah, AR_Q_TXE, 1 << q);
60 }
61 
63 {
64  u32 npend;
65 
66  npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
67  if (npend == 0) {
68 
69  if (REG_READ(ah, AR_Q_TXE) & (1 << q))
70  npend = 1;
71  }
72 
73  return npend;
74 }
75 
76 /**
77  * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
78  *
79  * @ah: atheros hardware struct
80  * @bIncTrigLevel: whether or not the frame trigger level should be updated
81  *
82  * The frame trigger level specifies the minimum number of bytes,
83  * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
84  * before the PCU will initiate sending the frame on the air. This can
85  * mean we initiate transmit before a full frame is on the PCU TX FIFO.
86  * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
87  * first)
88  *
89  * Caution must be taken to ensure to set the frame trigger level based
90  * on the DMA request size. For example if the DMA request size is set to
91  * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
92  * there need to be enough space in the tx FIFO for the requested transfer
93  * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
94  * the threshold to a value beyond 6, then the transmit will hang.
95  *
96  * Current dual stream devices have a PCU TX FIFO size of 8 KB.
97  * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
98  * there is a hardware issue which forces us to use 2 KB instead so the
99  * frame trigger level must not exceed 2 KB for these chipsets.
100  */
101 int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
102 {
103  u32 txcfg, curLevel, newLevel;
104 
105  if (ah->tx_trig_level >= ah->config.max_txtrig_level)
106  return 0;
107 
109 
111  curLevel = MS(txcfg, AR_FTRIG);
112  newLevel = curLevel;
113  if (bIncTrigLevel) {
114  if (curLevel < ah->config.max_txtrig_level)
115  newLevel++;
116  } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
117  newLevel--;
118  if (newLevel != curLevel)
120  (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
121 
123 
124  ah->tx_trig_level = newLevel;
125 
126  return newLevel != curLevel;
127 }
128 
130 {
131  int i, q;
132 
134 
138 
139  for (q = 0; q < AR_NUM_QCU; q++) {
140  for (i = 0; i < 1000; i++) {
141  if (i)
142  udelay(5);
143 
144  if (!ath9k_hw_numtxpending(ah, q))
145  break;
146  }
147  }
148 
152 
153  REG_WRITE(ah, AR_Q_TXD, 0);
154 }
155 
156 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
157 {
158  *txqs &= ah->intr_txqs;
159  ah->intr_txqs &= ~(*txqs);
160 }
161 
162 int ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
163  const struct ath9k_tx_queue_info *qinfo)
164 {
165  u32 cw;
166  struct ath9k_tx_queue_info *qi;
167 
168  qi = &ah->txq[q];
169  if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
170  DBG("ath9k: "
171  "Set TXQ properties, inactive queue: %d\n", q);
172  return 0;
173  }
174 
175  DBG2("ath9k: Set queue properties for: %d\n", q);
176 
177  qi->tqi_ver = qinfo->tqi_ver;
178  qi->tqi_subtype = qinfo->tqi_subtype;
179  qi->tqi_qflags = qinfo->tqi_qflags;
180  qi->tqi_priority = qinfo->tqi_priority;
181  if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
182  qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
183  else
184  qi->tqi_aifs = INIT_AIFS;
185  if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
186  cw = min(qinfo->tqi_cwmin, 1024U);
187  qi->tqi_cwmin = 1;
188  while (qi->tqi_cwmin < cw)
189  qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
190  } else
191  qi->tqi_cwmin = qinfo->tqi_cwmin;
192  if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
193  cw = min(qinfo->tqi_cwmax, 1024U);
194  qi->tqi_cwmax = 1;
195  while (qi->tqi_cwmax < cw)
196  qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
197  } else
198  qi->tqi_cwmax = INIT_CWMAX;
199 
200  if (qinfo->tqi_shretry != 0)
201  qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
202  else
204  if (qinfo->tqi_lgretry != 0)
205  qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
206  else
208  qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
210  qi->tqi_burstTime = qinfo->tqi_burstTime;
211  qi->tqi_readyTime = qinfo->tqi_readyTime;
212 
213  return 1;
214 }
215 
217  const struct ath9k_tx_queue_info *qinfo)
218 {
219  struct ath9k_tx_queue_info *qi;
220  int q;
221 
222  for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
223  if (ah->txq[q].tqi_type ==
225  break;
226  if (q == ATH9K_NUM_TX_QUEUES) {
227  DBG("No available TX queue\n");
228  return -1;
229  }
230 
231  DBG2("ath9K: Setup TX queue: %d\n", q);
232 
233  qi = &ah->txq[q];
234  if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
235  DBG("ath9k: TX queue: %d already active\n", q);
236  return -1;
237  }
238  memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
239  qi->tqi_type = type;
240  if (qinfo == NULL) {
241  qi->tqi_qflags =
245  qi->tqi_aifs = INIT_AIFS;
247  qi->tqi_cwmax = INIT_CWMAX;
250  qi->tqi_physCompBuf = 0;
251  } else {
252  qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
253  (void) ath9k_hw_set_txq_props(ah, q, qinfo);
254  }
255 
256  return q;
257 }
258 
260 {
261  struct ath9k_tx_queue_info *qi;
262 
263  qi = &ah->txq[q];
264  if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
265  DBG("ath9k: "
266  "Release TXQ, inactive queue: %d\n", q);
267  return 0;
268  }
269 
270  DBG2("ath9k: Release TX queue: %d\n", q);
271 
273  ah->txok_interrupt_mask &= ~(1 << q);
274  ah->txerr_interrupt_mask &= ~(1 << q);
275  ah->txdesc_interrupt_mask &= ~(1 << q);
276  ah->txeol_interrupt_mask &= ~(1 << q);
277  ah->txurn_interrupt_mask &= ~(1 << q);
279 
280  return 1;
281 }
282 
284 {
285  struct ath9k_channel *chan = ah->curchan;
286  struct ath9k_tx_queue_info *qi;
287  u32 cwMin, chanCwMin, value __unused;
288 
289  qi = &ah->txq[q];
290  if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
291  DBG("ath9k: "
292  "Reset TXQ, inactive queue: %d\n", q);
293  return 1;
294  }
295 
296  DBG2("ath9k: Reset TX queue: %d\n", q);
297 
298  if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
299  if (chan && IS_CHAN_B(chan))
300  chanCwMin = INIT_CWMIN_11B;
301  else
302  chanCwMin = INIT_CWMIN;
303 
304  for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
305  } else
306  cwMin = qi->tqi_cwmin;
307 
309 
311  SM(cwMin, AR_D_LCL_IFS_CWMIN) |
314 
319 
321 
322  if (AR_SREV_9340(ah))
323  REG_WRITE(ah, AR_DMISC(q),
325  else
326  REG_WRITE(ah, AR_DMISC(q),
328 
329  if (qi->tqi_cbrPeriod) {
330  REG_WRITE(ah, AR_QCBRCFG(q),
334  (qi->tqi_cbrOverflowLimit ?
336  }
337  if (qi->tqi_readyTime) {
341  }
342 
345  (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
346 
347  if (qi->tqi_burstTime
350 
353 
355 
358 
360  REG_SET_BIT(ah, AR_DMISC(q),
364  }
365 
368 
370  ah->txok_interrupt_mask |= 1 << q;
371  else
372  ah->txok_interrupt_mask &= ~(1 << q);
374  ah->txerr_interrupt_mask |= 1 << q;
375  else
376  ah->txerr_interrupt_mask &= ~(1 << q);
378  ah->txdesc_interrupt_mask |= 1 << q;
379  else
380  ah->txdesc_interrupt_mask &= ~(1 << q);
382  ah->txeol_interrupt_mask |= 1 << q;
383  else
384  ah->txeol_interrupt_mask &= ~(1 << q);
386  ah->txurn_interrupt_mask |= 1 << q;
387  else
388  ah->txurn_interrupt_mask &= ~(1 << q);
390 
391  return 1;
392 }
393 
394 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
395  struct ath_rx_status *rs, u64 tsf __unused)
396 {
397  struct ar5416_desc ads;
398  struct ar5416_desc *adsp = AR5416DESC(ds);
399  u32 phyerr;
400 
401  if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
402  return -EINPROGRESS;
403 
404  ads.u.rx = adsp->u.rx;
405 
406  rs->rs_status = 0;
407  rs->rs_flags = 0;
408 
409  rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
410  rs->rs_tstamp = ads.AR_RcvTimestamp;
411 
412  if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
413  rs->rs_rssi = ATH9K_RSSI_BAD;
420  } else {
421  rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
422  rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
424  rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
426  rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
428  rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
430  rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
432  rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
434  }
435  if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
436  rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
437  else
439 
440  rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
441  rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
442 
443  rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
444  rs->rs_moreaggr =
445  (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
446  rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
447  rs->rs_flags =
448  (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
449  rs->rs_flags |=
450  (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
451 
452  if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
454  if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
456  if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
458 
459  if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
460  /*
461  * Treat these errors as mutually exclusive to avoid spurious
462  * extra error reports from the hardware. If a CRC error is
463  * reported, then decryption and MIC errors are irrelevant,
464  * the frame is going to be dropped either way
465  */
466  if (ads.ds_rxstatus8 & AR_CRCErr)
467  rs->rs_status |= ATH9K_RXERR_CRC;
468  else if (ads.ds_rxstatus8 & AR_PHYErr) {
469  rs->rs_status |= ATH9K_RXERR_PHY;
470  phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
471  rs->rs_phyerr = phyerr;
472  } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
474  else if (ads.ds_rxstatus8 & AR_MichaelErr)
475  rs->rs_status |= ATH9K_RXERR_MIC;
476  else if (ads.ds_rxstatus8 & AR_KeyMiss)
478  }
479 
480  return 0;
481 }
482 
483 /*
484  * This can stop or re-enables RX.
485  *
486  * If bool is set this will kill any frame which is currently being
487  * transferred between the MAC and baseband and also prevent any new
488  * frames from getting started.
489  */
490 int ath9k_hw_setrxabort(struct ath_hw *ah, int set)
491 {
492  u32 reg;
493 
494  if (set) {
497 
499  0, AH_WAIT_TIMEOUT)) {
501  (AR_DIAG_RX_DIS |
503 
505  DBG("ath9k: "
506  "RX failed to go idle in 10 ms RXSM=0x%x\n",
507  reg);
508 
509  return 0;
510  }
511  } else {
514  }
515 
516  return 1;
517 }
518 
520 {
522 }
523 
524 void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning)
525 {
526  ath9k_ani_reset(ah, is_scanning);
527 
529 }
530 
532 {
534 }
535 
536 int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset)
537 {
538 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
539  u32 mac_status, last_mac_status = 0;
540  int i;
541 
542  /* Enable access to the DMA observation bus */
547 
549 
550  /* Wait for rx enable bit to go low */
551  for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
552  if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
553  break;
554 
556  mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
557  if (mac_status == 0x1c0 && mac_status == last_mac_status) {
558  *reset = 1;
559  break;
560  }
561 
562  last_mac_status = mac_status;
563  }
564 
566  }
567 
568  if (i == 0) {
569  DBG("ath9k: "
570  "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
571  AH_RX_STOP_DMA_TIMEOUT / 1000,
572  REG_READ(ah, AR_CR),
575  return 0;
576  } else {
577  return 1;
578  }
579 
580 #undef AH_RX_STOP_DMA_TIMEOUT
581 }
582 
584 {
585  u32 host_isr;
586 
587  if (AR_SREV_9100(ah) || !(ah->ah_ier & AR_IER_ENABLE))
588  return 1;
589 
590  host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
591  if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
592  return 1;
593 
594  host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
595  if ((host_isr & AR_INTR_SYNC_DEFAULT)
596  && (host_isr != AR_INTR_SPURIOUS))
597  return 1;
598 
599  return 0;
600 }
601 
603 {
604  DBG2("ath9k: disable IER\n");
605  REG_WRITE(ah, AR_IER, ah->ah_ier);
606  (void) REG_READ(ah, AR_IER);
607  if (!AR_SREV_9100(ah)) {
610 
613  }
614 }
615 
617 {
618  u32 sync_default = AR_INTR_SYNC_DEFAULT;
619 
620  if (!(ah->imask & ATH9K_INT_GLOBAL))
621  return;
622 
623  if (AR_SREV_9340(ah))
624  sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
625 
626  DBG2("ath9k: enable IER\n");
627  REG_WRITE(ah, AR_IER, ah->ah_ier);
628  if (!AR_SREV_9100(ah)) {
632 
633 
634  REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
635  REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
636  }
637  DBG2("ath9k: AR_IMR 0x%x IER 0x%x\n",
639 }
640 
641 void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
642 {
643  enum ath9k_int omask = ah->imask;
644  u32 mask, mask2;
645  struct ath9k_hw_capabilities *pCap = &ah->caps;
646 
647  if (!(ints & ATH9K_INT_GLOBAL))
649 
650  DBG2("ath9k: 0x%x => 0x%x\n", omask, ints);
651 
652  /* TODO: global int Ref count */
653  mask = ints & ATH9K_INT_COMMON;
654  mask2 = 0;
655 
656  if (ints & ATH9K_INT_TX) {
657  if (ah->config.tx_intr_mitigation)
658  mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
659  else {
660  if (ah->txok_interrupt_mask)
661  mask |= AR_IMR_TXOK;
662  if (ah->txdesc_interrupt_mask)
663  mask |= AR_IMR_TXDESC;
664  }
665  if (ah->txerr_interrupt_mask)
666  mask |= AR_IMR_TXERR;
667  if (ah->txeol_interrupt_mask)
668  mask |= AR_IMR_TXEOL;
669  }
670  if (ints & ATH9K_INT_RX) {
672  mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
673  if (ah->config.rx_intr_mitigation) {
674  mask &= ~AR_IMR_RXOK_LP;
675  mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
676  } else {
677  mask |= AR_IMR_RXOK_LP;
678  }
679  } else {
680  if (ah->config.rx_intr_mitigation)
681  mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
682  else
683  mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
684  }
685  if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
686  mask |= AR_IMR_GENTMR;
687  }
688 
689  if (ints & ATH9K_INT_GENTIMER)
690  mask |= AR_IMR_GENTMR;
691 
692  if (ints & (ATH9K_INT_BMISC)) {
693  mask |= AR_IMR_BCNMISC;
694  if (ints & ATH9K_INT_TIM)
695  mask2 |= AR_IMR_S2_TIM;
696  if (ints & ATH9K_INT_DTIM)
697  mask2 |= AR_IMR_S2_DTIM;
698  if (ints & ATH9K_INT_DTIMSYNC)
699  mask2 |= AR_IMR_S2_DTIMSYNC;
700  if (ints & ATH9K_INT_CABEND)
701  mask2 |= AR_IMR_S2_CABEND;
702  if (ints & ATH9K_INT_TSFOOR)
703  mask2 |= AR_IMR_S2_TSFOOR;
704  }
705 
706  if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
707  mask |= AR_IMR_BCNMISC;
708  if (ints & ATH9K_INT_GTT)
709  mask2 |= AR_IMR_S2_GTT;
710  if (ints & ATH9K_INT_CST)
711  mask2 |= AR_IMR_S2_CST;
712  }
713 
714  DBG2("ath9k: new IMR 0x%x\n", mask);
715  REG_WRITE(ah, AR_IMR, mask);
716  ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
719  ah->imrs2_reg |= mask2;
720  REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
721 
722  if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
723  if (ints & ATH9K_INT_TIM_TIMER)
725  else
727  }
728 
729  if (ints & ATH9K_INT_GLOBAL)
731 
732  return;
733 }
#define AR_CR_RXE
Definition: reg.h:25
#define AR_DMISC(_i)
Definition: reg.h:577
int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:283
u8 rs_moreaggr
Definition: mac.h:153
#define AR_QCBRCFG(_i)
Definition: reg.h:402
#define ATH9K_RX_DELIM_CRC_PRE
Definition: mac.h:199
#define AR_IMR_S2_CABEND
Definition: reg.h:312
int8_t rs_rssi_ext0
Definition: mac.h:149
ath9k_tx_queue
Definition: mac.h:575
iPXE I/O API
#define AR_DIAG_RX_ABORT
Definition: reg.h:1524
Definition: hw.h:656
int ath9k_hw_setrxabort(struct ath_hw *ah, int set)
Definition: ath9k_mac.c:490
#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS
Definition: mac.h:598
#define AR_GI
Definition: mac.h:534
#define AR_QMISC(_i)
Definition: reg.h:441
u8 rs_more
Definition: mac.h:145
#define AR_IMR_S2_TIM
Definition: reg.h:311
#define AR_RxRSSIAnt01
Definition: mac.h:518
#define AR_DRETRY_LIMIT(_i)
Definition: reg.h:542
void ath9k_hw_enable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:616
#define AR_RxRSSIAnt02
Definition: mac.h:520
#define AR_D_LCL_IFS_CWMIN
Definition: reg.h:523
u8 rs_flags
Definition: mac.h:155
#define AR_INTR_ASYNC_CAUSE
Definition: reg.h:975
#define AR_OBS_BUS_1
Definition: reg.h:1558
#define AR_D_MISC_FRAG_BKOFF_EN
Definition: reg.h:582
#define AR_D_RETRY_LIMIT_STA_SH
Definition: reg.h:545
#define AR_IMR_S2_QCU_TXURN
Definition: reg.h:307
#define AR_FTRIG
Definition: reg.h:89
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
Definition: reg.h:593
#define AR_IMR_RXMINTR
Definition: reg.h:290
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
#define AR_IMR_RXOK_HP
Definition: reg.h:261
int8_t rs_rssi_ctl0
Definition: mac.h:146
#define ATH9K_RXERR_MIC
Definition: mac.h:193
#define AR_QTXDP(_i)
Definition: reg.h:381
u32 tqi_intFlags
Definition: mac.h:630
u32 rs_tstamp
Definition: mac.h:137
#define AR_MACMISC_MISC_OBS_BUS_1
Definition: reg.h:147
u32 tqi_priority
Definition: mac.h:619
int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset)
Definition: ath9k_mac.c:536
void ath9k_ani_reset(struct ath_hw *ah, int is_scanning)
Definition: ath9k_ani.c:466
#define MS(_v, _f)
Definition: hw.h:102
#define AR_OBS_BUS_1_RX_STATE
Definition: reg.h:1573
u8 rs_rate
Definition: mac.h:143
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:62
uint8_t type
Type.
Definition: ena.h:16
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_IMR_TXERR
Definition: reg.h:269
#define AR_Q_TXD_M
Definition: reg.h:390
#define AR_IER
Definition: reg.h:54
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_2040
Definition: mac.h:535
#define AR_RxDone
Definition: mac.h:555
#define AR_Q_TXD
Definition: reg.h:389
#define AR_RXDP
Definition: reg.h:29
#define ATH9K_RXERR_CRC
Definition: mac.h:189
#define AR_IMR_RXDESC
Definition: reg.h:260
ath9k_int
Definition: hw.h:251
#define min(x, y)
Definition: ath.h:34
#define AR_PHYErrCode
Definition: mac.h:566
#define AR_IMR_GENTMR
Definition: reg.h:287
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
Definition: ath9k_mac.c:50
#define AR_D_LCL_IFS_CWMAX
Definition: reg.h:525
int8_t rs_rssi_ext1
Definition: mac.h:150
void ath9k_hw_abortpcurecv(struct ath_hw *ah)
Definition: ath9k_mac.c:531
#define AR_RxRSSIAnt00
Definition: mac.h:516
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_IMR_TXINTM
Definition: reg.h:291
#define AR_RxMoreAggr
Definition: mac.h:568
#define ATH9K_RX_DECRYPT_BUSY
Definition: mac.h:201
#define AR_D_MISC_CW_BKOFF_EN
Definition: reg.h:583
#define AR_CR
Definition: reg.h:24
#define AR_IMR_RXOK
Definition: reg.h:259
#define AR_Q_DESC_CRCCHK_EN
Definition: reg.h:481
#define AR_Q_RDYTIMECFG_EN
Definition: reg.h:421
struct net80211_channel * chan
Definition: hw.h:347
#define AR_DIAG_FORCE_CH_IDLE_HIGH
Definition: reg.h:1521
#define AR_D_LCL_IFS_AIFS
Definition: reg.h:527
Definition: mac.h:240
#define INIT_SSH_RETRY
Definition: mac.h:76
#define AR_RxRSSIAnt12
Definition: mac.h:546
#define AR_Q_RDYTIMECFG_DURATION
Definition: reg.h:419
#define AR_DMADBG_7
Definition: reg.h:357
#define ATH9K_RX_DELIM_CRC_POST
Definition: mac.h:200
int8_t rs_rssi_ext2
Definition: mac.h:151
#define AR_D_RETRY_LIMIT_STA_LG
Definition: reg.h:547
#define AR_IER_ENABLE
Definition: reg.h:55
#define ATH9K_RXKEYIX_INVALID
Definition: mac.h:203
#define AR_RxRSSICombined
Definition: mac.h:548
#define AR_DCHNTIME(_i)
Definition: reg.h:561
#define ATH9K_RSSI_BAD
Definition: hw.h:72
void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:55
#define AR_PostDelimCRCErr
Definition: mac.h:570
#define AR_RxKeyIdxValid
Definition: mac.h:563
#define AR_DLCL_IFS(_i)
Definition: reg.h:522
#define AR_IMR_S2_CABTO
Definition: reg.h:315
u16 rs_datalen
Definition: mac.h:138
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define INIT_AIFS
Definition: mac.h:70
#define AR_IMR_S0_QCU_TXOK
Definition: reg.h:295
int ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo)
Definition: ath9k_mac.c:162
int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, struct ath_rx_status *rs, u64 tsf __unused)
Definition: ath9k_mac.c:394
#define AR_IMR_S2_GTT
Definition: reg.h:310
#define AR_D_CHNTIME_DUR
Definition: reg.h:562
static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, struct ath9k_tx_queue_info *qi __unused)
Definition: ath9k_mac.c:25
#define SM(_v, _f)
Definition: hw.h:101
#define AR_Q_TXE
Definition: reg.h:386
#define AR_IMR_TXOK
Definition: reg.h:267
#define AR_RxRSSIAnt11
Definition: mac.h:544
int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:259
#define AR_PCU_MISC
Definition: reg.h:1640
#define AR_MichaelErr
Definition: mac.h:560
u8 rs_antenna
Definition: mac.h:144
#define AR5416DESC(_ds)
Definition: mac.h:318
#define ATH9K_TXQ_USEDEFAULT
Definition: mac.h:597
enum ath9k_tx_queue_flags tqi_qflags
Definition: mac.h:618
#define AR_TXCFG
Definition: reg.h:79
#define AR_D_MISC_POST_FR_BKOFF_DIS
Definition: reg.h:596
#define AH_RX_STOP_DMA_TIMEOUT
#define AR_IMR_S5
Definition: reg.h:328
#define AR_MACMISC_DMA_OBS_LINE_8
Definition: reg.h:140
#define AR_D_MISC_ARB_LOCKOUT_CNTRL
Definition: reg.h:589
#define AR_KeyMiss
Definition: mac.h:573
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
u32 tqi_cbrPeriod
Definition: mac.h:625
uint64_t u64
Definition: stdint.h:25
int ath9k_hw_intrpend(struct ath_hw *ah)
Definition: ath9k_mac.c:583
#define INIT_SLG_RETRY
Definition: mac.h:77
void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
Definition: ath9k_mac.c:641
#define AR_INTR_SPURIOUS
Definition: reg.h:919
#define AR_Q_MISC_RDYTIME_EXP_POLICY
Definition: reg.h:454
void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
Definition: ath9k_mac.c:129
#define INIT_SH_RETRY
Definition: mac.h:74
void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
Definition: ath9k_mac.c:156
u8 rs_status
Definition: mac.h:139
#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF
Definition: reg.h:636
#define INIT_LG_RETRY
Definition: mac.h:75
#define AR_SREV_9340(_ah)
Definition: reg.h:878
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
u32 tqi_readyTime
Definition: mac.h:628
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
#define AR_RxAggr
Definition: mac.h:569
#define AR_INTR_SYNC_CAUSE
Definition: reg.h:922
#define AR_IMR_S2_TSFOOR
Definition: reg.h:317
#define RXSTATUS_RATE(ah, ads)
Definition: mac.h:27
#define AR_DIAG_RX_DIS
Definition: reg.h:1510
u32 tqi_cbrOverflowLimit
Definition: mac.h:626
#define INIT_CWMIN_11B
Definition: mac.h:72
#define AR_IMR_S2_DTIMSYNC
Definition: reg.h:313
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
Definition: ath9k_mac.c:519
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo)
Definition: ath9k_mac.c:216
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_IMR_RXOK_LP
Definition: reg.h:262
#define ATH9K_RXERR_PHY
Definition: mac.h:190
#define AR_IMR_S1_QCU_TXEOL
Definition: reg.h:303
#define AR_RxMore
Definition: mac.h:527
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
#define AR_IMR_TXDESC
Definition: reg.h:268
#define AR_IMR_S2_CST
Definition: reg.h:309
#define AR_INTR_ASYNC_MASK
Definition: reg.h:966
#define MIN_TX_FIFO_THRESHOLD
Definition: mac.h:101
int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
Definition: ath9k_mac.c:101
#define AR_IMR_S2
Definition: reg.h:306
int8_t rs_rssi
Definition: mac.h:141
#define AR_PreDelimCRCErr
Definition: mac.h:561
Definition: sis900.h:30
#define AR_Q_CBRCFG_INTERVAL
Definition: reg.h:403
u32 tqi_physCompBuf
Definition: mac.h:629
u8 rs_keyix
Definition: mac.h:142
uint32_t ds
Definition: librm.h:254
#define AR_D_GBL_IFS_MISC
Definition: reg.h:628
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static fd_set * set
Definition: posix_io.h:48
#define AR_CR_RXD
Definition: reg.h:26
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
struct ar5416_desc::@32::@34 rx
#define INIT_CWMIN
Definition: mac.h:71
#define AR_CRCErr
Definition: mac.h:557
#define ATH9K_RX_GI
Definition: mac.h:197
#define AR_Q_STS_PEND_FR_CNT
Definition: reg.h:470
#define AR_MACMISC_MISC_OBS_BUS_MSB_S
Definition: reg.h:146
#define AR_Q_CBRCFG_OVF_THRESH
Definition: reg.h:405
#define AR_IMR_S5_TIM_TIMER
Definition: reg.h:247
#define ATH9K_RX_2040
Definition: mac.h:198
enum ath9k_tx_queue tqi_type
Definition: mac.h:616
u8 rs_isaggr
Definition: mac.h:152
#define ATH9K_RXERR_DECRYPT
Definition: mac.h:192
#define AR_IMR_RXERR
Definition: reg.h:263
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_INTR_MAC_IRQ
Definition: reg.h:915
#define AR_IMR_S2_DTIM
Definition: reg.h:316
#define AR_QSTS(_i)
Definition: reg.h:469
#define AR_IMR_TXEOL
Definition: reg.h:271
#define AR_INTR_SYNC_ENABLE
Definition: reg.h:926
#define INIT_CWMAX
Definition: mac.h:73
#define AH_WAIT_TIMEOUT
Definition: hw.h:145
#define AR_PCU_FORCE_QUIET_COLL
Definition: reg.h:1649
#define AR_IMR_S0
Definition: reg.h:294
#define AR_IMR_RXINTM
Definition: reg.h:292
#define AR_IMR_S1
Definition: reg.h:300
int8_t rs_rssi_ctl1
Definition: mac.h:147
Definition: sis900.h:32
#define AR_RxRSSIAnt10
Definition: mac.h:542
#define AR_PCU_CLEAR_VMF
Definition: reg.h:1651
#define AR_QRDYTIMECFG(_i)
Definition: reg.h:418
#define AR_MACMISC
Definition: reg.h:128
#define AH_TIME_QUANTUM
Definition: hw.h:147
#define AR_INTR_ASYNC_ENABLE
Definition: reg.h:977
#define AR_NUM_QCU
Definition: reg.h:359
#define AR_DecryptCRCErr
Definition: mac.h:558
uint8_t ah
Definition: registers.h:85
#define AR_DIAG_SW
Definition: reg.h:1504
#define AR_Q_DESC_CRCCHK
Definition: reg.h:479
Definition: sis900.h:31
#define AR_IMR_TXMINTR
Definition: reg.h:289
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
Definition: reg.h:453
#define AR_D_MISC_FRAG_WAIT_EN
Definition: reg.h:581
u32 tqi_burstTime
Definition: mac.h:627
#define AR_DecryptBusyErr
Definition: mac.h:572
#define AR_INTR_SYNC_MASK
Definition: reg.h:970
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_MACMISC_DMA_OBS_S
Definition: reg.h:131
#define AR_Q_MISC_DCU_EARLY_TERM_REQ
Definition: reg.h:456
#define AR_IMR_BCNMISC
Definition: reg.h:282
void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning)
Definition: ath9k_mac.c:524
#define AR_IMR_S0_QCU_TXDESC
Definition: reg.h:297
#define AR_PHYErr
Definition: mac.h:559
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR_D_RETRY_LIMIT_FR_SH
Definition: reg.h:543
int8_t rs_rssi_ctl2
Definition: mac.h:148
union ar5416_desc::@32 u
#define AR_RxAntenna
Definition: mac.h:539
uint32_t u32
Definition: stdint.h:23
#define AR_IMR
Definition: reg.h:258
#define AR_RxFrameOK
Definition: mac.h:556
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR_D_CHNTIME_EN
Definition: reg.h:564
#define AR_IMR_S1_QCU_TXERR
Definition: reg.h:301
#define DBG2(...)
Definition: compiler.h:515
#define AR_Q_MISC_FSP_CBR
Definition: reg.h:444
#define AR_DataLen
Definition: mac.h:526
void * memset(void *dest, int character, size_t len) __nonnull
u8 rs_phyerr
Definition: mac.h:140
#define AR_KeyIdx
Definition: mac.h:564