iPXE
pcnet32.h
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1 /*
2  * Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  */
20 
21 FILE_LICENCE ( GPL2_OR_LATER );
22 
23 #ifndef _PCNET32_H_
24 #define _PCNET32_H_
25 
26 /*
27  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
28  * Set default values to 16 Tx buffers and 32 Rx buffers.
29  */
30 #define PCNET32_LOG_TX_BUFFERS 4
31 #define PCNET32_LOG_RX_BUFFERS 5
32 
33 /* Maximum number of descriptor rings is 512 */
34 #define PCNET32_LOG_MAX_TX_BUFFERS 9
35 #define PCNET32_LOG_MAX_RX_BUFFERS 9
36 
37 #define TX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
38 #define TX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
39 
40 #define RX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
41 #define RX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
42 
43 #define RX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
44 #define TX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
45 
46 #define PKT_BUF_SIZE 1536
47 
48 #define RX_RING_ALIGN 16
49 #define TX_RING_ALIGN 16
50 
51 #define INIT_BLOCK_ALIGN 32
52 
53 #define PCNET32_WIO_RDP 0x10
54 #define PCNET32_WIO_RAP 0x12
55 #define PCNET32_WIO_RESET 0x14
56 #define PCNET32_WIO_BDP 0x16
57 
58 #define PCNET32_DWIO_RDP 0x10
59 #define PCNET32_DWIO_RAP 0x14
60 #define PCNET32_DWIO_RESET 0x18
61 #define PCNET32_DWIO_BDP 0x1C
62 
63 #define PCNET32_PORT_AUI 0x00
64 #define PCNET32_PORT_10BT 0x01
65 #define PCNET32_PORT_GPSI 0x02
66 #define PCNET32_PORT_MII 0x03
67 
68 #define PCNET32_PORT_PORTSEL 0x03
69 #define PCNET32_PORT_ASEL 0x04
70 #define PCNET32_PORT_100 0x40
71 #define PCNET32_PORT_FD 0x80
72 
73 #define PCNET32_SWSTYLE_LANCE 0x00
74 #define PCNET32_SWSTYLE_ILACC 0x01
75 #define PCNET32_SWSTYLE_PCNET32 0x02
76 
77 #define PCNET32_MAX_PHYS 32
78 
79 #ifndef PCI_VENDOR_ID_AT
80 #define PCI_VENDOR_ID_AT 0x1259
81 #endif
82 
83 #ifndef PCI_SUBDEVICE_ID_AT_2700FX
84 #define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
85 #endif
86 
87 #ifndef PCI_SUBDEVICE_ID_AT_2701FX
88 #define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
89 #endif
90 
97 };
98 
105 };
106 
115 };
116 
118  u16 ( *read_csr ) ( unsigned long, int );
119  void ( *write_csr ) ( unsigned long, int, u16 );
120  u16 ( *read_bcr ) ( unsigned long, int );
121  void ( *write_bcr ) ( unsigned long, int, u16 );
122  u16 ( *read_rap ) ( unsigned long );
123  void ( *write_rap ) ( unsigned long, u16 );
124  void ( *reset ) ( unsigned long );
125 };
126 
128  struct pcnet32_init_block init_block __attribute__((aligned(32)));
131 
134 
141 
142  struct pcnet32_access *a;
143  int options;
144  unsigned int mii:1,
145  full_duplex:1;
146 
147  unsigned short chip_version;
148 
150 };
151 
153  DescOwn = (1 << 15),
154  StartOfPacket = (1 << 9),
155  EndOfPacket = (1 << 8)
156 };
157 
159  /* CSR0 bits - Controller status register */
160  RxInt = (1 << 10),
161  TxInt = (1 << 9),
162  InitDone = (1 << 8),
163  IntFlag = (1 << 7),
164  IntEnable = (1 << 6),
165  TxDemand = (1 << 3),
166  Stop = (1 << 2),
167  Strt = (1 << 1),
168  Init = (1 << 0),
169 
170  /* CSR3 bits - Controller status register */
171  BablMask = (1 << 14),
172  MissFrameMask = (1 << 12),
173  MemErrMask = (1 << 11),
174  RxIntMask = (1 << 10),
175  TxIntMask = (1 << 9),
176  InitDoneMask = (1 << 8)
177 
178 };
179 
180 #endif /* _PCNET32_H_ */
unsigned int mii
Definition: pcnet32.h:144
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
uint32_t tx_curr
Definition: pcnet32.h:138
int16_t s16
Definition: stdint.h:20
Definition: pcnet32.h:168
void(* write_rap)(unsigned long, u16)
Definition: pcnet32.h:123
uint32_t tx_tail
Definition: pcnet32.h:139
struct pci_device * pci_dev
Definition: pcnet32.h:129
s16 buf_length
Definition: pcnet32.h:93
Definition: pcnet32.h:161
Definition: pcnet32.h:160
pcnet32_register_content
Definition: pcnet32.h:158
#define RX_RING_SIZE
Definition: pcnet32.h:40
#define TX_RING_SIZE
Definition: pcnet32.h:37
u32 msg_length
Definition: pcnet32.h:95
struct io_buffer * rx_iobuf[RX_RING_SIZE]
Definition: pcnet32.h:132
struct pcnet32_rx_desc * rx_base
Definition: pcnet32.h:135
A 16-bit general register.
Definition: registers.h:24
void(* write_csr)(unsigned long, int, u16)
Definition: pcnet32.h:119
pcnet32_desc_status_bit
Definition: pcnet32.h:152
A PCI device.
Definition: pci.h:187
A network device.
Definition: netdevice.h:348
uint32_t tx_fill_ctr
Definition: pcnet32.h:140
u16(* read_rap)(unsigned long)
Definition: pcnet32.h:122
unsigned int uint32_t
Definition: stdint.h:12
unsigned short chip_version
Definition: pcnet32.h:147
struct pcnet32_access * a
Definition: pcnet32.h:142
Definition: pcnet32.h:167
unsigned int full_duplex
Definition: pcnet32.h:144
struct io_buffer * tx_iobuf[TX_RING_SIZE]
Definition: pcnet32.h:133
void(* write_bcr)(unsigned long, int, u16)
Definition: pcnet32.h:121
struct pcnet32_tx_desc * tx_base
Definition: pcnet32.h:136
void(* reset)(unsigned long)
Definition: pcnet32.h:124
u16(* read_bcr)(unsigned long, int)
Definition: pcnet32.h:120
struct net_device * netdev
Definition: pcnet32.h:130
u16(* read_csr)(unsigned long, int)
Definition: pcnet32.h:118
Definition: pcnet32.h:166
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
char irq_enabled
Definition: pcnet32.h:149
A persistent I/O buffer.
Definition: iobuf.h:32
FILE_LICENCE(GPL2_OR_LATER)
uint32_t rx_curr
Definition: pcnet32.h:137