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iPXE
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Go to the source code of this file.
Macros | |
| #define | CHANSEL_DIV 15 |
| #define | CHANSEL_2G(_freq) |
| #define | CHANSEL_5G(_freq) |
| #define | AR_PHY_BASE 0x9800 |
| #define | AR_PHY(_n) |
| #define | AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 |
| #define | AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 |
| #define | AR_PHY_TX_GAIN_CLC 0x0000001E |
| #define | AR_PHY_TX_GAIN_CLC_S 1 |
| #define | AR_PHY_TX_GAIN 0x0007F000 |
| #define | AR_PHY_TX_GAIN_S 12 |
| #define | AR_PHY_CLC_TBL1 0xa35c |
| #define | AR_PHY_CLC_I0 0x07ff0000 |
| #define | AR_PHY_CLC_I0_S 16 |
| #define | AR_PHY_CLC_Q0 0x0000ffd0 |
| #define | AR_PHY_CLC_Q0_S 5 |
| #define | ANTSWAP_AB 0x0001 |
| #define | REDUCE_CHAIN_0 0x00000050 |
| #define | REDUCE_CHAIN_1 0x00000051 |
| #define | AR_PHY_CHIP_ID 0x9818 |
| #define | AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 |
| #define | AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 |
| #define | AR_PHY_PLL_CONTROL 0x16180 |
| #define | AR_PHY_PLL_MODE 0x16184 |
Functions | |
| FILE_LICENCE (BSD2) | |
| FILE_SECBOOT (FORBIDDEN) | |
| #define CHANSEL_2G | ( | _freq | ) |
Definition at line 24 of file phy.h.
Referenced by ar9002_hw_set_channel(), and ar9003_hw_set_channel().
| #define CHANSEL_5G | ( | _freq | ) |
Definition at line 25 of file phy.h.
Referenced by ar9002_hw_set_channel(), and ar9003_hw_set_channel().
| #define AR_PHY_BASE 0x9800 |
Definition at line 27 of file phy.h.
Referenced by ath9k_hw_chip_test(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), and ath9k_hw_set_def_power_cal_table().
| #define AR_PHY | ( | _n | ) |
Definition at line 28 of file phy.h.
Referenced by ar5008_hw_process_ini(), ar5008_hw_set_channel(), ar9002_hw_get_radiorev(), and ar9002_hw_rf_claim().
| #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 |
Definition at line 30 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_TX_GAIN_CLC 0x0000001E |
Definition at line 32 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_TX_GAIN_CLC_S 1 |
Definition at line 33 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CLC_TBL1 0xa35c |
Definition at line 37 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CLC_I0 0x07ff0000 |
Definition at line 38 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CLC_I0_S 16 |
Definition at line 39 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CLC_Q0 0x0000ffd0 |
Definition at line 40 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CLC_Q0_S 5 |
Definition at line 41 of file phy.h.
Referenced by ar9285_hw_clc().
| #define AR_PHY_CHIP_ID 0x9818 |
Definition at line 46 of file phy.h.
Referenced by __ath9k_hw_init().
| #define AR_PHY_PLL_CONTROL 0x16180 |
Definition at line 51 of file phy.h.
Referenced by ath9k_hw_init_pll().
| #define AR_PHY_PLL_MODE 0x16184 |
Definition at line 52 of file phy.h.
Referenced by ath9k_hw_init_pll().
| FILE_LICENCE | ( | BSD2 | ) |
| FILE_SECBOOT | ( | FORBIDDEN | ) |