iPXE
ath9k_eeprom_9287.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/io.h>
21 
22 #include "hw.h"
23 #include "ar9002_phy.h"
24 
25 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
26 
28 {
29  return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
30 }
31 
33 {
34  return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
35 }
36 
38 {
39  struct ar9287_eeprom *eep = &ah->eeprom.map9287;
41  u16 *eep_data;
42  unsigned int addr;
43  int eep_start_loc = AR9287_EEP_START_LOC;
44  eep_data = (u16 *)eep;
45 
46  for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
47  if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
48  eep_data)) {
49  DBG("ath9k: "
50  "Unable to read eeprom region\n");
51  return 0;
52  }
53  eep_data++;
54  }
55 
56  return 1;
57 }
58 
60 {
61  u16 *eep_data = (u16 *)&ah->eeprom.map9287;
62 
66  return 1;
67 }
68 
70 {
72 
73  if (!ath9k_hw_use_flash(ah)) {
74  DBG2("ath9k: "
75  "Reading from EEPROM, not flash\n");
76  }
77 
78  if (common->bus_ops->ath_bus_type == ATH_USB)
80  else
82 }
83 
85 {
86  u32 sum = 0, el, integer;
87  u16 temp, word, magic, magic2, *eepdata;
88  unsigned int i, addr;
89  int need_swap = 0;
90  struct ar9287_eeprom *eep = &ah->eeprom.map9287;
92 
93  if (!ath9k_hw_use_flash(ah)) {
95  &magic)) {
96  DBG("ath9k: Reading Magic # failed\n");
97  return 0;
98  }
99 
100  DBG2("ath9k: "
101  "Read Magic = 0x%04X\n", magic);
102 
103  if (magic != AR5416_EEPROM_MAGIC) {
104  magic2 = swab16(magic);
105 
106  if (magic2 == AR5416_EEPROM_MAGIC) {
107  need_swap = 1;
108  eepdata = (u16 *)(&ah->eeprom);
109 
110  for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
111  temp = swab16(*eepdata);
112  *eepdata = temp;
113  eepdata++;
114  }
115  } else {
116  DBG("ath9k: "
117  "Invalid EEPROM Magic. Endianness mismatch.\n");
118  return -EINVAL;
119  }
120  }
121  }
122 
123  DBG2("ath9k: need_swap = %s.\n",
124  need_swap ? "True" : "False");
125 
126  if (need_swap)
127  el = swab16(ah->eeprom.map9287.baseEepHeader.length);
128  else
129  el = ah->eeprom.map9287.baseEepHeader.length;
130 
131  if (el > sizeof(struct ar9287_eeprom))
132  el = sizeof(struct ar9287_eeprom) / sizeof(u16);
133  else
134  el = el / sizeof(u16);
135 
136  eepdata = (u16 *)(&ah->eeprom);
137 
138  for (i = 0; i < el; i++)
139  sum ^= *eepdata++;
140 
141  if (need_swap) {
143  eep->baseEepHeader.length = word;
144 
146  eep->baseEepHeader.checksum = word;
147 
149  eep->baseEepHeader.version = word;
150 
151  word = swab16(eep->baseEepHeader.regDmn[0]);
152  eep->baseEepHeader.regDmn[0] = word;
153 
154  word = swab16(eep->baseEepHeader.regDmn[1]);
155  eep->baseEepHeader.regDmn[1] = word;
156 
158  eep->baseEepHeader.rfSilent = word;
159 
162 
165 
166  integer = swab32(eep->modalHeader.antCtrlCommon);
167  eep->modalHeader.antCtrlCommon = integer;
168 
169  for (i = 0; i < AR9287_MAX_CHAINS; i++) {
170  integer = swab32(eep->modalHeader.antCtrlChain[i]);
171  eep->modalHeader.antCtrlChain[i] = integer;
172  }
173 
174  for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
177  }
178  }
179 
180  if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
181  || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
182  DBG("ath9k: Bad EEPROM checksum 0x%x or revision 0x%04x\n",
183  sum, ah->eep_ops->get_eeprom_ver(ah));
184  return -EINVAL;
185  }
186 
187  return 0;
188 }
189 
191  enum eeprom_param param)
192 {
193  struct ar9287_eeprom *eep = &ah->eeprom.map9287;
194  struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
195  struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
196  u16 ver_minor;
197 
198  ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
199 
200  switch (param) {
201  case EEP_NFTHRESH_2:
202  return pModal->noiseFloorThreshCh[0];
203  case EEP_MAC_LSW:
204  return pBase->macAddr[0] << 8 | pBase->macAddr[1];
205  case EEP_MAC_MID:
206  return pBase->macAddr[2] << 8 | pBase->macAddr[3];
207  case EEP_MAC_MSW:
208  return pBase->macAddr[4] << 8 | pBase->macAddr[5];
209  case EEP_REG_0:
210  return pBase->regDmn[0];
211  case EEP_REG_1:
212  return pBase->regDmn[1];
213  case EEP_OP_CAP:
214  return pBase->deviceCap;
215  case EEP_OP_MODE:
216  return pBase->opCapFlags;
217  case EEP_RF_SILENT:
218  return pBase->rfSilent;
219  case EEP_MINOR_REV:
220  return ver_minor;
221  case EEP_TX_MASK:
222  return pBase->txMask;
223  case EEP_RX_MASK:
224  return pBase->rxMask;
225  case EEP_DEV_TYPE:
226  return pBase->deviceType;
227  case EEP_OL_PWRCTRL:
228  return pBase->openLoopPwrCntl;
229  case EEP_TEMPSENSE_SLOPE:
230  if (ver_minor >= AR9287_EEP_MINOR_VER_2)
231  return pBase->tempSensSlope;
232  else
233  return 0;
235  if (ver_minor >= AR9287_EEP_MINOR_VER_3)
236  return pBase->tempSensSlopePalOn;
237  else
238  return 0;
239  default:
240  return 0;
241  }
242 }
243 
245  struct ath9k_channel *chan,
246  struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
247  u8 *pCalChans, u16 availPiers, int8_t *pPwr)
248 {
249  u16 idxL = 0, idxR = 0, numPiers;
250  int match;
251  struct chan_centers centers;
252 
253  ath9k_hw_get_channel_centers(ah, chan, &centers);
254 
255  for (numPiers = 0; numPiers < availPiers; numPiers++) {
256  if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
257  break;
258  }
259 
261  (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
262  pCalChans, numPiers, &idxL, &idxR);
263 
264  if (match) {
265  *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
266  } else {
267  *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
268  (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
269  }
270 
271 }
272 
274  int32_t txPower, u16 chain)
275 {
276  u32 tmpVal;
277  u32 a;
278 
279  /* Enable OLPC for chain 0 */
280 
281  tmpVal = REG_READ(ah, 0xa270);
282  tmpVal = tmpVal & 0xFCFFFFFF;
283  tmpVal = tmpVal | (0x3 << 24);
284  REG_WRITE(ah, 0xa270, tmpVal);
285 
286  /* Enable OLPC for chain 1 */
287 
288  tmpVal = REG_READ(ah, 0xb270);
289  tmpVal = tmpVal & 0xFCFFFFFF;
290  tmpVal = tmpVal | (0x3 << 24);
291  REG_WRITE(ah, 0xb270, tmpVal);
292 
293  /* Write the OLPC ref power for chain 0 */
294 
295  if (chain == 0) {
296  tmpVal = REG_READ(ah, 0xa398);
297  tmpVal = tmpVal & 0xff00ffff;
298  a = (txPower)&0xff;
299  tmpVal = tmpVal | (a << 16);
300  REG_WRITE(ah, 0xa398, tmpVal);
301  }
302 
303  /* Write the OLPC ref power for chain 1 */
304 
305  if (chain == 1) {
306  tmpVal = REG_READ(ah, 0xb398);
307  tmpVal = tmpVal & 0xff00ffff;
308  a = (txPower)&0xff;
309  tmpVal = tmpVal | (a << 16);
310  REG_WRITE(ah, 0xb398, tmpVal);
311  }
312 }
313 
315  struct ath9k_channel *chan,
316  int16_t *pTxPowerIndexOffset)
317 {
318  struct cal_data_per_freq_ar9287 *pRawDataset;
319  struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
320  u8 *pCalBChans = NULL;
321  u16 pdGainOverlap_t2;
322  u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
323  u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
324  u16 numPiers = 0, i, j;
325  u16 numXpdGain, xpdMask;
326  u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
327  u32 reg32, regOffset, regChainOffset, regval;
328  int16_t diff = 0;
329  struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
330 
331  xpdMask = pEepData->modalHeader.xpdGain;
332 
333  if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
335  pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
336  else
337  pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
339 
340  if (IS_CHAN_2GHZ(chan)) {
341  pCalBChans = pEepData->calFreqPier2G;
342  numPiers = AR9287_NUM_2G_CAL_PIERS;
344  pRawDatasetOpenLoop =
345  (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
346  ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
347  }
348  }
349 
350  numXpdGain = 0;
351 
352  /* Calculate the value of xpdgains from the xpdGain Mask */
353  for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
354  if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
355  if (numXpdGain >= AR5416_NUM_PD_GAINS)
356  break;
357  xpdGainValues[numXpdGain] =
359  numXpdGain++;
360  }
361  }
362 
364  (numXpdGain - 1) & 0x3);
366  xpdGainValues[0]);
368  xpdGainValues[1]);
370  xpdGainValues[2]);
371 
372  for (i = 0; i < AR9287_MAX_CHAINS; i++) {
373  regChainOffset = i * 0x1000;
374 
375  if (pEepData->baseEepHeader.txMask & (1 << i)) {
376  pRawDatasetOpenLoop =
377  (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
378 
380  int8_t txPower;
382  pRawDatasetOpenLoop,
383  pCalBChans, numPiers,
384  &txPower);
385  ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
386  } else {
387  pRawDataset =
388  (struct cal_data_per_freq_ar9287 *)
389  pEepData->calPierData2G[i];
390 
392  pRawDataset,
393  pCalBChans, numPiers,
394  pdGainOverlap_t2,
395  gainBoundaries,
396  pdadcValues,
397  numXpdGain);
398  }
399 
401 
402  if (i == 0) {
404  EEP_OL_PWRCTRL)) {
405 
406  regval = SM(pdGainOverlap_t2,
408  | SM(gainBoundaries[0],
410  | SM(gainBoundaries[1],
412  | SM(gainBoundaries[2],
414  | SM(gainBoundaries[3],
416 
417  REG_WRITE(ah,
418  AR_PHY_TPCRG5 + regChainOffset,
419  regval);
420  }
421  }
422 
424  pEepData->baseEepHeader.pwrTableOffset) {
425  diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
427  diff *= 2;
428 
429  for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
430  pdadcValues[j] = pdadcValues[j+diff];
431 
432  for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
433  j < AR5416_NUM_PDADC_VALUES; j++)
434  pdadcValues[j] =
435  pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
436  }
437 
439  regOffset = AR_PHY_BASE +
440  (672 << 2) + regChainOffset;
441 
442  for (j = 0; j < 32; j++) {
443  reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)
444  | ((pdadcValues[4*j + 1] & 0xFF) << 8)
445  | ((pdadcValues[4*j + 2] & 0xFF) << 16)
446  | ((pdadcValues[4*j + 3] & 0xFF) << 24);
447 
448  REG_WRITE(ah, regOffset, reg32);
449  regOffset += 4;
450  }
451  }
453  }
454  }
455 
456  *pTxPowerIndexOffset = 0;
457 }
458 
460  struct ath9k_channel *chan,
461  int16_t *ratesArray,
462  u16 cfgCtl,
463  u16 AntennaReduction,
464  u16 twiceMaxRegulatoryPower,
465  u16 powerLimit)
466 {
467 #define CMP_CTL \
468  (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
469  pEepData->ctlIndex[i])
470 
471 #define CMP_NO_CTL \
472  (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
473  ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
474 
475 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
476 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
477 
478  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
479  u16 twiceMaxEdgePower = MAX_RATE_POWER;
480  static const u16 tpScaleReductionTable[5] =
481  { 0, 3, 6, 9, MAX_RATE_POWER };
482  unsigned int i;
483  int16_t twiceLargestAntenna;
484  struct cal_ctl_data_ar9287 *rep;
485  struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
486  targetPowerCck = {0, {0, 0, 0, 0} };
487  struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
488  targetPowerCckExt = {0, {0, 0, 0, 0} };
489  struct cal_target_power_ht targetPowerHt20,
490  targetPowerHt40 = {0, {0, 0, 0, 0} };
491  u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
492  static const u16 ctlModesFor11g[] = {
495  };
496  u16 numCtlModes = 0;
497  const u16 *pCtlMode = NULL;
498  u16 ctlMode, freq;
499  struct chan_centers centers;
500  int tx_chainmask;
501  u16 twiceMinEdgePower;
502  struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
503  tx_chainmask = ah->txchainmask;
504 
505  ath9k_hw_get_channel_centers(ah, chan, &centers);
506 
507  /* Compute TxPower reduction due to Antenna Gain */
508  twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
509  pEepData->modalHeader.antennaGainCh[1]);
510  twiceLargestAntenna = (int16_t)min((AntennaReduction) -
511  twiceLargestAntenna, 0);
512 
513  /*
514  * scaledPower is the minimum of the user input power level
515  * and the regulatory allowed power level.
516  */
517  maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
518 
519  if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
520  maxRegAllowedPower -=
521  (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
522 
523  scaledPower = min(powerLimit, maxRegAllowedPower);
524 
525  /*
526  * Reduce scaled Power by number of chains active
527  * to get the per chain tx power level.
528  */
529  switch (ar5416_get_ntxchains(tx_chainmask)) {
530  case 1:
531  break;
532  case 2:
533  if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
534  scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
535  else
536  scaledPower = 0;
537  break;
538  case 3:
539  if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
540  scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
541  else
542  scaledPower = 0;
543  break;
544  }
545  scaledPower = max((u16)0, scaledPower);
546 
547  /*
548  * Get TX power from EEPROM.
549  */
550  if (IS_CHAN_2GHZ(chan)) {
551  /* CTL_11B, CTL_11G, CTL_2GHT20 */
552  numCtlModes =
553  ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
554 
555  pCtlMode = ctlModesFor11g;
556 
558  pEepData->calTargetPowerCck,
560  &targetPowerCck, 4, 0);
562  pEepData->calTargetPower2G,
564  &targetPowerOfdm, 4, 0);
566  pEepData->calTargetPower2GHT20,
568  &targetPowerHt20, 8, 0);
569 
570  if (IS_CHAN_HT40(chan)) {
571  /* All 2G CTLs */
572  numCtlModes = ARRAY_SIZE(ctlModesFor11g);
574  pEepData->calTargetPower2GHT40,
576  &targetPowerHt40, 8, 1);
578  pEepData->calTargetPowerCck,
580  &targetPowerCckExt, 4, 1);
582  pEepData->calTargetPower2G,
584  &targetPowerOfdmExt, 4, 1);
585  }
586  }
587 
588  for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
589  int isHt40CtlMode =
590  (pCtlMode[ctlMode] == CTL_2GHT40) ? 1 : 0;
591 
592  if (isHt40CtlMode)
593  freq = centers.synth_center;
594  else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
595  freq = centers.ext_center;
596  else
597  freq = centers.ctl_center;
598 
599  /* Walk through the CTL indices stored in EEPROM */
600  for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
601  struct cal_ctl_edges *pRdEdgesPower;
602 
603  /*
604  * Compare test group from regulatory channel list
605  * with test mode from pCtlMode list
606  */
607  if (CMP_CTL || CMP_NO_CTL) {
608  rep = &(pEepData->ctlData[i]);
609  pRdEdgesPower =
610  rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
611 
612  twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
613  pRdEdgesPower,
614  IS_CHAN_2GHZ(chan),
616 
617  if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
618  twiceMaxEdgePower = min(twiceMaxEdgePower,
619  twiceMinEdgePower);
620  } else {
621  twiceMaxEdgePower = twiceMinEdgePower;
622  break;
623  }
624  }
625  }
626 
627  minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
628 
629  /* Apply ctl mode to correct target power set */
630  switch (pCtlMode[ctlMode]) {
631  case CTL_11B:
632  for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
633  targetPowerCck.tPow2x[i] =
634  (u8)min((u16)targetPowerCck.tPow2x[i],
635  minCtlPower);
636  }
637  break;
638  case CTL_11A:
639  case CTL_11G:
640  for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
641  targetPowerOfdm.tPow2x[i] =
642  (u8)min((u16)targetPowerOfdm.tPow2x[i],
643  minCtlPower);
644  }
645  break;
646  case CTL_5GHT20:
647  case CTL_2GHT20:
648  for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
649  targetPowerHt20.tPow2x[i] =
650  (u8)min((u16)targetPowerHt20.tPow2x[i],
651  minCtlPower);
652  }
653  break;
654  case CTL_11B_EXT:
655  targetPowerCckExt.tPow2x[0] =
656  (u8)min((u16)targetPowerCckExt.tPow2x[0],
657  minCtlPower);
658  break;
659  case CTL_11A_EXT:
660  case CTL_11G_EXT:
661  targetPowerOfdmExt.tPow2x[0] =
662  (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
663  minCtlPower);
664  break;
665  case CTL_5GHT40:
666  case CTL_2GHT40:
667  for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
668  targetPowerHt40.tPow2x[i] =
669  (u8)min((u16)targetPowerHt40.tPow2x[i],
670  minCtlPower);
671  }
672  break;
673  default:
674  break;
675  }
676  }
677 
678  /* Now set the rates array */
679 
680  ratesArray[rate6mb] =
681  ratesArray[rate9mb] =
682  ratesArray[rate12mb] =
683  ratesArray[rate18mb] =
684  ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
685 
686  ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
687  ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
688  ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
689  ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
690 
691  for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
692  ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
693 
694  if (IS_CHAN_2GHZ(chan)) {
695  ratesArray[rate1l] = targetPowerCck.tPow2x[0];
696  ratesArray[rate2s] =
697  ratesArray[rate2l] = targetPowerCck.tPow2x[1];
698  ratesArray[rate5_5s] =
699  ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
700  ratesArray[rate11s] =
701  ratesArray[rate11l] = targetPowerCck.tPow2x[3];
702  }
703  if (IS_CHAN_HT40(chan)) {
704  for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
705  ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
706 
707  ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
708  ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
709  ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
710 
711  if (IS_CHAN_2GHZ(chan))
712  ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
713  }
714 
715 #undef CMP_CTL
716 #undef CMP_NO_CTL
717 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
718 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
719 }
720 
722  struct ath9k_channel *chan, u16 cfgCtl,
723  u8 twiceAntennaReduction,
724  u8 twiceMaxRegulatoryPower,
725  u8 powerLimit, int test)
726 {
727  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
728  struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
729  struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
730  int16_t ratesArray[Ar5416RateSize];
731  int16_t txPowerIndexOffset = 0;
733  unsigned int i;
734 
735  memset(ratesArray, 0, sizeof(ratesArray));
736 
737  if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
740 
742  &ratesArray[0], cfgCtl,
743  twiceAntennaReduction,
744  twiceMaxRegulatoryPower,
745  powerLimit);
746 
747  ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
748 
749  regulatory->max_power_level = 0;
750  for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
751  ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
752  if (ratesArray[i] > MAX_RATE_POWER)
753  ratesArray[i] = MAX_RATE_POWER;
754 
755  if (ratesArray[i] > regulatory->max_power_level)
756  regulatory->max_power_level = ratesArray[i];
757  }
758 
759  if (test)
760  return;
761 
762  if (IS_CHAN_2GHZ(chan))
763  i = rate1l;
764  else
765  i = rate6mb;
766 
767  regulatory->max_power_level = ratesArray[i];
768 
770  for (i = 0; i < Ar5416RateSize; i++)
771  ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
772  }
773 
775 
776  /* OFDM power per rate */
778  ATH9K_POW_SM(ratesArray[rate18mb], 24)
779  | ATH9K_POW_SM(ratesArray[rate12mb], 16)
780  | ATH9K_POW_SM(ratesArray[rate9mb], 8)
781  | ATH9K_POW_SM(ratesArray[rate6mb], 0));
782 
784  ATH9K_POW_SM(ratesArray[rate54mb], 24)
785  | ATH9K_POW_SM(ratesArray[rate48mb], 16)
786  | ATH9K_POW_SM(ratesArray[rate36mb], 8)
787  | ATH9K_POW_SM(ratesArray[rate24mb], 0));
788 
789  /* CCK power per rate */
790  if (IS_CHAN_2GHZ(chan)) {
792  ATH9K_POW_SM(ratesArray[rate2s], 24)
793  | ATH9K_POW_SM(ratesArray[rate2l], 16)
794  | ATH9K_POW_SM(ratesArray[rateXr], 8)
795  | ATH9K_POW_SM(ratesArray[rate1l], 0));
797  ATH9K_POW_SM(ratesArray[rate11s], 24)
798  | ATH9K_POW_SM(ratesArray[rate11l], 16)
799  | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
800  | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
801  }
802 
803  /* HT20 power per rate */
805  ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
806  | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
807  | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
808  | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
809 
811  ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
812  | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
813  | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
814  | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
815 
816  /* HT40 power per rate */
817  if (IS_CHAN_HT40(chan)) {
820  ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
821  | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
822  | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
823  | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
824 
826  ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
827  | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
828  | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
829  | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
830  } else {
832  ATH9K_POW_SM(ratesArray[rateHt40_3] +
834  | ATH9K_POW_SM(ratesArray[rateHt40_2] +
836  | ATH9K_POW_SM(ratesArray[rateHt40_1] +
838  | ATH9K_POW_SM(ratesArray[rateHt40_0] +
840 
842  ATH9K_POW_SM(ratesArray[rateHt40_7] +
844  | ATH9K_POW_SM(ratesArray[rateHt40_6] +
846  | ATH9K_POW_SM(ratesArray[rateHt40_5] +
848  | ATH9K_POW_SM(ratesArray[rateHt40_4] +
850  }
851 
852  /* Dup/Ext power per rate */
854  ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
855  | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
856  | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
857  | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
858  }
860 }
861 
863  struct ath9k_channel *chan __unused)
864 {
865 }
866 
868  struct ath9k_channel *chan)
869 {
870  struct ar9287_eeprom *eep = &ah->eeprom.map9287;
871  struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
872  u32 regChainOffset, regval;
873  u8 txRxAttenLocal;
874  int i;
875 
876  pModal = &eep->modalHeader;
877 
879 
880  for (i = 0; i < AR9287_MAX_CHAINS; i++) {
881  regChainOffset = i * 0x1000;
882 
883  REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
884  pModal->antCtrlChain[i]);
885 
886  REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
887  (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
890  SM(pModal->iqCalICh[i],
892  SM(pModal->iqCalQCh[i],
894 
895  txRxAttenLocal = pModal->txRxAttenCh[i];
896 
897  REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
899  pModal->bswMargin[i]);
900  REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
902  pModal->bswAtten[i]);
903  REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
905  txRxAttenLocal);
906  REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
908  pModal->rxTxMarginCh[i]);
909  }
910 
911 
912  if (IS_CHAN_HT40(chan))
915  else
918 
921 
927 
930 
935 
936  regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
937  regval &= ~(AR9287_AN_RF2G3_DB1 |
943  regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
944  SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
945  SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
946  SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
947  SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
949 
951 
952  regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
953  regval &= ~(AR9287_AN_RF2G3_DB1 |
959  regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
960  SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
961  SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
962  SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
963  SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
965 
967 
972 
976  pModal->xpaBiasLvl);
977 }
978 
980  u16 i, int is2GHz)
981 {
982 #define EEP_MAP9287_SPURCHAN \
983  (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
984 
985  u16 spur_val = AR_NO_SPUR;
986 
987  DBG2("ath9k: "
988  "Getting spur idx:%d is2Ghz:%d val:%x\n",
989  i, is2GHz, ah->config.spurchans[i][is2GHz]);
990 
991  switch (ah->config.spurmode) {
992  case SPUR_DISABLE:
993  break;
994  case SPUR_ENABLE_IOCTL:
995  spur_val = ah->config.spurchans[i][is2GHz];
996  DBG2("ath9k: "
997  "Getting spur val from new loc. %d\n", spur_val);
998  break;
999  case SPUR_ENABLE_EEPROM:
1000  spur_val = EEP_MAP9287_SPURCHAN;
1001  break;
1002  }
1003 
1004  return spur_val;
1005 
1006 #undef EEP_MAP9287_SPURCHAN
1007 }
1008 
1009 const struct eeprom_ops eep_ar9287_ops = {
1011  .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1012  .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1013  .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1014  .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1015  .set_board_values = ath9k_hw_ar9287_set_board_values,
1016  .set_addac = ath9k_hw_ar9287_set_addac,
1017  .set_txpower = ath9k_hw_ar9287_set_txpower,
1018  .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1019 };
struct cal_target_power_ht calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:626
#define AR9287_EEP_MINOR_VER_3
Definition: eeprom.h:188
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON
Definition: ar9002_phy.h:86
void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, int isHt40Target)
Definition: ath9k_eeprom.c:216
#define AR5416_NUM_PD_GAINS
Definition: eeprom.h:153
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
#define AR_PHY_POWER_TX_RATE5
Definition: ar9002_phy.h:555
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF
Definition: ar9002_phy.h:80
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR9287_AN_TOP2_XPABIAS_LVL_S
Definition: reg.h:1424
u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]
Definition: eeprom.h:619
iPXE I/O API
#define AR9287_NUM_2G_CCK_TARGET_POWERS
Definition: eeprom.h:196
u8 bswMargin[AR9287_MAX_CHAINS]
Definition: eeprom.h:496
Definition: hw.h:656
u16 synth_center
Definition: hw.h:422
int8_t tempSensSlopePalOn
Definition: eeprom.h:469
u32 antCtrlChain[AR9287_MAX_CHAINS]
Definition: eeprom.h:474
#define AR_PHY_RF_CTL3
Definition: ar9002_phy.h:62
#define AR_PHY_RXGAIN
Definition: ar9002_phy.h:95
#define AR_PHY_POWER_TX_RATE3
Definition: ar9002_phy.h:451
#define max(x, y)
Definition: ath.h:39
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define ar5416_get_ntxchains(_txchainmask)
Definition: eeprom.h:706
#define CTL_2GHT40
Definition: eeprom.h:75
#define AR9287_HTC_EEP_START_LOC
Definition: eeprom.h:194
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
Definition: ar9002_phy.h:190
static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_POWER_TX_RATE2
Definition: ar9002_phy.h:207
#define AR9287_AN_RF2G3_CH1
Definition: reg.h:1400
#define AR5416_EEPROM_MAGIC_OFFSET
Definition: eeprom.h:59
struct cal_ctl_edges ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]
Definition: eeprom.h:552
#define AR9287_PWR_TABLE_OFFSET_DB
Definition: eeprom.h:209
static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, u8 *pCalChans, u16 availPiers, int8_t *pPwr)
#define EXT_ADDITIVE
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define AR9287_EEP_VER
Definition: eeprom.h:184
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
#define MS(_v, _f)
Definition: hw.h:102
u16 ext_center
Definition: hw.h:424
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
int8_t iqCalICh[AR9287_MAX_CHAINS]
Definition: eeprom.h:488
static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
#define AR_PHY_RF_CTL2
Definition: ar9002_phy.h:56
#define AR_PHY_POWER_TX_RATE4
Definition: ar9002_phy.h:452
#define SPUR_DISABLE
Definition: hw.h:235
#define min(x, y)
Definition: ath.h:34
uint32_t magic
Magic signature.
Definition: fdt.h:12
#define AR_PHY_TPCRG1_PD_GAIN_3
Definition: ar9002_phy.h:467
static int ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
#define ATH9K_POW_SM(_r, _s)
Definition: eeprom.h:101
#define AR9287_EEP_MINOR_VER_2
Definition: eeprom.h:187
#define AR9287_AN_RF2G3_DB1
Definition: reg.h:1401
int8_t antennaGainCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:476
#define AR9287_AN_TOP2
Definition: reg.h:1422
#define AR9280_PHY_CCA_THRESH62
Definition: ar9002_phy.h:136
#define AR_PHY_POWER_TX_RATE1
Definition: ar9002_phy.h:206
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2
Definition: ar9002_phy.h:543
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define FREQ2FBIN(x, y)
Definition: eeprom.h:102
#define AR5416_PD_GAINS_IN_MASK
Definition: eeprom.h:154
Definition: ath.h:127
#define AR_PHY_DESIRED_SZ
Definition: ar9002_phy.h:105
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
Definition: ath9k_eeprom.c:32
#define AR_PHY_SWITCH_COM
Definition: ar9002_phy.h:252
#define AR9287_NUM_2G_CAL_PIERS
Definition: eeprom.h:195
int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:485
#define SM(_v, _f)
Definition: hw.h:101
struct cal_target_power_leg calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:624
#define AR9287_AN_RF2G3_DB2
Definition: reg.h:1403
static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
#define SIZE_EEPROM_AR9287
#define AR_PHY_TX_END_DATA_START
Definition: ar9002_phy.h:57
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB
Definition: ar9002_phy.h:436
static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u16 AntennaReduction, u16 twiceMaxRegulatoryPower, u16 powerLimit)
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains)
Definition: ath9k_eeprom.c:318
#define AR_PHY_TIMING_CTRL4(_i)
Definition: ar9002_phy.h:187
static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset)
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define AR_PHY_TX_END_TO_A2_RX_ON
Definition: ar9002_phy.h:63
#define AR_PHY_SETTLING_SWITCH
Definition: ar9002_phy.h:92
static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, u16 i, int is2GHz)
#define AR_PHY_RF_CTL4
Definition: ar9002_phy.h:79
#define u8
Definition: igbvf_osdep.h:38
Definition: eeprom.h:267
static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
#define SPUR_ENABLE_EEPROM
Definition: hw.h:237
signed char int8_t
Definition: stdint.h:15
#define AR9287_NUM_2G_40_TARGET_POWERS
Definition: eeprom.h:198
Definition: eeprom.h:266
struct cal_target_power_leg calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]
Definition: eeprom.h:622
#define AR9287_AN_RF2G3_OB_PSK
Definition: reg.h:1407
#define ath9k_hw_use_flash(_ah)
Definition: eeprom.h:103
#define AR_PHY_TPCRG1_PD_GAIN_2
Definition: ar9002_phy.h:465
#define AR5416_NUM_PDADC_VALUES
Definition: eeprom.h:156
u16 spurChan
Definition: eeprom.h:331
const struct eeprom_ops eep_ar9287_ops
int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR)
Definition: ath9k_eeprom.c:69
#define AR_PHY_TPCRG1_PD_GAIN_1
Definition: ar9002_phy.h:463
#define AR5416_EEP_NO_BACK_VER
Definition: eeprom.h:130
#define AR5416_NUM_BAND_EDGES
Definition: eeprom.h:152
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
#define CTL_11G_EXT
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, int is2GHz, int num_band_edges)
Definition: ath9k_eeprom.c:271
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
Definition: ar9002_phy.h:432
#define AR5416_BCHAN_UNUSED
Definition: eeprom.h:157
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
static int __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]
Definition: eeprom.h:506
union cal_data_per_freq_ar9287_u calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]
Definition: eeprom.h:620
static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah, int32_t txPower, u16 chain)
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_PHY_TPCRG1
Definition: ar9002_phy.h:459
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
u32 addr
Definition: sky2.h:8
#define CMP_NO_CTL
#define AR_PHY_EXT_CCA0_THRESH62
Definition: ar9002_phy.h:328
#define CTL_11A
Definition: eeprom.h:70
#define AR9287_NUM_CTLS
Definition: eeprom.h:199
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
Definition: ath9k_eeprom.c:40
#define AR9287_NUM_2G_20_TARGET_POWERS
Definition: eeprom.h:197
#define CTL_11G
Definition: eeprom.h:72
#define AR_NO_SPUR
Definition: hw.h:240
#define AR_PHY_SETTLING
Definition: ar9002_phy.h:91
static int __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
struct ib_cm_common common
Definition: ib_mad.h:11
u8 rxTxMarginCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:479
struct cal_target_power_ht calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]
Definition: eeprom.h:628
int(* check_eeprom)(struct ath_hw *hw)
Definition: eeprom.h:653
static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, int isExtTarget)
Definition: ath9k_eeprom.c:161
#define AR9287_AN_RF2G3_OB_QAM
Definition: reg.h:1409
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN
#define AR_PHY_CCA
Definition: ar9002_phy.h:129
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define SUB_NUM_CTL_MODES_AT_2G_40
#define SD_NO_CTL
Definition: eeprom.h:67
#define EEP_MAP9287_SPURCHAN
#define AR9280_PHY_RXGAIN_TXRX_ATTEN
Definition: ar9002_phy.h:100
#define swab16
Definition: ath.h:66
#define AR9287_AN_TOP2_XPABIAS_LVL
Definition: reg.h:1423
#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP
Definition: ar9002_phy.h:539
struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]
Definition: eeprom.h:631
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size)
Definition: ath9k_eeprom.c:97
signed int int32_t
Definition: stdint.h:17
#define CTL_11A_EXT
eeprom_param
Definition: eeprom.h:225
#define AR_PHY_TX_END_PA_ON
Definition: ar9002_phy.h:59
#define AR_PHY_GAIN_2GHZ
Definition: ar9002_phy.h:422
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4
Definition: ar9002_phy.h:547
#define AR_PHY_BASE
Definition: phy.h:26
#define AR9287_AN_RF2G3_OB_CCK
Definition: reg.h:1405
#define CTL_2GHT20
Definition: eeprom.h:73
#define AR_PHY_TPCRG5
Definition: ar9002_phy.h:538
#define CTL_11B
Definition: eeprom.h:71
#define AR5416_EEPROM_MAGIC
Definition: eeprom.h:33
#define AR_PHY_EXT_CCA0
Definition: ar9002_phy.h:327
unsigned short word
Definition: smc9000.h:39
#define CMP_CTL
#define CTL_MODE_M
Definition: eeprom.h:69
#define CTL_11B_EXT
#define AR9287_AN_RF2G3_OB_PAL_OFF
Definition: reg.h:1411
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
#define SPUR_ENABLE_IOCTL
Definition: hw.h:236
uint8_t ah
Definition: registers.h:85
#define AR_PHY_SWITCH_CHAIN_0
Definition: ar9002_phy.h:251
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3
Definition: ar9002_phy.h:545
signed short int16_t
Definition: stdint.h:16
#define AR_PHY_POWER_TX_RATE9
Definition: ar9002_phy.h:563
#define AR_PHY_DESIRED_SZ_ADC
Definition: ar9002_phy.h:106
#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
Definition: ar9002_phy.h:541
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF
Definition: ar9002_phy.h:82
#define AR9280_PHY_RXGAIN_TXRX_MARGIN
Definition: ar9002_phy.h:102
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN
#define CTL_5GHT40
Definition: eeprom.h:76
struct modal_eep_ar9287_header modalHeader
Definition: eeprom.h:618
u8 txRxAttenCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:478
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
Definition: eeprom.h:266
#define AR9287_AN_RF2G3_CH0
Definition: reg.h:1399
struct base_eep_ar9287_header baseEepHeader
Definition: eeprom.h:616
#define AR9287_EEP_VER_MINOR_MASK
Definition: eeprom.h:185
#define CTL_5GHT20
Definition: eeprom.h:74
u8 bswAtten[AR9287_MAX_CHAINS]
Definition: eeprom.h:495
u8 ctlIndex[AR9287_NUM_CTLS]
Definition: eeprom.h:630
uint8_t u8
Definition: stdint.h:19
static int test
Definition: epic100.c:73
u16 max_power_level
Definition: ath.h:139
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23
#define AR_PHY_TPCRG1_NUM_PD_GAIN
Definition: ar9002_phy.h:460
#define AR9287_MAX_CHAINS
Definition: eeprom.h:204
#define swab32
Definition: ath.h:67
#define AR9287_EEP_START_LOC
Definition: eeprom.h:193
Definition: eeprom.h:266
#define AR_PHY_POWER_TX_RATE7
Definition: ar9002_phy.h:561
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR_PHY_POWER_TX_RATE8
Definition: ar9002_phy.h:562
#define DBG2(...)
Definition: compiler.h:515
if(natsemi->flags &NATSEMI_64BIT) return 1
#define AR_PHY_POWER_TX_RATE6
Definition: ar9002_phy.h:556
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON
Definition: ar9002_phy.h:84
u32 tp_scale
Definition: ath.h:140
void * memset(void *dest, int character, size_t len) __nonnull
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
Definition: ar9002_phy.h:188
int8_t iqCalQCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:489
u16 ctl_center
Definition: hw.h:423