iPXE
ath9k_ar9002_hw.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 FILE_LICENCE ( BSD2 );
21 
22 #include "hw.h"
23 #include "ar5008_initvals.h"
24 #include "ar9001_initvals.h"
25 #include "ar9002_initvals.h"
26 #include "ar9002_phy.h"
27 
29 
30 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
31 
32 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
33 {
34  if (AR_SREV_9271(ah)) {
37  INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
39  INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
42  INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
45  INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
48  INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
50  INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
53  INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
56  return;
57  }
58 
64  if (ah->config.pcie_clock_req)
65  INIT_INI_ARRAY(&ah->iniPcieSerdes,
68  else
69  INIT_INI_ARRAY(&ah->iniPcieSerdes,
72  2);
73  } else if (AR_SREV_9285_12_OR_LATER(ah)) {
74 
75 
80 
81  if (ah->config.pcie_clock_req) {
82  INIT_INI_ARRAY(&ah->iniPcieSerdes,
85  } else {
86  INIT_INI_ARRAY(&ah->iniPcieSerdes,
89  2);
90  }
91  } else if (AR_SREV_9280_20_OR_LATER(ah)) {
96 
97  if (ah->config.pcie_clock_req) {
98  INIT_INI_ARRAY(&ah->iniPcieSerdes,
101  } else {
102  INIT_INI_ARRAY(&ah->iniPcieSerdes,
105  }
106  INIT_INI_ARRAY(&ah->iniModesAdditional,
109  } else if (AR_SREV_9160_10_OR_LATER(ah)) {
110  INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
112  INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
114  INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
116  INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
118  INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
120  INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
122  INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
124  INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
126  INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
128  INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
130  if (AR_SREV_9160_11(ah)) {
131  INIT_INI_ARRAY(&ah->iniAddac,
134  } else {
135  INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
137  }
138  } else if (AR_SREV_9100_OR_LATER(ah)) {
139  INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
141  INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
143  INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
145  INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
147  INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
149  INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
151  INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
153  INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
155  INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
157  INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
159  INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
161  } else {
162  INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
163  ARRAY_SIZE(ar5416Modes), 6);
164  INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
166  INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
167  ARRAY_SIZE(ar5416Bank0), 2);
168  INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
170  INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
171  ARRAY_SIZE(ar5416Bank1), 2);
172  INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
173  ARRAY_SIZE(ar5416Bank2), 2);
174  INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
175  ARRAY_SIZE(ar5416Bank3), 3);
176  INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
177  ARRAY_SIZE(ar5416Bank6), 3);
178  INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
180  INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
181  ARRAY_SIZE(ar5416Bank7), 2);
182  INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
183  ARRAY_SIZE(ar5416Addac), 2);
184  }
185 }
186 
187 /* Support for Japan ch.14 (2484) spread */
189 {
191  INIT_INI_ARRAY(&ah->iniCckfirNormal,
194  2);
195  INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
198  2);
199  }
200 }
201 
203 {
204  u32 rxgain_type;
205 
206  if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
208  rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
209 
210  if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
211  INIT_INI_ARRAY(&ah->iniModesRxGain,
214  else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
215  INIT_INI_ARRAY(&ah->iniModesRxGain,
218  else
219  INIT_INI_ARRAY(&ah->iniModesRxGain,
222  } else {
223  INIT_INI_ARRAY(&ah->iniModesRxGain,
226  }
227 }
228 
230 {
231  u32 txgain_type;
232 
233  if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
235  txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
236 
237  if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
238  INIT_INI_ARRAY(&ah->iniModesTxGain,
241  else
242  INIT_INI_ARRAY(&ah->iniModesTxGain,
245  } else {
246  INIT_INI_ARRAY(&ah->iniModesTxGain,
249  }
250 }
251 
253 {
255  INIT_INI_ARRAY(&ah->iniModesRxGain,
258  else if (AR_SREV_9280_20(ah))
260 
262  INIT_INI_ARRAY(&ah->iniModesTxGain,
265  } else if (AR_SREV_9280_20(ah)) {
267  } else if (AR_SREV_9285_12_OR_LATER(ah)) {
268  u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
269 
270  /* txgain table */
271  if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
272  if (AR_SREV_9285E_20(ah)) {
273  INIT_INI_ARRAY(&ah->iniModesTxGain,
275  ARRAY_SIZE(
277  } else {
278  INIT_INI_ARRAY(&ah->iniModesTxGain,
280  ARRAY_SIZE(
282  }
283  } else {
284  if (AR_SREV_9285E_20(ah)) {
285  INIT_INI_ARRAY(&ah->iniModesTxGain,
287  ARRAY_SIZE(
289  } else {
290  INIT_INI_ARRAY(&ah->iniModesTxGain,
292  ARRAY_SIZE(
294  }
295  }
296  }
297 }
298 
299 /*
300  * Helper for ASPM support.
301  *
302  * Disable PLL when in L0s as well as receiver clock when in L1.
303  * This power saving option must be enabled through the SerDes.
304  *
305  * Programming the SerDes must go through the same 288 bit serial shift
306  * register as the other analog registers. Hence the 9 writes.
307  */
309  int restore,
310  int power_off)
311 {
312  u8 i;
313  u32 val;
314 
315  if (ah->is_pciexpress != 1)
316  return;
317 
318  /* Do not touch SerDes registers */
319  if (ah->config.pcie_powersave_enable == 2)
320  return;
321 
322  /* Nothing to do on restore for 11N */
323  if (!restore) {
325  /*
326  * AR9280 2.0 or later chips use SerDes values from the
327  * initvals.h initialized depending on chipset during
328  * __ath9k_hw_init()
329  */
330  for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
331  REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
332  INI_RA(&ah->iniPcieSerdes, i, 1));
333  }
334  } else {
336 
337  REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
338  REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
339 
340  /* RX shut off when elecidle is asserted */
341  REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
342  REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
343  REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
344 
345  /*
346  * Ignore ah->ah_config.pcie_clock_req setting for
347  * pre-AR9280 11n
348  */
349  REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
350 
351  REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
352  REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
353  REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
354 
355  /* Load the new settings */
356  REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
357 
359  }
360 
361  udelay(1000);
362  }
363 
364  if (power_off) {
365  /* clear bit 19 to disable L1 */
367 
368  val = REG_READ(ah, AR_WA);
369 
370  /*
371  * Set PCIe workaround bits
372  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
373  * should only be set when device enters D3 and be
374  * cleared when device comes back to D0.
375  */
376  if (ah->config.pcie_waen) {
377  if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
379  } else {
380  if (((AR_SREV_9285(ah) ||
381  AR_SREV_9271(ah) ||
382  AR_SREV_9287(ah)) &&
384  (AR_SREV_9280(ah) &&
387  }
388  }
389 
390  if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
391  /*
392  * Disable bit 6 and 7 before entering D3 to
393  * prevent system hang.
394  */
395  val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
396  }
397 
398  if (AR_SREV_9280(ah))
399  val |= AR_WA_BIT22;
400 
401  if (AR_SREV_9285E_20(ah))
402  val |= AR_WA_BIT23;
403 
404  REG_WRITE(ah, AR_WA, val);
405  } else {
406  if (ah->config.pcie_waen) {
407  val = ah->config.pcie_waen;
408  if (!power_off)
409  val &= (~AR_WA_D3_L1_DISABLE);
410  } else {
411  if (AR_SREV_9285(ah) ||
412  AR_SREV_9271(ah) ||
413  AR_SREV_9287(ah)) {
415  if (!power_off)
416  val &= (~AR_WA_D3_L1_DISABLE);
417  }
418  else if (AR_SREV_9280(ah)) {
419  /*
420  * For AR9280 chips, bit 22 of 0x4004
421  * needs to be set.
422  */
424  if (!power_off)
425  val &= (~AR_WA_D3_L1_DISABLE);
426  } else {
427  val = AR_WA_DEFAULT;
428  }
429  }
430 
431  /* WAR for ASPM system hang */
432  if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
433  val |= (AR_WA_BIT6 | AR_WA_BIT7);
434 
435  if (AR_SREV_9285E_20(ah))
436  val |= AR_WA_BIT23;
437 
438  REG_WRITE(ah, AR_WA, val);
439 
440  /* set bit 19 to allow forcing of pcie core into L1 state */
442  }
443 }
444 
445 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
446 {
447  u32 val;
448  int i;
449 
451 
452  REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
453  for (i = 0; i < 8; i++)
454  REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
455 
457 
458  val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
459  val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
460 
461  return ath9k_hw_reverse_bits(val, 8);
462 }
463 
465 {
466  u32 val;
467 
468  REG_WRITE(ah, AR_PHY(0), 0x00000007);
469 
471  switch (val & AR_RADIO_SREV_MAJOR) {
472  case 0:
474  break;
479  break;
480  default:
481  DBG("ath9k: "
482  "Radio Chip Rev 0x%02X not supported\n",
484  return -EOPNOTSUPP;
485  }
486 
487  ah->hw_version.analog5GhzRev = val;
488 
489  return 0;
490 }
491 
493 {
502  }
503 }
504 
505 /*
506  * If Async FIFO is enabled, the following counters change as MAC now runs
507  * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
508  *
509  * The values below tested for ht40 2 chain.
510  * Overwrite the delay/timeouts initialized in process ini.
511  */
513 {
521 
524 
529  }
530 }
531 
532 /*
533  * We don't enable WEP aggregation on mac80211 but we keep this
534  * around for HAL unification purposes.
535  */
537 {
541  }
542 }
543 
544 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
546 {
547  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
548  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
549 
552 
554 
558 
561 }
562 
563 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
564 {
565  u32 modesIndex;
566  unsigned int i;
567 
568  switch (chan->chanmode) {
569  case CHANNEL_A:
570  case CHANNEL_A_HT20:
571  modesIndex = 1;
572  break;
573  case CHANNEL_A_HT40PLUS:
574  case CHANNEL_A_HT40MINUS:
575  modesIndex = 2;
576  break;
577  case CHANNEL_G:
578  case CHANNEL_G_HT20:
579  case CHANNEL_B:
580  modesIndex = 4;
581  break;
582  case CHANNEL_G_HT40PLUS:
583  case CHANNEL_G_HT40MINUS:
584  modesIndex = 3;
585  break;
586 
587  default:
588  return;
589  }
590 
592 
593  for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
594  u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
595  u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
596  u32 val_orig;
597 
598  if (reg == AR_PHY_CCK_DETECT) {
599  val_orig = REG_READ(ah, reg);
602 
603  REG_WRITE(ah, reg, val|val_orig);
604  } else
605  REG_WRITE(ah, reg, val);
606  }
607 
609 }
#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP
Definition: reg.h:1840
#define AR_PHY(_n)
Definition: phy.h:27
static const u32 ar5416Bank1[][2]
static __unused const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2]
#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
Definition: reg.h:626
void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
#define AR_PCIE_SERDES
Definition: reg.h:981
u32 chanmode
Definition: hw.h:351
#define AR_RAD5133_SREV_MAJOR
Definition: reg.h:896
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
Definition: hw.h:656
static const u32 ar5416Bank6TPC_9160[][3]
void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
static const u32 ar5416BB_RfGain_9160[][3]
static __unused const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2]
#define AR_RAD5122_SREV_MAJOR
Definition: reg.h:898
static const u32 ar5416Bank7_9160[][2]
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
Definition: reg.h:1466
#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
Definition: reg.h:621
static __unused const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2]
static const u32 ar5416Bank6TPC[][3]
#define AR5416_EEP_MINOR_VER_17
Definition: eeprom.h:138
#define AR_D_GBL_IFS_SIFS
Definition: reg.h:603
static const u32 ar5416Bank3[][3]
static __unused const u32 ar9280Modes_9280_2[][6]
#define AR_SREV_9160_11(_ah)
Definition: reg.h:819
static __unused const u32 ar9271Modes_high_power_tx_gain_9271[][6]
#define AR_AHB_MODE
Definition: reg.h:901
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_PHY_MODE_ASYNCFIFO
Definition: ar9002_phy.h:397
#define AR_SREV_9100_OR_LATER(_ah)
Definition: reg.h:812
#define AR_AHB_CUSTOM_BURST_EN
Definition: reg.h:910
#define CHANNEL_A_HT40MINUS
Definition: hw.h:322
void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
static __unused const u32 ar9285Modes_XE2_0_normal_power[][6]
static const u32 ar5416Bank6_9100[][3]
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
#define AR_WA_BIT6
Definition: reg.h:699
static __unused const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6]
static const u32 ar5416Addac_9160[][2]
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define AR_PCIE_SERDES2
Definition: reg.h:982
#define AR5416_EEP_TXGAIN_HIGH_POWER
Definition: eeprom.h:170
static const u32 ar5416Bank1_9160[][2]
#define CHANNEL_A
Definition: ath5k.h:638
static __unused const u32 ar9287Modes_9287_1_1[][6]
void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
static const u32 ar5416Common_9160[][2]
static int ar9002_hw_get_radiorev(struct ath_hw *ah)
#define AR_SREV_9280_20(_ah)
Definition: reg.h:826
static const u32 ar5416Modes[][6]
static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
#define AR_SREV_9287(_ah)
Definition: reg.h:834
static const u32 ar5416Bank2_9100[][2]
void ar9002_hw_update_async_fifo(struct ath_hw *ah)
void ar9002_hw_attach_ops(struct ath_hw *ah)
static const u32 ar5416BB_RfGain_9100[][3]
static __unused const u32 ar9271Modes_9271[][6]
static __unused const u32 ar9280PciePhy_clkreq_off_L1_9280[][2]
#define AR_TIME_OUT
Definition: reg.h:1461
#define AR5416_EEP_RXGAIN_23DB_BACKOFF
Definition: eeprom.h:164
#define CHANNEL_G
Definition: ath5k.h:640
#define AR_WA_D3_L1_DISABLE
Definition: reg.h:702
#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
Definition: reg.h:605
static const u32 ar5416Common[][2]
static const u32 ar5416Bank6[][3]
#define AR_USEC
Definition: reg.h:1476
#define AR_RAD2122_SREV_MAJOR
Definition: reg.h:899
static __unused const u32 ar9287Modes_tx_gain_9287_1_1[][6]
static const u32 ar5416Bank6_9160[][3]
#define AR9280_WA_DEFAULT
Definition: reg.h:710
#define AR_RAD2133_SREV_MAJOR
Definition: reg.h:897
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
int ar9002_hw_rf_claim(struct ath_hw *ah)
#define AR_WA_BIT7
Definition: reg.h:700
#define AR_WA_BIT22
Definition: reg.h:708
static __unused const u32 ar9271Common_normal_cck_fir_coeff_9271[][2]
static __unused const u32 ar9280Modes_original_rxgain_9280_2[][6]
static const u32 ar5416Addac[][2]
static __unused const u32 ar9280Modes_fast_clock_9280_2[][3]
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
Definition: ar9002_phy.h:414
#define CHANNEL_A_HT20
Definition: hw.h:318
FILE_LICENCE(BSD2)
static __unused const u32 ar9285Modes_original_tx_gain_9285_1_2[][6]
static __unused const u32 ar9287Common_9287_1_1[][2]
#define AR9285_WA_DEFAULT
Definition: reg.h:709
static __unused const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6]
static const u32 ar5416BB_RfGain[][3]
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_SREV_9280(_ah)
Definition: reg.h:822
#define AR_PCIE_PM_CTRL
Definition: reg.h:983
static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
static __unused const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2]
static __unused const u32 ar9271Modes_9271_1_0_only[][6]
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
static const u32 ar5416Bank2[][2]
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
static __unused const u32 ar9271Common_9271[][2]
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
static __unused const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2]
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:413
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition: hw.h:604
#define AR_D_GBL_IFS_EIFS
Definition: reg.h:623
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
static __unused const u32 ar9280Common_9280_2[][2]
static __unused const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2]
static __unused const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2]
#define AR_MAC_PCU_LOGIC_ANALYZER
Definition: reg.h:1813
static __unused const u32 ar9271Modes_9271_ANI_reg[][6]
static __unused const u32 ar9285Common_9285_1_2[][2]
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static const u32 ar5416Bank0[][2]
void __asmcall int val
Definition: setjmp.h:28
static const u32 ar5416Bank3_9100[][3]
#define AR_SREV_9285E_20(_ah)
Definition: reg.h:881
static const u32 ar5416Modes_9160[][6]
#define AR_USEC_ASYNC_FIFO_DUR
Definition: reg.h:1482
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
static const u32 ar5416Bank2_9160[][2]
static __unused const u32 ar9280Modes_original_tx_gain_9280_2[][6]
static __unused const u32 ar9280Modes_high_power_tx_gain_9280_2[][6]
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
int modparam_force_new_ani
static const u32 ar5416Addac_9100[][2]
#define INIT_INI_ARRAY(iniarray, array, rows, columns)
Definition: calib.h:39
static const u32 ar5416Addac_9160_1_1[][2]
void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
static const u32 ar5416Common_9100[][2]
#define AR5416_EEP_RXGAIN_13DB_BACKOFF
Definition: eeprom.h:165
static __unused const u32 ar9271Modes_normal_power_tx_gain_9271[][6]
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
static const u32 ar5416Bank6TPC_9100[][3]
#define AR_MAC_PCU_ASYNC_FIFO_REG3
Definition: reg.h:1845
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
#define AR_WA_BIT23
Definition: reg.h:701
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_SREV_9287_13_OR_LATER(_ah)
Definition: reg.h:848
static void ar9002_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
static const u32 ar5416Bank0_9100[][2]
static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
#define AR_PCIE_PM_CTRL_ENA
Definition: reg.h:984
static __unused const u32 ar9287Modes_rx_gain_9287_1_1[][6]
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
Definition: reg.h:1846
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
Definition: reg.h:1814
#define CHANNEL_G_HT20
Definition: hw.h:317
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
static const u32 ar5416Bank7_9100[][2]
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
#define AR_PHY_MODE
Definition: ar9002_phy.h:396
#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
Definition: reg.h:912
static const u32 ar5416Bank0_9160[][2]
#define AR_RADIO_SREV_MAJOR
Definition: reg.h:895
#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
Definition: reg.h:1847
static const u32 ar5416Bank1_9100[][2]
static const u32 ar5416Modes_9100[][6]
#define AR_D_GBL_IFS_SLOT
Definition: reg.h:618
static const u32 ar5416Bank7[][2]
static __unused const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2]
uint8_t u8
Definition: stdint.h:19
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320
void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
uint32_t u32
Definition: stdint.h:23
static __unused const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6]
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR5416_EEP_MINOR_VER_19
Definition: eeprom.h:139
static const u32 ar5416Bank3_9160[][3]
static __unused const u32 ar9285Modes_9285_1_2[][6]
#define AR_WA_DEFAULT
Definition: reg.h:711
static __unused const u32 ar9285Modes_XE2_0_high_power[][6]
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
Definition: ath9k_hw.c:125