iPXE
ath9k_ar5008_phy.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/malloc.h>
21 #include <ipxe/io.h>
22 
23 #include "hw.h"
24 #include "hw-ops.h"
25 #include "../regd.h"
26 #include "ar9002_phy.h"
27 
28 /* All code below is for AR5008, AR9001, AR9002 */
29 
30 static const int firstep_table[] =
31 /* level: 0 1 2 3 4 5 6 7 8 */
32  { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
33 
34 static const int cycpwrThr1_table[] =
35 /* level: 0 1 2 3 4 5 6 7 8 */
36  { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
37 
38 /*
39  * register values to turn OFDM weak signal detection OFF
40  */
41 static const int m1ThreshLow_off = 127;
42 static const int m2ThreshLow_off = 127;
43 static const int m1Thresh_off = 127;
44 static const int m2Thresh_off = 127;
45 static const int m2CountThr_off = 31;
46 static const int m2CountThrLow_off = 63;
47 static const int m1ThreshLowExt_off = 127;
48 static const int m2ThreshLowExt_off = 127;
49 static const int m1ThreshExt_off = 127;
50 static const int m2ThreshExt_off = 127;
51 
52 
53 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
54  int col)
55 {
56  unsigned int i;
57 
58  for (i = 0; i < array->ia_rows; i++)
59  bank[i] = INI_RA(array, i, col);
60 }
61 
62 
63 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
64  ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
65 
66 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
67  u32 *data, unsigned int *writecnt)
68 {
69  unsigned int r;
70 
72 
73  for (r = 0; r < array->ia_rows; r++) {
74  REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
75  DO_DELAY(*writecnt);
76  }
77 
79 }
80 
81 /**
82  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
83  * @rfbuf:
84  * @reg32:
85  * @numBits:
86  * @firstBit:
87  * @column:
88  *
89  * Performs analog "swizzling" of parameters into their location.
90  * Used on external AR2133/AR5133 radios.
91  */
92 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
93  u32 numBits, u32 firstBit,
94  u32 column)
95 {
96  u32 tmp32, mask, arrayEntry, lastBit;
97  int32_t bitPosition, bitsLeft;
98 
99  tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
100  arrayEntry = (firstBit - 1) / 8;
101  bitPosition = (firstBit - 1) % 8;
102  bitsLeft = numBits;
103  while (bitsLeft > 0) {
104  lastBit = (bitPosition + bitsLeft > 8) ?
105  8 : bitPosition + bitsLeft;
106  mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
107  (column * 8);
108  rfBuf[arrayEntry] &= ~mask;
109  rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
110  (column * 8)) & mask;
111  bitsLeft -= 8 - bitPosition;
112  tmp32 = tmp32 >> (8 - bitPosition);
113  bitPosition = 0;
114  arrayEntry++;
115  }
116 }
117 
118 /*
119  * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
120  * rf_pwd_icsyndiv.
121  *
122  * Theoretical Rules:
123  * if 2 GHz band
124  * if forceBiasAuto
125  * if synth_freq < 2412
126  * bias = 0
127  * else if 2412 <= synth_freq <= 2422
128  * bias = 1
129  * else // synth_freq > 2422
130  * bias = 2
131  * else if forceBias > 0
132  * bias = forceBias & 7
133  * else
134  * no change, use value from ini file
135  * else
136  * no change, invalid band
137  *
138  * 1st Mod:
139  * 2422 also uses value of 2
140  * <approved>
141  *
142  * 2nd Mod:
143  * Less than 2412 uses value of 0, 2412 and above uses value of 2
144  */
145 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
146 {
147  u32 tmp_reg;
148  unsigned int reg_writes = 0;
149  u32 new_bias = 0;
150 
151  if (!AR_SREV_5416(ah) || synth_freq >= 3000)
152  return;
153 
154  if (synth_freq < 2412)
155  new_bias = 0;
156  else if (synth_freq < 2422)
157  new_bias = 1;
158  else
159  new_bias = 2;
160 
161  /* pre-reverse this field */
162  tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
163 
164  DBG("ath9k: Force rf_pwd_icsyndiv to %1d on %4d\n",
165  new_bias, synth_freq);
166 
167  /* swizzle rf_pwd_icsyndiv */
168  ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
169 
170  /* write Bank 6 with new params */
171  REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
172 }
173 
174 /**
175  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
176  * @ah: atheros hardware structure
177  * @chan:
178  *
179  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
180  * the channel value. Assumes writes enabled to analog bus and bank6 register
181  * cache in ah->analogBank6Data.
182  */
183 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
184 {
185  u32 channelSel = 0;
186  u32 bModeSynth = 0;
187  u32 aModeRefSel = 0;
188  u32 reg32 = 0;
189  u16 freq;
190  struct chan_centers centers;
191 
192  ath9k_hw_get_channel_centers(ah, chan, &centers);
193  freq = centers.synth_center;
194 
195  if (freq < 4800) {
196  u32 txctl;
197 
198  if (((freq - 2192) % 5) == 0) {
199  channelSel = ((freq - 672) * 2 - 3040) / 10;
200  bModeSynth = 0;
201  } else if (((freq - 2224) % 5) == 0) {
202  channelSel = ((freq - 704) * 2 - 3040) / 10;
203  bModeSynth = 1;
204  } else {
205  DBG("ath9k: Invalid channel %d MHz\n", freq);
206  return -EINVAL;
207  }
208 
209  channelSel = (channelSel << 2) & 0xff;
210  channelSel = ath9k_hw_reverse_bits(channelSel, 8);
211 
212  txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
213  if (freq == 2484) {
214 
216  txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
217  } else {
219  txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
220  }
221 
222  } else if ((freq % 20) == 0 && freq >= 5120) {
223  channelSel =
224  ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
225  aModeRefSel = ath9k_hw_reverse_bits(1, 2);
226  } else if ((freq % 10) == 0) {
227  channelSel =
228  ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
230  aModeRefSel = ath9k_hw_reverse_bits(2, 2);
231  else
232  aModeRefSel = ath9k_hw_reverse_bits(1, 2);
233  } else if ((freq % 5) == 0) {
234  channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
235  aModeRefSel = ath9k_hw_reverse_bits(1, 2);
236  } else {
237  DBG("ath9k: Invalid channel %d MHz\n", freq);
238  return -EINVAL;
239  }
240 
241  ar5008_hw_force_bias(ah, freq);
242 
243  reg32 =
244  (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
245  (1 << 5) | 0x1;
246 
247  REG_WRITE(ah, AR_PHY(0x37), reg32);
248 
249  ah->curchan = chan;
250  ah->curchan_rad_index = -1;
251 
252  return 0;
253 }
254 
255 /**
256  * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
257  * @ah: atheros hardware structure
258  * @chan:
259  *
260  * For non single-chip solutions. Converts to baseband spur frequency given the
261  * input channel frequency and compute register settings below.
262  */
263 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
264  struct ath9k_channel *chan)
265 {
266  int bb_spur = AR_NO_SPUR;
267  int bin, cur_bin;
268  int spur_freq_sd;
269  int spur_delta_phase;
270  int denominator;
271  int upper, lower, cur_vit_mask;
272  int tmp, new;
273  int i;
274  static int pilot_mask_reg[4] = {
277  };
278  static int chan_mask_reg[4] = {
281  };
282  static int inc[4] = { 0, 100, 0, 0 };
283 
284  int8_t mask_m[123];
285  int8_t mask_p[123];
286  int8_t mask_amt;
287  int tmp_mask;
288  int cur_bb_spur;
289  int is2GHz = IS_CHAN_2GHZ(chan);
290 
291  memset(&mask_m, 0, sizeof(int8_t) * 123);
292  memset(&mask_p, 0, sizeof(int8_t) * 123);
293 
294  for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
295  cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
296  if (AR_NO_SPUR == cur_bb_spur)
297  break;
298  cur_bb_spur = cur_bb_spur - (chan->channel * 10);
299  if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
300  bb_spur = cur_bb_spur;
301  break;
302  }
303  }
304 
305  if (AR_NO_SPUR == bb_spur)
306  return;
307 
308  bin = bb_spur * 32;
309 
315 
316  REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
317 
324 
325  spur_delta_phase = ((bb_spur * 524288) / 100) &
327 
328  denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
329  spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
330 
332  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
333  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
335 
336  cur_bin = -6000;
337  upper = bin + 100;
338  lower = bin - 100;
339 
340  for (i = 0; i < 4; i++) {
341  int pilot_mask = 0;
342  int chan_mask = 0;
343  int bp = 0;
344  for (bp = 0; bp < 30; bp++) {
345  if ((cur_bin > lower) && (cur_bin < upper)) {
346  pilot_mask = pilot_mask | 0x1 << bp;
347  chan_mask = chan_mask | 0x1 << bp;
348  }
349  cur_bin += 100;
350  }
351  cur_bin += inc[i];
352  REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
353  REG_WRITE(ah, chan_mask_reg[i], chan_mask);
354  }
355 
356  cur_vit_mask = 6100;
357  upper = bin + 120;
358  lower = bin - 120;
359 
360  for (i = 0; i < 123; i++) {
361  if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
362 
363  /* workaround for gcc bug #37014 */
364  volatile int tmp_v = abs(cur_vit_mask - bin);
365 
366  if (tmp_v < 75)
367  mask_amt = 1;
368  else
369  mask_amt = 0;
370  if (cur_vit_mask < 0)
371  mask_m[abs(cur_vit_mask / 100)] = mask_amt;
372  else
373  mask_p[cur_vit_mask / 100] = mask_amt;
374  }
375  cur_vit_mask -= 100;
376  }
377 
378  tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
379  | (mask_m[48] << 26) | (mask_m[49] << 24)
380  | (mask_m[50] << 22) | (mask_m[51] << 20)
381  | (mask_m[52] << 18) | (mask_m[53] << 16)
382  | (mask_m[54] << 14) | (mask_m[55] << 12)
383  | (mask_m[56] << 10) | (mask_m[57] << 8)
384  | (mask_m[58] << 6) | (mask_m[59] << 4)
385  | (mask_m[60] << 2) | (mask_m[61] << 0);
386  REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
388 
389  tmp_mask = (mask_m[31] << 28)
390  | (mask_m[32] << 26) | (mask_m[33] << 24)
391  | (mask_m[34] << 22) | (mask_m[35] << 20)
392  | (mask_m[36] << 18) | (mask_m[37] << 16)
393  | (mask_m[48] << 14) | (mask_m[39] << 12)
394  | (mask_m[40] << 10) | (mask_m[41] << 8)
395  | (mask_m[42] << 6) | (mask_m[43] << 4)
396  | (mask_m[44] << 2) | (mask_m[45] << 0);
397  REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
398  REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
399 
400  tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
401  | (mask_m[18] << 26) | (mask_m[18] << 24)
402  | (mask_m[20] << 22) | (mask_m[20] << 20)
403  | (mask_m[22] << 18) | (mask_m[22] << 16)
404  | (mask_m[24] << 14) | (mask_m[24] << 12)
405  | (mask_m[25] << 10) | (mask_m[26] << 8)
406  | (mask_m[27] << 6) | (mask_m[28] << 4)
407  | (mask_m[29] << 2) | (mask_m[30] << 0);
408  REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
409  REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
410 
411  tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
412  | (mask_m[2] << 26) | (mask_m[3] << 24)
413  | (mask_m[4] << 22) | (mask_m[5] << 20)
414  | (mask_m[6] << 18) | (mask_m[7] << 16)
415  | (mask_m[8] << 14) | (mask_m[9] << 12)
416  | (mask_m[10] << 10) | (mask_m[11] << 8)
417  | (mask_m[12] << 6) | (mask_m[13] << 4)
418  | (mask_m[14] << 2) | (mask_m[15] << 0);
419  REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
420  REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
421 
422  tmp_mask = (mask_p[15] << 28)
423  | (mask_p[14] << 26) | (mask_p[13] << 24)
424  | (mask_p[12] << 22) | (mask_p[11] << 20)
425  | (mask_p[10] << 18) | (mask_p[9] << 16)
426  | (mask_p[8] << 14) | (mask_p[7] << 12)
427  | (mask_p[6] << 10) | (mask_p[5] << 8)
428  | (mask_p[4] << 6) | (mask_p[3] << 4)
429  | (mask_p[2] << 2) | (mask_p[1] << 0);
430  REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
431  REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
432 
433  tmp_mask = (mask_p[30] << 28)
434  | (mask_p[29] << 26) | (mask_p[28] << 24)
435  | (mask_p[27] << 22) | (mask_p[26] << 20)
436  | (mask_p[25] << 18) | (mask_p[24] << 16)
437  | (mask_p[23] << 14) | (mask_p[22] << 12)
438  | (mask_p[21] << 10) | (mask_p[20] << 8)
439  | (mask_p[19] << 6) | (mask_p[18] << 4)
440  | (mask_p[17] << 2) | (mask_p[16] << 0);
441  REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
442  REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
443 
444  tmp_mask = (mask_p[45] << 28)
445  | (mask_p[44] << 26) | (mask_p[43] << 24)
446  | (mask_p[42] << 22) | (mask_p[41] << 20)
447  | (mask_p[40] << 18) | (mask_p[39] << 16)
448  | (mask_p[38] << 14) | (mask_p[37] << 12)
449  | (mask_p[36] << 10) | (mask_p[35] << 8)
450  | (mask_p[34] << 6) | (mask_p[33] << 4)
451  | (mask_p[32] << 2) | (mask_p[31] << 0);
452  REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
453  REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
454 
455  tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
456  | (mask_p[59] << 26) | (mask_p[58] << 24)
457  | (mask_p[57] << 22) | (mask_p[56] << 20)
458  | (mask_p[55] << 18) | (mask_p[54] << 16)
459  | (mask_p[53] << 14) | (mask_p[52] << 12)
460  | (mask_p[51] << 10) | (mask_p[50] << 8)
461  | (mask_p[49] << 6) | (mask_p[48] << 4)
462  | (mask_p[47] << 2) | (mask_p[46] << 0);
463  REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
464  REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
465 }
466 
467 /**
468  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
469  * @ah: atheros hardware structure
470  *
471  * Only required for older devices with external AR2133/AR5133 radios.
472  */
474 {
475 #define ATH_ALLOC_BANK(bank, size) do { \
476  bank = zalloc((sizeof(u32) * size)); \
477  if (!bank) { \
478  DBG("ath9k: Cannot allocate RF banks\n"); \
479  return -ENOMEM; \
480  } \
481  } while (0);
482 
483  ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
484  ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
485  ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
486  ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
487  ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
488  ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
489  ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
490  ATH_ALLOC_BANK(ah->addac5416_21,
491  ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
492  ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
493 
494  return 0;
495 #undef ATH_ALLOC_BANK
496 }
497 
498 
499 /**
500  * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
501  * @ah: atheros hardware struture
502  * For the external AR2133/AR5133 radios banks.
503  */
505 {
506 #define ATH_FREE_BANK(bank) do { \
507  free(bank); \
508  bank = NULL; \
509  } while (0);
510 
511  ATH_FREE_BANK(ah->analogBank0Data);
512  ATH_FREE_BANK(ah->analogBank1Data);
513  ATH_FREE_BANK(ah->analogBank2Data);
514  ATH_FREE_BANK(ah->analogBank3Data);
515  ATH_FREE_BANK(ah->analogBank6Data);
516  ATH_FREE_BANK(ah->analogBank6TPCData);
517  ATH_FREE_BANK(ah->analogBank7Data);
518  ATH_FREE_BANK(ah->addac5416_21);
519  ATH_FREE_BANK(ah->bank6Temp);
520 
521 #undef ATH_FREE_BANK
522 }
523 
524 /* *
525  * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
526  * @ah: atheros hardware structure
527  * @chan:
528  * @modesIndex:
529  *
530  * Used for the external AR2133/AR5133 radios.
531  *
532  * Reads the EEPROM header info from the device structure and programs
533  * all rf registers. This routine requires access to the analog
534  * rf device. This is not required for single-chip devices.
535  */
536 static int ar5008_hw_set_rf_regs(struct ath_hw *ah,
537  struct ath9k_channel *chan,
538  u16 modesIndex)
539 {
540  u32 eepMinorRev;
541  u32 ob5GHz = 0, db5GHz = 0;
542  u32 ob2GHz = 0, db2GHz = 0;
543  unsigned int regWrites = 0;
544 
545  /*
546  * Software does not need to program bank data
547  * for single chip devices, that is AR9280 or anything
548  * after that.
549  */
551  return 1;
552 
553  /* Setup rf parameters */
554  eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
555 
556  /* Setup Bank 0 Write */
557  ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
558 
559  /* Setup Bank 1 Write */
560  ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
561 
562  /* Setup Bank 2 Write */
563  ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
564 
565  /* Setup Bank 6 Write */
566  ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
567  modesIndex);
568  {
569  unsigned int i;
570  for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
571  ah->analogBank6Data[i] =
572  INI_RA(&ah->iniBank6TPC, i, modesIndex);
573  }
574  }
575 
576  /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
577  if (eepMinorRev >= 2) {
578  if (IS_CHAN_2GHZ(chan)) {
579  ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
580  db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
581  ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
582  ob2GHz, 3, 197, 0);
583  ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
584  db2GHz, 3, 194, 0);
585  } else {
586  ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
587  db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
588  ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
589  ob5GHz, 3, 203, 0);
590  ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
591  db5GHz, 3, 200, 0);
592  }
593  }
594 
595  /* Setup Bank 7 Setup */
596  ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
597 
598  /* Write Analog registers */
599  REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
600  regWrites);
601  REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
602  regWrites);
603  REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
604  regWrites);
605  REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
606  regWrites);
607  REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
608  regWrites);
609  REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
610  regWrites);
611 
612  return 1;
613 }
614 
615 static void ar5008_hw_init_bb(struct ath_hw *ah,
616  struct ath9k_channel *chan)
617 {
618  u32 synthDelay;
619 
621  if (IS_CHAN_B(chan))
622  synthDelay = (4 * synthDelay) / 22;
623  else
624  synthDelay /= 10;
625 
627 
628  udelay(synthDelay + BASE_ACTIVATE_DELAY);
629 }
630 
632 {
633  int rx_chainmask, tx_chainmask;
634 
635  rx_chainmask = ah->rxchainmask;
636  tx_chainmask = ah->txchainmask;
637 
638 
639  switch (rx_chainmask) {
640  case 0x5:
643  /* Fall through */
644  case 0x3:
645  if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
648  break;
649  }
650  /* Fall through */
651  case 0x1:
652  case 0x2:
653  case 0x7:
655  REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
656  REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
657  break;
658  default:
660  break;
661  }
662 
663  REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
664 
666 
667  if (tx_chainmask == 0x5) {
670  }
671  if (AR_SREV_9100(ah))
673  REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
674 }
675 
676 static void ar5008_hw_override_ini(struct ath_hw *ah,
677  struct ath9k_channel *chan __unused)
678 {
679  u32 val;
680 
681  /*
682  * Set the RX_ABORT and RX_DIS and clear if off only after
683  * RXE is set for MAC. This prevents frames with corrupted
684  * descriptor status.
685  */
687 
690 
691  if (!AR_SREV_9271(ah))
693 
696 
698  }
699 
702  return;
703  /*
704  * Disable BB clock gating
705  * Necessary to avoid issues on AR5416 2.0
706  */
707  REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
708 
709  /*
710  * Disable RIFS search on some chips to avoid baseband
711  * hang issues.
712  */
713  if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
717  }
718 }
719 
721  struct ath9k_channel *chan)
722 {
723  u32 phymode;
724  u32 enableDacFifo = 0;
725 
727  enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
729 
731  | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
732 
733  if (IS_CHAN_HT40(chan)) {
734  phymode |= AR_PHY_FC_DYN2040_EN;
735 
736  if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
737  (chan->chanmode == CHANNEL_G_HT40PLUS))
738  phymode |= AR_PHY_FC_DYN2040_PRI_CH;
739 
740  }
741  REG_WRITE(ah, AR_PHY_TURBO, phymode);
742 
744 
746 
749 
751 }
752 
753 
754 static int ar5008_hw_process_ini(struct ath_hw *ah,
755  struct ath9k_channel *chan)
756 {
757  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
758  struct ath_common *common = ath9k_hw_common(ah);
759  unsigned int i, regWrites = 0;
760  struct net80211_channel *channel = chan->chan;
761  u32 modesIndex, freqIndex;
762 
763  switch (chan->chanmode) {
764  case CHANNEL_A:
765  case CHANNEL_A_HT20:
766  modesIndex = 1;
767  freqIndex = 1;
768  break;
769  case CHANNEL_A_HT40PLUS:
770  case CHANNEL_A_HT40MINUS:
771  modesIndex = 2;
772  freqIndex = 1;
773  break;
774  case CHANNEL_G:
775  case CHANNEL_G_HT20:
776  case CHANNEL_B:
777  modesIndex = 4;
778  freqIndex = 2;
779  break;
780  case CHANNEL_G_HT40PLUS:
781  case CHANNEL_G_HT40MINUS:
782  modesIndex = 3;
783  freqIndex = 2;
784  break;
785 
786  default:
787  return -EINVAL;
788  }
789 
790  /*
791  * Set correct baseband to analog shift setting to
792  * access analog chips.
793  */
794  REG_WRITE(ah, AR_PHY(0), 0x00000007);
795 
796  /* Write ADDAC shifts */
798  ah->eep_ops->set_addac(ah, chan);
799 
801  REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
802  } else {
803  struct ar5416IniArray temp;
804  u32 addacSize =
805  sizeof(u32) * ah->iniAddac.ia_rows *
806  ah->iniAddac.ia_columns;
807 
808  /* For AR5416 2.0/2.1 */
809  memcpy(ah->addac5416_21,
810  ah->iniAddac.ia_array, addacSize);
811 
812  /* override CLKDRV value at [row, column] = [31, 1] */
813  (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
814 
815  temp.ia_array = ah->addac5416_21;
816  temp.ia_columns = ah->iniAddac.ia_columns;
817  temp.ia_rows = ah->iniAddac.ia_rows;
818  REG_WRITE_ARRAY(&temp, 1, regWrites);
819  }
820 
822 
824 
825  for (i = 0; i < ah->iniModes.ia_rows; i++) {
826  u32 reg = INI_RA(&ah->iniModes, i, 0);
827  u32 val = INI_RA(&ah->iniModes, i, modesIndex);
828 
829  if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
831 
832  REG_WRITE(ah, reg, val);
833 
834  if (reg >= 0x7800 && reg < 0x78a0
835  && ah->config.analog_shiftreg
836  && (common->bus_ops->ath_bus_type != ATH_USB)) {
837  udelay(100);
838  }
839 
840  DO_DELAY(regWrites);
841  }
842 
844 
846  REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
847 
850  REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
851 
852  if (AR_SREV_9271_10(ah))
853  REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
854  modesIndex, regWrites);
855 
857 
858  /* Write common array parameters */
859  for (i = 0; i < ah->iniCommon.ia_rows; i++) {
860  u32 reg = INI_RA(&ah->iniCommon, i, 0);
861  u32 val = INI_RA(&ah->iniCommon, i, 1);
862 
863  REG_WRITE(ah, reg, val);
864 
865  if (reg >= 0x7800 && reg < 0x78a0
866  && ah->config.analog_shiftreg
867  && (common->bus_ops->ath_bus_type != ATH_USB)) {
868  udelay(100);
869  }
870 
871  DO_DELAY(regWrites);
872  }
873 
875 
876  if (AR_SREV_9271(ah)) {
877  if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
878  REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
879  modesIndex, regWrites);
880  else
881  REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
882  modesIndex, regWrites);
883  }
884 
885  REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
886 
887  if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
888  REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
889  regWrites);
890  }
891 
892  ar5008_hw_override_ini(ah, chan);
896 
897  /* Set TX power */
898  ah->eep_ops->set_txpower(ah, chan,
899  ath9k_regd_get_ctl(regulatory, chan),
900  0,
901  channel->maxpower * 2,
903  (u32) regulatory->power_limit), 0);
904 
905  /* Write analog registers */
906  if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
907  DBG("ath9k: ar5416SetRfRegs failed\n");
908  return -EIO;
909  }
910 
911  return 0;
912 }
913 
914 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
915 {
916  u32 rfMode = 0;
917 
918  if (chan == NULL)
919  return;
920 
921  rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
923 
925  rfMode |= (IS_CHAN_5GHZ(chan)) ?
927 
928  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
930 
931  REG_WRITE(ah, AR_PHY_MODE, rfMode);
932 }
933 
935 {
937 }
938 
939 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
940  struct ath9k_channel *chan)
941 {
942  u32 coef_scaled, ds_coef_exp, ds_coef_man;
943  u32 clockMhzScaled = 0x64000000;
944  struct chan_centers centers;
945 
946  if (IS_CHAN_HALF_RATE(chan))
947  clockMhzScaled = clockMhzScaled >> 1;
948  else if (IS_CHAN_QUARTER_RATE(chan))
949  clockMhzScaled = clockMhzScaled >> 2;
950 
951  ath9k_hw_get_channel_centers(ah, chan, &centers);
952  coef_scaled = clockMhzScaled / centers.synth_center;
953 
954  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
955  &ds_coef_exp);
956 
958  AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
960  AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
961 
962  coef_scaled = (9 * coef_scaled) / 10;
963 
964  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
965  &ds_coef_exp);
966 
968  AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
970  AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
971 }
972 
973 static int ar5008_hw_rfbus_req(struct ath_hw *ah)
974 {
978 }
979 
980 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
981 {
983  if (IS_CHAN_B(ah->curchan))
984  synthDelay = (4 * synthDelay) / 22;
985  else
986  synthDelay /= 10;
987 
988  udelay(synthDelay + BASE_ACTIVATE_DELAY);
989 
991 }
992 
993 static void ar5008_restore_chainmask(struct ath_hw *ah)
994 {
995  int rx_chainmask = ah->rxchainmask;
996 
997  if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
998  REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
999  REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1000  }
1001 }
1002 
1003 static void ar5008_set_diversity(struct ath_hw *ah, int value)
1004 {
1006  if (value)
1008  else
1011 }
1012 
1014  struct ath9k_channel *chan)
1015 {
1016  if (chan && IS_CHAN_5GHZ(chan))
1017  return 0x1450;
1018  return 0x1458;
1019 }
1020 
1022  struct ath9k_channel *chan)
1023 {
1024  u32 pll;
1025 
1026  pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1027 
1028  if (chan && IS_CHAN_HALF_RATE(chan))
1029  pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1030  else if (chan && IS_CHAN_QUARTER_RATE(chan))
1031  pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1032 
1033  if (chan && IS_CHAN_5GHZ(chan))
1034  pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1035  else
1036  pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1037 
1038  return pll;
1039 }
1040 
1042  struct ath9k_channel *chan)
1043 {
1044  u32 pll;
1045 
1047 
1048  if (chan && IS_CHAN_HALF_RATE(chan))
1049  pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1050  else if (chan && IS_CHAN_QUARTER_RATE(chan))
1051  pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1052 
1053  if (chan && IS_CHAN_5GHZ(chan))
1054  pll |= SM(0xa, AR_RTC_PLL_DIV);
1055  else
1056  pll |= SM(0xb, AR_RTC_PLL_DIV);
1057 
1058  return pll;
1059 }
1060 
1062  enum ath9k_ani_cmd cmd,
1063  int param)
1064 {
1065  struct ar5416AniState *aniState = &ah->curchan->ani;
1066 
1067  switch (cmd & ah->ani_function) {
1069  u32 level = param;
1070 
1071  if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1072  DBG("ath9k: "
1073  "level out of range (%d > %zd)\n",
1074  level, ARRAY_SIZE(ah->totalSizeDesired));
1075  return 0;
1076  }
1077 
1080  ah->totalSizeDesired[level]);
1083  ah->coarse_low[level]);
1086  ah->coarse_high[level]);
1089  ah->firpwr[level]);
1090 
1091  if (level > aniState->noiseImmunityLevel)
1092  ah->stats.ast_ani_niup++;
1093  else if (level < aniState->noiseImmunityLevel)
1094  ah->stats.ast_ani_nidown++;
1095  aniState->noiseImmunityLevel = level;
1096  break;
1097  }
1099  static const int m1ThreshLow[] = { 127, 50 };
1100  static const int m2ThreshLow[] = { 127, 40 };
1101  static const int m1Thresh[] = { 127, 0x4d };
1102  static const int m2Thresh[] = { 127, 0x40 };
1103  static const int m2CountThr[] = { 31, 16 };
1104  static const int m2CountThrLow[] = { 63, 48 };
1105  u32 on = param ? 1 : 0;
1106 
1109  m1ThreshLow[on]);
1112  m2ThreshLow[on]);
1115  m1Thresh[on]);
1118  m2Thresh[on]);
1121  m2CountThr[on]);
1124  m2CountThrLow[on]);
1125 
1128  m1ThreshLow[on]);
1131  m2ThreshLow[on]);
1134  m1Thresh[on]);
1137  m2Thresh[on]);
1138 
1139  if (on)
1142  else
1145 
1146  if (on != aniState->ofdmWeakSigDetect) {
1147  if (on)
1148  ah->stats.ast_ani_ofdmon++;
1149  else
1150  ah->stats.ast_ani_ofdmoff++;
1151  aniState->ofdmWeakSigDetect = on;
1152  }
1153  break;
1154  }
1156  static const int weakSigThrCck[] = { 8, 6 };
1157  u32 high = param ? 1 : 0;
1158 
1161  weakSigThrCck[high]);
1162  if (high != aniState->cckWeakSigThreshold) {
1163  if (high)
1164  ah->stats.ast_ani_cckhigh++;
1165  else
1166  ah->stats.ast_ani_ccklow++;
1167  aniState->cckWeakSigThreshold = high;
1168  }
1169  break;
1170  }
1172  static const int firstep[] = { 0, 4, 8 };
1173  u32 level = param;
1174 
1175  if (level >= ARRAY_SIZE(firstep)) {
1176  DBG("ath9k: "
1177  "level out of range (%d > %zd)\n",
1178  level, ARRAY_SIZE(firstep));
1179  return 0;
1180  }
1183  firstep[level]);
1184  if (level > aniState->firstepLevel)
1185  ah->stats.ast_ani_stepup++;
1186  else if (level < aniState->firstepLevel)
1187  ah->stats.ast_ani_stepdown++;
1188  aniState->firstepLevel = level;
1189  break;
1190  }
1192  static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1193  u32 level = param;
1194 
1195  if (level >= ARRAY_SIZE(cycpwrThr1)) {
1196  DBG("ath9k: "
1197  "level out of range (%d > %zd)\n",
1198  level, ARRAY_SIZE(cycpwrThr1));
1199  return 0;
1200  }
1203  cycpwrThr1[level]);
1204  if (level > aniState->spurImmunityLevel)
1205  ah->stats.ast_ani_spurup++;
1206  else if (level < aniState->spurImmunityLevel)
1207  ah->stats.ast_ani_spurdown++;
1208  aniState->spurImmunityLevel = level;
1209  break;
1210  }
1211  case ATH9K_ANI_PRESENT:
1212  break;
1213  default:
1214  DBG("ath9k: invalid cmd %d\n", cmd);
1215  return 0;
1216  }
1217 
1218  DBG2("ath9k: ANI parameters:\n");
1219  DBG2(
1220  "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetect=%d\n",
1221  aniState->noiseImmunityLevel,
1222  aniState->spurImmunityLevel,
1223  aniState->ofdmWeakSigDetect);
1224  DBG2(
1225  "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1226  aniState->cckWeakSigThreshold,
1227  aniState->firstepLevel,
1228  aniState->listenTime);
1229  DBG2(
1230  "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1231  aniState->ofdmPhyErrCount,
1232  aniState->cckPhyErrCount);
1233 
1234  return 1;
1235 }
1236 
1238  enum ath9k_ani_cmd cmd,
1239  int param)
1240 {
1241  struct ath9k_channel *chan = ah->curchan;
1242  struct ar5416AniState *aniState = &chan->ani;
1243  s32 value, value2;
1244 
1245  switch (cmd & ah->ani_function) {
1247  /*
1248  * on == 1 means ofdm weak signal detection is ON
1249  * on == 1 is the default, for less noise immunity
1250  *
1251  * on == 0 means ofdm weak signal detection is OFF
1252  * on == 0 means more noise imm
1253  */
1254  u32 on = param ? 1 : 0;
1255  /*
1256  * make register setting for default
1257  * (weak sig detect ON) come from INI file
1258  */
1259  int m1ThreshLow = on ?
1260  aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1261  int m2ThreshLow = on ?
1262  aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1263  int m1Thresh = on ?
1264  aniState->iniDef.m1Thresh : m1Thresh_off;
1265  int m2Thresh = on ?
1266  aniState->iniDef.m2Thresh : m2Thresh_off;
1267  int m2CountThr = on ?
1268  aniState->iniDef.m2CountThr : m2CountThr_off;
1269  int m2CountThrLow = on ?
1271  int m1ThreshLowExt = on ?
1273  int m2ThreshLowExt = on ?
1275  int m1ThreshExt = on ?
1276  aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1277  int m2ThreshExt = on ?
1278  aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1279 
1282  m1ThreshLow);
1285  m2ThreshLow);
1287  AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1289  AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1291  AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1294  m2CountThrLow);
1295 
1297  AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1299  AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1301  AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1303  AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1304 
1305  if (on)
1308  else
1311 
1312  if (on != aniState->ofdmWeakSigDetect) {
1313  DBG2("ath9k: "
1314  "** ch %d: ofdm weak signal: %s=>%s\n",
1315  chan->channel,
1316  aniState->ofdmWeakSigDetect ?
1317  "on" : "off",
1318  on ? "on" : "off");
1319  if (on)
1320  ah->stats.ast_ani_ofdmon++;
1321  else
1322  ah->stats.ast_ani_ofdmoff++;
1323  aniState->ofdmWeakSigDetect = on;
1324  }
1325  break;
1326  }
1328  u32 level = param;
1329 
1330  if (level >= ARRAY_SIZE(firstep_table)) {
1331  DBG("ath9k: "
1332  "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
1333  level, ARRAY_SIZE(firstep_table));
1334  return 0;
1335  }
1336 
1337  /*
1338  * make register setting relative to default
1339  * from INI file & cap value
1340  */
1341  value = firstep_table[level] -
1343  aniState->iniDef.firstep;
1350  value);
1351  /*
1352  * we need to set first step low register too
1353  * make register setting relative to default
1354  * from INI file & cap value
1355  */
1356  value2 = firstep_table[level] -
1358  aniState->iniDef.firstepLow;
1359  if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1361  if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1363 
1365  AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1366 
1367  if (level != aniState->firstepLevel) {
1368  DBG2("ath9k: "
1369  "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1370  chan->channel,
1371  aniState->firstepLevel,
1372  level,
1374  value,
1375  aniState->iniDef.firstep);
1376  DBG2("ath9k: "
1377  "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1378  chan->channel,
1379  aniState->firstepLevel,
1380  level,
1382  value2,
1383  aniState->iniDef.firstepLow);
1384  if (level > aniState->firstepLevel)
1385  ah->stats.ast_ani_stepup++;
1386  else if (level < aniState->firstepLevel)
1387  ah->stats.ast_ani_stepdown++;
1388  aniState->firstepLevel = level;
1389  }
1390  break;
1391  }
1393  u32 level = param;
1394 
1395  if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1396  DBG("ath9k: "
1397  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
1398  level, ARRAY_SIZE(cycpwrThr1_table));
1399  return 0;
1400  }
1401  /*
1402  * make register setting relative to default
1403  * from INI file & cap value
1404  */
1405  value = cycpwrThr1_table[level] -
1407  aniState->iniDef.cycpwrThr1;
1414  value);
1415 
1416  /*
1417  * set AR_PHY_EXT_CCA for extension channel
1418  * make register setting relative to default
1419  * from INI file & cap value
1420  */
1421  value2 = cycpwrThr1_table[level] -
1423  aniState->iniDef.cycpwrThr1Ext;
1424  if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1426  if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1430 
1431  if (level != aniState->spurImmunityLevel) {
1432  DBG2("ath9k: "
1433  "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1434  chan->channel,
1435  aniState->spurImmunityLevel,
1436  level,
1438  value,
1439  aniState->iniDef.cycpwrThr1);
1440  DBG2("ath9k: "
1441  "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1442  chan->channel,
1443  aniState->spurImmunityLevel,
1444  level,
1446  value2,
1447  aniState->iniDef.cycpwrThr1Ext);
1448  if (level > aniState->spurImmunityLevel)
1449  ah->stats.ast_ani_spurup++;
1450  else if (level < aniState->spurImmunityLevel)
1451  ah->stats.ast_ani_spurdown++;
1452  aniState->spurImmunityLevel = level;
1453  }
1454  break;
1455  }
1456  case ATH9K_ANI_MRC_CCK:
1457  /*
1458  * You should not see this as AR5008, AR9001, AR9002
1459  * does not have hardware support for MRC CCK.
1460  */
1461  break;
1462  case ATH9K_ANI_PRESENT:
1463  break;
1464  default:
1465  DBG("ath9k: invalid cmd %d\n", cmd);
1466  return 0;
1467  }
1468 
1469  DBG2("ath9k: "
1470  "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1471  aniState->spurImmunityLevel,
1472  aniState->ofdmWeakSigDetect ? "on" : "off",
1473  aniState->firstepLevel,
1474  !aniState->mrcCCKOff ? "on" : "off",
1475  aniState->listenTime,
1476  aniState->ofdmPhyErrCount,
1477  aniState->cckPhyErrCount);
1478  return 1;
1479 }
1480 
1481 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1482  int16_t nfarray[NUM_NF_READINGS])
1483 {
1484  int16_t nf;
1485 
1487  nfarray[0] = sign_extend32(nf, 8);
1488 
1490  nfarray[1] = sign_extend32(nf, 8);
1491 
1493  nfarray[2] = sign_extend32(nf, 8);
1494 
1495  if (!IS_CHAN_HT40(ah->curchan))
1496  return;
1497 
1499  nfarray[3] = sign_extend32(nf, 8);
1500 
1502  nfarray[4] = sign_extend32(nf, 8);
1503 
1505  nfarray[5] = sign_extend32(nf, 8);
1506 }
1507 
1508 /*
1509  * Initialize the ANI register values with default (ini) values.
1510  * This routine is called during a (full) hardware reset after
1511  * all the registers are initialised from the INI.
1512  */
1514 {
1515  struct ath9k_channel *chan = ah->curchan;
1516  struct ar5416AniState *aniState = &chan->ani;
1517  struct ath9k_ani_default *iniDef;
1518  u32 val;
1519 
1520  iniDef = &aniState->iniDef;
1521 
1522  DBG2("ath9k: ver %d.%d chan %d Mhz/0x%x\n",
1523  ah->hw_version.macVersion,
1524  ah->hw_version.macRev,
1525  chan->channel,
1526  chan->channelFlags);
1527 
1529  iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1530  iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1532 
1537 
1543  iniDef->firstep = REG_READ_FIELD(ah,
1546  iniDef->firstepLow = REG_READ_FIELD(ah,
1549  iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1552  iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1555 
1556  /* these levels just got reset to defaults by the INI */
1560  aniState->mrcCCKOff = 1; /* not available on pre AR9003 */
1561 }
1562 
1563 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1564 {
1567  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1570  ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1571 }
1572 
1574  struct ath_hw_radar_conf *conf)
1575 {
1576  u32 radar_0 = 0, radar_1 = 0;
1577 
1578  if (!conf) {
1580  return;
1581  }
1582 
1584  radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1585  radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1586  radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1587  radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1588  radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1589 
1590  radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1591  radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1592  radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1594  radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1595 
1596  REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1597  REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1598  if (conf->ext_channel)
1600  else
1602 }
1603 
1604 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1605 {
1606  struct ath_hw_radar_conf *conf = &ah->radar_conf;
1607 
1608  conf->fir_power = -33;
1609  conf->radar_rssi = 20;
1610  conf->pulse_height = 10;
1611  conf->pulse_rssi = 24;
1612  conf->pulse_inband = 15;
1613  conf->pulse_maxlen = 255;
1614  conf->pulse_inband_step = 12;
1615  conf->radar_inband = 8;
1616 }
1617 
1619 {
1620  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1621  static const u32 ar5416_cca_regs[6] = {
1622  AR_PHY_CCA,
1628  };
1629 
1630  priv_ops->rf_set_freq = ar5008_hw_set_channel;
1632 
1635  priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1637  priv_ops->init_bb = ar5008_hw_init_bb;
1638  priv_ops->process_ini = ar5008_hw_process_ini;
1639  priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1642  priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1643  priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1645  priv_ops->set_diversity = ar5008_set_diversity;
1646  priv_ops->do_getnf = ar5008_hw_do_getnf;
1648 
1649  if (modparam_force_new_ani) {
1652  } else
1654 
1655  if (AR_SREV_9100(ah))
1657  else if (AR_SREV_9160_10_OR_LATER(ah))
1659  else
1661 
1664  memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1665 }
#define BASE_ACTIVATE_DELAY
Definition: hw.h:133
static const int m1ThreshExt_off
#define AR_PHY(_n)
Definition: phy.h:27
#define AR_PHY_TIMING8
Definition: ar9002_phy.h:272
#define AR_PHY_SFCORR_LOW
Definition: ar9002_phy.h:139
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW
Definition: ar9002_phy.h:145
#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ
Definition: ar9002_phy.h:594
static const int m2ThreshExt_off
uint16_t u16
Definition: stdint.h:21
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:577
#define AR_PHY_CCA_NOM_VAL_5416_5GHZ
Definition: ar9002_phy.h:590
#define AR_PHY_TIMING7
Definition: ar9002_phy.h:271
static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, u32 *data, unsigned int *writecnt)
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR_RTC_9160_PLL_REFDIV
Definition: reg.h:1152
void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
u16 channel
Definition: hw.h:349
iPXE I/O API
static const int m1ThreshLow_off
u32 chanmode
Definition: hw.h:351
#define AR_DIAG_RX_ABORT
Definition: reg.h:1524
#define AR_PHY_CH2_MINCCA_PWR
Definition: ar9002_phy.h:576
#define AR_PHY_MASK2_M_16_30
Definition: ar9002_phy.h:511
#define AR_PHY_TIMING9
Definition: ar9002_phy.h:290
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
u32 listenTime
Definition: ani.h:130
Definition: hw.h:656
u16 synth_center
Definition: hw.h:422
static int ar5008_hw_ani_control_new(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
#define AR_PHY_CCK_TX_CTRL_JAPAN
Definition: ar9002_phy.h:409
#define AR_PHY_CH1_CCA
Definition: ar9002_phy.h:569
u16 m1ThreshLow
Definition: ani.h:103
#define AR_GTXTO_TIMEOUT_LIMIT_S
Definition: reg.h:155
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW
Definition: ar9002_phy.h:143
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
#define AR_PHY_HALFGI_DSC_MAN
Definition: ar9002_phy.h:356
u8 spurImmunityLevel
Definition: ani.h:126
#define AR_PHY_MASK2_M_31_45
Definition: ar9002_phy.h:510
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
#define AR_PHY_AGC_CTL1_COARSE_LOW
Definition: ar9002_phy.h:124
u8 mrcCCKOff
Definition: ani.h:125
int32_t s32
Definition: stdint.h:22
#define AR_PHY_RFBUS_REQ_EN
Definition: ar9002_phy.h:269
static const int firstep_table[]
#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
Definition: ar9002_phy.h:419
static int ar5008_hw_rfbus_req(struct ath_hw *ah)
u16 m2CountThrLow
Definition: ani.h:108
#define AR_PHY_FC_DYN2040_PRI_CH
Definition: ar9002_phy.h:30
u16 m2CountThr
Definition: ani.h:107
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
Definition: ar9002_phy.h:197
void(* rf_free_ext_banks)(struct ath_hw *ah)
Definition: hw.h:566
#define AR_PHY_AGC_CTL1_COARSE_HIGH
Definition: ar9002_phy.h:126
#define AR_PHY_RIFS_INIT_DELAY
Definition: ar9002_phy.h:367
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
#define DO_DELAY(x)
Definition: hw.h:112
#define MS(_v, _f)
Definition: hw.h:102
#define AR_PHY_RADAR_0_FFT_ENA
Definition: ar9002_phy.h:226
static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, u32 numBits, u32 firstBit, u32 column)
ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters @rfbuf: @reg32: @numBits: @...
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_PHY_CH2_EXT_MINCCA_PWR
Definition: ar9002_phy.h:586
#define ATH9K_SIG_FIRSTEP_SETTING_MAX
Definition: ani.h:72
#define AR_PHY_ACTIVE_EN
Definition: ar9002_phy.h:53
#define AR_PHY_BIN_MASK_1
Definition: ar9002_phy.h:281
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_PHY_FC_ENABLE_DAC_FIFO
Definition: ar9002_phy.h:37
static int32_t sign_extend32(uint32_t value, int index)
Definition: ath.h:69
#define AR_PHY_RADAR_EXT
Definition: ar9002_phy.h:221
#define min(x, y)
Definition: ath.h:34
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
Definition: ath9k_hw.c:964
#define AR_PHY_FIND_SIG_LOW
Definition: ar9002_phy.h:119
int(* rf_alloc_ext_banks)(struct ath_hw *ah)
Definition: hw.h:565
#define AR_PHY_FIND_SIG_FIRPWR
Definition: ar9002_phy.h:116
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW
Definition: ar9002_phy.h:349
static void ar5008_restore_chainmask(struct ath_hw *ah)
#define AR_PHY_RADAR_1_MAX_RRSSI
Definition: ar9002_phy.h:244
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:362
#define AR_PHY_TURBO
Definition: ar9002_phy.h:25
uint16_t bp
Definition: registers.h:23
#define CHANNEL_A_HT40MINUS
Definition: hw.h:322
#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
Definition: ar9002_phy.h:525
#define AR_PHY_TIMING11_SPUR_FREQ_SD
Definition: ar9003_phy.h:36
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:579
#define AR_SREV_5416_20_OR_LATER(_ah)
Definition: reg.h:801
u16 m1ThreshExt
Definition: ani.h:111
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW
Definition: ar9002_phy.h:351
static int ar5008_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
u16 cycpwrThr1Ext
Definition: ani.h:116
static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
#define AR_PHY_ACTIVE
Definition: ar9002_phy.h:52
static void ar5008_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_PHY_CHANNEL_MASK_01_30
Definition: ar9002_phy.h:532
#define AR_PHY_ADC_SERIAL_CTL
Definition: ar9002_phy.h:75
#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr)
static void ar5008_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_MODE_RF5GHZ
Definition: ar9002_phy.h:403
#define AR_RTC_PLL_REFDIV_5
Definition: reg.h:1184
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
Definition: ar9002_phy.h:522
#define AR_PHY_CHANNEL_MASK_31_60
Definition: ar9002_phy.h:533
static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
struct net80211_channel * chan
Definition: hw.h:347
u32 channelFlags
Definition: hw.h:350
static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
#define CHANNEL_A
Definition: ath5k.h:638
#define AR_PHY_BIN_MASK2_3
Definition: ar9002_phy.h:278
static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
#define AR_PHY_MASK2_P_61_45
Definition: ar9002_phy.h:516
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
Definition: ar9002_phy.h:198
u16 m2Thresh
Definition: ani.h:106
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_PHY_ACTIVE_DIS
Definition: ar9002_phy.h:54
static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
Dynamic memory allocation.
#define abs(x)
Definition: ath.h:44
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:576
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:331
#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ
Definition: ar9002_phy.h:593
#define AR_PHY_RADAR_1
Definition: ar9002_phy.h:238
Definition: ath.h:127
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:363
#define AR_PHY_DESIRED_SZ
Definition: ar9002_phy.h:105
unsigned int pulse_maxlen
Definition: hw.h:516
#define AR_SELFGEN_MASK
Definition: reg.h:1823
int ext_channel
Definition: hw.h:522
#define AR_PHY_HALFGI
Definition: ar9002_phy.h:355
static void ath9k_olc_init(struct ath_hw *ah)
Definition: hw-ops.h:198
#define AR_PHY_SFCORR_EXT_M2_THRESH
Definition: ar9002_phy.h:347
static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_TIMING5
Definition: ar9002_phy.h:202
void * memcpy(void *dest, const void *src, size_t len) __nonnull
u16 firstepLow
Definition: ani.h:114
#define AR_CST
Definition: reg.h:163
#define AR_PHY_MASK2_P_45_31
Definition: ar9002_phy.h:515
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
#define AR_PHY_EXT_MINCCA_PWR
Definition: ar9002_phy.h:339
uint32_t array
Array number.
Definition: edd.h:30
#define AR_PHY_SEL_INTERNAL_ADDAC
Definition: ar9002_phy.h:76
#define SM(_v, _f)
Definition: hw.h:101
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:573
#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
Definition: ar9002_phy.h:199
#define AR_RTC_9160_PLL_DIV
Definition: reg.h:1150
#define AR_PHY_RX_DELAY_DELAY
Definition: ar9002_phy.h:185
static const int m2CountThrLow_off
#define AR_PHY_ANALOG_SWAP
Definition: ar9002_phy.h:535
#define AR_PHY_RADAR_0_HEIGHT
Definition: ar9002_phy.h:231
#define AR_PHY_CCK_TX_CTRL
Definition: ar9002_phy.h:408
#define CHANNEL_G
Definition: ath5k.h:640
#define AR_PHY_SFCORR_M1_THRESH
Definition: ar9002_phy.h:151
#define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ
Definition: ar9002_phy.h:591
u16 m1Thresh
Definition: ani.h:105
#define AR_PHY_FC_SHORT_GI_40
Definition: ar9002_phy.h:34
#define AR_SREV_9160(_ah)
Definition: reg.h:815
u8 ofdmWeakSigDetect
Definition: ani.h:128
#define AR_PHY_TIMING10
Definition: ar9002_phy.h:291
#define AR_PHY_TIMING_CTRL4(_i)
Definition: ar9002_phy.h:187
#define AR_PCU_MISC_MODE2_HWWAR2
Definition: reg.h:1842
static int ar5008_hw_ani_control_old(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
unsigned int pulse_inband_step
Definition: hw.h:513
unsigned int pulse_height
Definition: hw.h:514
static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios @ah: atheros hardware ...
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
Definition: ar9002_phy.h:141
int(* set_rf_regs)(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw.h:567
#define u32
Definition: vga.h:21
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
unsigned int radar_rssi
Definition: hw.h:518
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_RTC_PLL_CLKSEL
Definition: reg.h:1185
#define ATH_FREE_BANK(bank)
#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
Definition: ar9002_phy.h:200
#define AR_PHY_RADAR_1_RELSTEP_THRESH
Definition: ar9002_phy.h:246
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
#define AR_PHY_RADAR_0_RRSSI
Definition: ar9002_phy.h:233
signed char int8_t
Definition: stdint.h:15
u32 ia_rows
Definition: calib.h:35
int16_t power_limit
Definition: ath.h:143
static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers @ah: atheros hardware strut...
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
u8 firstepLevel
Definition: ani.h:127
static int ar5008_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
#define AR_PHY_MASK2_P_30_16
Definition: ar9002_phy.h:514
#define AR_PHY_FC_WALSH
Definition: ar9002_phy.h:35
#define ATH9K_ANI_FIRSTEP_LVL_NEW
Definition: ani.h:55
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
Definition: ar9002_phy.h:414
int fir_power
Definition: hw.h:520
#define AR_PHY_TIMING5_CYCPWR_THR1
Definition: ar9002_phy.h:203
#define CHANNEL_A_HT20
Definition: hw.h:318
static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming @ah: atheros hardware s...
u32 ia_columns
Definition: calib.h:36
#define AR_PHY_RFBUS_GRANT_EN
Definition: ar9002_phy.h:389
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ
Definition: ar9002_phy.h:592
#define AR_PHY_CH2_EXT_CCA
Definition: ar9002_phy.h:585
static const int m2ThreshLowExt_off
u16 cycpwrThr1
Definition: ani.h:115
#define ATH9K_SIG_SPUR_IMM_SETTING_MIN
Definition: ani.h:73
#define AR_PHY_RADAR_0_INBAND
Definition: ar9002_phy.h:227
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
Definition: ar9002_phy.h:526
#define AR_DIAG_RX_DIS
Definition: reg.h:1510
#define AR_PHY_TIMING3_DSC_EXP
Definition: ar9002_phy.h:45
#define AR_PHY_RADAR_0_PRSSI
Definition: ar9002_phy.h:229
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
Definition: ar9002_phy.h:519
#define AR_SREV_9271_10(_ah)
Definition: reg.h:855
#define AR_PHY_TIMING11
Definition: ar9002_phy.h:295
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_PHY_CH1_MINCCA_PWR
Definition: ar9002_phy.h:570
struct ath_hw_radar_conf - radar detection initialization parameters
Definition: hw.h:511
#define AR_SREV_9280(_ah)
Definition: reg.h:822
#define AR_RTC_9160_PLL_CLKSEL
Definition: reg.h:1154
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
static const int m2Thresh_off
#define AR_PHY_RX_CHAINMASK
Definition: ar9002_phy.h:301
#define AR_PHY_RADAR_1_MAXLEN
Definition: ar9002_phy.h:248
#define AR_PHY_RX_DELAY
Definition: ar9002_phy.h:183
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
Definition: ar9002_phy.h:140
uint8_t * tmp
Definition: entropy.h:156
#define AR_PHY_CH1_EXT_CCA
Definition: ar9002_phy.h:579
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
Definition: ar9002_phy.h:296
An 802.11 RF channel.
Definition: net80211.h:385
#define AR_RTC_PLL_DIV
Definition: reg.h:1181
uint32_t column[4]
Viewed as an array of four-byte columns.
Definition: aes.h:14
#define AR_PHY_FIND_SIG_FIRSTEP_LOW
Definition: ar9002_phy.h:120
#define AR_PHY_SPUR_REG
Definition: ar9002_phy.h:517
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
#define AR_PHY_BIN_MASK2_4
Definition: ar9002_phy.h:279
#define AR_PHY_MASK2_M_00_15
Definition: ar9002_phy.h:512
#define AR_PHY_CAL_CHAINMASK
Definition: ar9002_phy.h:558
#define AR_SREV_REVISION_5416_10
Definition: reg.h:768
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define AR_PHY_SWAP_ALT_CHAIN
Definition: ar9002_phy.h:536
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:413
#define AR_PHY_MASK_CTL
Definition: ar9002_phy.h:285
#define ATH9K_SIG_SPUR_IMM_SETTING_MAX
Definition: ani.h:74
static const int m2CountThr_off
#define AR_PHY_CH1_EXT_MINCCA_PWR
Definition: ar9002_phy.h:580
#define AR_NO_SPUR
Definition: hw.h:240
unsigned int radar_inband
Definition: hw.h:519
#define AR_PHY_SFCORR_M2COUNT_THR
Definition: ar9002_phy.h:149
static void ar5008_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
Definition: ani.h:52
#define IS_CHAN_G(_c)
Definition: hw.h:355
static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios @ah: atheros hardware s...
unsigned int pulse_rssi
Definition: hw.h:515
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR_PHY_SPUR_REG_MASK_RATE_SELECT
Definition: ar9002_phy.h:523
#define AR_PHY_CH2_CCA
Definition: ar9002_phy.h:575
static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:575
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define AR_PHY_RADAR_0_ENA
Definition: ar9002_phy.h:225
#define AR_RTC_PLL_DIV2
Definition: reg.h:1183
#define AR_AN_TOP2_PWDCLKIND
Definition: reg.h:1274
#define AR_PHY_FIND_SIG_FIRSTEP
Definition: ar9002_phy.h:114
#define AR_PHY_MASK2_P_15_01
Definition: ar9002_phy.h:513
#define AR_PHY_TIMING3_DSC_MAN
Definition: ar9002_phy.h:43
#define IS_CHAN_5GHZ(_c)
Definition: hw.h:360
u8 cckWeakSigThreshold
Definition: ani.h:129
void __asmcall int val
Definition: setjmp.h:28
#define AR_CST_TIMEOUT_LIMIT_S
Definition: reg.h:166
#define AR_PHY_RADAR_0_FIRPWR
Definition: ar9002_phy.h:235
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:581
#define AR_PHY_CCA
Definition: ar9002_phy.h:129
#define AR_PHY_SFCORR
Definition: ar9002_phy.h:148
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
u16 m2ThreshLowExt
Definition: ani.h:110
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define AR_SREV_5416(_ah)
Definition: reg.h:798
ath9k_ani_cmd
Definition: ani.h:80
#define AR_PHY_TIMING3
Definition: ar9002_phy.h:42
#define AR_PHY_FC_DYN2040_EN
Definition: ar9002_phy.h:28
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:578
#define AR_PHY_BIN_MASK_2
Definition: ar9002_phy.h:282
int modparam_force_new_ani
#define REG_WRITE_ARRAY(iniarray, column, regWr)
Definition: hw.h:119
#define ATH_ALLOC_BANK(bank, size)
static const int m1ThreshLowExt_off
#define AR_PHY_PILOT_MASK_31_60
Definition: ar9002_phy.h:530
#define AR_PHY_SFCORR_M2_THRESH
Definition: ar9002_phy.h:153
#define AR_PHY_MINCCA_PWR
Definition: ar9002_phy.h:130
#define AR_PHY_MODE_DYN_CCK_DISABLE
Definition: ar9002_phy.h:406
#define AR_GTXTO
Definition: reg.h:152
signed int int32_t
Definition: stdint.h:17
#define AR_PHY_FC_SINGLE_HT_LTF1
Definition: ar9002_phy.h:36
#define AR_SREV_5416_22_OR_LATER(_ah)
Definition: reg.h:805
#define AR_PCU_MISC_MODE2_HWWAR1
Definition: reg.h:1841
static void ar5008_hw_override_ini(struct ath_hw *ah, struct ath9k_channel *chan __unused)
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:344
struct ar5416AniState ani
Definition: hw.h:348
#define AR_PHY_FC_HT_EN
Definition: ar9002_phy.h:33
#define AR_PHY_RADAR_1_BLOCK_CHECK
Definition: ar9002_phy.h:243
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_RFBUS_REQ
Definition: ar9002_phy.h:268
#define AR_PHY_PILOT_MASK_01_30
Definition: ar9002_phy.h:529
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Definition: ath9k_hw.c:1973
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
#define EIO
Input/output error.
Definition: errno.h:433
static const int m1Thresh_off
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AH_WAIT_TIMEOUT
Definition: hw.h:145
#define NUM_NF_READINGS
Definition: calib.h:30
u16 m1ThreshLowExt
Definition: ani.h:109
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:105
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:584
#define ATH9K_SIG_FIRSTEP_SETTING_MIN
Definition: ani.h:71
#define AR_PHY_SFCORR_EXT_M1_THRESH
Definition: ar9002_phy.h:345
static const int cycpwrThr1_table[]
#define AR_PHY_FIND_SIG
Definition: ar9002_phy.h:113
#define ATH9K_ANI_USE_OFDM_WEAK_SIG
Definition: ani.h:48
#define AR_PHY_MODE_RF2GHZ
Definition: ar9002_phy.h:402
static const int m2ThreshLow_off
u32 ofdmPhyErrCount
Definition: ani.h:134
static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array, int col)
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
u16 m2ThreshLow
Definition: ani.h:104
static void ar5008_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_DESIRED_SZ_TOT_DES
Definition: ar9002_phy.h:110
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:570
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
#define AR_PHY_RADAR_0
Definition: ar9002_phy.h:224
unsigned int pulse_inband
Definition: hw.h:512
#define AR_PHY_MODE_OFDM
Definition: ar9002_phy.h:405
uint8_t ah
Definition: registers.h:85
#define AR_DIAG_SW
Definition: reg.h:1504
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:587
#define SPUR_RSSI_THRESH
Definition: hw.h:150
#define CHANNEL_G_HT20
Definition: hw.h:317
uint32_t high
High 32 bits of address.
Definition: intel.h:22
signed short int16_t
Definition: stdint.h:16
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
#define AR_PHY_SEL_EXTERNAL_RADIO
Definition: ar9002_phy.h:77
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
void(* restore_chainmask)(struct ath_hw *ah)
Definition: hw.h:580
u32 cckPhyErrCount
Definition: ani.h:135
struct ath9k_ani_default iniDef
Definition: ani.h:139
u32 * ia_array
Definition: calib.h:34
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
u16 m2ThreshExt
Definition: ani.h:112
#define AR_PHY_MODE
Definition: ar9002_phy.h:396
#define AR_PHY_EXT_TIMING5_CYCPWR_THR1
Definition: ar9002_phy.h:336
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
Definition: hw.h:364
#define AR_AN_TOP2
Definition: reg.h:1269
#define AR_PHY_BIN_MASK2_1
Definition: ar9002_phy.h:276
#define AR_PHY_RADAR_EXT_ENA
Definition: ar9002_phy.h:222
#define AR_PHY_BIN_MASK2_2
Definition: ar9002_phy.h:277
#define AR_PHY_RFBUS_GRANT
Definition: ar9002_phy.h:388
#define AR_PHY_CCA_NOM_VAL_5416_2GHZ
Definition: ar9002_phy.h:589
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS
Definition: ar9002_phy.h:366
#define AR_PHY_AGC_CTL1
Definition: ar9002_phy.h:123
static void ar5008_hw_rfbus_done(struct ath_hw *ah)
#define AR_PHY_BIN_MASK_3
Definition: ar9002_phy.h:283
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320
u8 noiseImmunityLevel
Definition: ani.h:121
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23
#define AR_PHY_TIMING11_USE_SPUR_IN_AGC
Definition: ar9002_phy.h:298
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
static void ar5008_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
#define DBG2(...)
Definition: compiler.h:515
static int ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw-ops.h:170
#define AR_PHY_MODE_DYNAMIC
Definition: ar9002_phy.h:401
#define AR_PHY_RADAR_1_RELPWR_THRESH
Definition: ar9002_phy.h:241
static void ar5008_set_diversity(struct ath_hw *ah, int value)
void * memset(void *dest, int character, size_t len) __nonnull
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
Definition: ath9k_hw.c:125
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:54
#define AR_PHY_HALFGI_DSC_EXP
Definition: ar9002_phy.h:358
#define AR_PHY_VIT_MASK2_M_46_61
Definition: ar9002_phy.h:509