24 #define AR9285_CLCAL_REDO_THRESH 1 37 switch (
ah->supp_cals & cal_type) {
65 "starting IQ Mismatch Calibration\n");
70 "starting ADC Gain Calibration\n");
75 "starting ADC DC Calibration\n");
98 if (
ah->cal_samples >=
100 int i, numChains = 0;
102 if (rxchainmask & (1 << i))
126 ah->totalPowerMeasI[i] +=
128 ah->totalPowerMeasQ[i] +=
130 ah->totalIqCorrMeas[i] +=
133 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
134 ah->cal_samples, i,
ah->totalPowerMeasI[i],
135 ah->totalPowerMeasQ[i],
136 ah->totalIqCorrMeas[i]);
145 ah->totalAdcIOddPhase[i] +=
147 ah->totalAdcIEvenPhase[i] +=
149 ah->totalAdcQOddPhase[i] +=
151 ah->totalAdcQEvenPhase[i] +=
155 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
157 ah->totalAdcIOddPhase[i],
158 ah->totalAdcIEvenPhase[i],
159 ah->totalAdcQOddPhase[i],
160 ah->totalAdcQEvenPhase[i]);
169 ah->totalAdcDcOffsetIOddPhase[i] +=
171 ah->totalAdcDcOffsetIEvenPhase[i] +=
173 ah->totalAdcDcOffsetQOddPhase[i] +=
175 ah->totalAdcDcOffsetQEvenPhase[i] +=
179 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
181 ah->totalAdcDcOffsetIOddPhase[i],
182 ah->totalAdcDcOffsetIEvenPhase[i],
183 ah->totalAdcDcOffsetQOddPhase[i],
184 ah->totalAdcDcOffsetQEvenPhase[i]);
190 u32 powerMeasQ, powerMeasI, iqCorrMeas;
191 u32 qCoffDenom, iCoffDenom;
195 for (i = 0; i < numChains; i++) {
196 powerMeasI =
ah->totalPowerMeasI[i];
197 powerMeasQ =
ah->totalPowerMeasQ[i];
198 iqCorrMeas =
ah->totalIqCorrMeas[i];
201 "Starting IQ Cal and Correction for Chain %d\n",
205 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
206 i,
ah->totalIqCorrMeas[i]);
210 if (iqCorrMeas > 0x80000000) {
211 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
216 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
218 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
219 DBG2(
"ath9k: iqCorrNeg is 0x%08x\n",
222 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
223 qCoffDenom = powerMeasQ / 64;
225 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
227 iCoff = iqCorrMeas / iCoffDenom;
228 qCoff = powerMeasI / qCoffDenom - 64;
230 "Chn %d iCoff = 0x%08x\n", i,
iCoff);
232 "Chn %d qCoff = 0x%08x\n", i,
qCoff);
236 "New: Chn %d iCoff = 0x%08x\n", i,
iCoff);
237 if (iqCorrNeg == 0x0)
242 else if (
qCoff <= -16)
246 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
256 "IQ Cal and Correction done for Chain %d\n",
267 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
268 u32 qGainMismatch, iGainMismatch,
val, i;
270 for (i = 0; i < numChains; i++) {
271 iOddMeasOffset =
ah->totalAdcIOddPhase[i];
272 iEvenMeasOffset =
ah->totalAdcIEvenPhase[i];
273 qOddMeasOffset =
ah->totalAdcQOddPhase[i];
274 qEvenMeasOffset =
ah->totalAdcQEvenPhase[i];
277 "Starting ADC Gain Cal for Chain %d\n", i);
280 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
283 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
286 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
289 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
292 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
294 ((iEvenMeasOffset * 32) /
295 iOddMeasOffset) & 0x3f;
297 ((qOddMeasOffset * 32) /
298 qEvenMeasOffset) & 0x3f;
301 "Chn %d gain_mismatch_i = 0x%08x\n", i,
304 "Chn %d gain_mismatch_q = 0x%08x\n", i,
309 val |= (qGainMismatch) | (iGainMismatch << 6);
313 "ADC Gain Cal done for Chain %d\n", i);
324 u32 iOddMeasOffset, iEvenMeasOffset,
val, i;
325 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
327 ah->cal_list_curr->calData;
331 for (i = 0; i < numChains; i++) {
332 iOddMeasOffset =
ah->totalAdcDcOffsetIOddPhase[i];
333 iEvenMeasOffset =
ah->totalAdcDcOffsetIEvenPhase[i];
334 qOddMeasOffset =
ah->totalAdcDcOffsetQOddPhase[i];
335 qEvenMeasOffset =
ah->totalAdcDcOffsetQEvenPhase[i];
338 "Starting ADC DC Offset Cal for Chain %d\n", i);
341 "Chn %d pwr_meas_odd_i = %d\n", i,
344 "Chn %d pwr_meas_even_i = %d\n", i,
347 "Chn %d pwr_meas_odd_q = %d\n", i,
350 "Chn %d pwr_meas_even_q = %d\n", i,
353 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
355 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
359 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
362 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
367 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
371 "ADC DC Offset Cal done for Chain %d\n", i);
382 int32_t delta, currPDADC, slope;
387 if (
ah->initPDADC == 0 || currPDADC == 0) {
400 delta = ((currPDADC -
ah->initPDADC)*4) / slope;
412 int delta, currPDADC, regval;
417 if (
ah->initPDADC == 0 || currPDADC == 0)
421 delta = (currPDADC -
ah->initPDADC + 4) / 8;
423 delta = (currPDADC -
ah->initPDADC + 5) / 10;
425 if (delta !=
ah->PDADCdelta) {
426 ah->PDADCdelta = delta;
428 regval =
ah->originalGain[i] - delta;
461 regVal |= (0x1 << 27);
503 for (i = 6; i > 0; i--) {
505 regVal |= (1 << (20 + i));
509 regVal &= (~(0x1 << (20 + i)));
515 regVal = (regVal >> 20) & 0x7f;
518 if ((!is_reset) && ((
unsigned int)
ah->pacal_info.prev_offset == regVal)) {
520 ah->pacal_info.max_skipcount =
521 2 *
ah->pacal_info.max_skipcount;
522 ah->pacal_info.skipcount =
ah->pacal_info.max_skipcount;
524 ah->pacal_info.max_skipcount = 1;
525 ah->pacal_info.skipcount = 0;
526 ah->pacal_info.prev_offset = regVal;
535 regVal &= (~(0x1 << 27));
548 int offset, offs_6_1, offs_0;
549 u32 ccomp_org, reg_field;
560 DBG2(
"ath9k: Running PA Calibration\n");
574 regVal |= (0x1 << 27);
597 for (i = 6; i > 0; i--) {
599 regVal |= (1 << (19 + i));
603 regVal &= (~(0x1 << (19 + i)));
605 regVal |= (reg_field << (19 + i));
616 offset = (offs_6_1<<1) | offs_0;
621 if ((!is_reset) && (
ah->pacal_info.prev_offset ==
offset)) {
623 ah->pacal_info.max_skipcount =
624 2 *
ah->pacal_info.max_skipcount;
625 ah->pacal_info.skipcount =
ah->pacal_info.max_skipcount;
627 ah->pacal_info.max_skipcount = 1;
628 ah->pacal_info.skipcount = 0;
629 ah->pacal_info.prev_offset =
offset;
639 regVal &= (~(0x1 << 27));
651 if (is_reset || !
ah->pacal_info.skipcount)
654 ah->pacal_info.skipcount--;
656 if (is_reset || !
ah->pacal_info.skipcount)
659 ah->pacal_info.skipcount--;
678 int nfcal, nfcal_pending = 0;
682 nfcal_pending =
ah->caldata->nfcal_pending;
684 if (currCal && !nfcal &&
688 rxchainmask, currCal);
690 ah->cal_list_curr = currCal = currCal->
calNext;
700 if (longcal || nfcal_pending) {
740 "offset calibration failed to complete in 1ms; noisy environment?\n");
754 "offset calibration failed to complete in 1ms; noisy environment?\n");
769 uint32_t clc_gain, gain_mask = 0, clc_num = 0;
783 for (i = 0; i < (txgain_max+1); i++) {
786 if (!(gain_mask & (1 << clc_gain))) {
787 gain_mask |= (1 << clc_gain);
792 for (i = 0; i < clc_num; i++) {
803 total_num = i0_num + q0_num;
848 "offset calibration failed to complete in 1ms; noisy environment?\n");
868 ah->caldata->nfcal_pending = 1;
870 ah->cal_list =
ah->cal_list_last =
ah->cal_list_curr =
NULL;
886 "enabling ADC Gain Calibration.\n");
893 "enabling ADC DC Calibration.\n");
900 "enabling IQ Calibration.\n");
903 ah->cal_list_curr =
ah->cal_list;
905 if (
ah->cal_list_curr)
910 ah->caldata->CalValid = 0;
969 ah->adcgain_caldata.calData =
971 ah->adcdc_caldata.calData =
975 ah->adcgain_caldata.calData =
977 ah->adcdc_caldata.calData =
static const struct ath9k_percal_data iq_cal_multi_sample
#define AR_PHY_CAL_MEAS_3(_i)
static void ar9271_hw_pa_cal(struct ath_hw *ah, int is_reset)
#define AR9285_AN_RF2G2_OFFCAL
#define AR_SREV_9287_11_OR_LATER(_ah)
#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE
#define AR9285_AN_RF2G1_ENPACAL
static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
#define AR_PHY_CALMODE_ADC_DC_PER
#define AR9285_RF2G5_IC50TX_SET
#define AR_SREV_9280_20_OR_LATER(_ah)
#define AR_PHY_TX_PWRCTRL4
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
static int ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
static const struct ath9k_percal_data adc_gain_cal_multi_sample
#define AR9285_RF2G5_IC50TX
#define AR_PHY_PARALLEL_CAL_ENABLE
#define AR9285_AN_RF2G8_PADRVGN2TAB0
#define AR9280_TX_GAIN_TABLE_SIZE
static void ar9285_hw_pa_cal(struct ath_hw *ah, int is_reset)
static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
#define AR_PHY_TX_GAIN_TBL1
#define AR9285_AN_RF2G1_PDPADRV1
void(* calPostProc)(struct ath_hw *, u8)
void ath9k_hw_start_nfcal(struct ath_hw *ah, int update)
#define AR_PHY_CL_CAL_CTL
#define AR9285_AN_RF2G1_PDPADRV2
#define AR_PHY_TX_GAIN_CLC
#define AR9285_AN_RF2G1_PDPAOUT
#define REG_CLR_BIT(_a, _r, _f)
void(* init_cal_settings)(struct ath_hw *ah)
static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
#define REGWRITE_BUFFER_FLUSH(_ah)
static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
struct ath9k_cal_list * calNext
struct ath_hw_private_ops - callbacks used internally by hardware code
#define AR9285_AN_RF2G7_PADRVGN2TAB0
static void ar9002_hw_setup_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal)
#define AR_SREV_9285(_ah)
void(* setup_calibration)(struct ath_hw *ah, struct ath9k_cal_list *currCal)
#define AR9285_AN_RF2G3_PDVCCOMP
#define AR5416_EEP_TXGAIN_HIGH_POWER
#define OLC_FOR_AR9287_10_LATER
static int ar9002_hw_per_calibration(struct ath_hw *ah, struct ath9k_channel *ichan __unused, u8 rxchainmask, struct ath9k_cal_list *currCal)
void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
#define AR_PHY_AGC_CONTROL_CAL
#define REG_RMW_FIELD(_a, _r, _f, _v)
#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE
static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
#define AR_SREV_9287(_ah)
static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
#define AR_PHY_ADC_CTL_OFF_PWDADC
static int ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR9285_RF2G5_IC50TX_XE_SET
#define INIT_CAL(_perCal)
#define AR_PHY_TIMING_CTRL4(_i)
#define __unused
Declare a variable or data structure as unused.
#define AR9271_AN_RF2G3_CCOMP
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_AGC_CONTROL
static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
static const struct ath9k_percal_data adc_dc_cal_multi_sample
void(* calCollect)(struct ath_hw *)
#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP
static void ar9002_hw_pa_cal(struct ath_hw *ah, int is_reset)
#define AR9285_AN_TOP3_PWDDAC
#define AR_PHY_TPCRG1_PD_CAL_ENABLE
#define AR_PHY_CH1_TX_PWRCTRL11
#define AR_PHY_CAL_MEAS_2(_i)
struct ath_hw_ops - callbacks used by hardware code and driver code
int(* calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
#define INSERT_CAL(_ahp, _perCal)
#define OLC_FOR_AR9280_20_LATER
const struct ath9k_percal_data * calData
#define AR_SREV_9285_12_OR_LATER(_ah)
#define AR9285_AN_RXTXBB1_PDV2I
#define AR_PHY_AGC_CONTROL_NF
#define AR9285_AN_RXTXBB1_SPARE9
#define AR_PHY_CL_CAL_ENABLE
#define PER_MAX_LOG_COUNT
#define AR_PHY_CALMODE_ADC_GAIN
#define AR_PHY_CH0_TX_PWRCTRL11
#define REG_READ(_ah, _reg)
#define AR9271_AN_RF2G6_OFFS
#define PER_MIN_LOG_COUNT
#define AR_SREV_9285E_20(_ah)
#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE
#define AR5416_MAX_CHAINS
static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
#define REG_SET_BIT(_a, _r, _f)
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
#define AR9285_AN_RF2G6_CCOMP
#define AR_PHY_FC_DYN2040_EN
#define AR9285_AN_RXTXBB1_PDRXTXBB1
#define AR9285_CLCAL_REDO_THRESH
#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
#define REG_WRITE(_ah, _reg, _val)
#define AR9285_AN_RF2G7_PWDDB
static const struct ath9k_percal_data iq_cal_single_sample
#define AR9285_AN_RXTXBB1_PDDACIF
#define AR_SREV_9271(_ah)
#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX
#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i)
static const struct ath9k_percal_data adc_dc_cal_single_sample
#define AR9285_AN_RXTXBB1
static int ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_CAL_MEAS_1(_i)
#define AR9285_AN_RF2G6_OFFS
#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT
#define AR_PHY_TX_GAIN_CLC_S
int ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
uint16_t offset
Offset to command line.
static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
#define AR_SREV_9160_10_OR_LATER(_ah)
#define AR_PHY_TX_PWRCTRL7
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
#define AR_PHY_TIMING_CTRL4_DO_CAL
#define DBG(...)
Print a debugging message.
uint32_t supported
Bitmask of supported AENQ groups (device -> host)
static int ar9002_hw_is_cal_supported(struct ath_hw *ah, struct ath9k_channel *chan, enum ar9002_cal_types cal_type)
static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
void ath9k_hw_reset_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal)
static const struct ath9k_percal_data adc_gain_cal_single_sample
static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
#define NULL
NULL pointer (VOID *)
#define AR_PHY_CAL_MEAS_0(_i)
enum ath9k_cal_state calState
#define MAX_PACAL_SKIPCOUNT
int(* init_cal)(struct ath_hw *ah, struct ath9k_channel *chan)
#define ENABLE_REGWRITE_BUFFER(_ah)
#define AR_PHY_CALMODE_IQ
#define AR_PHY_AGC_CONTROL_FLTR_CAL
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF