Realtek 10/100/1000 network card driver. More...

#include <ipxe/spi.h>
#include <ipxe/spi_bit.h>
#include <ipxe/nvo.h>
#include <ipxe/if_ether.h>

Data Structures
struct	realtek_descriptor
	A packet descriptor. More...

struct	realtek_legacy_header
	A legacy mode receive packet header. More...

struct	realtek_ring
	A Realtek descriptor ring. More...

struct	realtek_rx_buffer
	Receive buffer (legacy mode *) More...

struct	realtek_nic
	A Realtek network card. More...

Macros
#define	RTL_BAR_SIZE 0x100
	PCI memory BAR size. More...

#define	RTL_DESC_SIZE_MASK 0x3fff
	Descriptor buffer size mask. More...

#define	RTL_RING_ALIGN 256
	Descriptor ring alignment. More...

#define	RTL_IDR0 0x00
	ID Register 0 (6 bytes) More...

#define	RTL_MAR0 0x08
	Multicast Register 0 (dword) More...

#define	RTL_MAR4 0x0c
	Multicast Register 4 (dword) More...

#define	RTL_TSD(n) ( 0x10 + 4 * (n) )
	Transmit Status of Descriptor N (dword, 8139 only) More...

#define	RTL_TSD_ERTXTH(x) ( (x) << 16 )
	Early TX threshold. More...

#define	RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )

#define	RTL_TSD_OWN 0x00002000UL
	Ownership. More...

#define	RTL_TSAD(n) ( 0x20 + 4 * (n) )
	Transmit Start Address of Descriptor N (dword, 8139 only) More...

#define	RTL_TNPDS 0x20
	Transmit Normal Priority Descriptors (qword) More...

#define	RTL_NUM_TX_DESC 4
	Number of transmit descriptors. More...

#define	RTL_RBSTART 0x30
	Receive Buffer Start Address (dword, 8139 only) More...

#define	RTL_RXBUF_LEN 8192
	Receive buffer length. More...

#define	RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
	Receive buffer padding. More...

#define	RTL_RXBUF_ALIGN 16
	Receive buffer alignment. More...

#define	RTL_CR 0x37
	Command Register (byte) More...

#define	RTL_CR_RST 0x10
	Reset. More...

#define	RTL_CR_RE 0x08
	Receiver Enable. More...

#define	RTL_CR_TE 0x04
	Transmit Enable. More...

#define	RTL_CR_BUFE 0x01
	Receive buffer empty. More...

#define	RTL_RESET_MAX_WAIT_MS 100
	Maximum time to wait for a reset, in milliseconds. More...

#define	RTL_CAPR 0x38
	Current Address of Packet Read (word, 8139 only) More...

#define	RTL_TPPOLL_8169 0x38
	Transmit Priority Polling Register (byte, 8169 only) More...

#define	RTL_TPPOLL_NPQ 0x40
	Normal Priority Queue Polling. More...

#define	RTL_IMR 0x3c
	Interrupt Mask Register (word) More...

#define	RTL_IRQ_PUN_LINKCHG 0x0020
	Packet underrun / link change. More...

#define	RTL_IRQ_TER 0x0008
	Transmit error. More...

#define	RTL_IRQ_TOK 0x0004
	Transmit OK. More...

#define	RTL_IRQ_RER 0x0002
	Receive error. More...

#define	RTL_IRQ_ROK 0x0001
	Receive OK. More...

#define	RTL_ISR 0x3e
	Interrupt Status Register (word) More...

#define	RTL_TCR 0x40
	Transmit (Tx) Configuration Register (dword) More...

#define	RTL_TCR_MXDMA(x) ( (x) << 8 )
	Max DMA burst size. More...

#define	RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )

#define	RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )

#define	RTL_RCR 0x44
	Receive (Rx) Configuration Register (dword) More...

#define	RTL_RCR_STOP_WORKING 0x01000000UL
	Here be dragons. More...

#define	RTL_RCR_RXFTH(x) ( (x) << 13 )
	Receive FIFO threshold. More...

#define	RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )

#define	RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )

#define	RTL_RCR_RBLEN(x) ( (x) << 11 )
	Receive buffer length. More...

#define	RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )

#define	RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )

#define	RTL_RCR_MXDMA(x) ( (x) << 8 )
	Max DMA burst size. More...

#define	RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )

#define	RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )

#define	RTL_RCR_WRAP 0x00000080UL
	Overrun receive buffer. More...

#define	RTL_RCR_9356SEL 0x00000040UL
	EEPROM is a 93C56. More...

#define	RTL_RCR_AB 0x00000008UL
	Accept broadcast packets. More...

#define	RTL_RCR_AM 0x00000004UL
	Accept multicast packets. More...

#define	RTL_RCR_APM 0x00000002UL
	Accept physical match. More...

#define	RTL_RCR_AAP 0x00000001UL
	Accept all packets. More...

#define	RTL_9346CR 0x50
	93C46 (93C56) Command Register (byte) More...

#define	RTL_9346CR_EEM(x) ( (x) << 6 )
	Mode select. More...

#define	RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 )
	EEPROM mode. More...

#define	RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 )
	Normal mode. More...

#define	RTL_9346CR_EECS 0x08
	Chip select. More...

#define	RTL_9346CR_EESK 0x04
	Clock. More...

#define	RTL_9346CR_EEDI 0x02
	Data in. More...

#define	RTL_9346CR_EEDO 0x01
	Data out. More...

#define	RTL_EEPROM_ID ( 0x00 / 2 )
	Word offset of ID code word within EEPROM. More...

#define	RTL_EEPROM_ID_MAGIC 0x8129
	EEPROM code word magic value. More...

#define	RTL_EEPROM_MAC ( 0x0e / 2 )
	Word offset of MAC address within EEPROM. More...

#define	RTL_EEPROM_VPD ( 0x40 / 2 )
	Word offset of VPD / non-volatile options within EEPROM. More...

#define	RTL_EEPROM_VPD_LEN 0x40
	Length of VPD / non-volatile options within EEPROM. More...

#define	RTL_CONFIG1 0x52
	Configuration Register 1 (byte) More...

#define	RTL_CONFIG1_VPD 0x02
	Vital Product Data enabled. More...

#define	RTL_MSR 0x58
	Media Status Register (byte, 8139 only) More...

#define	RTL_MSR_TXFCE 0x80
	TX flow control enabled. More...

#define	RTL_MSR_RXFCE 0x40
	RX flow control enabled. More...

#define	RTL_MSR_AUX_STATUS 0x10
	Aux power present. More...

#define	RTL_MSR_SPEED_10 0x08
	10Mbps More...

#define	RTL_MSR_LINKB 0x04
	Inverse of link status. More...

#define	RTL_MSR_TXPF 0x02
	TX pause flag. More...

#define	RTL_MSR_RXPF 0x01
	RX pause flag. More...

#define	RTL_PHYAR 0x60
	PHY Access Register (dword, 8169 only) More...

#define	RTL_PHYAR_FLAG 0x80000000UL
	Read/write flag. More...

#define	RTL_PHYAR_VALUE(flag, reg, data) ( (flag) \| ( (reg) << 16 ) \| (data) )
	Construct PHY Access Register value. More...

#define	RTL_PHYAR_DATA(value) ( (value) & 0xffff )
	Extract PHY Access Register data. More...

#define	RTL_MII_MAX_WAIT_US 500
	Maximum time to wait for PHY access, in microseconds. More...

#define	RTL_PHYSTATUS 0x6c
	PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) More...

#define	RTL_PHYSTATUS_ENTBI 0x80
	TBI / GMII mode. More...

#define	RTL_PHYSTATUS_TXFLOW 0x40
	TX flow control enabled. More...

#define	RTL_PHYSTATUS_RXFLOW 0x20
	RX flow control enabled. More...

#define	RTL_PHYSTATUS_1000MF 0x10
	1000Mbps full-duplex More...

#define	RTL_PHYSTATUS_100M 0x08
	100Mbps More...

#define	RTL_PHYSTATUS_10M 0x04
	10Mbps More...

#define	RTL_PHYSTATUS_LINKSTS 0x02
	Link ok. More...

#define	RTL_PHYSTATUS_FULLDUP 0x01
	Full duplex. More...

#define	RTL_TPPOLL_8139CP 0xd9
	Transmit Priority Polling Register (byte, 8139C+ only) More...

#define	RTL_RMS 0xda
	RX Packet Maximum Size Register (word) More...

#define	RTL_CPCR 0xe0
	C+ Command Register (word) More...

#define	RTL_CPCR_VLAN 0x0040
	VLAN tag stripping enable. More...

#define	RTL_CPCR_DAC 0x0010
	PCI Dual Address Cycle enable. More...

#define	RTL_CPCR_MULRW 0x0008
	PCI Multiple Read/Write enable. More...

#define	RTL_CPCR_CPRX 0x0002
	C+ receive enable. More...

#define	RTL_CPCR_CPTX 0x0001
	C+ transmit enable. More...

#define	RTL_RDSAR 0xe4
	Receive Descriptor Start Address Register (qword) More...

#define	RTL_NUM_RX_DESC 4
	Number of receive descriptors. More...

#define	RTL_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN / + 4 / CRC / + 4 / extra space */ )
	Receive buffer length. More...

Enumerations
enum	realtek_descriptor_flags { RTL_DESC_OWN = 0x8000, RTL_DESC_EOR = 0x4000, RTL_DESC_FS = 0x2000, RTL_DESC_LS = 0x1000, RTL_DESC_RES = 0x0020 }
	Packet descriptor flags. More...

enum	realtek_legacy_status { RTL_STAT_ROK = 0x0001 }
	Legacy mode status bits. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

static void	realtek_init_ring (struct realtek_ring *ring, unsigned int count, unsigned int reg)
	Initialise descriptor ring. More...

Detailed Description

Realtek 10/100/1000 network card driver.

Definition in file realtek.h.

Macro Definition Documentation

◆ RTL_BAR_SIZE

#define RTL_BAR_SIZE 0x100

PCI memory BAR size.

Definition at line 18 of file realtek.h.

◆ RTL_DESC_SIZE_MASK

#define RTL_DESC_SIZE_MASK 0x3fff

Descriptor buffer size mask.

Definition at line 33 of file realtek.h.

◆ RTL_RING_ALIGN

#define RTL_RING_ALIGN 256

Descriptor ring alignment.

Definition at line 50 of file realtek.h.

◆ RTL_IDR0

#define RTL_IDR0 0x00

ID Register 0 (6 bytes)

Definition at line 69 of file realtek.h.

◆ RTL_MAR0

#define RTL_MAR0 0x08

Multicast Register 0 (dword)

Definition at line 72 of file realtek.h.

◆ RTL_MAR4

#define RTL_MAR4 0x0c

Multicast Register 4 (dword)

Definition at line 75 of file realtek.h.

◆ RTL_TSD

#define RTL_TSD ( n ) ( 0x10 + 4 * (n) )

Transmit Status of Descriptor N (dword, 8139 only)

Definition at line 78 of file realtek.h.

◆ RTL_TSD_ERTXTH

#define RTL_TSD_ERTXTH ( x ) ( (x) << 16 )

Early TX threshold.

Definition at line 79 of file realtek.h.

◆ RTL_TSD_ERTXTH_DEFAULT

#define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )

Definition at line 80 of file realtek.h.

◆ RTL_TSD_OWN

#define RTL_TSD_OWN 0x00002000UL

Ownership.

Definition at line 81 of file realtek.h.

◆ RTL_TSAD

#define RTL_TSAD ( n ) ( 0x20 + 4 * (n) )

Transmit Start Address of Descriptor N (dword, 8139 only)

Definition at line 84 of file realtek.h.

◆ RTL_TNPDS

#define RTL_TNPDS 0x20

Transmit Normal Priority Descriptors (qword)

Definition at line 87 of file realtek.h.

◆ RTL_NUM_TX_DESC

#define RTL_NUM_TX_DESC 4

Number of transmit descriptors.

This is a hardware limit when using legacy mode.

Definition at line 93 of file realtek.h.

◆ RTL_RBSTART

#define RTL_RBSTART 0x30

Receive Buffer Start Address (dword, 8139 only)

Definition at line 96 of file realtek.h.

◆ RTL_RXBUF_LEN

#define RTL_RXBUF_LEN 8192

Receive buffer length.

Definition at line 99 of file realtek.h.

◆ RTL_RXBUF_PAD

#define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */

Receive buffer padding.

Definition at line 102 of file realtek.h.

◆ RTL_RXBUF_ALIGN

#define RTL_RXBUF_ALIGN 16

Receive buffer alignment.

Definition at line 105 of file realtek.h.

◆ RTL_CR

#define RTL_CR 0x37

Command Register (byte)

Definition at line 108 of file realtek.h.

◆ RTL_CR_RST

#define RTL_CR_RST 0x10

Reset.

Definition at line 109 of file realtek.h.

◆ RTL_CR_RE

#define RTL_CR_RE 0x08

Receiver Enable.

Definition at line 110 of file realtek.h.

◆ RTL_CR_TE

#define RTL_CR_TE 0x04

Transmit Enable.

Definition at line 111 of file realtek.h.

◆ RTL_CR_BUFE

#define RTL_CR_BUFE 0x01

Receive buffer empty.

Definition at line 112 of file realtek.h.

◆ RTL_RESET_MAX_WAIT_MS

#define RTL_RESET_MAX_WAIT_MS 100

Maximum time to wait for a reset, in milliseconds.

Definition at line 115 of file realtek.h.

◆ RTL_CAPR

#define RTL_CAPR 0x38

Current Address of Packet Read (word, 8139 only)

Definition at line 118 of file realtek.h.

◆ RTL_TPPOLL_8169

#define RTL_TPPOLL_8169 0x38

Transmit Priority Polling Register (byte, 8169 only)

Definition at line 121 of file realtek.h.

◆ RTL_TPPOLL_NPQ

#define RTL_TPPOLL_NPQ 0x40

Normal Priority Queue Polling.

Definition at line 122 of file realtek.h.

◆ RTL_IMR

#define RTL_IMR 0x3c

Interrupt Mask Register (word)

Definition at line 125 of file realtek.h.

◆ RTL_IRQ_PUN_LINKCHG

#define RTL_IRQ_PUN_LINKCHG 0x0020

Packet underrun / link change.

Definition at line 126 of file realtek.h.

◆ RTL_IRQ_TER

#define RTL_IRQ_TER 0x0008

Transmit error.

Definition at line 127 of file realtek.h.

◆ RTL_IRQ_TOK

#define RTL_IRQ_TOK 0x0004

Transmit OK.

Definition at line 128 of file realtek.h.

◆ RTL_IRQ_RER

#define RTL_IRQ_RER 0x0002

Receive error.

Definition at line 129 of file realtek.h.

◆ RTL_IRQ_ROK

#define RTL_IRQ_ROK 0x0001

Receive OK.

Definition at line 130 of file realtek.h.

◆ RTL_ISR

#define RTL_ISR 0x3e

Interrupt Status Register (word)

Definition at line 133 of file realtek.h.

◆ RTL_TCR

#define RTL_TCR 0x40

Transmit (Tx) Configuration Register (dword)

Definition at line 136 of file realtek.h.

◆ RTL_TCR_MXDMA

#define RTL_TCR_MXDMA ( x ) ( (x) << 8 )

Max DMA burst size.

Definition at line 137 of file realtek.h.

◆ RTL_TCR_MXDMA_MASK

#define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )

Definition at line 138 of file realtek.h.

◆ RTL_TCR_MXDMA_DEFAULT

#define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )

Definition at line 139 of file realtek.h.

◆ RTL_RCR

#define RTL_RCR 0x44

Receive (Rx) Configuration Register (dword)

Definition at line 142 of file realtek.h.

◆ RTL_RCR_STOP_WORKING

#define RTL_RCR_STOP_WORKING 0x01000000UL

Here be dragons.

Definition at line 143 of file realtek.h.

◆ RTL_RCR_RXFTH

#define RTL_RCR_RXFTH ( x ) ( (x) << 13 )

Receive FIFO threshold.

Definition at line 144 of file realtek.h.

◆ RTL_RCR_RXFTH_MASK

#define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )

Definition at line 145 of file realtek.h.

◆ RTL_RCR_RXFTH_DEFAULT

#define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )

Definition at line 146 of file realtek.h.

◆ RTL_RCR_RBLEN

#define RTL_RCR_RBLEN ( x ) ( (x) << 11 )

Receive buffer length.

Definition at line 147 of file realtek.h.

◆ RTL_RCR_RBLEN_MASK

#define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )

Definition at line 148 of file realtek.h.

◆ RTL_RCR_RBLEN_DEFAULT

#define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )

Definition at line 149 of file realtek.h.

◆ RTL_RCR_MXDMA

#define RTL_RCR_MXDMA ( x ) ( (x) << 8 )

Max DMA burst size.

Definition at line 150 of file realtek.h.

◆ RTL_RCR_MXDMA_MASK

#define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )

Definition at line 151 of file realtek.h.

◆ RTL_RCR_MXDMA_DEFAULT

#define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )

Definition at line 152 of file realtek.h.

◆ RTL_RCR_WRAP

#define RTL_RCR_WRAP 0x00000080UL

Overrun receive buffer.

Definition at line 153 of file realtek.h.

◆ RTL_RCR_9356SEL

#define RTL_RCR_9356SEL 0x00000040UL

EEPROM is a 93C56.

Definition at line 154 of file realtek.h.

◆ RTL_RCR_AB

#define RTL_RCR_AB 0x00000008UL

Accept broadcast packets.

Definition at line 155 of file realtek.h.

◆ RTL_RCR_AM

#define RTL_RCR_AM 0x00000004UL

Accept multicast packets.

Definition at line 156 of file realtek.h.

◆ RTL_RCR_APM

#define RTL_RCR_APM 0x00000002UL

Accept physical match.

Definition at line 157 of file realtek.h.

◆ RTL_RCR_AAP

#define RTL_RCR_AAP 0x00000001UL

Accept all packets.

Definition at line 158 of file realtek.h.

◆ RTL_9346CR

#define RTL_9346CR 0x50

93C46 (93C56) Command Register (byte)

Definition at line 161 of file realtek.h.

◆ RTL_9346CR_EEM

#define RTL_9346CR_EEM ( x ) ( (x) << 6 )

Mode select.

Definition at line 162 of file realtek.h.

◆ RTL_9346CR_EEM_EEPROM

#define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 )

EEPROM mode.

Definition at line 163 of file realtek.h.

◆ RTL_9346CR_EEM_NORMAL

#define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 )

Normal mode.

Definition at line 164 of file realtek.h.

◆ RTL_9346CR_EECS

#define RTL_9346CR_EECS 0x08

Chip select.

Definition at line 165 of file realtek.h.

◆ RTL_9346CR_EESK

#define RTL_9346CR_EESK 0x04

Clock.

Definition at line 166 of file realtek.h.

◆ RTL_9346CR_EEDI

#define RTL_9346CR_EEDI 0x02

Data in.

Definition at line 167 of file realtek.h.

◆ RTL_9346CR_EEDO

#define RTL_9346CR_EEDO 0x01

Data out.

Definition at line 168 of file realtek.h.

◆ RTL_EEPROM_ID

#define RTL_EEPROM_ID ( 0x00 / 2 )

Word offset of ID code word within EEPROM.

Definition at line 171 of file realtek.h.

◆ RTL_EEPROM_ID_MAGIC

#define RTL_EEPROM_ID_MAGIC 0x8129

EEPROM code word magic value.

Definition at line 174 of file realtek.h.

◆ RTL_EEPROM_MAC

#define RTL_EEPROM_MAC ( 0x0e / 2 )

Word offset of MAC address within EEPROM.

Definition at line 177 of file realtek.h.

◆ RTL_EEPROM_VPD

#define RTL_EEPROM_VPD ( 0x40 / 2 )

Word offset of VPD / non-volatile options within EEPROM.

Definition at line 180 of file realtek.h.

◆ RTL_EEPROM_VPD_LEN

#define RTL_EEPROM_VPD_LEN 0x40

Length of VPD / non-volatile options within EEPROM.

Definition at line 183 of file realtek.h.

◆ RTL_CONFIG1

#define RTL_CONFIG1 0x52

Configuration Register 1 (byte)

Definition at line 186 of file realtek.h.

◆ RTL_CONFIG1_VPD

#define RTL_CONFIG1_VPD 0x02

Vital Product Data enabled.

Definition at line 187 of file realtek.h.

◆ RTL_MSR

#define RTL_MSR 0x58

Media Status Register (byte, 8139 only)

Definition at line 190 of file realtek.h.

◆ RTL_MSR_TXFCE

#define RTL_MSR_TXFCE 0x80

TX flow control enabled.

Definition at line 191 of file realtek.h.

◆ RTL_MSR_RXFCE

#define RTL_MSR_RXFCE 0x40

RX flow control enabled.

Definition at line 192 of file realtek.h.

◆ RTL_MSR_AUX_STATUS

#define RTL_MSR_AUX_STATUS 0x10

Aux power present.

Definition at line 193 of file realtek.h.

◆ RTL_MSR_SPEED_10

#define RTL_MSR_SPEED_10 0x08

10Mbps

Definition at line 194 of file realtek.h.

◆ RTL_MSR_LINKB

#define RTL_MSR_LINKB 0x04

Inverse of link status.

Definition at line 195 of file realtek.h.

◆ RTL_MSR_TXPF

#define RTL_MSR_TXPF 0x02

TX pause flag.

Definition at line 196 of file realtek.h.

◆ RTL_MSR_RXPF

#define RTL_MSR_RXPF 0x01

RX pause flag.

Definition at line 197 of file realtek.h.

◆ RTL_PHYAR

#define RTL_PHYAR 0x60

PHY Access Register (dword, 8169 only)

Definition at line 200 of file realtek.h.

◆ RTL_PHYAR_FLAG

#define RTL_PHYAR_FLAG 0x80000000UL

Read/write flag.

Definition at line 201 of file realtek.h.

◆ RTL_PHYAR_VALUE

#define RTL_PHYAR_VALUE	(	flag,
		reg,
		data
	)	( (flag) \| ( (reg) << 16 ) \| (data) )

Construct PHY Access Register value.

Definition at line 204 of file realtek.h.

◆ RTL_PHYAR_DATA

#define RTL_PHYAR_DATA ( value ) ( (value) & 0xffff )

Extract PHY Access Register data.

Definition at line 207 of file realtek.h.

◆ RTL_MII_MAX_WAIT_US

#define RTL_MII_MAX_WAIT_US 500

Maximum time to wait for PHY access, in microseconds.

Definition at line 210 of file realtek.h.

◆ RTL_PHYSTATUS

#define RTL_PHYSTATUS 0x6c

PHY (GMII, MII, or TBI) Status Register (byte, 8169 only)

Definition at line 213 of file realtek.h.

◆ RTL_PHYSTATUS_ENTBI

#define RTL_PHYSTATUS_ENTBI 0x80

TBI / GMII mode.

Definition at line 214 of file realtek.h.

◆ RTL_PHYSTATUS_TXFLOW

#define RTL_PHYSTATUS_TXFLOW 0x40

TX flow control enabled.

Definition at line 215 of file realtek.h.

◆ RTL_PHYSTATUS_RXFLOW

#define RTL_PHYSTATUS_RXFLOW 0x20

RX flow control enabled.

Definition at line 216 of file realtek.h.

◆ RTL_PHYSTATUS_1000MF

#define RTL_PHYSTATUS_1000MF 0x10

1000Mbps full-duplex

Definition at line 217 of file realtek.h.

◆ RTL_PHYSTATUS_100M

#define RTL_PHYSTATUS_100M 0x08

100Mbps

Definition at line 218 of file realtek.h.

◆ RTL_PHYSTATUS_10M

#define RTL_PHYSTATUS_10M 0x04

10Mbps

Definition at line 219 of file realtek.h.

◆ RTL_PHYSTATUS_LINKSTS

#define RTL_PHYSTATUS_LINKSTS 0x02

Link ok.

Definition at line 220 of file realtek.h.

◆ RTL_PHYSTATUS_FULLDUP

#define RTL_PHYSTATUS_FULLDUP 0x01

Full duplex.

Definition at line 221 of file realtek.h.

◆ RTL_TPPOLL_8139CP

#define RTL_TPPOLL_8139CP 0xd9

Transmit Priority Polling Register (byte, 8139C+ only)

Definition at line 224 of file realtek.h.

◆ RTL_RMS

#define RTL_RMS 0xda

RX Packet Maximum Size Register (word)

Definition at line 227 of file realtek.h.

◆ RTL_CPCR

#define RTL_CPCR 0xe0

C+ Command Register (word)

Definition at line 230 of file realtek.h.

◆ RTL_CPCR_VLAN

#define RTL_CPCR_VLAN 0x0040

VLAN tag stripping enable.

Definition at line 231 of file realtek.h.

◆ RTL_CPCR_DAC

#define RTL_CPCR_DAC 0x0010

PCI Dual Address Cycle enable.

Definition at line 232 of file realtek.h.

◆ RTL_CPCR_MULRW

#define RTL_CPCR_MULRW 0x0008

PCI Multiple Read/Write enable.

Definition at line 233 of file realtek.h.

◆ RTL_CPCR_CPRX

#define RTL_CPCR_CPRX 0x0002

C+ receive enable.

Definition at line 234 of file realtek.h.

◆ RTL_CPCR_CPTX

#define RTL_CPCR_CPTX 0x0001

C+ transmit enable.

Definition at line 235 of file realtek.h.

◆ RTL_RDSAR

#define RTL_RDSAR 0xe4

Receive Descriptor Start Address Register (qword)

Definition at line 238 of file realtek.h.

◆ RTL_NUM_RX_DESC

#define RTL_NUM_RX_DESC 4

Number of receive descriptors.

Definition at line 241 of file realtek.h.

◆ RTL_RX_MAX_LEN

#define RTL_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ + 4 /* extra space */ )

Receive buffer length.

Definition at line 244 of file realtek.h.

Enumeration Type Documentation

◆ realtek_descriptor_flags

enum realtek_descriptor_flags

Packet descriptor flags.

Enumerator
RTL_DESC_OWN	Descriptor is owned by NIC.
RTL_DESC_EOR	End of descriptor ring.
RTL_DESC_FS	First segment descriptor.
RTL_DESC_LS	Last segment descriptor.
RTL_DESC_RES	Receive error summary.

Definition at line 36 of file realtek.h.

                               {
         /** Descriptor is owned by NIC */
         RTL_DESC_OWN = 0x8000,
         /** End of descriptor ring */
         RTL_DESC_EOR = 0x4000,
         /** First segment descriptor */
         RTL_DESC_FS = 0x2000,
         /** Last segment descriptor */
         RTL_DESC_LS = 0x1000,
         /** Receive error summary */
         RTL_DESC_RES = 0x0020,
 };

◆ realtek_legacy_status

enum realtek_legacy_status

Legacy mode status bits.

Enumerator
RTL_STAT_ROK	Received OK.

Definition at line 63 of file realtek.h.

                            {
         /** Received OK */
         RTL_STAT_ROK = 0x0001,
 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

◆ realtek_init_ring()

static void realtek_init_ring	(	struct realtek_ring *	ring,
		unsigned int	count,
		unsigned int	reg
	)

inlinestatic

Initialise descriptor ring.

Parameters

ring	Descriptor ring
count	Number of descriptors
reg	Descriptor start address register

Definition at line 272 of file realtek.h.

                                        {
         ring->len = ( count * sizeof ( ring->desc[0] ) );
         ring->reg = reg;
 }

References count, realtek_ring::desc, realtek_ring::len, reg, and realtek_ring::reg.

Referenced by realtek_probe().

Data Structures

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ RTL_BAR_SIZE

◆ RTL_DESC_SIZE_MASK

◆ RTL_RING_ALIGN

◆ RTL_IDR0

◆ RTL_MAR0

◆ RTL_MAR4

◆ RTL_TSD

◆ RTL_TSD_ERTXTH

◆ RTL_TSD_ERTXTH_DEFAULT

◆ RTL_TSD_OWN

◆ RTL_TSAD

◆ RTL_TNPDS

◆ RTL_NUM_TX_DESC

◆ RTL_RBSTART

◆ RTL_RXBUF_LEN

◆ RTL_RXBUF_PAD

◆ RTL_RXBUF_ALIGN

◆ RTL_CR

◆ RTL_CR_RST

◆ RTL_CR_RE

◆ RTL_CR_TE

◆ RTL_CR_BUFE

◆ RTL_RESET_MAX_WAIT_MS

◆ RTL_CAPR

◆ RTL_TPPOLL_8169

◆ RTL_TPPOLL_NPQ

◆ RTL_IMR

◆ RTL_IRQ_PUN_LINKCHG

◆ RTL_IRQ_TER

◆ RTL_IRQ_TOK

◆ RTL_IRQ_RER

◆ RTL_IRQ_ROK

◆ RTL_ISR

◆ RTL_TCR

◆ RTL_TCR_MXDMA

◆ RTL_TCR_MXDMA_MASK

◆ RTL_TCR_MXDMA_DEFAULT

◆ RTL_RCR

◆ RTL_RCR_STOP_WORKING

◆ RTL_RCR_RXFTH

◆ RTL_RCR_RXFTH_MASK

◆ RTL_RCR_RXFTH_DEFAULT

◆ RTL_RCR_RBLEN

◆ RTL_RCR_RBLEN_MASK

◆ RTL_RCR_RBLEN_DEFAULT

◆ RTL_RCR_MXDMA

◆ RTL_RCR_MXDMA_MASK

◆ RTL_RCR_MXDMA_DEFAULT

◆ RTL_RCR_WRAP

◆ RTL_RCR_9356SEL

◆ RTL_RCR_AB

◆ RTL_RCR_AM

◆ RTL_RCR_APM

◆ RTL_RCR_AAP

◆ RTL_9346CR

◆ RTL_9346CR_EEM

◆ RTL_9346CR_EEM_EEPROM

◆ RTL_9346CR_EEM_NORMAL

◆ RTL_9346CR_EECS

◆ RTL_9346CR_EESK

◆ RTL_9346CR_EEDI

◆ RTL_9346CR_EEDO

◆ RTL_EEPROM_ID

◆ RTL_EEPROM_ID_MAGIC

◆ RTL_EEPROM_MAC

◆ RTL_EEPROM_VPD

◆ RTL_EEPROM_VPD_LEN

◆ RTL_CONFIG1

◆ RTL_CONFIG1_VPD

◆ RTL_MSR

◆ RTL_MSR_TXFCE

◆ RTL_MSR_RXFCE

◆ RTL_MSR_AUX_STATUS

◆ RTL_MSR_SPEED_10