iPXE
realtek.h
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1 #ifndef _REALTEK_H
2 #define _REALTEK_H
3 
4 /** @file
5  *
6  * Realtek 10/100/1000 network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <ipxe/spi.h>
13 #include <ipxe/spi_bit.h>
14 #include <ipxe/nvo.h>
15 #include <ipxe/if_ether.h>
16 
17 /** PCI memory BAR size */
18 #define RTL_BAR_SIZE 0x100
19 
20 /** A packet descriptor */
22  /** Buffer size */
24  /** Flags */
26  /** Reserved */
28  /** Buffer address */
30 } __attribute__ (( packed ));
31 
32 /** Descriptor buffer size mask */
33 #define RTL_DESC_SIZE_MASK 0x3fff
34 
35 /** Packet descriptor flags */
37  /** Descriptor is owned by NIC */
38  RTL_DESC_OWN = 0x8000,
39  /** End of descriptor ring */
40  RTL_DESC_EOR = 0x4000,
41  /** First segment descriptor */
42  RTL_DESC_FS = 0x2000,
43  /** Last segment descriptor */
44  RTL_DESC_LS = 0x1000,
45  /** Receive error summary */
46  RTL_DESC_RES = 0x0020,
47 };
48 
49 /** Descriptor ring alignment */
50 #define RTL_RING_ALIGN 256
51 
52 /** A legacy mode receive packet header */
54  /** Status */
56  /** Length */
58  /** Packet data */
60 } __attribute__ (( packed ));
61 
62 /** Legacy mode status bits */
64  /** Received OK */
65  RTL_STAT_ROK = 0x0001,
66 };
67 
68 /** ID Register 0 (6 bytes) */
69 #define RTL_IDR0 0x00
70 
71 /** Multicast Register 0 (dword) */
72 #define RTL_MAR0 0x08
73 
74 /** Multicast Register 4 (dword) */
75 #define RTL_MAR4 0x0c
76 
77 /** Transmit Status of Descriptor N (dword, 8139 only) */
78 #define RTL_TSD(n) ( 0x10 + 4 * (n) )
79 #define RTL_TSD_ERTXTH(x) ( (x) << 16 ) /**< Early TX threshold */
80 #define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )
81 #define RTL_TSD_OWN 0x00002000UL /**< Ownership */
82 
83 /** Transmit Start Address of Descriptor N (dword, 8139 only) */
84 #define RTL_TSAD(n) ( 0x20 + 4 * (n) )
85 
86 /** Transmit Normal Priority Descriptors (qword) */
87 #define RTL_TNPDS 0x20
88 
89 /** Number of transmit descriptors
90  *
91  * This is a hardware limit when using legacy mode.
92  */
93 #define RTL_NUM_TX_DESC 4
94 
95 /** Receive Buffer Start Address (dword, 8139 only) */
96 #define RTL_RBSTART 0x30
97 
98 /** Receive buffer length */
99 #define RTL_RXBUF_LEN 8192
100 
101 /** Receive buffer padding */
102 #define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
103 
104 /** Receive buffer alignment */
105 #define RTL_RXBUF_ALIGN 16
106 
107 /** Command Register (byte) */
108 #define RTL_CR 0x37
109 #define RTL_CR_RST 0x10 /**< Reset */
110 #define RTL_CR_RE 0x08 /**< Receiver Enable */
111 #define RTL_CR_TE 0x04 /**< Transmit Enable */
112 #define RTL_CR_BUFE 0x01 /**< Receive buffer empty */
113 
114 /** Maximum time to wait for a reset, in milliseconds */
115 #define RTL_RESET_MAX_WAIT_MS 100
116 
117 /** Current Address of Packet Read (word, 8139 only) */
118 #define RTL_CAPR 0x38
119 
120 /** Transmit Priority Polling Register (byte, 8169 only) */
121 #define RTL_TPPOLL_8169 0x38
122 #define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
123 
124 /** Interrupt Mask Register (word) */
125 #define RTL_IMR 0x3c
126 #define RTL_IRQ_PUN_LINKCHG 0x0020 /**< Packet underrun / link change */
127 #define RTL_IRQ_TER 0x0008 /**< Transmit error */
128 #define RTL_IRQ_TOK 0x0004 /**< Transmit OK */
129 #define RTL_IRQ_RER 0x0002 /**< Receive error */
130 #define RTL_IRQ_ROK 0x0001 /**< Receive OK */
131 
132 /** Interrupt Status Register (word) */
133 #define RTL_ISR 0x3e
134 
135 /** Transmit (Tx) Configuration Register (dword) */
136 #define RTL_TCR 0x40
137 #define RTL_TCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
138 #define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )
139 #define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )
140 
141 /** Receive (Rx) Configuration Register (dword) */
142 #define RTL_RCR 0x44
143 #define RTL_RCR_STOP_WORKING 0x01000000UL /**< Here be dragons */
144 #define RTL_RCR_RXFTH(x) ( (x) << 13 ) /**< Receive FIFO threshold */
145 #define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )
146 #define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )
147 #define RTL_RCR_RBLEN(x) ( (x) << 11 ) /**< Receive buffer length */
148 #define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )
149 #define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )
150 #define RTL_RCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
151 #define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )
152 #define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )
153 #define RTL_RCR_WRAP 0x00000080UL /**< Overrun receive buffer */
154 #define RTL_RCR_9356SEL 0x00000040UL /**< EEPROM is a 93C56 */
155 #define RTL_RCR_AB 0x00000008UL /**< Accept broadcast packets */
156 #define RTL_RCR_AM 0x00000004UL /**< Accept multicast packets */
157 #define RTL_RCR_APM 0x00000002UL /**< Accept physical match */
158 #define RTL_RCR_AAP 0x00000001UL /**< Accept all packets */
159 
160 /** 93C46 (93C56) Command Register (byte) */
161 #define RTL_9346CR 0x50
162 #define RTL_9346CR_EEM(x) ( (x) << 6 ) /**< Mode select */
163 #define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 ) /**< EEPROM mode */
164 #define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 ) /**< Normal mode */
165 #define RTL_9346CR_EECS 0x08 /**< Chip select */
166 #define RTL_9346CR_EESK 0x04 /**< Clock */
167 #define RTL_9346CR_EEDI 0x02 /**< Data in */
168 #define RTL_9346CR_EEDO 0x01 /**< Data out */
169 
170 /** Word offset of ID code word within EEPROM */
171 #define RTL_EEPROM_ID ( 0x00 / 2 )
172 
173 /** EEPROM code word magic value */
174 #define RTL_EEPROM_ID_MAGIC 0x8129
175 
176 /** Word offset of MAC address within EEPROM */
177 #define RTL_EEPROM_MAC ( 0x0e / 2 )
178 
179 /** Word offset of VPD / non-volatile options within EEPROM */
180 #define RTL_EEPROM_VPD ( 0x40 / 2 )
181 
182 /** Length of VPD / non-volatile options within EEPROM */
183 #define RTL_EEPROM_VPD_LEN 0x40
184 
185 /** Configuration Register 1 (byte) */
186 #define RTL_CONFIG1 0x52
187 #define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
188 
189 /** Media Status Register (byte, 8139 only) */
190 #define RTL_MSR 0x58
191 #define RTL_MSR_TXFCE 0x80 /**< TX flow control enabled */
192 #define RTL_MSR_RXFCE 0x40 /**< RX flow control enabled */
193 #define RTL_MSR_AUX_STATUS 0x10 /**< Aux power present */
194 #define RTL_MSR_SPEED_10 0x08 /**< 10Mbps */
195 #define RTL_MSR_LINKB 0x04 /**< Inverse of link status */
196 #define RTL_MSR_TXPF 0x02 /**< TX pause flag */
197 #define RTL_MSR_RXPF 0x01 /**< RX pause flag */
198 
199 /** PHY Access Register (dword, 8169 only) */
200 #define RTL_PHYAR 0x60
201 #define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
202 
203 /** Construct PHY Access Register value */
204 #define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
205 
206 /** Extract PHY Access Register data */
207 #define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
208 
209 /** Maximum time to wait for PHY access, in microseconds */
210 #define RTL_MII_MAX_WAIT_US 500
211 
212 /** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
213 #define RTL_PHYSTATUS 0x6c
214 #define RTL_PHYSTATUS_ENTBI 0x80 /**< TBI / GMII mode */
215 #define RTL_PHYSTATUS_TXFLOW 0x40 /**< TX flow control enabled */
216 #define RTL_PHYSTATUS_RXFLOW 0x20 /**< RX flow control enabled */
217 #define RTL_PHYSTATUS_1000MF 0x10 /**< 1000Mbps full-duplex */
218 #define RTL_PHYSTATUS_100M 0x08 /**< 100Mbps */
219 #define RTL_PHYSTATUS_10M 0x04 /**< 10Mbps */
220 #define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
221 #define RTL_PHYSTATUS_FULLDUP 0x01 /**< Full duplex */
222 
223 /** Transmit Priority Polling Register (byte, 8139C+ only) */
224 #define RTL_TPPOLL_8139CP 0xd9
225 
226 /** RX Packet Maximum Size Register (word) */
227 #define RTL_RMS 0xda
228 
229 /** C+ Command Register (word) */
230 #define RTL_CPCR 0xe0
231 #define RTL_CPCR_DAC 0x0010 /**< PCI Dual Address Cycle Enable */
232 #define RTL_CPCR_MULRW 0x0008 /**< PCI Multiple Read/Write Enable */
233 #define RTL_CPCR_CPRX 0x0002 /**< C+ receive enable */
234 #define RTL_CPCR_CPTX 0x0001 /**< C+ transmit enable */
235 
236 /** Receive Descriptor Start Address Register (qword) */
237 #define RTL_RDSAR 0xe4
238 
239 /** Number of receive descriptors */
240 #define RTL_NUM_RX_DESC 4
241 
242 /** Receive buffer length */
243 #define RTL_RX_MAX_LEN \
244  ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ + 4 /* extra space */ )
245 
246 /** A Realtek descriptor ring */
247 struct realtek_ring {
248  /** Descriptors */
250  /** Descriptor ring DMA mapping */
251  struct dma_mapping map;
252  /** Producer index */
253  unsigned int prod;
254  /** Consumer index */
255  unsigned int cons;
256 
257  /** Descriptor start address register */
258  unsigned int reg;
259  /** Length (in bytes) */
260  size_t len;
261 };
262 
263 /**
264  * Initialise descriptor ring
265  *
266  * @v ring Descriptor ring
267  * @v count Number of descriptors
268  * @v reg Descriptor start address register
269  */
270 static inline __attribute__ (( always_inline)) void
271 realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
272  unsigned int reg ) {
273  ring->len = ( count * sizeof ( ring->desc[0] ) );
274  ring->reg = reg;
275 }
276 
277 /** Receive buffer (legacy mode *) */
279  /** Buffer */
280  void *data;
281  /** Buffer DMA mapping */
282  struct dma_mapping map;
283  /** Offset within buffer */
284  unsigned int offset;
285 };
286 
287 /** A Realtek network card */
288 struct realtek_nic {
289  /** Registers */
290  void *regs;
291  /** DMA device */
292  struct dma_device *dma;
293  /** SPI bit-bashing interface */
295  /** EEPROM */
297  /** Non-volatile options */
298  struct nvo_block nvo;
299  /** MII interface */
301  /** MII device */
302  struct mii_device mii;
303 
304  /** Legacy datapath mode */
305  int legacy;
306  /** PHYAR and PHYSTATUS registers are present */
308  /** TPPoll register offset */
309  unsigned int tppoll;
310 
311  /** Transmit descriptor ring */
312  struct realtek_ring tx;
313  /** Receive descriptor ring */
314  struct realtek_ring rx;
315  /** Receive I/O buffers */
317  /** Receive buffer (legacy mode) */
319 };
320 
321 #endif /* _REALTEK_H */
#define __attribute__(x)
Definition: compiler.h:10
struct realtek_descriptor * desc
Descriptors.
Definition: realtek.h:249
unsigned short uint16_t
Definition: stdint.h:11
static unsigned int unsigned int reg
Definition: myson.h:162
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: realtek.h:251
A packet descriptor.
Definition: realtek.h:21
unsigned int prod
Producer index.
Definition: realtek.h:253
SPI bit-bashing interface.
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
uint16_t length
Buffer size.
Definition: realtek.h:23
struct nvo_block nvo
Non-volatile options.
Definition: realtek.h:298
int have_phy_regs
PHYAR and PHYSTATUS registers are present.
Definition: realtek.h:307
void * data
Buffer.
Definition: realtek.h:280
uint16_t status
Status.
Definition: realtek.h:55
unsigned long long uint64_t
Definition: stdint.h:13
void * regs
Registers.
Definition: realtek.h:290
uint32_t reserved
Reserved.
Definition: realtek.h:27
A legacy mode receive packet header.
Definition: realtek.h:53
unsigned int reg
Descriptor start address register.
Definition: realtek.h:258
struct realtek_rx_buffer rxbuf
Receive buffer (legacy mode)
Definition: realtek.h:318
eeprom
Definition: 3c90x.h:232
struct mii_device mii
MII device.
Definition: realtek.h:302
An MII device.
Definition: mii.h:49
SPI interface.
struct dma_device * dma
DMA device.
Definition: realtek.h:292
realtek_legacy_status
Legacy mode status bits.
Definition: realtek.h:63
struct realtek_ring rx
Receive descriptor ring.
Definition: realtek.h:314
unsigned int offset
Offset within buffer.
Definition: realtek.h:284
Descriptor is owned by NIC.
Definition: realtek.h:38
A Realtek network card.
Definition: realtek.h:288
struct dma_mapping map
Buffer DMA mapping.
Definition: realtek.h:282
A bit-bashing SPI bus.
Definition: spi_bit.h:16
size_t len
Length (in bytes)
Definition: realtek.h:260
static void realtek_init_ring(struct realtek_ring *ring, unsigned int count, unsigned int reg)
Initialise descriptor ring.
Definition: realtek.h:271
realtek_descriptor_flags
Packet descriptor flags.
Definition: realtek.h:36
Non-volatile stored options.
A block of non-volatile stored options.
Definition: nvo.h:22
Receive buffer (legacy mode *)
Definition: realtek.h:278
uint16_t flags
Flags.
Definition: realtek.h:25
unsigned int cons
Consumer index.
Definition: realtek.h:255
unsigned char uint8_t
Definition: stdint.h:10
End of descriptor ring.
Definition: realtek.h:40
unsigned int uint32_t
Definition: stdint.h:12
int legacy
Legacy datapath mode.
Definition: realtek.h:305
struct mii_interface mdio
MII interface.
Definition: realtek.h:300
uint16_t count
Number of entries.
Definition: ena.h:22
An MII interface.
Definition: mii.h:43
unsigned int tppoll
TPPoll register offset.
Definition: realtek.h:309
Receive error summary.
Definition: realtek.h:46
An SPI device.
Definition: spi.h:86
uint64_t address
Buffer address.
Definition: realtek.h:29
uint16_t length
Length.
Definition: realtek.h:57
A Realtek descriptor ring.
Definition: realtek.h:247
Last segment descriptor.
Definition: realtek.h:44
A DMA mapping.
Definition: dma.h:32
First segment descriptor.
Definition: realtek.h:42
uint8_t data[0]
Packet data.
Definition: realtek.h:59
struct realtek_ring tx
Transmit descriptor ring.
Definition: realtek.h:312
struct io_buffer * rx_iobuf[RTL_NUM_RX_DESC]
Receive I/O buffers.
Definition: realtek.h:316
Received OK.
Definition: realtek.h:65
#define RTL_NUM_RX_DESC
Number of receive descriptors.
Definition: realtek.h:240
struct spi_bit_basher spibit
SPI bit-bashing interface.
Definition: realtek.h:294
A DMA-capable device.
Definition: dma.h:47
A persistent I/O buffer.
Definition: iobuf.h:33