USB Enhanced Host Controller Interface (EHCI) driver. More...

#include <ipxe/pci.h>
#include <ipxe/usb.h>

Data Structures
struct	ehci_periodic_frame
	A periodic frame list entry. More...

struct	ehci_transfer_descriptor
	A transfer descriptor. More...

struct	ehci_queue_head
	A queue head. More...

struct	ehci_ring
	A transfer descriptor ring. More...

struct	ehci_transfer
	An EHCI transfer. More...

struct	ehci_device
	An EHCI device. More...

struct	ehci_endpoint
	An EHCI endpoint. More...

Macros
#define	EHCI_MIN_ALIGN 32
	Minimum alignment required for data structures. More...

#define	EHCI_MTU 16384
	Maximum transfer size. More...

#define	EHCI_PAGE_ALIGN 4096
	Page-alignment required for some data structures. More...

#define	EHCI_BAR PCI_BASE_ADDRESS_0
	EHCI PCI BAR. More...

#define	EHCI_CAP_CAPLENGTH 0x00
	Capability register length. More...

#define	EHCI_CAP_HCIVERSION 0x02
	Host controller interface version number. More...

#define	EHCI_CAP_HCSPARAMS 0x04
	Structural parameters. More...

#define	EHCI_HCSPARAMS_PORTS(params) ( ( (params) >> 0 ) & 0x0f )
	Number of ports. More...

#define	EHCI_CAP_HCCPARAMS 0x08
	Capability parameters. More...

#define	EHCI_HCCPARAMS_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
	64-bit addressing capability More...

#define	EHCI_HCCPARAMS_FLSIZE(params) ( ( (params) >> 1 ) & 0x1 )
	Programmable frame list flag. More...

#define	EHCI_HCCPARAMS_EECP(params) ( ( ( (params) >> 8 ) & 0xff ) )
	EHCI extended capabilities pointer. More...

#define	EHCI_EECP_ID(eecp) ( ( (eecp) >> 0 ) & 0xff )
	EHCI extended capability ID. More...

#define	EHCI_EECP_NEXT(eecp) ( ( ( (eecp) >> 8 ) & 0xff ) )
	Next EHCI extended capability pointer. More...

#define	EHCI_EECP_ID_LEGACY 1
	USB legacy support extended capability. More...

#define	EHCI_USBLEGSUP_BIOS 0x02
	USB legacy support BIOS owned semaphore. More...

#define	EHCI_USBLEGSUP_BIOS_OWNED 0x01
	USB legacy support BIOS ownership flag. More...

#define	EHCI_USBLEGSUP_OS 0x03
	USB legacy support OS owned semaphore. More...

#define	EHCI_USBLEGSUP_OS_OWNED 0x01
	USB legacy support OS ownership flag. More...

#define	EHCI_USBLEGSUP_CTLSTS 0x04
	USB legacy support control/status. More...

#define	EHCI_OP_USBCMD 0x00
	USB command register. More...

#define	EHCI_USBCMD_RUN 0x00000001UL
	Run/stop. More...

#define	EHCI_USBCMD_HCRST 0x00000002UL
	Host controller reset. More...

#define	EHCI_USBCMD_FLSIZE(flsize) ( (flsize) << 2 )
	Frame list size. More...

#define	EHCI_USBCMD_FLSIZE_MASK EHCI_USBCMD_FLSIZE ( 3 )
	Frame list size mask. More...

#define	EHCI_FLSIZE_DEFAULT 0
	Default frame list size. More...

#define	EHCI_FLSIZE_SMALL 2
	Smallest allowed frame list size. More...

#define	EHCI_PERIODIC_FRAMES(flsize) ( 1024 >> (flsize) )
	Number of elements in frame list. More...

#define	EHCI_USBCMD_PERIODIC 0x00000010UL
	Periodic schedule enable. More...

#define	EHCI_USBCMD_ASYNC 0x00000020UL
	Asynchronous schedule enable. More...

#define	EHCI_USBCMD_ASYNC_ADVANCE 0x000040UL
	Asyncchronous schedule advance doorbell. More...

#define	EHCI_OP_USBSTS 0x04
	USB status register. More...

#define	EHCI_USBSTS_USBINT 0x00000001UL
	USB interrupt. More...

#define	EHCI_USBSTS_USBERRINT 0x00000002UL
	USB error interrupt. More...

#define	EHCI_USBSTS_PORT 0x00000004UL
	Port change detect. More...

#define	EHCI_USBSTS_ROLLOVER 0x00000008UL
	Frame list rollover. More...

#define	EHCI_USBSTS_SYSERR 0x00000010UL
	Host system error. More...

#define	EHCI_USBSTS_ASYNC_ADVANCE 0x00000020UL
	Asynchronous schedule advanced. More...

#define	EHCI_USBSTS_PERIODIC 0x00004000UL
	Periodic schedule enabled. More...

#define	EHCI_USBSTS_ASYNC 0x00008000UL
	Asynchronous schedule enabled. More...

#define	EHCI_USBSTS_HCH 0x00001000UL
	Host controller halted. More...

#define	EHCI_USBSTS_CHANGE
	USB status change mask. More...

#define	EHCI_OP_USBINTR 0x08
	USB interrupt enable register. More...

#define	EHCI_OP_FRINDEX 0x0c
	Frame index register. More...

#define	EHCI_OP_CTRLDSSEGMENT 0x10
	Control data structure segment register. More...

#define	EHCI_OP_PERIODICLISTBASE 0x14
	Periodic frame list base address register. More...

#define	EHCI_OP_ASYNCLISTADDR 0x18
	Current asynchronous list address register. More...

#define	EHCI_OP_CONFIGFLAG 0x40
	Configure flag register. More...

#define	EHCI_CONFIGFLAG_CF 0x00000001UL
	Configure flag. More...

#define	EHCI_OP_PORTSC(port) ( 0x40 + ( (port) << 2 ) )
	Port status and control register. More...

#define	EHCI_PORTSC_CCS 0x00000001UL
	Current connect status. More...

#define	EHCI_PORTSC_CSC 0x00000002UL
	Connect status change. More...

#define	EHCI_PORTSC_PED 0x00000004UL
	Port enabled. More...

#define	EHCI_PORTSC_PEC 0x00000008UL
	Port enabled/disabled change. More...

#define	EHCI_PORTSC_OCC 0x00000020UL
	Over-current change. More...

#define	EHCI_PORTSC_PR 0x00000100UL
	Port reset. More...

#define	EHCI_PORTSC_LINE_STATUS(portsc) ( ( (portsc) >> 10 ) & 0x3 )
	Line status. More...

#define	EHCI_PORTSC_LINE_STATUS_LOW 0x1
	Line status: low-speed device. More...

#define	EHCI_PORTSC_PP 0x00001000UL
	Port power. More...

#define	EHCI_PORTSC_OWNER 0x00002000UL
	Port owner. More...

#define	EHCI_PORTSC_CHANGE ( EHCI_PORTSC_CSC \| EHCI_PORTSC_PEC \| EHCI_PORTSC_OCC )
	Port status change mask. More...

#define	EHCI_LINK_TERMINATE 0x00000001UL
	List terminator. More...

#define	EHCI_LINK_TYPE(type) ( (type) << 1 )
	Frame list type. More...

#define	EHCI_LINK_TYPE_QH EHCI_LINK_TYPE ( 1 )
	Queue head type. More...

#define	EHCI_STATUS_XACT_ERR 0x08
	Transaction error. More...

#define	EHCI_STATUS_BABBLE 0x10
	Babble detected. More...

#define	EHCI_STATUS_BUFFER 0x20
	Data buffer error. More...

#define	EHCI_STATUS_HALTED 0x40
	Halted. More...

#define	EHCI_STATUS_ACTIVE 0x80
	Active. More...

#define	EHCI_FL_PID(code) ( (code) << 0 )
	PID code. More...

#define	EHCI_FL_PID_OUT EHCI_FL_PID ( 0 )
	OUT token. More...

#define	EHCI_FL_PID_IN EHCI_FL_PID ( 1 )
	IN token. More...

#define	EHCI_FL_PID_SETUP EHCI_FL_PID ( 2 )
	SETUP token. More...

#define	EHCI_FL_CERR(count) ( (count) << 2 )
	Error counter. More...

#define	EHCI_FL_CERR_MAX EHCI_FL_CERR ( 3 )
	Error counter maximum value. More...

#define	EHCI_FL_IOC 0x80
	Interrupt on completion. More...

#define	EHCI_LEN_MASK 0x7fff
	Length mask. More...

#define	EHCI_LEN_TOGGLE 0x8000
	Data toggle. More...

#define	EHCI_CHR_ADDRESS(address) ( (address) << 0 )
	Device address. More...

#define	EHCI_CHR_ENDPOINT(address) ( ( (address) & 0xf ) << 8 )
	Endpoint number. More...

#define	EHCI_CHR_EPS(eps) ( (eps) << 12 )
	Endpoint speed. More...

#define	EHCI_CHR_EPS_FULL EHCI_CHR_EPS ( 0 )
	Full-speed endpoint. More...

#define	EHCI_CHR_EPS_LOW EHCI_CHR_EPS ( 1 )
	Low-speed endpoint. More...

#define	EHCI_CHR_EPS_HIGH EHCI_CHR_EPS ( 2 )
	High-speed endpoint. More...

#define	EHCI_CHR_TOGGLE 0x00004000UL
	Explicit data toggles. More...

#define	EHCI_CHR_HEAD 0x00008000UL
	Head of reclamation list flag. More...

#define	EHCI_CHR_MAX_LEN(len) ( (len) << 16 )
	Maximum packet length. More...

#define	EHCI_CHR_CONTROL 0x08000000UL
	Control endpoint flag. More...

#define	EHCI_CAP_INTR_SCHED(uframe) ( 1 << ( (uframe) + 0 ) )
	Interrupt schedule mask. More...

#define	EHCI_CAP_SPLIT_SCHED(uframe) ( 1 << ( (uframe) + 8 ) )
	Split completion schedule mask. More...

#define	EHCI_CAP_SPLIT_SCHED_DEFAULT
	Default split completion schedule mask. More...

#define	EHCI_CAP_TT_HUB(address) ( (address) << 16 )
	Transaction translator hub address. More...

#define	EHCI_CAP_TT_PORT(port) ( (port) << 23 )
	Transaction translator port number. More...

#define	EHCI_CAP_MULT(mult) ( (mult) << 30 )
	High-bandwidth pipe multiplier. More...

#define	EHCI_RING_COUNT 64
	Number of transfer descriptors in a ring. More...

#define	EHCI_PORT_POWER_DELAY_MS 20
	Time to delay after enabling power to a port. More...

#define	EHCI_DISOWN_DELAY_MS 100
	Time to delay after releasing ownership of a port. More...

#define	EHCI_USBLEGSUP_MAX_WAIT_MS 100
	Maximum time to wait for BIOS to release ownership. More...

#define	EHCI_ASYNC_ADVANCE_MAX_WAIT_MS 100
	Maximum time to wait for asynchronous schedule to advance. More...

#define	EHCI_STOP_MAX_WAIT_MS 100
	Maximum time to wait for host controller to stop. More...

#define	EHCI_RESET_MAX_WAIT_MS 500
	Maximum time to wait for reset to complete. More...

#define	EHCI_PORT_RESET_MAX_WAIT_MS 500
	Maximum time to wait for a port reset to complete. More...

#define	EHCI_FL_TOGGLE 0x8000
	Set initial data toggle. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

static unsigned int	ehci_ring_fill (struct ehci_ring *ring)
	Calculate space used in transfer descriptor ring. More...

static unsigned int	ehci_ring_remaining (struct ehci_ring *ring)
	Calculate space remaining in transfer descriptor ring. More...

unsigned int	ehci_companion (struct pci_device *pci)
	Locate EHCI companion controller. More...

Detailed Description

USB Enhanced Host Controller Interface (EHCI) driver.

Definition in file ehci.h.

Macro Definition Documentation

◆ EHCI_MIN_ALIGN

#define EHCI_MIN_ALIGN 32

Minimum alignment required for data structures.

With the exception of the periodic frame list (which is page-aligned), data structures used by EHCI generally require 32-byte alignment and must not cross a 4kB page boundary. We simplify this requirement by aligning each structure on its own size, with a minimum of a 32 byte alignment.

Definition at line 23 of file ehci.h.

◆ EHCI_MTU

#define EHCI_MTU 16384

Maximum transfer size.

EHCI allows for transfers of up to 20kB with page-alignment, or 16kB with arbitrary alignment.

Definition at line 30 of file ehci.h.

◆ EHCI_PAGE_ALIGN

#define EHCI_PAGE_ALIGN 4096

Page-alignment required for some data structures.

Definition at line 33 of file ehci.h.

◆ EHCI_BAR

#define EHCI_BAR PCI_BASE_ADDRESS_0

EHCI PCI BAR.

Definition at line 36 of file ehci.h.

◆ EHCI_CAP_CAPLENGTH

#define EHCI_CAP_CAPLENGTH 0x00

Capability register length.

Definition at line 39 of file ehci.h.

◆ EHCI_CAP_HCIVERSION

#define EHCI_CAP_HCIVERSION 0x02

Host controller interface version number.

Definition at line 42 of file ehci.h.

◆ EHCI_CAP_HCSPARAMS

#define EHCI_CAP_HCSPARAMS 0x04

Structural parameters.

Definition at line 45 of file ehci.h.

◆ EHCI_HCSPARAMS_PORTS

#define EHCI_HCSPARAMS_PORTS ( params ) ( ( (params) >> 0 ) & 0x0f )

Number of ports.

Definition at line 48 of file ehci.h.

◆ EHCI_CAP_HCCPARAMS

#define EHCI_CAP_HCCPARAMS 0x08

Capability parameters.

Definition at line 51 of file ehci.h.

◆ EHCI_HCCPARAMS_ADDR64

#define EHCI_HCCPARAMS_ADDR64 ( params ) ( ( (params) >> 0 ) & 0x1 )

64-bit addressing capability

Definition at line 54 of file ehci.h.

◆ EHCI_HCCPARAMS_FLSIZE

#define EHCI_HCCPARAMS_FLSIZE ( params ) ( ( (params) >> 1 ) & 0x1 )

Programmable frame list flag.

Definition at line 57 of file ehci.h.

◆ EHCI_HCCPARAMS_EECP

#define EHCI_HCCPARAMS_EECP ( params ) ( ( ( (params) >> 8 ) & 0xff ) )

EHCI extended capabilities pointer.

Definition at line 60 of file ehci.h.

◆ EHCI_EECP_ID

#define EHCI_EECP_ID ( eecp ) ( ( (eecp) >> 0 ) & 0xff )

EHCI extended capability ID.

Definition at line 63 of file ehci.h.

◆ EHCI_EECP_NEXT

#define EHCI_EECP_NEXT ( eecp ) ( ( ( (eecp) >> 8 ) & 0xff ) )

Next EHCI extended capability pointer.

Definition at line 66 of file ehci.h.

◆ EHCI_EECP_ID_LEGACY

#define EHCI_EECP_ID_LEGACY 1

USB legacy support extended capability.

Definition at line 69 of file ehci.h.

◆ EHCI_USBLEGSUP_BIOS

#define EHCI_USBLEGSUP_BIOS 0x02

USB legacy support BIOS owned semaphore.

Definition at line 72 of file ehci.h.

◆ EHCI_USBLEGSUP_BIOS_OWNED

#define EHCI_USBLEGSUP_BIOS_OWNED 0x01

USB legacy support BIOS ownership flag.

Definition at line 75 of file ehci.h.

◆ EHCI_USBLEGSUP_OS

#define EHCI_USBLEGSUP_OS 0x03

USB legacy support OS owned semaphore.

Definition at line 78 of file ehci.h.

◆ EHCI_USBLEGSUP_OS_OWNED

#define EHCI_USBLEGSUP_OS_OWNED 0x01

USB legacy support OS ownership flag.

Definition at line 81 of file ehci.h.

◆ EHCI_USBLEGSUP_CTLSTS

#define EHCI_USBLEGSUP_CTLSTS 0x04

USB legacy support control/status.

Definition at line 84 of file ehci.h.

◆ EHCI_OP_USBCMD

#define EHCI_OP_USBCMD 0x00

USB command register.

Definition at line 87 of file ehci.h.

◆ EHCI_USBCMD_RUN

#define EHCI_USBCMD_RUN 0x00000001UL

Run/stop.

Definition at line 90 of file ehci.h.

◆ EHCI_USBCMD_HCRST

#define EHCI_USBCMD_HCRST 0x00000002UL

Host controller reset.

Definition at line 93 of file ehci.h.

◆ EHCI_USBCMD_FLSIZE

#define EHCI_USBCMD_FLSIZE ( flsize ) ( (flsize) << 2 )

Frame list size.

Definition at line 96 of file ehci.h.

◆ EHCI_USBCMD_FLSIZE_MASK

#define EHCI_USBCMD_FLSIZE_MASK EHCI_USBCMD_FLSIZE ( 3 )

Frame list size mask.

Definition at line 99 of file ehci.h.

◆ EHCI_FLSIZE_DEFAULT

#define EHCI_FLSIZE_DEFAULT 0

Default frame list size.

Definition at line 102 of file ehci.h.

◆ EHCI_FLSIZE_SMALL

#define EHCI_FLSIZE_SMALL 2

Smallest allowed frame list size.

Definition at line 105 of file ehci.h.

◆ EHCI_PERIODIC_FRAMES

#define EHCI_PERIODIC_FRAMES ( flsize ) ( 1024 >> (flsize) )

Number of elements in frame list.

Definition at line 108 of file ehci.h.

◆ EHCI_USBCMD_PERIODIC

#define EHCI_USBCMD_PERIODIC 0x00000010UL

Periodic schedule enable.

Definition at line 111 of file ehci.h.

◆ EHCI_USBCMD_ASYNC

#define EHCI_USBCMD_ASYNC 0x00000020UL

Asynchronous schedule enable.

Definition at line 114 of file ehci.h.

◆ EHCI_USBCMD_ASYNC_ADVANCE

#define EHCI_USBCMD_ASYNC_ADVANCE 0x000040UL

Asyncchronous schedule advance doorbell.

Definition at line 117 of file ehci.h.

◆ EHCI_OP_USBSTS

#define EHCI_OP_USBSTS 0x04

USB status register.

Definition at line 120 of file ehci.h.

◆ EHCI_USBSTS_USBINT

#define EHCI_USBSTS_USBINT 0x00000001UL

USB interrupt.

Definition at line 123 of file ehci.h.

◆ EHCI_USBSTS_USBERRINT

#define EHCI_USBSTS_USBERRINT 0x00000002UL

USB error interrupt.

Definition at line 126 of file ehci.h.

◆ EHCI_USBSTS_PORT

#define EHCI_USBSTS_PORT 0x00000004UL

Port change detect.

Definition at line 129 of file ehci.h.

◆ EHCI_USBSTS_ROLLOVER

#define EHCI_USBSTS_ROLLOVER 0x00000008UL

Frame list rollover.

Definition at line 132 of file ehci.h.

◆ EHCI_USBSTS_SYSERR

#define EHCI_USBSTS_SYSERR 0x00000010UL

Host system error.

Definition at line 135 of file ehci.h.

◆ EHCI_USBSTS_ASYNC_ADVANCE

#define EHCI_USBSTS_ASYNC_ADVANCE 0x00000020UL

Asynchronous schedule advanced.

Definition at line 138 of file ehci.h.

◆ EHCI_USBSTS_PERIODIC

#define EHCI_USBSTS_PERIODIC 0x00004000UL

Periodic schedule enabled.

Definition at line 141 of file ehci.h.

◆ EHCI_USBSTS_ASYNC

#define EHCI_USBSTS_ASYNC 0x00008000UL

Asynchronous schedule enabled.

Definition at line 144 of file ehci.h.

◆ EHCI_USBSTS_HCH

#define EHCI_USBSTS_HCH 0x00001000UL

Host controller halted.

Definition at line 147 of file ehci.h.

◆ EHCI_USBSTS_CHANGE

#define EHCI_USBSTS_CHANGE

Value:

( EHCI_USBSTS_USBINT | EHCI_USBSTS_USBERRINT |                  \
          EHCI_USBSTS_PORT | EHCI_USBSTS_ROLLOVER |                     \
          EHCI_USBSTS_SYSERR | EHCI_USBSTS_ASYNC_ADVANCE )

USB status change mask.

Definition at line 150 of file ehci.h.

◆ EHCI_OP_USBINTR

#define EHCI_OP_USBINTR 0x08

USB interrupt enable register.

Definition at line 156 of file ehci.h.

◆ EHCI_OP_FRINDEX

#define EHCI_OP_FRINDEX 0x0c

Frame index register.

Definition at line 159 of file ehci.h.

◆ EHCI_OP_CTRLDSSEGMENT

#define EHCI_OP_CTRLDSSEGMENT 0x10

Control data structure segment register.

Definition at line 162 of file ehci.h.

◆ EHCI_OP_PERIODICLISTBASE

#define EHCI_OP_PERIODICLISTBASE 0x14

Periodic frame list base address register.

Definition at line 165 of file ehci.h.

◆ EHCI_OP_ASYNCLISTADDR

#define EHCI_OP_ASYNCLISTADDR 0x18

Current asynchronous list address register.

Definition at line 168 of file ehci.h.

◆ EHCI_OP_CONFIGFLAG

#define EHCI_OP_CONFIGFLAG 0x40

Configure flag register.

Definition at line 171 of file ehci.h.

◆ EHCI_CONFIGFLAG_CF

#define EHCI_CONFIGFLAG_CF 0x00000001UL

Configure flag.

Definition at line 174 of file ehci.h.

◆ EHCI_OP_PORTSC

#define EHCI_OP_PORTSC ( port ) ( 0x40 + ( (port) << 2 ) )

Port status and control register.

Definition at line 177 of file ehci.h.

◆ EHCI_PORTSC_CCS

#define EHCI_PORTSC_CCS 0x00000001UL

Current connect status.

Definition at line 180 of file ehci.h.

◆ EHCI_PORTSC_CSC

#define EHCI_PORTSC_CSC 0x00000002UL

Connect status change.

Definition at line 183 of file ehci.h.

◆ EHCI_PORTSC_PED

#define EHCI_PORTSC_PED 0x00000004UL

Port enabled.

Definition at line 186 of file ehci.h.

◆ EHCI_PORTSC_PEC

#define EHCI_PORTSC_PEC 0x00000008UL

Port enabled/disabled change.

Definition at line 189 of file ehci.h.

◆ EHCI_PORTSC_OCC

#define EHCI_PORTSC_OCC 0x00000020UL

Over-current change.

Definition at line 192 of file ehci.h.

◆ EHCI_PORTSC_PR

#define EHCI_PORTSC_PR 0x00000100UL

Port reset.

Definition at line 195 of file ehci.h.

◆ EHCI_PORTSC_LINE_STATUS

#define EHCI_PORTSC_LINE_STATUS ( portsc ) ( ( (portsc) >> 10 ) & 0x3 )

Line status.

Definition at line 198 of file ehci.h.

◆ EHCI_PORTSC_LINE_STATUS_LOW

#define EHCI_PORTSC_LINE_STATUS_LOW 0x1

Line status: low-speed device.

Definition at line 201 of file ehci.h.

◆ EHCI_PORTSC_PP

#define EHCI_PORTSC_PP 0x00001000UL

Port power.

Definition at line 204 of file ehci.h.

◆ EHCI_PORTSC_OWNER

#define EHCI_PORTSC_OWNER 0x00002000UL

Port owner.

Definition at line 207 of file ehci.h.

◆ EHCI_PORTSC_CHANGE

#define EHCI_PORTSC_CHANGE ( EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC )

Port status change mask.

Definition at line 210 of file ehci.h.

◆ EHCI_LINK_TERMINATE

#define EHCI_LINK_TERMINATE 0x00000001UL

List terminator.

Definition at line 214 of file ehci.h.

◆ EHCI_LINK_TYPE

#define EHCI_LINK_TYPE ( type ) ( (type) << 1 )

Frame list type.

Definition at line 217 of file ehci.h.

◆ EHCI_LINK_TYPE_QH

#define EHCI_LINK_TYPE_QH EHCI_LINK_TYPE ( 1 )

Queue head type.

Definition at line 220 of file ehci.h.

◆ EHCI_STATUS_XACT_ERR

#define EHCI_STATUS_XACT_ERR 0x08

Transaction error.

Definition at line 249 of file ehci.h.

◆ EHCI_STATUS_BABBLE

#define EHCI_STATUS_BABBLE 0x10

Babble detected.

Definition at line 252 of file ehci.h.

◆ EHCI_STATUS_BUFFER

#define EHCI_STATUS_BUFFER 0x20

Data buffer error.

Definition at line 255 of file ehci.h.

◆ EHCI_STATUS_HALTED

#define EHCI_STATUS_HALTED 0x40

Halted.

Definition at line 258 of file ehci.h.

◆ EHCI_STATUS_ACTIVE

#define EHCI_STATUS_ACTIVE 0x80

Active.

Definition at line 261 of file ehci.h.

◆ EHCI_FL_PID

#define EHCI_FL_PID ( code ) ( (code) << 0 )

PID code.

Definition at line 264 of file ehci.h.

◆ EHCI_FL_PID_OUT

#define EHCI_FL_PID_OUT EHCI_FL_PID ( 0 )

OUT token.

Definition at line 267 of file ehci.h.

◆ EHCI_FL_PID_IN

#define EHCI_FL_PID_IN EHCI_FL_PID ( 1 )

IN token.

Definition at line 270 of file ehci.h.

◆ EHCI_FL_PID_SETUP

#define EHCI_FL_PID_SETUP EHCI_FL_PID ( 2 )

SETUP token.

Definition at line 273 of file ehci.h.

◆ EHCI_FL_CERR

#define EHCI_FL_CERR ( count ) ( (count) << 2 )

Error counter.

Definition at line 276 of file ehci.h.

◆ EHCI_FL_CERR_MAX

#define EHCI_FL_CERR_MAX EHCI_FL_CERR ( 3 )

Error counter maximum value.

Definition at line 279 of file ehci.h.

◆ EHCI_FL_IOC

#define EHCI_FL_IOC 0x80

Interrupt on completion.

Definition at line 282 of file ehci.h.

◆ EHCI_LEN_MASK

#define EHCI_LEN_MASK 0x7fff

Length mask.

Definition at line 285 of file ehci.h.

◆ EHCI_LEN_TOGGLE

#define EHCI_LEN_TOGGLE 0x8000

Data toggle.

Definition at line 288 of file ehci.h.

◆ EHCI_CHR_ADDRESS

#define EHCI_CHR_ADDRESS ( address ) ( (address) << 0 )

Device address.

Definition at line 305 of file ehci.h.

◆ EHCI_CHR_ENDPOINT

#define EHCI_CHR_ENDPOINT ( address ) ( ( (address) & 0xf ) << 8 )

Endpoint number.

Definition at line 308 of file ehci.h.

◆ EHCI_CHR_EPS

#define EHCI_CHR_EPS ( eps ) ( (eps) << 12 )

Endpoint speed.

Definition at line 311 of file ehci.h.

◆ EHCI_CHR_EPS_FULL

#define EHCI_CHR_EPS_FULL EHCI_CHR_EPS ( 0 )

Full-speed endpoint.

Definition at line 314 of file ehci.h.

◆ EHCI_CHR_EPS_LOW

#define EHCI_CHR_EPS_LOW EHCI_CHR_EPS ( 1 )

Low-speed endpoint.

Definition at line 317 of file ehci.h.

◆ EHCI_CHR_EPS_HIGH

#define EHCI_CHR_EPS_HIGH EHCI_CHR_EPS ( 2 )

High-speed endpoint.

Definition at line 320 of file ehci.h.

◆ EHCI_CHR_TOGGLE

#define EHCI_CHR_TOGGLE 0x00004000UL

Explicit data toggles.

Definition at line 323 of file ehci.h.

◆ EHCI_CHR_HEAD

#define EHCI_CHR_HEAD 0x00008000UL

Head of reclamation list flag.

Definition at line 326 of file ehci.h.

◆ EHCI_CHR_MAX_LEN

#define EHCI_CHR_MAX_LEN ( len ) ( (len) << 16 )

Maximum packet length.

Definition at line 329 of file ehci.h.

◆ EHCI_CHR_CONTROL

#define EHCI_CHR_CONTROL 0x08000000UL

Control endpoint flag.

Definition at line 332 of file ehci.h.

◆ EHCI_CAP_INTR_SCHED

#define EHCI_CAP_INTR_SCHED ( uframe ) ( 1 << ( (uframe) + 0 ) )

Interrupt schedule mask.

Definition at line 335 of file ehci.h.

◆ EHCI_CAP_SPLIT_SCHED

#define EHCI_CAP_SPLIT_SCHED ( uframe ) ( 1 << ( (uframe) + 8 ) )

Split completion schedule mask.

Definition at line 338 of file ehci.h.

◆ EHCI_CAP_SPLIT_SCHED_DEFAULT

#define EHCI_CAP_SPLIT_SCHED_DEFAULT

Value:

( EHCI_CAP_SPLIT_SCHED ( 2 ) | EHCI_CAP_SPLIT_SCHED ( 3 ) |     \
          EHCI_CAP_SPLIT_SCHED ( 4 ) | EHCI_CAP_SPLIT_SCHED ( 5 ) |     \
          EHCI_CAP_SPLIT_SCHED ( 6 ) | EHCI_CAP_SPLIT_SCHED ( 7 ) )

Default split completion schedule mask.

We schedule all split starts in microframe 0, on the assumption that we will never have to deal with more than sixteen actively interrupting devices via the same transaction translator. We schedule split completions for all remaining microframes after microframe 1 (in which the low-speed or full-speed transaction is assumed to execute). This is a very crude approximation designed to avoid the need for calculating exactly when low-speed and full-speed transactions will execute. Since we only ever deal with interrupt endpoints (rather than isochronous endpoints), the volume of periodic traffic is extremely low, and this approximation should remain valid.

Definition at line 354 of file ehci.h.

◆ EHCI_CAP_TT_HUB

#define EHCI_CAP_TT_HUB ( address ) ( (address) << 16 )

Transaction translator hub address.

Definition at line 360 of file ehci.h.

◆ EHCI_CAP_TT_PORT

#define EHCI_CAP_TT_PORT ( port ) ( (port) << 23 )

Transaction translator port number.

Definition at line 363 of file ehci.h.

◆ EHCI_CAP_MULT

#define EHCI_CAP_MULT ( mult ) ( (mult) << 30 )

High-bandwidth pipe multiplier.

Definition at line 366 of file ehci.h.

◆ EHCI_RING_COUNT

#define EHCI_RING_COUNT 64

Number of transfer descriptors in a ring.

This is a policy decision.

Definition at line 391 of file ehci.h.

◆ EHCI_PORT_POWER_DELAY_MS

#define EHCI_PORT_POWER_DELAY_MS 20

Time to delay after enabling power to a port.

This is not mandated by EHCI; we use the value given for xHCI.

Definition at line 425 of file ehci.h.

◆ EHCI_DISOWN_DELAY_MS

#define EHCI_DISOWN_DELAY_MS 100

Time to delay after releasing ownership of a port.

This is a policy decision.

Definition at line 431 of file ehci.h.

◆ EHCI_USBLEGSUP_MAX_WAIT_MS

#define EHCI_USBLEGSUP_MAX_WAIT_MS 100

Maximum time to wait for BIOS to release ownership.

This is a policy decision.

Definition at line 437 of file ehci.h.

◆ EHCI_ASYNC_ADVANCE_MAX_WAIT_MS

#define EHCI_ASYNC_ADVANCE_MAX_WAIT_MS 100

Maximum time to wait for asynchronous schedule to advance.

This is a policy decision.

Definition at line 443 of file ehci.h.

◆ EHCI_STOP_MAX_WAIT_MS

#define EHCI_STOP_MAX_WAIT_MS 100

Maximum time to wait for host controller to stop.

This is a policy decision.

Definition at line 449 of file ehci.h.

◆ EHCI_RESET_MAX_WAIT_MS

#define EHCI_RESET_MAX_WAIT_MS 500

Maximum time to wait for reset to complete.

This is a policy decision.

Definition at line 455 of file ehci.h.

◆ EHCI_PORT_RESET_MAX_WAIT_MS

#define EHCI_PORT_RESET_MAX_WAIT_MS 500

Maximum time to wait for a port reset to complete.

This is a policy decision.

Definition at line 461 of file ehci.h.

◆ EHCI_FL_TOGGLE

#define EHCI_FL_TOGGLE 0x8000

Set initial data toggle.

Definition at line 480 of file ehci.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

◆ ehci_ring_fill()

static unsigned int ehci_ring_fill ( struct ehci_ring * ring )

inlinestatic

Calculate space used in transfer descriptor ring.

Parameters

ring	Transfer descriptor ring

Return values

fill	Number of entries used

Definition at line 400 of file ehci.h.

                                           {
         unsigned int fill;
 
         fill = ( ring->prod - ring->cons );
         assert ( fill <= EHCI_RING_COUNT );
         return fill;
 }

References assert(), ehci_ring::cons, EHCI_RING_COUNT, fill, and ehci_ring::prod.

Referenced by ehci_dequeue(), ehci_endpoint_close(), ehci_endpoint_poll(), ehci_ring_free(), and ehci_ring_remaining().

◆ ehci_ring_remaining()

static unsigned int ehci_ring_remaining ( struct ehci_ring * ring )

inlinestatic

Calculate space remaining in transfer descriptor ring.

Parameters

ring	Transfer descriptor ring

Return values

remaining Number of entries remaining

Definition at line 415 of file ehci.h.

                                                {
         unsigned int fill = ehci_ring_fill ( ring );
 
         return ( EHCI_RING_COUNT - fill );
 }

References EHCI_RING_COUNT, ehci_ring_fill(), and fill.

Referenced by ehci_enqueue().

◆ ehci_companion()

unsigned int ehci_companion ( struct pci_device * pci )

Locate EHCI companion controller.

Parameters

pci	PCI device

Return values

busdevfn EHCI companion controller bus:dev.fn (if any)

Definition at line 420 of file ehci.c.

                                                        {
         struct pci_device tmp;
         unsigned int busdevfn;
         int rc;
 
         /* Look for an EHCI function on the same PCI device */
         busdevfn = pci->busdevfn;
         while ( ++busdevfn <= PCI_LAST_FUNC ( pci->busdevfn ) ) {
                 pci_init ( &tmp, busdevfn );
                 if ( ( rc = pci_read_config ( &tmp ) ) != 0 )
                         continue;
                 if ( tmp.class == PCI_CLASS ( PCI_CLASS_SERIAL,
                                               PCI_CLASS_SERIAL_USB,
                                               PCI_CLASS_SERIAL_USB_EHCI ) )
                         return busdevfn;
         }
 
         return 0;
 }

References busdevfn, pci_device::busdevfn, PCI_CLASS, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL_USB_EHCI, pci_init(), PCI_LAST_FUNC, pci_read_config(), rc, and tmp.

Data Structures

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ EHCI_MIN_ALIGN

◆ EHCI_MTU

◆ EHCI_PAGE_ALIGN

◆ EHCI_BAR

◆ EHCI_CAP_CAPLENGTH

◆ EHCI_CAP_HCIVERSION

◆ EHCI_CAP_HCSPARAMS

◆ EHCI_HCSPARAMS_PORTS

◆ EHCI_CAP_HCCPARAMS

◆ EHCI_HCCPARAMS_ADDR64

◆ EHCI_HCCPARAMS_FLSIZE

◆ EHCI_HCCPARAMS_EECP

◆ EHCI_EECP_ID

◆ EHCI_EECP_NEXT

◆ EHCI_EECP_ID_LEGACY

◆ EHCI_USBLEGSUP_BIOS

◆ EHCI_USBLEGSUP_BIOS_OWNED

◆ EHCI_USBLEGSUP_OS

◆ EHCI_USBLEGSUP_OS_OWNED

◆ EHCI_USBLEGSUP_CTLSTS

◆ EHCI_OP_USBCMD

◆ EHCI_USBCMD_RUN

◆ EHCI_USBCMD_HCRST

◆ EHCI_USBCMD_FLSIZE

◆ EHCI_USBCMD_FLSIZE_MASK

◆ EHCI_FLSIZE_DEFAULT

◆ EHCI_FLSIZE_SMALL

◆ EHCI_PERIODIC_FRAMES

◆ EHCI_USBCMD_PERIODIC

◆ EHCI_USBCMD_ASYNC

◆ EHCI_USBCMD_ASYNC_ADVANCE

◆ EHCI_OP_USBSTS

◆ EHCI_USBSTS_USBINT

◆ EHCI_USBSTS_USBERRINT

◆ EHCI_USBSTS_PORT

◆ EHCI_USBSTS_ROLLOVER

◆ EHCI_USBSTS_SYSERR

◆ EHCI_USBSTS_ASYNC_ADVANCE

◆ EHCI_USBSTS_PERIODIC

◆ EHCI_USBSTS_ASYNC

◆ EHCI_USBSTS_HCH

◆ EHCI_USBSTS_CHANGE

◆ EHCI_OP_USBINTR

◆ EHCI_OP_FRINDEX

◆ EHCI_OP_CTRLDSSEGMENT

◆ EHCI_OP_PERIODICLISTBASE

◆ EHCI_OP_ASYNCLISTADDR

◆ EHCI_OP_CONFIGFLAG

◆ EHCI_CONFIGFLAG_CF

◆ EHCI_OP_PORTSC

◆ EHCI_PORTSC_CCS

◆ EHCI_PORTSC_CSC

◆ EHCI_PORTSC_PED

◆ EHCI_PORTSC_PEC

◆ EHCI_PORTSC_OCC

◆ EHCI_PORTSC_PR

◆ EHCI_PORTSC_LINE_STATUS

◆ EHCI_PORTSC_LINE_STATUS_LOW

◆ EHCI_PORTSC_PP

◆ EHCI_PORTSC_OWNER

◆ EHCI_PORTSC_CHANGE

◆ EHCI_LINK_TERMINATE

◆ EHCI_LINK_TYPE

◆ EHCI_LINK_TYPE_QH

◆ EHCI_STATUS_XACT_ERR

◆ EHCI_STATUS_BABBLE

◆ EHCI_STATUS_BUFFER

◆ EHCI_STATUS_HALTED

◆ EHCI_STATUS_ACTIVE

◆ EHCI_FL_PID

◆ EHCI_FL_PID_OUT

◆ EHCI_FL_PID_IN

◆ EHCI_FL_PID_SETUP

◆ EHCI_FL_CERR

◆ EHCI_FL_CERR_MAX