iPXE
golan.h
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1 #ifndef _GOLAN_H_
2 #define _GOLAN_H_
3 
4 /*
5  * Copyright (C) 2013-2015 Mellanox Technologies Ltd.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of the
10  * License, or any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20  * 02110-1301, USA.
21  */
22 
23 FILE_LICENCE ( GPL2_OR_LATER );
24 
25 #include <ipxe/pci.h>
26 #include <ipxe/pcibackup.h>
27 #include <byteswap.h>
28 #include <errno.h>
29 #include <ipxe/io.h>
30 #include <stdio.h>
31 #include <unistd.h>
32 #include "CIB_PRM.h"
34 
35 #define GOLAN_PCI_CONFIG_BAR_SIZE 0x100000//HERMON_PCI_CONFIG_BAR_SIZE //TODO: What is the BAR size?
36 
37 #define GOLAN_PAS_SIZE sizeof(uint64_t)
38 
39 #define GOLAN_INVALID_LKEY 0x00000100UL
40 
41 #define GOLAN_MAX_PORTS 2
42 #define GOLAN_PORT_BASE 1
43 
44 #define MELLANOX_VID 0x15b3
45 #define GOLAN_HCA_BAR PCI_BASE_ADDRESS_0 //BAR 0
46 
47 #define GOLAN_HCR_MAX_WAIT_MS 10000
48 
49 #define min(a,b) ((a)<(b)?(a):(b))
50 
51 #define GOLAN_PAGE_SHIFT 12
52 #define GOLAN_PAGE_SIZE (1 << GOLAN_PAGE_SHIFT)
53 #define GOLAN_PAGE_MASK (GOLAN_PAGE_SIZE - 1)
54 
55 #define MAX_MBOX ( GOLAN_PAGE_SIZE / MAILBOX_STRIDE )
56 #define DEF_CMD_IDX 1
57 #define MEM_CMD_IDX 0
58 #define NO_MBOX 0xffff
59 #define MEM_MBOX MEM_CMD_IDX
60 #define GEN_MBOX DEF_CMD_IDX
61 
62 #define CMD_IF_REV 4
63 
64 #define MAX_PASE_MBOX ((GOLAN_CMD_PAS_CNT) - 2)
65 
66 #define CMD_STATUS( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->status
67 #define CMD_SYND( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->syndrome
68 #define QRY_PAGES_OUT( golan, idx ) ((struct golan_query_pages_outbox *)(get_cmd( (golan) , (idx) )->out))
69 
70 #define VIRT_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )virt_to_bus(addr)))
71 #define BE64_BUS_2_VIRT( addr ) bus_to_virt(be64_to_cpu(addr))
72 #define USR_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )user_to_phys(addr, 0)))
73 #define BE64_BUS_2_USR( addr ) be64_to_cpu(phys_to_user(addr))
74 
75 #define GET_INBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.inbox))[idx]))
76 #define GET_OUTBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.outbox))[idx]))
77 
78 #define GOLAN_MBOX_IN( cmd_ptr, in_ptr ) ( { \
79  union { \
80  __be32 raw[4]; \
81  typeof ( *(in_ptr) ) cooked; \
82  } *u = container_of ( &(cmd_ptr)->in[0], typeof ( *u ), raw[0] ); \
83  &u->cooked; } )
84 
85 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
86 
87 /* Fw status fields */
88 typedef enum {
89  NO_ERRORS = 0x0,
91  TOKEN_ERROR = 0x2,
93  BAD_OUTPUT_POINTER = 0x4, // pointer not align to mailbox size
94  BAD_INPUT_POINTER = 0x5, // pointer not align to mailbox size
96  INPUT_LEN_ERROR = 0x7, // input length less than 0x8.
97  OUTPUT_LEN_ERROR = 0x8, // output length less than 0x8.
99  BAD_CMD_TYPE = 0x10,
100 } return_hdr_t;
101 
103  void *addr;
106 };
107 
108 struct golan_uar {
110  void *virt;
111  unsigned long phys;
112 };
113 
114 
116  /* length of area in pages */
118  /** Firmware area in external memory
119  *
120  * This is allocated when first needed, and freed only on
121  * final teardown, in order to avoid memory map changes at
122  * runtime.
123  */
125 };
126 /* Queue Pair */
127 #define GOLAN_SEND_WQE_BB_SIZE 64
128 #define GOLAN_SEND_UD_WQE_SIZE sizeof(struct golan_send_wqe_ud)
129 #define GOLAN_RECV_WQE_SIZE sizeof(struct golan_recv_wqe_ud)
130 #define GOLAN_WQEBBS_PER_SEND_UD_WQE DIV_ROUND_UP(GOLAN_SEND_UD_WQE_SIZE, GOLAN_SEND_WQE_BB_SIZE)
131 #define GOLAN_SEND_OPCODE 0x0a
132 #define GOLAN_WQE_CTRL_WQE_IDX_BIT 8
133 
142 };
143 
148 };
149 
153 };
154 
157 };
158 
161  /* WQ size in bytes */
162  int size;
163  /* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
165  /** GRH buffers (if applicable) */
167  /** Size of GRH buffers */
168  size_t grh_size;
169 };
170 
173  /* WQ size in bytes */
174  int size;
175  /* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
177 };
178 
180  void *wqes;
181  int size;
187 };
188 
189 /* Completion Queue */
190 #define GOLAN_CQE_OPCODE_NOT_VALID 0x0f
191 #define GOLAN_CQE_OPCODE_BIT 4
192 #define GOLAN_CQ_DB_RECORD_SIZE sizeof(uint64_t)
193 #define GOLAN_CQE_OWNER_MASK 1
194 
195 #define MANAGE_PAGES_PSA_OFFSET 0
196 #define PXE_CMDIF_REF 5
197 
198 enum {
201 };
202 
203 enum {
206 };
207 
209  struct golan_cqe64 *cqes;
210  int size;
212 };
213 
214 
215 /* Event Queue */
216 #define GOLAN_EQE_SIZE sizeof(struct golan_eqe)
217 #define GOLAN_NUM_EQES 8
218 #define GOLAN_EQ_DOORBELL_OFFSET 0x40
219 #define DB_BUFFER0_EVEN_OFFSET 0x800
220 #define DB_BUFFER0_ODD_OFFSET 0x900
221 
222 #define GOLAN_EQ_MAP_ALL_EVENTS \
223  ((1 << GOLAN_EVENT_TYPE_PATH_MIG )| \
224  (1 << GOLAN_EVENT_TYPE_COMM_EST )| \
225  (1 << GOLAN_EVENT_TYPE_SQ_DRAINED )| \
226  (1 << GOLAN_EVENT_TYPE_SRQ_LAST_WQE )| \
227  (1 << GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT )| \
228  (1 << GOLAN_EVENT_TYPE_CQ_ERROR )| \
229  (1 << GOLAN_EVENT_TYPE_WQ_CATAS_ERROR )| \
230  (1 << GOLAN_EVENT_TYPE_PATH_MIG_FAILED )| \
231  (1 << GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR )| \
232  (1 << GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR )| \
233  (1 << GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR )| \
234  (1 << GOLAN_EVENT_TYPE_INTERNAL_ERROR )| \
235  (1 << GOLAN_EVENT_TYPE_PORT_CHANGE )| \
236  (1 << GOLAN_EVENT_TYPE_GPIO_EVENT )| \
237  (1 << GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER )| \
238  (1 << GOLAN_EVENT_TYPE_REMOTE_CONFIG )| \
239  (1 << GOLAN_EVENT_TYPE_DB_BF_CONGESTION )| \
240  (1 << GOLAN_EVENT_TYPE_STALL_EVENT )| \
241  (1 << GOLAN_EVENT_TYPE_PACKET_DROPPED )| \
242  (1 << GOLAN_EVENT_TYPE_CMD )| \
243  (1 << GOLAN_EVENT_TYPE_PAGE_REQUEST ))
244 
247 
253 
260 
264 // GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER = 0x16,
266 
269 
271 
275 };
276 
285 };
286 
287 
288 enum {
291 };
292 
293 enum {
296 };
297 
301  struct golan_eqe *eqes;
302  int size;
305 };
306 
307 struct golan_port {
308  /** Infiniband device */
309  struct ib_device *ibdev;
310  /** Network device */
312  /** VEP number */
314 };
315 
316 struct golan_mboxes {
317  void *inbox;
318  void *outbox;
319 };
320 
321 #define GOLAN_OPEN 0x1
322 
323 struct golan {
324  struct pci_device *pci;
327  struct golan_hca_cap caps; /* stored as big indian*/
329  struct list_head pages;
332  struct golan_uar uar;
338 
340 #define GOLAN_FW_AREAS_NUM 2
342 };
343 
344 #endif /* _GOLAN_H_*/
uint16_t u16
Definition: stdint.h:21
u32 doorbell_qpn
Definition: golan.h:185
iPXE I/O API
u16 next_idx
Definition: golan.h:176
struct golan_wqe_data_seg data[2]
Definition: golan.h:156
struct golan_firmware_area fw_areas[GOLAN_FW_AREAS_NUM]
Definition: golan.h:341
golan_port_sub_event
Definition: golan.h:277
return_hdr_t
Definition: golan.h:88
u16 next_idx
Definition: golan.h:164
uint32_t pdn
Definition: golan.h:334
Error codes.
struct golan_wqe_ctrl_seg ctrl
Definition: golan.h:145
unsigned long long uint64_t
Definition: stdint.h:13
struct pci_device * pci
Definition: golan.h:324
#define GOLAN_WQEBBS_PER_SEND_UD_WQE
Definition: golan.h:130
u32 mkey
Definition: golan.h:335
struct golan_hca_cap caps
Definition: golan.h:327
uint32_t cmd_bm
Definition: golan.h:330
unsigned long long __be64
Definition: CIB_PRM.h:25
A doubly-linked list entry (or list head)
Definition: list.h:18
An Infiniband device.
Definition: infiniband.h:398
u8 vep_number
VEP number.
Definition: golan.h:313
#define GOLAN_FW_AREAS_NUM
Definition: golan.h:340
uint8_t pad[GOLAN_WQEBBS_PER_SEND_UD_WQE *GOLAN_SEND_WQE_BB_SIZE]
Definition: golan.h:152
#define GOLAN_MAX_PORTS
Definition: golan.h:41
uint8_t eqn
Definition: golan.h:299
mlx_utils * utils
Definition: golan.h:337
Definition: golan.h:323
union golan_send_wqe * wqes
Definition: golan.h:172
struct golan_av datagram
Definition: golan.h:146
struct golan_port ports[GOLAN_MAX_PORTS]
Definition: golan.h:339
struct golan_hca_init_seg * iseg
Definition: golan.h:325
uint32_t cons_index
Definition: golan.h:304
uint32_t index
Definition: golan.h:109
void * wqes
Definition: golan.h:180
void * outbox
Definition: golan.h:318
An Infiniband Global Route Header.
Definition: ib_packet.h:89
u32 flags
Definition: golan.h:336
struct golan_wqe_data_seg data
Definition: golan.h:147
struct golan_mboxes mboxes
Definition: golan.h:328
golan_event
Definition: golan.h:245
struct net_device * netdev
Network device.
Definition: golan.h:311
PCI bus.
size_t grh_size
Size of GRH buffers.
Definition: golan.h:168
A PCI device.
Definition: pci.h:187
struct ib_device * ibdev
Infiniband device.
Definition: golan.h:309
A network device.
Definition: netdevice.h:348
void * virt
Definition: golan.h:110
struct golan_uar uar
Definition: golan.h:332
unsigned char uint8_t
Definition: stdint.h:10
unsigned int uint32_t
Definition: stdint.h:12
struct golan_event_queue eq
Definition: golan.h:333
uint32_t total_dma_pages
Definition: golan.h:331
struct ib_global_route_header * grh
GRH buffers (if applicable)
Definition: golan.h:166
uint32_t npages
Definition: golan.h:117
__be64 * doorbell_record
Definition: golan.h:211
struct golan_send_wq sq
Definition: golan.h:183
u16 log_stride
Definition: golan.h:104
uint32_t __be32
Definition: CIB_PRM.h:26
struct golan_recv_wqe_ud * wqes
Definition: golan.h:160
int size
Definition: golan.h:162
int size
Definition: golan.h:174
struct golan_cqe64 * cqes
Definition: golan.h:209
void * inbox
Definition: golan.h:317
struct golan_recv_wq rq
Definition: golan.h:182
struct golan_send_wqe_ud ud
Definition: golan.h:151
unsigned long phys
Definition: golan.h:111
struct golan_qp_db * doorbell_record
Definition: golan.h:184
struct golan_cmdq_md cmd
Definition: golan.h:326
struct list_head pages
Definition: golan.h:329
#define GOLAN_SEND_WQE_BB_SIZE
Definition: golan.h:127
enum golan_ib_qp_state state
Definition: golan.h:186
uint64_t mask
Definition: golan.h:300
FILE_LICENCE(GPL2_OR_LATER)
struct golan_eqe * eqes
Definition: golan.h:301
u16 size
Definition: golan.h:105
void * addr
Definition: golan.h:103
userptr_t area
Firmware area in external memory.
Definition: golan.h:124
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
unsigned long userptr_t
A pointer to a user buffer.
Definition: uaccess.h:33
__be32 * doorbell
Definition: golan.h:303
golan_ib_qp_state
Definition: golan.h:134
PCI configuration space backup and restoration.