20 #define INTELXL_BAR_SIZE 0x200000 26 #define INTELXL_ALIGN 256 36 #define INTELXL_ADMIN_CMD 0x080000 39 #define INTELXL_ADMIN_EVT 0x080080 42 #define INTELXL_ADMIN_BAL 0x000 45 #define INTELXL_ADMIN_BAH 0x100 48 #define INTELXL_ADMIN_LEN 0x200 49 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) 50 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL 53 #define INTELXL_ADMIN_HEAD 0x300 56 #define INTELXL_ADMIN_TAIL 0x400 87 #define INTELXL_ADMIN_VERSION 0x0001 110 #define INTELXL_ADMIN_DRIVER 0x0002 135 #define INTELXL_ADMIN_SHUTDOWN 0x0003 146 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01 149 #define INTELXL_ADMIN_MAC_READ 0x0107 160 #define INTELXL_ADMIN_MAC_READ_VALID_LAN 0x10 175 #define INTELXL_ADMIN_MAC_WRITE 0x0108 192 #define INTELXL_ADMIN_CLEAR_PXE 0x0110 203 #define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02 206 #define INTELXL_ADMIN_SWITCH 0x0200 231 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19 256 #define INTELXL_ADMIN_VSI 0x0212 283 #define INTELXL_ADMIN_PROMISC 0x0254 298 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001 301 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002 304 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004 307 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010 310 #define INTELXL_ADMIN_MAC_CONFIG 0x0603 323 #define INTELXL_ADMIN_MAC_CONFIG_FL_CRC 0x04 326 #define INTELXL_ADMIN_AUTONEG 0x0605 337 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02 340 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04 343 #define INTELXL_ADMIN_LINK 0x0607 362 #define INTELXL_ADMIN_LINK_NOTIFY 0x03 365 #define INTELXL_ADMIN_LINK_UP 0x01 398 #define INTELXL_ADMIN_BUFFER_SIZE 0x1000 433 #define INTELXL_ADMIN_FL_DD 0x0001 436 #define INTELXL_ADMIN_FL_CMP 0x0002 439 #define INTELXL_ADMIN_FL_ERR 0x0004 442 #define INTELXL_ADMIN_FL_RD 0x0400 445 #define INTELXL_ADMIN_FL_BUF 0x1000 448 #define INTELXL_ADMIN_EEXIST 13 483 #define INTELXL_ADMIN_NUM_DESC 4 486 #define INTELXL_ADMIN_MAX_WAIT_MS 100 489 #define INTELXL_ADMIN_API_MAJOR 1 499 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) ) 502 #define INTELXL_PFCM_LANCTXCTL 0x10c300 503 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \ 505 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \ 507 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \ 509 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \ 510 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) 511 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \ 512 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) 513 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \ 515 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \ 516 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) 517 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \ 518 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) 521 #define INTELXL_PFCM_LANCTXSTAT 0x10c380 522 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL 551 #define INTELXL_CTX_TX_FL_NEW 0x4000 554 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 ) 557 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 ) 560 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 ) 583 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \ 584 ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) ) 587 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 ) 590 #define INTELXL_CTX_RX_FL_DSIZE 0x10 593 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20 596 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 ) 599 #define INTELXL_CTX_MAX_WAIT_MS 100 602 #define INTELXL_QUEUE_ENABLE_DELAY_US 20 605 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400 608 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000 618 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) ) 621 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) ) 622 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \ 624 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \ 626 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \ 630 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) ) 633 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) ) 636 #define INTELXL_QXX_ENA 0x0000 637 #define INTELXL_QXX_ENA_REQ 0x00000001UL 638 #define INTELXL_QXX_ENA_STAT 0x00000004UL 641 #define INTELXL_QXX_CTL 0x4000 642 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) 643 #define INTELXL_QXX_CTL_PFVF_Q_PF \ 644 INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) 645 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) 648 #define INTELXL_QXX_TAIL 0x8000 661 #define INTELXL_TX_DATA_DTYP 0x0 664 #define INTELXL_TX_DATA_EOP 0x10 667 #define INTELXL_TX_DATA_RS 0x20 677 #define INTELXL_TX_DATA_JFDI 0x40 680 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 ) 693 #define INTELXL_TX_WB_FL_DD 0x01 730 #define INTELXL_RX_WB_FL_DD 0x00000001UL 733 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL 736 #define INTELXL_RX_WB_FL_RXE 0x00080000UL 739 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff ) 803 #define INTELXL_TX_NUM_DESC 64 806 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 ) 812 #define INTELXL_RX_NUM_DESC 64 818 #define INTELXL_RX_FILL 16 821 #define INTELXL_MAX_PKT_LEN ( 9728 - 4 ) 831 #define INTELXL_PFINT_DYN_CTL0 0x038480 832 #define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL 833 #define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL 834 #define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL 837 #define INTELXL_PFINT_LNKLST0 0x038500 838 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \ 840 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \ 841 INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) 842 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \ 844 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \ 845 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) 846 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \ 847 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) 850 #define INTELXL_PFINT_ICR0_ENA 0x038800 851 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL 854 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) ) 855 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) 856 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \ 857 INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) 858 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) 859 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \ 860 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) 861 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \ 862 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) 863 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL 866 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) ) 867 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) 868 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \ 869 INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) 870 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) 871 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \ 872 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) 873 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \ 874 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) 875 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL 878 #define INTELXL_PFFUNC_RID 0x09c000 879 #define INTELXL_PFFUNC_RID_FUNC_NUM(x) \ 880 ( ( (x) >> 0 ) & 0x7 ) 883 #define INTELXL_PFLAN_QALLOC 0x1c0400 884 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \ 885 ( ( (x) >> 0 ) & 0x7ff ) 886 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \ 887 ( ( (x) >> 16 ) & 0x7ff ) 890 #define INTELXL_PFGEN_PORTNUM 0x1c0480 891 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \ 892 ( ( (x) >> 0 ) & 0x3 ) 905 #define INTELXL_MSIX_VECTOR 0 uint8_t reserved_a[2]
Reserved.
uint8_t reserved_b[8]
Reserved.
uint16_t len
Data buffer length.
uint16_t info
Element specific information.
uint16_t head
Head pointer.
size_t len
Length (in bytes)
struct dma_device * dma
DMA device.
struct intelxl_admin_mac_config_params mac_config
Set MAC Configuration command parameters.
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
uint8_t reserved[13]
Reserved.
Admin queue data buffer command parameters.
struct pci_msix cap
PCI capability.
uint64_t address
Data buffer address.
void intelxl_free_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Admin queue Get Switch Configuration data buffer.
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
uint8_t pad[INTELXL_ADMIN_BUFFER_SIZE]
Maximum buffer size.
struct dma_mapping map
DMA mapping for dummy interrupt target.
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
uint16_t head
Head pointer.
uint8_t reserved[4]
Reserved.
Admin queue Get Link Status command parameters.
uint16_t mfs
Maximum frame size.
uint8_t reserved_b[11]
Reserved.
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
struct intelxl_admin_mac_read_params mac_read
Manage MAC Address Read command parameters.
uint32_t vector
MSI-X vector.
uint16_t queue[16]
Queue numbers.
union intelxl_admin_buffer * buf
Data buffers.
uint16_t qset[8]
Queue set handles for each traffic class.
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Admin queue register offsets.
Admin queue Restart Autonegotiation command parameters.
uint64_t address
Base address.
uint8_t type
Switching element type.
union intelxl_ring::@66 desc
Descriptors.
Admin queue Driver Version data buffer.
Admin queue Get VSI Parameters command parameters.
unsigned int qset
Queue set handle.
uint16_t count
Number of switching elements reported.
unsigned int prod
Producer index.
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Admin queue Shutdown command parameters.
char name[32]
Driver name.
unsigned long long uint64_t
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
unsigned int len
Length Register offset.
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
unsigned int bal
Base Address Low Register offset.
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
uint16_t ret
Return value.
size_t mfs
Maximum frame size.
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Admin queue Set MAC Configuration command parameters.
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned int base
Register block base.
union intelxl_tx_descriptor * tx
Transmit descriptors.
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
struct intelxl_admin_version api
API version.
uint8_t reserved_a[12]
Reserved.
uint8_t reserved[10]
Reserved.
unsigned int queue
Queue number.
Admin queue Clear PXE Mode command parameters.
unsigned int exp
PCI Express capability offset.
uint8_t revision
Revision.
uint8_t reserved[4]
Reserved.
uint32_t cookie
Opaque cookie.
#define INTELXL_ADMIN_BUFFER_SIZE
Maximum size of a data buffer.
uint64_t address
Data buffer address.
uint8_t reserved[15]
Reserved.
Admin queue command parameters.
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
unsigned int cons
Consumer index.
uint64_t address
Buffer address.
struct intelxl_admin_mac_write_params mac_write
Manage MAC Address Write command parameters.
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
uint8_t pf[ETH_ALEN]
Physical function MAC address.
struct intelxl_ring rx
Receive descriptor ring.
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
uint8_t reserved_a[1]
Reserved.
uint8_t reserved_a[2]
Reserved.
unsigned int index
Queue index.
uint8_t reserved_b[3]
Reserved.
Transmit writeback descriptor.
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
uint8_t magic
Magic value.
uint8_t sub
Sub-build version.
Admin queue version number.
unsigned int vsi
Virtual Station Interface switching element ID.
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
uint16_t high
MAC address first 16 bits, byte-swapped.
uint8_t wol[ETH_ALEN]
Physical function wake-on-LAN MAC address.
uint16_t count
Queue count.
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Admin queue Manage MAC Address Read data buffer.
static struct net_device * netdev
uint16_t minor
Minor version number.
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
uint16_t count
Number of entries.
struct intelxl_admin_promisc_params promisc
Set VSI Promiscuous Modes command parameters.
uint32_t low
MAC address last 32 bits, byte-swapped.
uint8_t reserved_a[8]
Reserved.
uint16_t downlink
Downlink switching element ID.
uint8_t reserved[15]
Reserved.
struct intelxl_msix msix
MSI-X interrupt.
uint8_t reserved_a
Reserved.
struct dma_mapping map
DMA mapping.
uint8_t reserved_b[4]
Reserved.
unsigned int reg
Register block.
uint32_t caps
Device capabilities.
uint8_t reserved_a[8]
Reserved.
struct intelxl_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
struct intelxl_admin_version_params version
Get Version command parameters.
uint16_t total
Total number of switching elements.
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Admin queue Driver Version command parameters.
Admin queue Manage MAC Address Read command parameters.
union intelxl_rx_descriptor * rx
Receive descriptors.
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
uint8_t minor
Minor version.
unsigned int intr
Interrupt control register.
uint32_t build
Firmware build ID.
struct intelxl_admin_descriptor * desc
Descriptors.
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
uint8_t reserved_b[7]
Reserved.
uint64_t base_count
Base address and queue count.
uint64_t base
Base address.
struct dma_mapping map
Descriptor ring DMA mapping.
unsigned int port
Port number.
unsigned int head
Head Register offset.
uint8_t valid
Valid addresses.
uint8_t reserved[20]
Reserved.
Admin queue Get Version command parameters.
Transmit data descriptor.
uint8_t reserved_c[2]
Reserved.
An Intel 40 Gigabit network card.
uint16_t vsi
VSI switching element ID.
uint8_t reserved_b[100]
Reserved.
union intelxl_admin_params params
Parameters.
uint8_t connection
Connection type.
uint8_t notify
Link status notification.
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
uint8_t reserved_c[4]
Reserved.
uint32_t high
Buffer address high.
struct intelxl_ring tx
Transmit descriptor ring.
uint64_t address
Buffer address.
uint16_t major
Major version number.
uint32_t teid
Transmit element ID.
struct intelxl_admin_switch_params sw
Get Switch Configuration command parameters.
uint16_t vsi
VSI switching element ID.
struct intelxl_admin_link_params link
Get Link Status command parameters.
Admin queue Set VSI Promiscuous Modes command parameters.
struct intelxl_admin_shutdown_params shutdown
Shutdown command parameters.
uint8_t unloading
Driver unloading.
uint16_t next
Starting switching element identifier.
unsigned int pf
Physical function number.
struct intelxl_admin_vsi_params vsi
Get VSI Parameters command parameters.
uint32_t low
Buffer address low.
uint16_t uplink
Uplink switching element ID.
struct intelxl_admin_clear_pxe_params pxe
Clear PXE Mode command parameters.
unsigned int bah
Base Address High Register offset.
uint16_t mfs
Maximum frame size.
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
uint8_t reserved_a[30]
Reserved.
Admin queue Manage MAC Address Write command parameters.
uint8_t reserved[15]
Reserved.
uint8_t reserved[ETH_ALEN]
Reserved.
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
uint8_t reserved_c[16]
Reserved.
Switching element configuration.
uint8_t reserved_c[16]
Reserved.
uint8_t reserved_b[34]
Reserved.
unsigned int base
Absolute queue number base.
struct intelxl_admin_switch_config cfg
Switch configuration.
uint8_t major
Driver version.
Admin queue Get VSI Parameters data buffer.
unsigned int tail
Tail register.
Receive writeback descriptor.
unsigned int tail
Tail Register offset.
uint8_t build
Build version.
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
uint8_t reserved[6]
Reserved.
const struct intelxl_admin_offsets * regs
Register offsets.
struct intelxl_admin_version firmware
Firmware version.
struct intelxl_admin_driver_params driver
Driver Version command parameters.
Admin queue Get Switch Configuration command parameters.
uint8_t status
Link status.
uint16_t valid
Valid flags.
uint8_t reserved[8]
Reserved.
uint8_t port[ETH_ALEN]
Port MAC address.
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
uint16_t seid
Switching element ID.
struct intelxl_admin_autoneg_params autoneg
Restart Autonegotiation command parameters.
uint8_t reserved[6]
Reserved.
struct intelxl_admin event
Admin event queue.
uint8_t reserved_c[8]
Reserved.
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
uint64_t address
Data buffer address.
uint32_t msg
MSI-X dummy interrupt target.
unsigned int vopcode
Current VF opcode.
struct intelxl_rx_data_descriptor data
Receive data descriptor.
uint8_t reserved_b[7]
Reserved.
uint8_t reserved[15]
Reserved.
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.