iPXE
intelxl.h
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1 #ifndef _INTELX_H
2 #define _INTELX_H
3 
4 /** @file
5  *
6  * Intel 40 Gigabit Ethernet network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/pcimsix.h>
15 
16 struct intelxl_nic;
17 
18 /** BAR size */
19 #define INTELXL_BAR_SIZE 0x200000
20 
21 /** Alignment
22  *
23  * No data structure requires greater than 256 byte alignment.
24  */
25 #define INTELXL_ALIGN 256
26 
27 /******************************************************************************
28  *
29  * Admin queue
30  *
31  ******************************************************************************
32  */
33 
34 /** PF Admin Command Queue register block */
35 #define INTELXL_ADMIN_CMD 0x080000
36 
37 /** PF Admin Event Queue register block */
38 #define INTELXL_ADMIN_EVT 0x080080
39 
40 /** Admin Queue Base Address Low Register (offset) */
41 #define INTELXL_ADMIN_BAL 0x000
42 
43 /** Admin Queue Base Address High Register (offset) */
44 #define INTELXL_ADMIN_BAH 0x100
45 
46 /** Admin Queue Length Register (offset) */
47 #define INTELXL_ADMIN_LEN 0x200
48 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
49 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
50 
51 /** Admin Queue Head Register (offset) */
52 #define INTELXL_ADMIN_HEAD 0x300
53 
54 /** Admin Queue Tail Register (offset) */
55 #define INTELXL_ADMIN_TAIL 0x400
56 
57 /** Admin queue register offsets
58  *
59  * The physical and virtual function register maps have no discernible
60  * relationship.
61  */
63  /** Base Address Low Register offset */
64  unsigned int bal;
65  /** Base Address High Register offset */
66  unsigned int bah;
67  /** Length Register offset */
68  unsigned int len;
69  /** Head Register offset */
70  unsigned int head;
71  /** Tail Register offset */
72  unsigned int tail;
73 };
74 
75 /** Admin queue data buffer command parameters */
77  /** Reserved */
79  /** Buffer address high */
81  /** Buffer address low */
83 } __attribute__ (( packed ));
84 
85 /** Admin queue Get Version command */
86 #define INTELXL_ADMIN_VERSION 0x0001
87 
88 /** Admin queue version number */
90  /** Major version number */
92  /** Minor version number */
94 } __attribute__ (( packed ));
95 
96 /** Admin queue Get Version command parameters */
98  /** ROM version */
100  /** Firmware build ID */
102  /** Firmware version */
104  /** API version */
106 } __attribute__ (( packed ));
107 
108 /** Admin queue Driver Version command */
109 #define INTELXL_ADMIN_DRIVER 0x0002
110 
111 /** Admin queue Driver Version command parameters */
113  /** Driver version */
115  /** Minor version */
117  /** Build version */
119  /** Sub-build version */
121  /** Reserved */
123  /** Data buffer address */
125 } __attribute__ (( packed ));
126 
127 /** Admin queue Driver Version data buffer */
129  /** Driver name */
130  char name[32];
131 } __attribute__ (( packed ));
132 
133 /** Admin queue Shutdown command */
134 #define INTELXL_ADMIN_SHUTDOWN 0x0003
135 
136 /** Admin queue Shutdown command parameters */
138  /** Driver unloading */
140  /** Reserved */
142 } __attribute__ (( packed ));
143 
144 /** Driver is unloading */
145 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
146 
147 /** Admin queue Clear PXE Mode command */
148 #define INTELXL_ADMIN_CLEAR_PXE 0x0110
149 
150 /** Admin queue Clear PXE Mode command parameters */
152  /** Magic value */
154  /** Reserved */
156 } __attribute__ (( packed ));
157 
158 /** Clear PXE Mode magic value */
159 #define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
160 
161 /** Admin queue Get Switch Configuration command */
162 #define INTELXL_ADMIN_SWITCH 0x0200
163 
164 /** Switching element configuration */
166  /** Switching element type */
168  /** Revision */
170  /** Switching element ID */
172  /** Uplink switching element ID */
174  /** Downlink switching element ID */
176  /** Reserved */
178  /** Connection type */
180  /** Reserved */
182  /** Element specific information */
184 } __attribute__ (( packed ));
185 
186 /** Virtual Station Inferface element type */
187 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
188 
189 /** Admin queue Get Switch Configuration command parameters */
191  /** Starting switching element identifier */
193  /** Reserved */
195  /** Data buffer address */
197 } __attribute__ (( packed ));
198 
199 /** Admin queue Get Switch Configuration data buffer */
201  /** Number of switching elements reported */
203  /** Total number of switching elements */
205  /** Reserved */
207  /** Switch configuration */
209 } __attribute__ (( packed ));
210 
211 /** Admin queue Get VSI Parameters command */
212 #define INTELXL_ADMIN_VSI 0x0212
213 
214 /** Admin queue Get VSI Parameters command parameters */
216  /** VSI switching element ID */
218  /** Reserved */
220  /** Data buffer address */
222 } __attribute__ (( packed ));
223 
224 /** Admin queue Get VSI Parameters data buffer */
226  /** Reserved */
228  /** Queue numbers */
230  /** Reserved */
232  /** Queue set handles for each traffic class */
234  /** Reserved */
236 } __attribute__ (( packed ));
237 
238 /** Admin queue Set VSI Promiscuous Modes command */
239 #define INTELXL_ADMIN_PROMISC 0x0254
240 
241 /** Admin queue Set VSI Promiscuous Modes command parameters */
243  /** Flags */
245  /** Valid flags */
247  /** VSI switching element ID */
249  /** Reserved */
251 } __attribute__ (( packed ));
252 
253 /** Promiscuous unicast mode */
254 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
255 
256 /** Promiscuous multicast mode */
257 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
258 
259 /** Promiscuous broadcast mode */
260 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
261 
262 /** Promiscuous VLAN mode */
263 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
264 
265 /** Admin queue Restart Autonegotiation command */
266 #define INTELXL_ADMIN_AUTONEG 0x0605
267 
268 /** Admin queue Restart Autonegotiation command parameters */
270  /** Flags */
272  /** Reserved */
274 } __attribute__ (( packed ));
275 
276 /** Restart autonegotiation */
277 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
278 
279 /** Enable link */
280 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
281 
282 /** Admin queue Get Link Status command */
283 #define INTELXL_ADMIN_LINK 0x0607
284 
285 /** Admin queue Get Link Status command parameters */
287  /** Link status notification */
289  /** Reserved */
291  /** PHY type */
293  /** Link speed */
295  /** Link status */
297  /** Reserved */
299 } __attribute__ (( packed ));
300 
301 /** Notify driver of link status changes */
302 #define INTELXL_ADMIN_LINK_NOTIFY 0x03
303 
304 /** Link is up */
305 #define INTELXL_ADMIN_LINK_UP 0x01
306 
307 /** Admin queue Send Message to PF command */
308 #define INTELXL_ADMIN_SEND_TO_PF 0x0801
309 
310 /** Admin queue Send Message to VF command */
311 #define INTELXL_ADMIN_SEND_TO_VF 0x0802
312 
313 /** Admin Queue VF Reset opcode */
314 #define INTELXL_ADMIN_VF_RESET 0x00000002
315 
316 /** Admin Queue VF Get Resources opcode */
317 #define INTELXL_ADMIN_VF_GET_RESOURCES 0x00000003
318 
319 /** Admin Queue VF Get Resources data buffer */
321  /** Reserved */
323  /** VSI switching element ID */
325  /** Reserved */
327  /** MAC address */
329 } __attribute__ (( packed ));
330 
331 /** Admin Queue VF Status Change Event opcode */
332 #define INTELXL_ADMIN_VF_STATUS 0x00000011
333 
334 /** Link status change event type */
335 #define INTELXL_ADMIN_VF_STATUS_LINK 0x00000001
336 
337 /** Link status change event data */
339  /** Link speed */
341  /** Link status */
343  /** Reserved */
345 } __attribute__ (( packed ));
346 
347 /** Admin Queue VF Status Change Event data buffer */
349  /** Event type */
351  /** Event data */
352  union {
353  /** Link change event data */
355  } data;
356  /** Reserved */
358 } __attribute__ (( packed ));
359 
360 /** Admin Queue VF Configure Queues opcode */
361 #define INTELXL_ADMIN_VF_CONFIGURE 0x00000006
362 
363 /** Admin Queue VF Configure Queues data buffer */
365  /** VSI switching element ID */
367  /** Number of queue pairs */
369  /** Reserved */
371  /** Transmit queue */
372  struct {
373  /** VSI switching element ID */
374  uint16_t vsi;
375  /** Queue ID */
377  /** Queue count */
378  uint16_t count;
379  /** Reserved */
380  uint8_t reserved_a[2];
381  /** Base address */
383  /** Reserved */
385  } __attribute__ (( packed )) tx;
386  /** Receive queue */
387  struct {
388  /** VSI switching element ID */
389  uint16_t vsi;
390  /** Queue ID */
391  uint16_t id;
392  /** Queue count */
394  /** Reserved */
395  uint8_t reserved_a[4];
396  /** Data buffer length */
398  /** Maximum frame size */
400  /** Reserved */
401  uint8_t reserved_b[4];
402  /** Base address */
403  uint64_t base;
404  /** Reserved */
406  } __attribute__ (( packed )) rx;
407  /** Reserved
408  *
409  * This field exists only due to a bug in the PF driver's
410  * message validation logic, which causes it to miscalculate
411  * the expected message length.
412  */
413  uint8_t reserved_b[64];
414 } __attribute__ (( packed ));
415 
416 /** Admin Queue VF IRQ Map opcode */
417 #define INTELXL_ADMIN_VF_IRQ_MAP 0x00000007
418 
419 /** Admin Queue VF IRQ Map data buffer */
421  /** Number of interrupt vectors */
423  /** VSI switching element ID */
425  /** Interrupt vector ID */
427  /** Receive queue bitmap */
429  /** Transmit queue bitmap */
431  /** Receive interrupt throttling index */
433  /** Transmit interrupt throttling index */
435  /** Reserved
436  *
437  * This field exists only due to a bug in the PF driver's
438  * message validation logic, which causes it to miscalculate
439  * the expected message length.
440  */
442 } __attribute__ (( packed ));
443 
444 /** Admin Queue VF Enable Queues opcode */
445 #define INTELXL_ADMIN_VF_ENABLE 0x00000008
446 
447 /** Admin Queue VF Disable Queues opcode */
448 #define INTELXL_ADMIN_VF_DISABLE 0x00000009
449 
450 /** Admin Queue VF Enable/Disable Queues data buffer */
452  /** VSI switching element ID */
454  /** Reserved */
456  /** Receive queue bitmask */
458  /** Transmit queue bitmask */
460 } __attribute__ (( packed ));
461 
462 /** Admin Queue VF Configure Promiscuous Mode opcode */
463 #define INTELXL_ADMIN_VF_PROMISC 0x0000000e
464 
465 /** Admin Queue VF Configure Promiscuous Mode data buffer */
467  /** VSI switching element ID */
469  /** Flags */
471 } __attribute__ (( packed ));
472 
473 /** Admin queue command parameters */
475  /** Additional data buffer command parameters */
477  /** Get Version command parameters */
479  /** Driver Version command parameters */
481  /** Shutdown command parameters */
483  /** Clear PXE Mode command parameters */
485  /** Get Switch Configuration command parameters */
487  /** Get VSI Parameters command parameters */
489  /** Set VSI Promiscuous Modes command parameters */
491  /** Restart Autonegotiation command parameters */
493  /** Get Link Status command parameters */
495 } __attribute__ (( packed ));
496 
497 /** Admin queue data buffer */
499  /** Driver Version data buffer */
501  /** Get Switch Configuration data buffer */
503  /** Get VSI Parameters data buffer */
505  /** VF Get Resources data buffer */
507  /** VF Status Change Event data buffer */
509  /** VF Configure Queues data buffer */
511  /** VF Enable/Disable Queues data buffer */
513  /** VF Configure Promiscuous Mode data buffer */
515  /*** VF IRQ Map data buffer */
517  /** Alignment padding */
519 } __attribute__ (( packed ));
520 
521 /** Admin queue descriptor */
523  /** Flags */
525  /** Opcode */
527  /** Data length */
529  /** Return value */
531  /** Opaque cookie / VF opcode */
532  union {
533  /** Cookie */
535  /** VF opcode */
537  };
538  /** VF return value */
540  /** Parameters */
542 } __attribute__ (( packed ));
543 
544 /** Admin descriptor done */
545 #define INTELXL_ADMIN_FL_DD 0x0001
546 
547 /** Admin descriptor contains a completion */
548 #define INTELXL_ADMIN_FL_CMP 0x0002
549 
550 /** Admin descriptor completed in error */
551 #define INTELXL_ADMIN_FL_ERR 0x0004
552 
553 /** Admin descriptor uses data buffer for command parameters */
554 #define INTELXL_ADMIN_FL_RD 0x0400
555 
556 /** Admin descriptor uses data buffer */
557 #define INTELXL_ADMIN_FL_BUF 0x1000
558 
559 /** Admin queue */
561  /** Descriptors */
563  /** Data buffers */
565  /** Queue index */
566  unsigned int index;
567 
568  /** Register block base */
569  unsigned int base;
570  /** Register offsets */
572 };
573 
574 /**
575  * Initialise admin queue
576  *
577  * @v admin Admin queue
578  * @v base Register block base
579  * @v regs Register offsets
580  */
581 static inline __attribute__ (( always_inline )) void
582 intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
583  const struct intelxl_admin_offsets *regs ) {
584 
585  admin->base = base;
586  admin->regs = regs;
587 }
588 
589 /** Number of admin queue descriptors */
590 #define INTELXL_ADMIN_NUM_DESC 4
591 
592 /** Maximum time to wait for an admin request to complete */
593 #define INTELXL_ADMIN_MAX_WAIT_MS 100
594 
595 /** Admin queue API major version */
596 #define INTELXL_ADMIN_API_MAJOR 1
597 
598 /******************************************************************************
599  *
600  * Transmit and receive queue context
601  *
602  ******************************************************************************
603  */
604 
605 /** CMLAN Context Data Register */
606 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
607 
608 /** CMLAN Context Control Register */
609 #define INTELXL_PFCM_LANCTXCTL 0x10c300
610 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
611  ( (x) << 0 ) /**< Queue number */
612 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
613  ( (x) << 12 ) /**< Sub-line */
614 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
615  ( (x) << 15 ) /**< Queue type */
616 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
617  INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
618 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
619  INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
620 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
621  ( (x) << 17 ) /**< Op code */
622 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
623  INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
624 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
625  INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
627 /** CMLAN Context Status Register */
628 #define INTELXL_PFCM_LANCTXSTAT 0x10c380
629 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
630 
631 /** Queue context line */
633  /** Raw data */
634  uint32_t raw[4];
635 } __attribute__ (( packed ));
637 /** Transmit queue context */
639  /** Head pointer */
640  uint16_t head;
641  /** Flags */
643  /** Base address */
645  /** Reserved */
647  /** Queue count */
649  /** Reserved */
651  /** Queue set */
653  /** Reserved */
655 } __attribute__ (( packed ));
657 /** New transmit queue context */
658 #define INTELXL_CTX_TX_FL_NEW 0x4000
659 
660 /** Transmit queue base address */
661 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
663 /** Transmit queue count */
664 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
666 /** Transmit queue set */
667 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
669 /** Receive queue context */
670 struct intelxl_context_rx {
671  /** Head pointer */
672  uint16_t head;
673  /** Reserved */
675  /** Base address and queue count */
677  /** Data buffer length */
679  /** Flags */
681  /** Reserved */
683  /** Maximum frame size */
685 } __attribute__ (( packed ));
687 /** Receive queue base address and queue count */
688 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
689  ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
690 
691 /** Receive queue data buffer length */
692 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
693 
694 /** Use 32-byte receive descriptors */
695 #define INTELXL_CTX_RX_FL_DSIZE 0x10
697 /** Strip CRC from received packets */
698 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
700 /** Receive queue maximum frame size */
701 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
703 /** Maximum time to wait for a context operation to complete */
704 #define INTELXL_CTX_MAX_WAIT_MS 100
706 /** Time to wait for a queue to become enabled */
707 #define INTELXL_QUEUE_ENABLE_DELAY_US 20
709 /** Time to wait for a transmit queue to become pre-disabled */
710 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
712 /** Maximum time to wait for a queue to become disabled */
713 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
715 /******************************************************************************
716  *
717  * Transmit and receive descriptors
718  *
719  ******************************************************************************
720  */
721 
722 /** Global Transmit Queue Head register */
723 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
724 
725 /** Global Transmit Pre Queue Disable register */
726 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
727 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
728  ( (x) << 0 ) /**< Queue index */
729 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
730  0x40000000UL /**< Set disable */
731 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
732  0x80000000UL /**< Clear disable */
733 
734 /** Global Transmit Queue register block */
735 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
737 /** Global Receive Queue register block */
738 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
739 
740 /** Queue Enable Register (offset) */
741 #define INTELXL_QXX_ENA 0x0000
742 #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
743 #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
744 
745 /** Queue Control Register (offset) */
746 #define INTELXL_QXX_CTL 0x4000
747 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
748 #define INTELXL_QXX_CTL_PFVF_Q_PF \
749  INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
750 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
752 /** Queue Tail Pointer Register (offset) */
753 #define INTELXL_QXX_TAIL 0x8000
754 
755 /** Global RLAN Control 0 register */
756 #define INTELXL_GLLAN_RCTL_0 0x12a500
757 #define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
759 /** Transmit data descriptor */
761  /** Buffer address */
763  /** Flags */
764  uint32_t flags;
765  /** Length */
766  uint32_t len;
767 } __attribute__ (( packed ));
768 
769 /** Transmit data descriptor type */
770 #define INTELXL_TX_DATA_DTYP 0x0
772 /** Transmit data descriptor end of packet */
773 #define INTELXL_TX_DATA_EOP 0x10
774 
775 /** Transmit data descriptor report status */
776 #define INTELXL_TX_DATA_RS 0x20
777 
778 /** Transmit data descriptor pretty please
779  *
780  * This bit is completely missing from older versions of the XL710
781  * datasheet. Later versions describe it innocuously as "reserved,
782  * must be 1". Without this bit, everything will appear to work (up
783  * to and including the port "transmit good octets" counter), but no
784  * packet will actually be sent.
785  */
786 #define INTELXL_TX_DATA_JFDI 0x40
787 
788 /** Transmit data descriptor length */
789 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
790 
791 /** Transmit writeback descriptor */
793  /** Reserved */
795  /** Flags */
796  uint8_t flags;
797  /** Reserved */
798  uint8_t reserved_b[7];
799 } __attribute__ (( packed ));
800 
801 /** Transmit writeback descriptor complete */
802 #define INTELXL_TX_WB_FL_DD 0x01
804 /** Transmit descriptor */
805 union intelxl_tx_descriptor {
806  /** Transmit data descriptor */
808  /** Transmit writeback descriptor */
810 };
811 
812 /** Receive data descriptor */
814  /** Buffer address */
816  /** Flags */
817  uint32_t flags;
818  /** Reserved */
819  uint8_t reserved[20];
820 } __attribute__ (( packed ));
821 
822 /** Receive writeback descriptor */
824  /** Reserved */
825  uint8_t reserved_a[2];
826  /** VLAN tag */
827  uint16_t vlan;
828  /** Reserved */
829  uint8_t reserved_b[4];
830  /** Flags */
831  uint32_t flags;
832  /** Length */
833  uint32_t len;
834  /** Reserved */
835  uint8_t reserved_c[16];
836 } __attribute__ (( packed ));
837 
838 /** Receive writeback descriptor complete */
839 #define INTELXL_RX_WB_FL_DD 0x00000001UL
841 /** Receive writeback descriptor VLAN tag present */
842 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
843 
844 /** Receive writeback descriptor error */
845 #define INTELXL_RX_WB_FL_RXE 0x00080000UL
846 
847 /** Receive writeback descriptor length */
848 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
849 
850 /** Packet descriptor */
851 union intelxl_rx_descriptor {
852  /** Receive data descriptor */
854  /** Receive writeback descriptor */
856 };
857 
858 /** Descriptor ring */
859 struct intelxl_ring {
860  /** Descriptors */
861  union {
862  /** Transmit descriptors */
863  union intelxl_tx_descriptor *tx;
864  /** Receive descriptors */
865  union intelxl_rx_descriptor *rx;
866  /** Raw data */
867  void *raw;
868  } desc;
869  /** Producer index */
870  unsigned int prod;
871  /** Consumer index */
872  unsigned int cons;
873 
874  /** Register block */
875  unsigned int reg;
876  /** Tail register */
877  unsigned int tail;
878  /** Length (in bytes) */
879  size_t len;
880  /** Program queue context
881  *
882  * @v intelxl Intel device
883  * @v address Descriptor ring base address
884  */
885  int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
886 };
887 
888 /**
889  * Initialise descriptor ring
890  *
891  * @v ring Descriptor ring
892  * @v count Number of descriptors
893  * @v len Length of a single descriptor
894  * @v context Method to program queue context
895  */
896 static inline __attribute__ (( always_inline)) void
897 intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
898  int ( * context ) ( struct intelxl_nic *intelxl,
899  physaddr_t address ) ) {
900 
901  ring->len = ( count * len );
902  ring->context = context;
903 }
904 
905 /** Number of transmit descriptors
906  *
907  * Chosen to exceed the receive ring fill level, in order to avoid
908  * running out of transmit descriptors when sending TCP ACKs.
909  */
910 #define INTELXL_TX_NUM_DESC 64
911 
912 /** Transmit descriptor ring maximum fill level */
913 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
914 
915 /** Number of receive descriptors
916  *
917  * Must be a multiple of 32.
918  */
919 #define INTELXL_RX_NUM_DESC 32
920 
921 /** Receive descriptor ring fill level
922  *
923  * Must be a multiple of 8 and greater than 8.
924  */
925 #define INTELXL_RX_FILL 16
926 
927 /******************************************************************************
928  *
929  * Top level
930  *
931  ******************************************************************************
932  */
933 
934 /** PF Interrupt Zero Dynamic Control Register */
935 #define INTELXL_PFINT_DYN_CTL0 0x038480
936 #define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL /**< Enable */
937 #define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL /**< Acknowledge */
938 #define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL /**< Ignore enable */
939 
940 /** PF Interrupt Zero Linked List Register */
941 #define INTELXL_PFINT_LNKLST0 0x038500
942 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
943  ( (x) << 0 ) /**< Queue index */
944 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
945  INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
946 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
947  ( (x) << 11 ) /**< Queue type */
948 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
949  INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
950 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
951  INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
953 /** PF Interrupt Zero Cause Enablement Register */
954 #define INTELXL_PFINT_ICR0_ENA 0x038800
955 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
956 
957 /** Receive Queue Interrupt Cause Control Register */
958 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
959 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
960 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
961  INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
962 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
963 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
964  INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
965 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
966  INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
967 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
968 
969 /** Transmit Queue Interrupt Cause Control Register */
970 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
971 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
972 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
973  INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
974 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
975 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
976  INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
977 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
978  INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
979 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
980 
981 /** PF Control Register */
982 #define INTELXL_PFGEN_CTRL 0x092400
983 #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
985 /** Time to delay for device reset, in milliseconds */
986 #define INTELXL_RESET_DELAY_MS 100
987 
988 /** PF Queue Allocation Register */
989 #define INTELXL_PFLAN_QALLOC 0x1c0400
990 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
991  ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
992 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
993  ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
994 
995 /** PF LAN Port Number Register */
996 #define INTELXL_PFGEN_PORTNUM 0x1c0480
997 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
998  ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
999 
1000 /** Port MAC Address Low Register */
1001 #define INTELXL_PRTGL_SAL 0x1e2120
1002 
1003 /** Port MAC Address High Register */
1004 #define INTELXL_PRTGL_SAH 0x1e2140
1005 #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
1006 #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
1007 
1008 /** Receive address */
1010  struct {
1012  uint32_t high;
1013  } __attribute__ (( packed )) reg;
1015 };
1017 /** An Intel 40Gigabit network card */
1018 struct intelxl_nic {
1019  /** Registers */
1020  void *regs;
1021  /** Maximum frame size */
1022  size_t mfs;
1023 
1024  /** Physical function number */
1025  unsigned int pf;
1026  /** Absolute queue number base */
1027  unsigned int base;
1028  /** Port number */
1029  unsigned int port;
1030  /** Queue number */
1031  unsigned int queue;
1032  /** Virtual Station Interface switching element ID */
1033  unsigned int vsi;
1034  /** Queue set handle */
1035  unsigned int qset;
1036  /** Interrupt control register */
1037  unsigned int intr;
1038  /** MSI-X capability */
1039  struct pci_msix msix;
1040  /** MSI-X dummy interrupt target */
1042  /** PCI Express capability offset */
1043  unsigned int exp;
1044 
1045  /** Admin command queue */
1046  struct intelxl_admin command;
1047  /** Admin event queue */
1048  struct intelxl_admin event;
1050  /** Current VF opcode */
1051  unsigned int vopcode;
1052  /** Current VF return value */
1053  int vret;
1054  /** Current VF event data buffer */
1055  union intelxl_admin_buffer vbuf;
1057  /** Transmit descriptor ring */
1059  /** Receive descriptor ring */
1060  struct intelxl_ring rx;
1061  /** Receive I/O buffers */
1063 };
1064 
1065 extern int intelxl_msix_enable ( struct intelxl_nic *intelxl,
1066  struct pci_device *pci );
1067 extern void intelxl_msix_disable ( struct intelxl_nic *intelxl,
1068  struct pci_device *pci );
1069 extern struct intelxl_admin_descriptor *
1071 extern union intelxl_admin_buffer *
1073 extern int intelxl_admin_command ( struct intelxl_nic *intelxl );
1074 extern void intelxl_poll_admin ( struct net_device *netdev );
1075 extern int intelxl_open_admin ( struct intelxl_nic *intelxl );
1076 extern void intelxl_reopen_admin ( struct intelxl_nic *intelxl );
1077 extern void intelxl_close_admin ( struct intelxl_nic *intelxl );
1078 extern int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
1079  struct intelxl_ring *ring );
1080 extern void intelxl_free_ring ( struct intelxl_nic *intelxl,
1081  struct intelxl_ring *ring );
1082 extern void intelxl_empty_rx ( struct intelxl_nic *intelxl );
1083 extern int intelxl_transmit ( struct net_device *netdev,
1084  struct io_buffer *iobuf );
1085 extern void intelxl_poll ( struct net_device *netdev );
1086 
1087 extern void intelxlvf_admin_event ( struct net_device *netdev,
1088  struct intelxl_admin_descriptor *evt,
1089  union intelxl_admin_buffer *buf );
1090 
1091 #endif /* _INTELXL_H */
struct intelxl_admin_vf_configure_buffer cfg
VF Configure Queues data buffer.
Definition: intelxl.h:510
uint8_t reserved_a[2]
Reserved.
Definition: intelxl.h:830
Receive queue context.
Definition: intelxl.h:674
uint16_t len
Data buffer length.
Definition: intelxl.h:682
void * regs
Registers.
Definition: intelxl.h:1030
#define __attribute__(x)
Definition: compiler.h:10
uint16_t info
Element specific information.
Definition: intelxl.h:183
uint16_t head
Head pointer.
Definition: intelxl.h:676
uint32_t tx
Transmit queue bitmask.
Definition: intelxl.h:459
size_t len
Length (in bytes)
Definition: intelxl.h:884
uint32_t flags
Flags.
Definition: intelxl.h:822
unsigned short uint16_t
Definition: stdint.h:11
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:833
Admin queue data buffer command parameters.
Definition: intelxl.h:76
uint8_t reserved_c[8]
Reserved.
Definition: intelxl.h:405
uint64_t address
Data buffer address.
Definition: intelxl.h:124
uint32_t raw[4]
Raw data.
Definition: intelxl.h:638
void intelxl_free_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Admin queue Get Switch Configuration data buffer.
Definition: intelxl.h:200
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:346
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:890
uint16_t head
Head pointer.
Definition: intelxl.h:644
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:159
uint16_t rxitr
Receive interrupt throttling index.
Definition: intelxl.h:432
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:688
int vret
Current VF return value.
Definition: intelxl.h:1063
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:229
A command-line command.
Definition: command.h:9
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:564
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:233
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:504
Admin queue register offsets.
Definition: intelxl.h:62
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:269
uint16_t vlan
VLAN tag.
Definition: intelxl.h:832
uint64_t address
Base address.
Definition: ena.h:24
uint8_t type
Switching element type.
Definition: intelxl.h:167
uint16_t opcode
Opcode.
Definition: intelxl.h:526
Queue context line.
Definition: intelxl.h:636
Admin queue.
Definition: intelxl.h:560
Admin queue Driver Version data buffer.
Definition: intelxl.h:128
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:215
unsigned int qset
Queue set handle.
Definition: intelxl.h:1045
uint8_t reserved_b[8]
Reserved.
Definition: intelxl.h:384
uint16_t count
Number of switching elements reported.
Definition: intelxl.h:202
unsigned int prod
Producer index.
Definition: intelxl.h:875
Admin Queue VF Get Resources data buffer.
Definition: intelxl.h:320
Admin queue Shutdown command parameters.
Definition: intelxl.h:137
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:324
char name[32]
Driver name.
Definition: intelxl.h:130
struct intelxl_admin_vf_irq_map_buffer irq
Definition: intelxl.h:516
uint8_t reserved_b[8]
Reserved.
Definition: intelxl.h:326
uint16_t flags
Flags.
Definition: intelxl.h:524
void intelxlvf_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle virtual function event.
Definition: intelxlvf.c:287
unsigned long long uint64_t
Definition: stdint.h:13
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:500
struct intelxl_admin_vf_get_resources_buffer res
VF Get Resources data buffer.
Definition: intelxl.h:506
PCI MSI-X interrupts.
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:290
uint32_t rx
Receive queue bitmask.
Definition: intelxl.h:457
unsigned int len
Length Register offset.
Definition: intelxl.h:68
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:860
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:25
uint8_t pad[INTELXL_ALIGN]
Alignment padding.
Definition: intelxl.h:518
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:453
unsigned int bal
Base Address Low Register offset.
Definition: intelxl.h:64
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:307
uint16_t ret
Return value.
Definition: intelxl.h:530
Admin Queue VF IRQ Map data buffer.
Definition: intelxl.h:420
size_t mfs
Maximum frame size.
Definition: intelxl.h:1032
uint32_t event
Event type.
Definition: intelxl.h:350
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:502
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned int base
Register block base.
Definition: intelxl.h:569
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:868
struct intelxl_admin_version api
API version.
Definition: intelxl.h:105
uint8_t reserved_a[12]
Reserved.
Definition: intelxl.h:206
uint8_t reserved[10]
Reserved.
Definition: intelxl.h:250
struct intelxl_admin_vf_status_buffer stat
VF Status Change Event data buffer.
Definition: intelxl.h:508
unsigned int queue
Queue number.
Definition: intelxl.h:1041
uint8_t raw[ETH_ALEN]
Definition: intelxl.h:1024
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:151
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:1053
uint16_t flags
Flags.
Definition: intelxl.h:646
uint32_t mfs
Maximum frame size.
Definition: intelxl.h:399
uint8_t revision
Revision.
Definition: intelxl.h:169
uint8_t reserved[4]
Reserved.
Definition: intelxl.h:122
uint32_t cookie
Cookie.
Definition: intelxl.h:534
uint64_t address
Data buffer address.
Definition: intelxl.h:196
Admin queue command parameters.
Definition: intelxl.h:474
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:1051
unsigned int cons
Consumer index.
Definition: intelxl.h:877
uint64_t address
Buffer address.
Definition: intelxl.h:820
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:923
uint16_t len
Data length.
Definition: intelxl.h:528
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:1070
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:582
uint16_t vec
Interrupt vector ID.
Definition: intelxl.h:426
uint8_t reserved_a[2]
Reserved.
Definition: intelxl.h:678
unsigned int index
Queue index.
Definition: intelxl.h:566
uint8_t reserved_b[3]
Reserved.
Definition: intelxl.h:177
Transmit writeback descriptor.
Definition: intelxl.h:797
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:1072
struct intelxl_admin_vf_configure_buffer::@60 tx
Transmit queue.
uint8_t magic
Magic value.
Definition: intelxl.h:153
uint32_t flags
Flags.
Definition: intelxl.h:769
uint8_t sub
Sub-build version.
Definition: intelxl.h:120
Admin queue version number.
Definition: intelxl.h:89
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:1043
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:812
Admin Queue VF Configure Queues data buffer.
Definition: intelxl.h:364
uint16_t count
Queue count.
Definition: intelxl.h:652
PCI MSI-X capability.
Definition: pcimsix.h:34
uint8_t reserved_a[20]
Reserved.
Definition: intelxl.h:322
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:780
void * raw
Raw data.
Definition: intelxl.h:872
uint16_t flags
Flags.
Definition: intelxl.h:244
uint16_t txmap
Transmit queue bitmap.
Definition: intelxl.h:430
uint8_t reserved[12]
Reserved.
Definition: intelxl.h:441
static struct net_device * netdev
Definition: gdbudp.c:52
uint16_t minor
Minor version number.
Definition: intelxl.h:93
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:924
struct intelxl_admin_promisc_params promisc
Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:490
uint8_t flags
Flags.
Definition: intelxl.h:684
uint8_t reserved_a[8]
Reserved.
Definition: intelxl.h:650
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:175
uint8_t reserved[15]
Reserved.
Definition: intelxl.h:155
uint8_t reserved_b[4]
Reserved.
Definition: intelxl.h:834
unsigned int reg
Register block.
Definition: intelxl.h:880
uint64_t base
Base address.
Definition: intelxl.h:382
uint8_t reserved_a[8]
Reserved.
Definition: intelxl.h:799
Receive data descriptor.
Definition: intelxl.h:818
struct intelxl_admin_version_params version
Get Version command parameters.
Definition: intelxl.h:478
uint8_t reserved_a[4]
Reserved.
Definition: intelxl.h:370
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:424
uint16_t total
Total number of switching elements.
Definition: intelxl.h:204
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1337
Admin queue Driver Version command parameters.
Definition: intelxl.h:112
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:870
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1587
union intelxl_admin_vf_status_buffer::@59 data
Event data.
uint8_t minor
Minor version.
Definition: intelxl.h:116
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:133
union intelxl_admin_buffer vbuf
Current VF event data buffer.
Definition: intelxl.h:1065
A PCI device.
Definition: pci.h:187
union intelxl_ring::@64 desc
Descriptors.
unsigned int intr
Interrupt control register.
Definition: intelxl.h:1047
uint32_t build
Firmware build ID.
Definition: intelxl.h:101
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:562
A network device.
Definition: netdevice.h:348
struct intelxl_admin_vf_configure_buffer::@61 rx
Receive queue.
uint8_t reserved_b[7]
Reserved.
Definition: intelxl.h:803
uint64_t base_count
Base address and queue count.
Definition: intelxl.h:680
uint64_t base
Base address.
Definition: intelxl.h:648
unsigned char uint8_t
Definition: stdint.h:10
int32_t vret
VF return value.
Definition: intelxl.h:539
unsigned int port
Port number.
Definition: intelxl.h:1039
uint16_t count
Number of interrupt vectors.
Definition: intelxl.h:422
unsigned int head
Head Register offset.
Definition: intelxl.h:70
uint8_t reserved[20]
Reserved.
Definition: intelxl.h:824
Admin queue Get Version command parameters.
Definition: intelxl.h:97
Transmit data descriptor.
Definition: intelxl.h:765
uint8_t reserved_c[2]
Reserved.
Definition: intelxl.h:181
An Intel 40Gigabit network card.
Definition: intelxl.h:1028
#define ETH_ALEN
Definition: if_ether.h:8
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:217
uint8_t reserved_b[100]
Reserved.
Definition: intelxl.h:654
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:541
uint8_t connection
Connection type.
Definition: intelxl.h:179
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:468
unsigned int uint32_t
Definition: stdint.h:12
Receive address.
Definition: intelxl.h:1019
uint32_t len
Length.
Definition: intelxl.h:771
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:902
uint16_t count
Number of queue pairs.
Definition: intelxl.h:368
uint8_t reserved_c[4]
Reserved.
Definition: intelxl.h:658
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:366
Admin Queue VF Configure Promiscuous Mode data buffer.
Definition: intelxl.h:466
uint32_t high
Buffer address high.
Definition: intelxl.h:80
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:1068
struct i386_regs regs
Definition: registers.h:15
uint64_t address
Buffer address.
Definition: intelxl.h:767
uint16_t base
Base address.
Definition: edd.h:14
uint16_t major
Major version number.
Definition: intelxl.h:91
struct intelxl_admin_switch_params sw
Get Switch Configuration command parameters.
Definition: intelxl.h:486
struct intelxl_receive_address::@65 reg
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:248
struct intelxl_admin_link_params link
Get Link Status command parameters.
Definition: intelxl.h:494
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:242
struct intelxl_admin_shutdown_params shutdown
Shutdown command parameters.
Definition: intelxl.h:482
uint8_t unloading
Driver unloading.
Definition: intelxl.h:139
unsigned long physaddr_t
Definition: stdint.h:20
uint16_t next
Starting switching element identifier.
Definition: intelxl.h:192
uint32_t len
Data buffer length.
Definition: intelxl.h:397
unsigned int pf
Physical function number.
Definition: intelxl.h:1035
struct intelxl_admin_vsi_params vsi
Get VSI Parameters command parameters.
Definition: intelxl.h:488
Admin queue descriptor.
Definition: intelxl.h:522
uint32_t low
Buffer address low.
Definition: intelxl.h:82
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:173
struct intelxl_admin_clear_pxe_params pxe
Clear PXE Mode command parameters.
Definition: intelxl.h:484
uint16_t rxmap
Receive queue bitmap.
Definition: intelxl.h:428
signed int int32_t
Definition: stdint.h:17
unsigned int bah
Base Address High Register offset.
Definition: intelxl.h:66
uint32_t len
Length.
Definition: ena.h:14
uint32_t rom
ROM version.
Definition: intelxl.h:99
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:895
struct pci_msix msix
MSI-X capability.
Definition: intelxl.h:1049
uint8_t reserved[4]
Reserved.
Definition: intelxl.h:357
struct intelxl_admin_vf_queues_buffer queues
VF Enable/Disable Queues data buffer.
Definition: intelxl.h:512
uint8_t reserved_a[30]
Reserved.
Definition: intelxl.h:227
uint8_t reserved[15]
Reserved.
Definition: intelxl.h:141
Admin Queue VF Status Change Event data buffer.
Definition: intelxl.h:348
uint16_t count
Number of entries.
Definition: ena.h:22
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:873
uint8_t reserved_c[16]
Reserved.
Definition: intelxl.h:235
Switching element configuration.
Definition: intelxl.h:165
uint8_t reserved_c[16]
Reserved.
Definition: intelxl.h:840
uint8_t reserved_b[34]
Reserved.
Definition: intelxl.h:231
uint8_t reserved[2]
Reserved.
Definition: intelxl.h:455
unsigned int base
Absolute queue number base.
Definition: intelxl.h:1037
Descriptor ring.
Definition: intelxl.h:864
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:208
uint8_t major
Driver version.
Definition: intelxl.h:114
Admin queue Get VSI Parameters data buffer.
Definition: intelxl.h:225
unsigned int tail
Tail register.
Definition: intelxl.h:882
Receive writeback descriptor.
Definition: intelxl.h:828
unsigned int tail
Tail Register offset.
Definition: intelxl.h:72
uint8_t build
Build version.
Definition: intelxl.h:118
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:476
uint8_t reserved[6]
Reserved.
Definition: intelxl.h:194
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:571
struct intelxl_admin_version firmware
Firmware version.
Definition: intelxl.h:103
struct intelxl_admin_driver_params driver
Driver Version command parameters.
Definition: intelxl.h:480
Admin Queue VF Enable/Disable Queues data buffer.
Definition: intelxl.h:451
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:190
uint16_t valid
Valid flags.
Definition: intelxl.h:246
uint8_t reserved[8]
Reserved.
Definition: intelxl.h:78
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:814
Transmit descriptor.
Definition: intelxl.h:810
uint16_t qset
Queue set.
Definition: intelxl.h:656
uint16_t txitr
Transmit interrupt throttling index.
Definition: intelxl.h:434
Transmit queue context.
Definition: intelxl.h:642
uint16_t seid
Switching element ID.
Definition: intelxl.h:171
struct intelxl_admin_autoneg_params autoneg
Restart Autonegotiation command parameters.
Definition: intelxl.h:492
uint8_t reserved[6]
Reserved.
Definition: intelxl.h:219
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1058
uint8_t mac[ETH_ALEN]
MAC address.
Definition: intelxl.h:328
Packet descriptor.
Definition: intelxl.h:856
Admin queue data buffer.
Definition: intelxl.h:498
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1465
uint64_t address
Data buffer address.
Definition: intelxl.h:221
unsigned int vopcode
Current VF opcode.
Definition: intelxl.h:1061
uint32_t vopcode
VF opcode.
Definition: intelxl.h:536
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:858
uint8_t reserved_b[7]
Reserved.
Definition: intelxl.h:686
uint32_t count
Queue count.
Definition: intelxl.h:393
struct intelxl_admin_vf_status_link link
Link change event data.
Definition: intelxl.h:354
A persistent I/O buffer.
Definition: iobuf.h:32
uint8_t reserved[15]
Reserved.
Definition: intelxl.h:273
struct intelxl_admin_vf_promisc_buffer promisc
VF Configure Promiscuous Mode data buffer.
Definition: intelxl.h:514