iPXE
Data Structures | Macros | Functions
intelxl.h File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/pcimsix.h>

Go to the source code of this file.

Data Structures

struct  intelxl_admin_offsets
 Admin queue register offsets. More...
 
struct  intelxl_admin_buffer_params
 Admin queue data buffer command parameters. More...
 
struct  intelxl_admin_version
 Admin queue version number. More...
 
struct  intelxl_admin_version_params
 Admin queue Get Version command parameters. More...
 
struct  intelxl_admin_driver_params
 Admin queue Driver Version command parameters. More...
 
struct  intelxl_admin_driver_buffer
 Admin queue Driver Version data buffer. More...
 
struct  intelxl_admin_shutdown_params
 Admin queue Shutdown command parameters. More...
 
struct  intelxl_admin_clear_pxe_params
 Admin queue Clear PXE Mode command parameters. More...
 
struct  intelxl_admin_switch_config
 Switching element configuration. More...
 
struct  intelxl_admin_switch_params
 Admin queue Get Switch Configuration command parameters. More...
 
struct  intelxl_admin_switch_buffer
 Admin queue Get Switch Configuration data buffer. More...
 
struct  intelxl_admin_vsi_params
 Admin queue Get VSI Parameters command parameters. More...
 
struct  intelxl_admin_vsi_buffer
 Admin queue Get VSI Parameters data buffer. More...
 
struct  intelxl_admin_promisc_params
 Admin queue Set VSI Promiscuous Modes command parameters. More...
 
struct  intelxl_admin_autoneg_params
 Admin queue Restart Autonegotiation command parameters. More...
 
struct  intelxl_admin_link_params
 Admin queue Get Link Status command parameters. More...
 
struct  intelxl_admin_vf_get_resources_buffer
 Admin Queue VF Get Resources data buffer. More...
 
struct  intelxl_admin_vf_status_link
 Link status change event data. More...
 
struct  intelxl_admin_vf_status_buffer
 Admin Queue VF Status Change Event data buffer. More...
 
struct  intelxl_admin_vf_configure_buffer
 Admin Queue VF Configure Queues data buffer. More...
 
struct  intelxl_admin_vf_irq_map_buffer
 Admin Queue VF IRQ Map data buffer. More...
 
struct  intelxl_admin_vf_queues_buffer
 Admin Queue VF Enable/Disable Queues data buffer. More...
 
struct  intelxl_admin_vf_promisc_buffer
 Admin Queue VF Configure Promiscuous Mode data buffer. More...
 
union  intelxl_admin_params
 Admin queue command parameters. More...
 
union  intelxl_admin_buffer
 Admin queue data buffer. More...
 
struct  intelxl_admin_descriptor
 Admin queue descriptor. More...
 
struct  intelxl_admin
 Admin queue. More...
 
struct  intelxl_context_line
 Queue context line. More...
 
struct  intelxl_context_tx
 Transmit queue context. More...
 
struct  intelxl_context_rx
 Receive queue context. More...
 
struct  intelxl_tx_data_descriptor
 Transmit data descriptor. More...
 
struct  intelxl_tx_writeback_descriptor
 Transmit writeback descriptor. More...
 
union  intelxl_tx_descriptor
 Transmit descriptor. More...
 
struct  intelxl_rx_data_descriptor
 Receive data descriptor. More...
 
struct  intelxl_rx_writeback_descriptor
 Receive writeback descriptor. More...
 
union  intelxl_rx_descriptor
 Packet descriptor. More...
 
struct  intelxl_ring
 Descriptor ring. More...
 
union  intelxl_receive_address
 Receive address. More...
 
struct  intelxl_nic
 An Intel 40Gigabit network card. More...
 

Macros

#define INTELXL_BAR_SIZE   0x200000
 BAR size. More...
 
#define INTELXL_ALIGN   256
 Alignment. More...
 
#define INTELXL_ADMIN_CMD   0x080000
 PF Admin Command Queue register block. More...
 
#define INTELXL_ADMIN_EVT   0x080080
 PF Admin Event Queue register block. More...
 
#define INTELXL_ADMIN_BAL   0x000
 Admin Queue Base Address Low Register (offset) More...
 
#define INTELXL_ADMIN_BAH   0x100
 Admin Queue Base Address High Register (offset) More...
 
#define INTELXL_ADMIN_LEN   0x200
 Admin Queue Length Register (offset) More...
 
#define INTELXL_ADMIN_LEN_LEN(x)   ( (x) << 0 )
 Queue length. More...
 
#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL
 Queue enable. More...
 
#define INTELXL_ADMIN_HEAD   0x300
 Admin Queue Head Register (offset) More...
 
#define INTELXL_ADMIN_TAIL   0x400
 Admin Queue Tail Register (offset) More...
 
#define INTELXL_ADMIN_VERSION   0x0001
 Admin queue Get Version command. More...
 
#define INTELXL_ADMIN_DRIVER   0x0002
 Admin queue Driver Version command. More...
 
#define INTELXL_ADMIN_SHUTDOWN   0x0003
 Admin queue Shutdown command. More...
 
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING   0x01
 Driver is unloading. More...
 
#define INTELXL_ADMIN_CLEAR_PXE   0x0110
 Admin queue Clear PXE Mode command. More...
 
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02
 Clear PXE Mode magic value. More...
 
#define INTELXL_ADMIN_SWITCH   0x0200
 Admin queue Get Switch Configuration command. More...
 
#define INTELXL_ADMIN_SWITCH_TYPE_VSI   19
 Virtual Station Inferface element type. More...
 
#define INTELXL_ADMIN_VSI   0x0212
 Admin queue Get VSI Parameters command. More...
 
#define INTELXL_ADMIN_PROMISC   0x0254
 Admin queue Set VSI Promiscuous Modes command. More...
 
#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001
 Promiscuous unicast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST   0x0002
 Promiscuous multicast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST   0x0004
 Promiscuous broadcast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010
 Promiscuous VLAN mode. More...
 
#define INTELXL_ADMIN_AUTONEG   0x0605
 Admin queue Restart Autonegotiation command. More...
 
#define INTELXL_ADMIN_AUTONEG_FL_RESTART   0x02
 Restart autonegotiation. More...
 
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE   0x04
 Enable link. More...
 
#define INTELXL_ADMIN_LINK   0x0607
 Admin queue Get Link Status command. More...
 
#define INTELXL_ADMIN_LINK_NOTIFY   0x03
 Notify driver of link status changes. More...
 
#define INTELXL_ADMIN_LINK_UP   0x01
 Link is up. More...
 
#define INTELXL_ADMIN_SEND_TO_PF   0x0801
 Admin queue Send Message to PF command. More...
 
#define INTELXL_ADMIN_SEND_TO_VF   0x0802
 Admin queue Send Message to VF command. More...
 
#define INTELXL_ADMIN_VF_RESET   0x00000002
 Admin Queue VF Reset opcode. More...
 
#define INTELXL_ADMIN_VF_GET_RESOURCES   0x00000003
 Admin Queue VF Get Resources opcode. More...
 
#define INTELXL_ADMIN_VF_STATUS   0x00000011
 Admin Queue VF Status Change Event opcode. More...
 
#define INTELXL_ADMIN_VF_STATUS_LINK   0x00000001
 Link status change event type. More...
 
#define INTELXL_ADMIN_VF_CONFIGURE   0x00000006
 Admin Queue VF Configure Queues opcode. More...
 
#define INTELXL_ADMIN_VF_IRQ_MAP   0x00000007
 Admin Queue VF IRQ Map opcode. More...
 
#define INTELXL_ADMIN_VF_ENABLE   0x00000008
 Admin Queue VF Enable Queues opcode. More...
 
#define INTELXL_ADMIN_VF_DISABLE   0x00000009
 Admin Queue VF Disable Queues opcode. More...
 
#define INTELXL_ADMIN_VF_PROMISC   0x0000000e
 Admin Queue VF Configure Promiscuous Mode opcode. More...
 
#define INTELXL_ADMIN_FL_DD   0x0001
 Admin descriptor done. More...
 
#define INTELXL_ADMIN_FL_CMP   0x0002
 Admin descriptor contains a completion. More...
 
#define INTELXL_ADMIN_FL_ERR   0x0004
 Admin descriptor completed in error. More...
 
#define INTELXL_ADMIN_FL_RD   0x0400
 Admin descriptor uses data buffer for command parameters. More...
 
#define INTELXL_ADMIN_FL_BUF   0x1000
 Admin descriptor uses data buffer. More...
 
#define INTELXL_ADMIN_NUM_DESC   4
 Number of admin queue descriptors. More...
 
#define INTELXL_ADMIN_MAX_WAIT_MS   100
 Maximum time to wait for an admin request to complete. More...
 
#define INTELXL_ADMIN_API_MAJOR   1
 Admin queue API major version. More...
 
#define INTELXL_PFCM_LANCTXDATA(x)   ( 0x10c100 + ( 0x80 * (x) ) )
 CMLAN Context Data Register. More...
 
#define INTELXL_PFCM_LANCTXCTL   0x10c300
 CMLAN Context Control Register. More...
 
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)   ( (x) << 0 )
 Queue number. More...
 
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)   ( (x) << 12 )
 Sub-line. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE(x)   ( (x) << 15 )
 Queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )
 RX queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )
 TX queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE(x)   ( (x) << 17 )
 Op code. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )
 Read context. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )
 Write context. More...
 
#define INTELXL_PFCM_LANCTXSTAT   0x10c380
 CMLAN Context Status Register. More...
 
#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL
 Complete. More...
 
#define INTELXL_CTX_TX_FL_NEW   0x4000
 New transmit queue context. More...
 
#define INTELXL_CTX_TX_BASE(base)   ( (base) >> 7 )
 Transmit queue base address. More...
 
#define INTELXL_CTX_TX_COUNT(count)   ( (count) << 1 )
 Transmit queue count. More...
 
#define INTELXL_CTX_TX_QSET(qset)   ( (qset) << 4 )
 Transmit queue set. More...
 
#define INTELXL_CTX_RX_BASE_COUNT(base, count)   ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
 Receive queue base address and queue count. More...
 
#define INTELXL_CTX_RX_LEN(len)   ( (len) >> 1 )
 Receive queue data buffer length. More...
 
#define INTELXL_CTX_RX_FL_DSIZE   0x10
 Use 32-byte receive descriptors. More...
 
#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20
 Strip CRC from received packets. More...
 
#define INTELXL_CTX_RX_MFS(mfs)   ( (mfs) >> 2 )
 Receive queue maximum frame size. More...
 
#define INTELXL_CTX_MAX_WAIT_MS   100
 Maximum time to wait for a context operation to complete. More...
 
#define INTELXL_QUEUE_ENABLE_DELAY_US   20
 Time to wait for a queue to become enabled. More...
 
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US   400
 Time to wait for a transmit queue to become pre-disabled. More...
 
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS   1000
 Maximum time to wait for a queue to become disabled. More...
 
#define INTELXL_QTX_HEAD(x)   ( 0x0e4000 + ( 0x4 * (x) ) )
 Global Transmit Queue Head register. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS(x)   ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
 Global Transmit Pre Queue Disable register. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)   ( (x) << 0 )
 Queue index. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL
 Set disable. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL
 Clear disable. More...
 
#define INTELXL_QTX(x)   ( 0x100000 + ( 0x4 * (x) ) )
 Global Transmit Queue register block. More...
 
#define INTELXL_QRX(x)   ( 0x120000 + ( 0x4 * (x) ) )
 Global Receive Queue register block. More...
 
#define INTELXL_QXX_ENA   0x0000
 Queue Enable Register (offset) More...
 
#define INTELXL_QXX_ENA_REQ   0x00000001UL
 Enable request. More...
 
#define INTELXL_QXX_ENA_STAT   0x00000004UL
 Enabled status. More...
 
#define INTELXL_QXX_CTL   0x4000
 Queue Control Register (offset) More...
 
#define INTELXL_QXX_CTL_PFVF_Q(x)   ( (x) << 0 )
 PF/VF queue. More...
 
#define INTELXL_QXX_CTL_PFVF_Q_PF   INTELXL_QXX_CTL_PFVF_Q ( 0x2 )
 PF queue. More...
 
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)   ( (x) << 2 )
 PF index. More...
 
#define INTELXL_QXX_TAIL   0x8000
 Queue Tail Pointer Register (offset) More...
 
#define INTELXL_GLLAN_RCTL_0   0x12a500
 Global RLAN Control 0 register. More...
 
#define INTELXL_GLLAN_RCTL_0_PXE_MODE   0x00000001UL
 PXE mode. More...
 
#define INTELXL_TX_DATA_DTYP   0x0
 Transmit data descriptor type. More...
 
#define INTELXL_TX_DATA_EOP   0x10
 Transmit data descriptor end of packet. More...
 
#define INTELXL_TX_DATA_RS   0x20
 Transmit data descriptor report status. More...
 
#define INTELXL_TX_DATA_JFDI   0x40
 Transmit data descriptor pretty please. More...
 
#define INTELXL_TX_DATA_LEN(len)   ( (len) << 2 )
 Transmit data descriptor length. More...
 
#define INTELXL_TX_WB_FL_DD   0x01
 Transmit writeback descriptor complete. More...
 
#define INTELXL_RX_WB_FL_DD   0x00000001UL
 Receive writeback descriptor complete. More...
 
#define INTELXL_RX_WB_FL_VLAN   0x00000004UL
 Receive writeback descriptor VLAN tag present. More...
 
#define INTELXL_RX_WB_FL_RXE   0x00080000UL
 Receive writeback descriptor error. More...
 
#define INTELXL_RX_WB_LEN(len)   ( ( (len) >> 6 ) & 0x3fff )
 Receive writeback descriptor length. More...
 
#define INTELXL_TX_NUM_DESC   64
 Number of transmit descriptors. More...
 
#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )
 Transmit descriptor ring maximum fill level. More...
 
#define INTELXL_RX_NUM_DESC   32
 Number of receive descriptors. More...
 
#define INTELXL_RX_FILL   16
 Receive descriptor ring fill level. More...
 
#define INTELXL_PFINT_DYN_CTL0   0x038480
 PF Interrupt Zero Dynamic Control Register. More...
 
#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL
 Enable. More...
 
#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL
 Acknowledge. More...
 
#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL
 Ignore enable. More...
 
#define INTELXL_PFINT_LNKLST0   0x038500
 PF Interrupt Zero Linked List Register. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)   ( (x) << 0 )
 Queue index. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE   INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x)   ( (x) << 11 )
 Queue type. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_PFINT_ICR0_ENA   0x038800
 PF Interrupt Zero Cause Enablement Register. More...
 
#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL
 Admin event. More...
 
#define INTELXL_QINT_RQCTL(x)   ( 0x03a000 + ( 0x4 * (x) ) )
 Receive Queue Interrupt Cause Control Register. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL
 Enable. More...
 
#define INTELXL_QINT_TQCTL(x)   ( 0x03c000 + ( 0x4 * (x) ) )
 Transmit Queue Interrupt Cause Control Register. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL
 Enable. More...
 
#define INTELXL_PFGEN_CTRL   0x092400
 PF Control Register. More...
 
#define INTELXL_PFGEN_CTRL_PFSWR   0x00000001UL
 Software Reset. More...
 
#define INTELXL_RESET_DELAY_MS   100
 Time to delay for device reset, in milliseconds. More...
 
#define INTELXL_PFLAN_QALLOC   0x1c0400
 PF Queue Allocation Register. More...
 
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)   ( ( (x) >> 0 ) & 0x7ff )
 First queue. More...
 
#define INTELXL_PFLAN_QALLOC_LASTQ(x)   ( ( (x) >> 16 ) & 0x7ff )
 Last queue. More...
 
#define INTELXL_PFGEN_PORTNUM   0x1c0480
 PF LAN Port Number Register. More...
 
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)   ( ( (x) >> 0 ) & 0x3 )
 Port number. More...
 
#define INTELXL_PRTGL_SAL   0x1e2120
 Port MAC Address Low Register. More...
 
#define INTELXL_PRTGL_SAH   0x1e2140
 Port MAC Address High Register. More...
 
#define INTELXL_PRTGL_SAH_MFS_GET(x)   ( (x) >> 16 )
 Max frame size. More...
 
#define INTELXL_PRTGL_SAH_MFS_SET(x)   ( (x) << 16 )
 Max frame size. More...
 

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
static void intelxl_init_admin (struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
 Initialise admin queue. More...
 
static void intelxl_init_ring (struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
 Initialise descriptor ring. More...
 
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci)
 Enable MSI-X dummy interrupt. More...
 
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci)
 Disable MSI-X dummy interrupt. More...
 
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor. More...
 
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer. More...
 
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command. More...
 
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue. More...
 
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues. More...
 
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset) More...
 
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues. More...
 
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring. More...
 
void intelxl_free_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers. More...
 
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets. More...
 
void intelxlvf_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
 Handle virtual function event. More...
 

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.h.

Macro Definition Documentation

◆ INTELXL_BAR_SIZE

#define INTELXL_BAR_SIZE   0x200000

BAR size.

Definition at line 19 of file intelxl.h.

◆ INTELXL_ALIGN

#define INTELXL_ALIGN   256

Alignment.

No data structure requires greater than 256 byte alignment.

Definition at line 25 of file intelxl.h.

◆ INTELXL_ADMIN_CMD

#define INTELXL_ADMIN_CMD   0x080000

PF Admin Command Queue register block.

Definition at line 35 of file intelxl.h.

◆ INTELXL_ADMIN_EVT

#define INTELXL_ADMIN_EVT   0x080080

PF Admin Event Queue register block.

Definition at line 38 of file intelxl.h.

◆ INTELXL_ADMIN_BAL

#define INTELXL_ADMIN_BAL   0x000

Admin Queue Base Address Low Register (offset)

Definition at line 41 of file intelxl.h.

◆ INTELXL_ADMIN_BAH

#define INTELXL_ADMIN_BAH   0x100

Admin Queue Base Address High Register (offset)

Definition at line 44 of file intelxl.h.

◆ INTELXL_ADMIN_LEN

#define INTELXL_ADMIN_LEN   0x200

Admin Queue Length Register (offset)

Definition at line 47 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_LEN

#define INTELXL_ADMIN_LEN_LEN (   x)    ( (x) << 0 )

Queue length.

Definition at line 48 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_ENABLE

#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL

Queue enable.

Definition at line 49 of file intelxl.h.

◆ INTELXL_ADMIN_HEAD

#define INTELXL_ADMIN_HEAD   0x300

Admin Queue Head Register (offset)

Definition at line 52 of file intelxl.h.

◆ INTELXL_ADMIN_TAIL

#define INTELXL_ADMIN_TAIL   0x400

Admin Queue Tail Register (offset)

Definition at line 55 of file intelxl.h.

◆ INTELXL_ADMIN_VERSION

#define INTELXL_ADMIN_VERSION   0x0001

Admin queue Get Version command.

Definition at line 86 of file intelxl.h.

◆ INTELXL_ADMIN_DRIVER

#define INTELXL_ADMIN_DRIVER   0x0002

Admin queue Driver Version command.

Definition at line 109 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN

#define INTELXL_ADMIN_SHUTDOWN   0x0003

Admin queue Shutdown command.

Definition at line 134 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN_UNLOADING

#define INTELXL_ADMIN_SHUTDOWN_UNLOADING   0x01

Driver is unloading.

Definition at line 145 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE

#define INTELXL_ADMIN_CLEAR_PXE   0x0110

Admin queue Clear PXE Mode command.

Definition at line 148 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE_MAGIC

#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02

Clear PXE Mode magic value.

Definition at line 159 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH

#define INTELXL_ADMIN_SWITCH   0x0200

Admin queue Get Switch Configuration command.

Definition at line 162 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH_TYPE_VSI

#define INTELXL_ADMIN_SWITCH_TYPE_VSI   19

Virtual Station Inferface element type.

Definition at line 187 of file intelxl.h.

◆ INTELXL_ADMIN_VSI

#define INTELXL_ADMIN_VSI   0x0212

Admin queue Get VSI Parameters command.

Definition at line 212 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC

#define INTELXL_ADMIN_PROMISC   0x0254

Admin queue Set VSI Promiscuous Modes command.

Definition at line 239 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_UNICAST

#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001

Promiscuous unicast mode.

Definition at line 254 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_MULTICAST

#define INTELXL_ADMIN_PROMISC_FL_MULTICAST   0x0002

Promiscuous multicast mode.

Definition at line 257 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_BROADCAST

#define INTELXL_ADMIN_PROMISC_FL_BROADCAST   0x0004

Promiscuous broadcast mode.

Definition at line 260 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_VLAN

#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010

Promiscuous VLAN mode.

Definition at line 263 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG

#define INTELXL_ADMIN_AUTONEG   0x0605

Admin queue Restart Autonegotiation command.

Definition at line 266 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_RESTART

#define INTELXL_ADMIN_AUTONEG_FL_RESTART   0x02

Restart autonegotiation.

Definition at line 277 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_ENABLE

#define INTELXL_ADMIN_AUTONEG_FL_ENABLE   0x04

Enable link.

Definition at line 280 of file intelxl.h.

◆ INTELXL_ADMIN_LINK

#define INTELXL_ADMIN_LINK   0x0607

Admin queue Get Link Status command.

Definition at line 283 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_NOTIFY

#define INTELXL_ADMIN_LINK_NOTIFY   0x03

Notify driver of link status changes.

Definition at line 302 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_UP

#define INTELXL_ADMIN_LINK_UP   0x01

Link is up.

Definition at line 305 of file intelxl.h.

◆ INTELXL_ADMIN_SEND_TO_PF

#define INTELXL_ADMIN_SEND_TO_PF   0x0801

Admin queue Send Message to PF command.

Definition at line 308 of file intelxl.h.

◆ INTELXL_ADMIN_SEND_TO_VF

#define INTELXL_ADMIN_SEND_TO_VF   0x0802

Admin queue Send Message to VF command.

Definition at line 311 of file intelxl.h.

◆ INTELXL_ADMIN_VF_RESET

#define INTELXL_ADMIN_VF_RESET   0x00000002

Admin Queue VF Reset opcode.

Definition at line 314 of file intelxl.h.

◆ INTELXL_ADMIN_VF_GET_RESOURCES

#define INTELXL_ADMIN_VF_GET_RESOURCES   0x00000003

Admin Queue VF Get Resources opcode.

Definition at line 317 of file intelxl.h.

◆ INTELXL_ADMIN_VF_STATUS

#define INTELXL_ADMIN_VF_STATUS   0x00000011

Admin Queue VF Status Change Event opcode.

Definition at line 332 of file intelxl.h.

◆ INTELXL_ADMIN_VF_STATUS_LINK

#define INTELXL_ADMIN_VF_STATUS_LINK   0x00000001

Link status change event type.

Definition at line 335 of file intelxl.h.

◆ INTELXL_ADMIN_VF_CONFIGURE

#define INTELXL_ADMIN_VF_CONFIGURE   0x00000006

Admin Queue VF Configure Queues opcode.

Definition at line 361 of file intelxl.h.

◆ INTELXL_ADMIN_VF_IRQ_MAP

#define INTELXL_ADMIN_VF_IRQ_MAP   0x00000007

Admin Queue VF IRQ Map opcode.

Definition at line 417 of file intelxl.h.

◆ INTELXL_ADMIN_VF_ENABLE

#define INTELXL_ADMIN_VF_ENABLE   0x00000008

Admin Queue VF Enable Queues opcode.

Definition at line 445 of file intelxl.h.

◆ INTELXL_ADMIN_VF_DISABLE

#define INTELXL_ADMIN_VF_DISABLE   0x00000009

Admin Queue VF Disable Queues opcode.

Definition at line 448 of file intelxl.h.

◆ INTELXL_ADMIN_VF_PROMISC

#define INTELXL_ADMIN_VF_PROMISC   0x0000000e

Admin Queue VF Configure Promiscuous Mode opcode.

Definition at line 463 of file intelxl.h.

◆ INTELXL_ADMIN_FL_DD

#define INTELXL_ADMIN_FL_DD   0x0001

Admin descriptor done.

Definition at line 545 of file intelxl.h.

◆ INTELXL_ADMIN_FL_CMP

#define INTELXL_ADMIN_FL_CMP   0x0002

Admin descriptor contains a completion.

Definition at line 548 of file intelxl.h.

◆ INTELXL_ADMIN_FL_ERR

#define INTELXL_ADMIN_FL_ERR   0x0004

Admin descriptor completed in error.

Definition at line 551 of file intelxl.h.

◆ INTELXL_ADMIN_FL_RD

#define INTELXL_ADMIN_FL_RD   0x0400

Admin descriptor uses data buffer for command parameters.

Definition at line 554 of file intelxl.h.

◆ INTELXL_ADMIN_FL_BUF

#define INTELXL_ADMIN_FL_BUF   0x1000

Admin descriptor uses data buffer.

Definition at line 557 of file intelxl.h.

◆ INTELXL_ADMIN_NUM_DESC

#define INTELXL_ADMIN_NUM_DESC   4

Number of admin queue descriptors.

Definition at line 590 of file intelxl.h.

◆ INTELXL_ADMIN_MAX_WAIT_MS

#define INTELXL_ADMIN_MAX_WAIT_MS   100

Maximum time to wait for an admin request to complete.

Definition at line 593 of file intelxl.h.

◆ INTELXL_ADMIN_API_MAJOR

#define INTELXL_ADMIN_API_MAJOR   1

Admin queue API major version.

Definition at line 596 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXDATA

#define INTELXL_PFCM_LANCTXDATA (   x)    ( 0x10c100 + ( 0x80 * (x) ) )

CMLAN Context Data Register.

Definition at line 606 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL

#define INTELXL_PFCM_LANCTXCTL   0x10c300

CMLAN Context Control Register.

Definition at line 609 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_QUEUE_NUM

#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM (   x)    ( (x) << 0 )

Queue number.

Definition at line 610 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_SUB_LINE

#define INTELXL_PFCM_LANCTXCTL_SUB_LINE (   x)    ( (x) << 12 )

Sub-line.

Definition at line 613 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE

#define INTELXL_PFCM_LANCTXCTL_TYPE (   x)    ( (x) << 15 )

Queue type.

Definition at line 616 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_RX

#define INTELXL_PFCM_LANCTXCTL_TYPE_RX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )

RX queue type.

Definition at line 619 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_TX

#define INTELXL_PFCM_LANCTXCTL_TYPE_TX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )

TX queue type.

Definition at line 621 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE (   x)    ( (x) << 17 )

Op code.

Definition at line 623 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_READ

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )

Read context.

Definition at line 626 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )

Write context.

Definition at line 628 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT

#define INTELXL_PFCM_LANCTXSTAT   0x10c380

CMLAN Context Status Register.

Definition at line 632 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT_DONE

#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL

Complete.

Definition at line 633 of file intelxl.h.

◆ INTELXL_CTX_TX_FL_NEW

#define INTELXL_CTX_TX_FL_NEW   0x4000

New transmit queue context.

Definition at line 662 of file intelxl.h.

◆ INTELXL_CTX_TX_BASE

#define INTELXL_CTX_TX_BASE (   base)    ( (base) >> 7 )

Transmit queue base address.

Definition at line 665 of file intelxl.h.

◆ INTELXL_CTX_TX_COUNT

#define INTELXL_CTX_TX_COUNT (   count)    ( (count) << 1 )

Transmit queue count.

Definition at line 668 of file intelxl.h.

◆ INTELXL_CTX_TX_QSET

#define INTELXL_CTX_TX_QSET (   qset)    ( (qset) << 4 )

Transmit queue set.

Definition at line 671 of file intelxl.h.

◆ INTELXL_CTX_RX_BASE_COUNT

#define INTELXL_CTX_RX_BASE_COUNT (   base,
  count 
)    ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )

Receive queue base address and queue count.

Definition at line 692 of file intelxl.h.

◆ INTELXL_CTX_RX_LEN

#define INTELXL_CTX_RX_LEN (   len)    ( (len) >> 1 )

Receive queue data buffer length.

Definition at line 696 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_DSIZE

#define INTELXL_CTX_RX_FL_DSIZE   0x10

Use 32-byte receive descriptors.

Definition at line 699 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_CRCSTRIP

#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20

Strip CRC from received packets.

Definition at line 702 of file intelxl.h.

◆ INTELXL_CTX_RX_MFS

#define INTELXL_CTX_RX_MFS (   mfs)    ( (mfs) >> 2 )

Receive queue maximum frame size.

Definition at line 705 of file intelxl.h.

◆ INTELXL_CTX_MAX_WAIT_MS

#define INTELXL_CTX_MAX_WAIT_MS   100

Maximum time to wait for a context operation to complete.

Definition at line 708 of file intelxl.h.

◆ INTELXL_QUEUE_ENABLE_DELAY_US

#define INTELXL_QUEUE_ENABLE_DELAY_US   20

Time to wait for a queue to become enabled.

Definition at line 711 of file intelxl.h.

◆ INTELXL_QUEUE_PRE_DISABLE_DELAY_US

#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US   400

Time to wait for a transmit queue to become pre-disabled.

Definition at line 714 of file intelxl.h.

◆ INTELXL_QUEUE_DISABLE_MAX_WAIT_MS

#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS   1000

Maximum time to wait for a queue to become disabled.

Definition at line 717 of file intelxl.h.

◆ INTELXL_QTX_HEAD

#define INTELXL_QTX_HEAD (   x)    ( 0x0e4000 + ( 0x4 * (x) ) )

Global Transmit Queue Head register.

Definition at line 727 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS (   x)    ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )

Global Transmit Pre Queue Disable register.

Definition at line 730 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_QINDX

#define INTELXL_GLLAN_TXPRE_QDIS_QINDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 731 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL

Set disable.

Definition at line 734 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL

Clear disable.

Definition at line 736 of file intelxl.h.

◆ INTELXL_QTX

#define INTELXL_QTX (   x)    ( 0x100000 + ( 0x4 * (x) ) )

Global Transmit Queue register block.

Definition at line 740 of file intelxl.h.

◆ INTELXL_QRX

#define INTELXL_QRX (   x)    ( 0x120000 + ( 0x4 * (x) ) )

Global Receive Queue register block.

Definition at line 743 of file intelxl.h.

◆ INTELXL_QXX_ENA

#define INTELXL_QXX_ENA   0x0000

Queue Enable Register (offset)

Definition at line 746 of file intelxl.h.

◆ INTELXL_QXX_ENA_REQ

#define INTELXL_QXX_ENA_REQ   0x00000001UL

Enable request.

Definition at line 747 of file intelxl.h.

◆ INTELXL_QXX_ENA_STAT

#define INTELXL_QXX_ENA_STAT   0x00000004UL

Enabled status.

Definition at line 748 of file intelxl.h.

◆ INTELXL_QXX_CTL

#define INTELXL_QXX_CTL   0x4000

Queue Control Register (offset)

Definition at line 751 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q

#define INTELXL_QXX_CTL_PFVF_Q (   x)    ( (x) << 0 )

PF/VF queue.

Definition at line 752 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q_PF

#define INTELXL_QXX_CTL_PFVF_Q_PF   INTELXL_QXX_CTL_PFVF_Q ( 0x2 )

PF queue.

Definition at line 753 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_PF_INDX

#define INTELXL_QXX_CTL_PFVF_PF_INDX (   x)    ( (x) << 2 )

PF index.

Definition at line 755 of file intelxl.h.

◆ INTELXL_QXX_TAIL

#define INTELXL_QXX_TAIL   0x8000

Queue Tail Pointer Register (offset)

Definition at line 758 of file intelxl.h.

◆ INTELXL_GLLAN_RCTL_0

#define INTELXL_GLLAN_RCTL_0   0x12a500

Global RLAN Control 0 register.

Definition at line 761 of file intelxl.h.

◆ INTELXL_GLLAN_RCTL_0_PXE_MODE

#define INTELXL_GLLAN_RCTL_0_PXE_MODE   0x00000001UL

PXE mode.

Definition at line 762 of file intelxl.h.

◆ INTELXL_TX_DATA_DTYP

#define INTELXL_TX_DATA_DTYP   0x0

Transmit data descriptor type.

Definition at line 775 of file intelxl.h.

◆ INTELXL_TX_DATA_EOP

#define INTELXL_TX_DATA_EOP   0x10

Transmit data descriptor end of packet.

Definition at line 778 of file intelxl.h.

◆ INTELXL_TX_DATA_RS

#define INTELXL_TX_DATA_RS   0x20

Transmit data descriptor report status.

Definition at line 781 of file intelxl.h.

◆ INTELXL_TX_DATA_JFDI

#define INTELXL_TX_DATA_JFDI   0x40

Transmit data descriptor pretty please.

This bit is completely missing from older versions of the XL710 datasheet. Later versions describe it innocuously as "reserved, must be 1". Without this bit, everything will appear to work (up to and including the port "transmit good octets" counter), but no packet will actually be sent.

Definition at line 791 of file intelxl.h.

◆ INTELXL_TX_DATA_LEN

#define INTELXL_TX_DATA_LEN (   len)    ( (len) << 2 )

Transmit data descriptor length.

Definition at line 794 of file intelxl.h.

◆ INTELXL_TX_WB_FL_DD

#define INTELXL_TX_WB_FL_DD   0x01

Transmit writeback descriptor complete.

Definition at line 807 of file intelxl.h.

◆ INTELXL_RX_WB_FL_DD

#define INTELXL_RX_WB_FL_DD   0x00000001UL

Receive writeback descriptor complete.

Definition at line 844 of file intelxl.h.

◆ INTELXL_RX_WB_FL_VLAN

#define INTELXL_RX_WB_FL_VLAN   0x00000004UL

Receive writeback descriptor VLAN tag present.

Definition at line 847 of file intelxl.h.

◆ INTELXL_RX_WB_FL_RXE

#define INTELXL_RX_WB_FL_RXE   0x00080000UL

Receive writeback descriptor error.

Definition at line 850 of file intelxl.h.

◆ INTELXL_RX_WB_LEN

#define INTELXL_RX_WB_LEN (   len)    ( ( (len) >> 6 ) & 0x3fff )

Receive writeback descriptor length.

Definition at line 853 of file intelxl.h.

◆ INTELXL_TX_NUM_DESC

#define INTELXL_TX_NUM_DESC   64

Number of transmit descriptors.

Chosen to exceed the receive ring fill level, in order to avoid running out of transmit descriptors when sending TCP ACKs.

Definition at line 915 of file intelxl.h.

◆ INTELXL_TX_FILL

#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 918 of file intelxl.h.

◆ INTELXL_RX_NUM_DESC

#define INTELXL_RX_NUM_DESC   32

Number of receive descriptors.

Must be a multiple of 32.

Definition at line 924 of file intelxl.h.

◆ INTELXL_RX_FILL

#define INTELXL_RX_FILL   16

Receive descriptor ring fill level.

Must be a multiple of 8 and greater than 8.

Definition at line 930 of file intelxl.h.

◆ INTELXL_PFINT_DYN_CTL0

#define INTELXL_PFINT_DYN_CTL0   0x038480

PF Interrupt Zero Dynamic Control Register.

Definition at line 940 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA

#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL

Enable.

Definition at line 941 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_CLEARPBA

#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL

Acknowledge.

Definition at line 942 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA_MASK

#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL

Ignore enable.

Definition at line 943 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0

#define INTELXL_PFINT_LNKLST0   0x038500

PF Interrupt Zero Linked List Register.

Definition at line 946 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 947 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE   INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )

End of list.

Definition at line 950 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE (   x)    ( (x) << 11 )

Queue type.

Definition at line 952 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 955 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 957 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA

#define INTELXL_PFINT_ICR0_ENA   0x038800

PF Interrupt Zero Cause Enablement Register.

Definition at line 961 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA_ADMINQ

#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL

Admin event.

Definition at line 962 of file intelxl.h.

◆ INTELXL_QINT_RQCTL

#define INTELXL_QINT_RQCTL (   x)    ( 0x03a000 + ( 0x4 * (x) ) )

Receive Queue Interrupt Cause Control Register.

Definition at line 965 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX

#define INTELXL_QINT_RQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 966 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 967 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 969 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 970 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 972 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_CAUSE_ENA

#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 974 of file intelxl.h.

◆ INTELXL_QINT_TQCTL

#define INTELXL_QINT_TQCTL (   x)    ( 0x03c000 + ( 0x4 * (x) ) )

Transmit Queue Interrupt Cause Control Register.

Definition at line 977 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX

#define INTELXL_QINT_TQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 978 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 979 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 981 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 982 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 984 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_CAUSE_ENA

#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 986 of file intelxl.h.

◆ INTELXL_PFGEN_CTRL

#define INTELXL_PFGEN_CTRL   0x092400

PF Control Register.

Definition at line 989 of file intelxl.h.

◆ INTELXL_PFGEN_CTRL_PFSWR

#define INTELXL_PFGEN_CTRL_PFSWR   0x00000001UL

Software Reset.

Definition at line 990 of file intelxl.h.

◆ INTELXL_RESET_DELAY_MS

#define INTELXL_RESET_DELAY_MS   100

Time to delay for device reset, in milliseconds.

Definition at line 993 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC

#define INTELXL_PFLAN_QALLOC   0x1c0400

PF Queue Allocation Register.

Definition at line 996 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_FIRSTQ

#define INTELXL_PFLAN_QALLOC_FIRSTQ (   x)    ( ( (x) >> 0 ) & 0x7ff )

First queue.

Definition at line 997 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_LASTQ

#define INTELXL_PFLAN_QALLOC_LASTQ (   x)    ( ( (x) >> 16 ) & 0x7ff )

Last queue.

Definition at line 1000 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM

#define INTELXL_PFGEN_PORTNUM   0x1c0480

PF LAN Port Number Register.

Definition at line 1005 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM_PORT_NUM

#define INTELXL_PFGEN_PORTNUM_PORT_NUM (   x)    ( ( (x) >> 0 ) & 0x3 )

Port number.

Definition at line 1006 of file intelxl.h.

◆ INTELXL_PRTGL_SAL

#define INTELXL_PRTGL_SAL   0x1e2120

Port MAC Address Low Register.

Definition at line 1011 of file intelxl.h.

◆ INTELXL_PRTGL_SAH

#define INTELXL_PRTGL_SAH   0x1e2140

Port MAC Address High Register.

Definition at line 1014 of file intelxl.h.

◆ INTELXL_PRTGL_SAH_MFS_GET

#define INTELXL_PRTGL_SAH_MFS_GET (   x)    ( (x) >> 16 )

Max frame size.

Definition at line 1015 of file intelxl.h.

◆ INTELXL_PRTGL_SAH_MFS_SET

#define INTELXL_PRTGL_SAH_MFS_SET (   x)    ( (x) << 16 )

Max frame size.

Definition at line 1016 of file intelxl.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ intelxl_init_admin()

static void intelxl_init_admin ( struct intelxl_admin admin,
unsigned int  base,
const struct intelxl_admin_offsets regs 
)
inlinestatic

Initialise admin queue.

Parameters
adminAdmin queue
baseRegister block base
regsRegister offsets

Definition at line 582 of file intelxl.h.

583  {
584 
585  admin->base = base;
586  admin->regs = regs;
587 }
unsigned int base
Register block base.
Definition: intelxl.h:569
struct i386_regs regs
Definition: registers.h:15
uint16_t base
Base address.
Definition: edd.h:14
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:571

References base, intelxl_admin::base, regs, and intelxl_admin::regs.

Referenced by intelxl_probe(), and intelxlvf_probe().

◆ intelxl_init_ring()

static void intelxl_init_ring ( struct intelxl_ring ring,
unsigned int  count,
size_t  len,
int(*)(struct intelxl_nic *intelxl, physaddr_t address context 
)
inlinestatic

Initialise descriptor ring.

Parameters
ringDescriptor ring
countNumber of descriptors
lenLength of a single descriptor
contextMethod to program queue context

Definition at line 902 of file intelxl.h.

1009  {

Referenced by intelxl_probe().

◆ intelxl_msix_enable()

int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci 
)

Enable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
Return values
rcReturn status code

Definition at line 133 of file intelxl.c.

134  {
135  int rc;
136 
137  /* Enable MSI-X capability */
138  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix ) ) != 0 ) {
139  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
140  intelxl, strerror ( rc ) );
141  return rc;
142  }
143 
144  /* Configure interrupt zero to write to dummy location */
145  pci_msix_map ( &intelxl->msix, 0, virt_to_bus ( &intelxl->msg ), 0 );
146 
147  /* Enable dummy interrupt zero */
148  pci_msix_unmask ( &intelxl->msix, 0 );
149 
150  return 0;
151 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:1051
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:72
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
struct pci_msix msix
MSI-X capability.
Definition: intelxl.h:1049
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:104
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:181

References DBGC, intelxl_nic::msg, intelxl_nic::msix, pci_msix_enable(), pci_msix_map(), pci_msix_unmask(), rc, strerror(), and virt_to_bus().

Referenced by intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci 
)

Disable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device

Definition at line 159 of file intelxl.c.

160  {
161 
162  /* Disable dummy interrupt zero */
163  pci_msix_mask ( &intelxl->msix, 0 );
164 
165  /* Disable MSI-X capability */
166  pci_msix_disable ( pci, &intelxl->msix );
167 }
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:60
struct pci_msix msix
MSI-X capability.
Definition: intelxl.h:1049

References intelxl_nic::msix, pci_msix_disable(), and pci_msix_mask().

Referenced by intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic intelxl)

Get next admin command queue descriptor.

Parameters
intelxlIntel device
Return values
cmdCommand descriptor

Definition at line 290 of file intelxl.c.

290  {
291  struct intelxl_admin *admin = &intelxl->command;
293 
294  /* Get and initialise next descriptor */
295  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
296  memset ( cmd, 0, sizeof ( *cmd ) );
297  return cmd;
298 }
Admin queue.
Definition: intelxl.h:560
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:590
unsigned int index
Queue index.
Definition: intelxl.h:566
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:562
Admin queue descriptor.
Definition: intelxl.h:522
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
void * memset(void *dest, int character, size_t len) __nonnull

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_configure(), intelxlvf_admin_get_resources(), intelxlvf_admin_irq_map(), intelxlvf_admin_promisc(), intelxlvf_admin_queues(), and intelxlvf_reset_admin().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl)

Get next admin command queue data buffer.

Parameters
intelxlIntel device
Return values
bufData buffer

Definition at line 307 of file intelxl.c.

307  {
308  struct intelxl_admin *admin = &intelxl->command;
309  union intelxl_admin_buffer *buf;
310 
311  /* Get next data buffer */
312  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
313  memset ( buf, 0, sizeof ( *buf ) );
314  return buf;
315 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:564
Admin queue.
Definition: intelxl.h:560
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:590
unsigned int index
Queue index.
Definition: intelxl.h:566
Admin queue data buffer.
Definition: intelxl.h:498
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by intelxl_admin_driver(), intelxl_admin_switch(), intelxl_admin_vsi(), intelxlvf_admin_configure(), intelxlvf_admin_irq_map(), intelxlvf_admin_promisc(), and intelxlvf_admin_queues().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 346 of file intelxl.c.

346  {
347  struct intelxl_admin *admin = &intelxl->command;
348  const struct intelxl_admin_offsets *regs = admin->regs;
349  void *admin_regs = ( intelxl->regs + admin->base );
351  union intelxl_admin_buffer *buf;
353  uint32_t cookie;
354  unsigned int index;
355  unsigned int tail;
356  unsigned int i;
357  int rc;
358 
359  /* Get next queue entry */
360  index = admin->index++;
361  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
362  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
363  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
364  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
365  intelxl, index, le16_to_cpu ( cmd->opcode ) );
366  if ( cmd->vopcode )
367  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->vopcode ) );
368  DBGC2 ( intelxl, ":\n" );
369 
370  /* Sanity checks */
371  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
372  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
373  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
374  assert ( cmd->ret == 0 );
375 
376  /* Populate data buffer address if applicable */
377  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
378  address = virt_to_bus ( buf );
379  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
380  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
381  }
382 
383  /* Populate cookie, if not being (ab)used for VF opcode */
384  if ( ! cmd->vopcode )
385  cmd->cookie = cpu_to_le32 ( index );
386 
387  /* Record cookie */
388  cookie = cmd->cookie;
389 
390  /* Post command descriptor */
391  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
392  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
393  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
394  le16_to_cpu ( cmd->len ) );
395  }
396  wmb();
397  writel ( tail, admin_regs + regs->tail );
398 
399  /* Wait for completion */
400  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
401 
402  /* If response is not complete, delay 1ms and retry */
403  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
404  mdelay ( 1 );
405  continue;
406  }
407  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
408  intelxl, index );
409  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
410  sizeof ( *cmd ) );
411 
412  /* Check for cookie mismatch */
413  if ( cmd->cookie != cookie ) {
414  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
415  "cookie %#x\n", intelxl, index,
416  le32_to_cpu ( cmd->cookie ) );
417  rc = -EPROTO;
418  goto err;
419  }
420 
421  /* Check for errors */
422  if ( cmd->ret != 0 ) {
423  DBGC ( intelxl, "INTELXL %p admin command %#x error "
424  "%d\n", intelxl, index,
425  le16_to_cpu ( cmd->ret ) );
426  rc = -EIO;
427  goto err;
428  }
429 
430  /* Success */
431  return 0;
432  }
433 
434  rc = -ETIMEDOUT;
435  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
436  intelxl, index );
437  err:
438  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
439  return rc;
440 }
void * regs
Registers.
Definition: intelxl.h:1030
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:551
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
wmb()
#define le32_to_cpu(value)
Definition: byteswap.h:113
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:564
Admin queue register offsets.
Definition: intelxl.h:62
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:560
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:569
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:590
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:548
unsigned int index
Queue index.
Definition: intelxl.h:566
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define DBGC_HDA(...)
Definition: compiler.h:506
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define EPROTO
Protocol error.
Definition: errno.h:624
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:562
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:557
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
struct i386_regs regs
Definition: registers.h:15
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Admin queue descriptor.
Definition: intelxl.h:522
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
#define cpu_to_le16(value)
Definition: byteswap.h:106
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:571
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:593
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:545
Admin queue data buffer.
Definition: intelxl.h:498

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, virt_to_bus(), virt_to_phys(), wmb(), and writel().

Referenced by intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), and intelxlvf_reset_admin().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters
netdevNetwork device

Definition at line 780 of file intelxl.c.

780  {
781  struct intelxl_nic *intelxl = netdev->priv;
782  struct intelxl_admin *admin = &intelxl->event;
783  struct intelxl_admin_descriptor *evt;
784  union intelxl_admin_buffer *buf;
785 
786  /* Check for events */
787  while ( 1 ) {
788 
789  /* Get next event descriptor and data buffer */
790  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
791  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
792 
793  /* Stop if descriptor is not yet completed */
794  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
795  return;
796  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
797  intelxl, admin->index );
798  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
799  sizeof ( *evt ) );
800  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
801  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
802  le16_to_cpu ( evt->len ) );
803  }
804 
805  /* Handle event */
806  switch ( evt->opcode ) {
809  break;
811  intelxlvf_admin_event ( netdev, evt, buf );
812  break;
813  default:
814  DBGC ( intelxl, "INTELXL %p admin event %#x "
815  "unrecognised opcode %#04x\n", intelxl,
816  admin->index, le16_to_cpu ( evt->opcode ) );
817  break;
818  }
819 
820  /* Reset descriptor and refill queue */
821  intelxl_admin_event_init ( intelxl, admin->index );
822  admin->index++;
823  intelxl_refill_admin ( intelxl );
824  }
825 }
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:283
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:564
uint16_t opcode
Opcode.
Definition: intelxl.h:526
Admin queue.
Definition: intelxl.h:560
#define DBGC(...)
Definition: compiler.h:505
uint16_t flags
Flags.
Definition: intelxl.h:524
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:590
uint16_t len
Data length.
Definition: intelxl.h:528
unsigned int index
Queue index.
Definition: intelxl.h:566
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:323
void * priv
Driver private data.
Definition: netdevice.h:425
static struct net_device * netdev
Definition: gdbudp.c:52
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:762
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:562
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:557
#define INTELXL_ADMIN_SEND_TO_VF
Admin queue Send Message to VF command.
Definition: intelxl.h:311
An Intel 40Gigabit network card.
Definition: intelxl.h:1028
#define le16_to_cpu(value)
Definition: byteswap.h:112
Admin queue descriptor.
Definition: intelxl.h:522
#define DBGC2(...)
Definition: compiler.h:522
__weak void intelxlvf_admin_event(struct net_device *netdev __unused, struct intelxl_admin_descriptor *evt __unused, union intelxl_admin_buffer *buf __unused)
Handle virtual function event (when VF driver is not present)
Definition: intelxl.c:750
#define cpu_to_le16(value)
Definition: byteswap.h:106
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:714
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1058
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:545
Admin queue data buffer.
Definition: intelxl.h:498

References intelxl_admin::buf, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_LINK, intelxl_admin_link(), INTELXL_ADMIN_NUM_DESC, INTELXL_ADMIN_SEND_TO_VF, intelxl_refill_admin(), intelxlvf_admin_event(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, intelxl_admin_descriptor::opcode, net_device::priv, and virt_to_phys().

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 833 of file intelxl.c.

833  {
834  int rc;
835 
836  /* Allocate admin event queue */
837  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
838  goto err_alloc_event;
839 
840  /* Allocate admin command queue */
841  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
842  goto err_alloc_command;
843 
844  /* (Re)open admin queues */
845  intelxl_reopen_admin ( intelxl );
846 
847  /* Get firmware version */
848  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
849  goto err_version;
850 
851  /* Report driver version */
852  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
853  goto err_driver;
854 
855  return 0;
856 
857  err_driver:
858  err_version:
859  intelxl_disable_admin ( intelxl, &intelxl->command );
860  intelxl_disable_admin ( intelxl, &intelxl->event );
861  intelxl_free_admin ( intelxl, &intelxl->command );
862  err_alloc_command:
863  intelxl_free_admin ( intelxl, &intelxl->event );
864  err_alloc_event:
865  return rc;
866 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
Admin queue version number.
Definition: intelxl.h:89
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:192
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:274
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:259
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:873
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:484
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1058

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_driver(), intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters
intelxlIntel device

Definition at line 873 of file intelxl.c.

873  {
874  unsigned int i;
875 
876  /* Enable admin event queue */
877  intelxl_enable_admin ( intelxl, &intelxl->event );
878 
879  /* Enable admin command queue */
880  intelxl_enable_admin ( intelxl, &intelxl->command );
881 
882  /* Initialise all admin event queue descriptors */
883  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
884  intelxl_admin_event_init ( intelxl, i );
885 
886  /* Post all descriptors to event queue */
887  intelxl_refill_admin ( intelxl );
888 }
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:220
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:590
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:323
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:762
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1058

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_admin().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters
intelxlIntel device

Definition at line 895 of file intelxl.c.

895  {
896 
897  /* Shut down admin queues */
898  intelxl_admin_shutdown ( intelxl );
899 
900  /* Disable admin queues */
901  intelxl_disable_admin ( intelxl, &intelxl->command );
902  intelxl_disable_admin ( intelxl, &intelxl->event );
903 
904  /* Free admin queues */
905  intelxl_free_admin ( intelxl, &intelxl->command );
906  intelxl_free_admin ( intelxl, &intelxl->event );
907 }
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:515
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1056
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:274
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:259
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1058

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 923 of file intelxl.c.

924  {
926  int rc;
927 
928  /* Allocate descriptor ring */
929  ring->desc.raw = malloc_dma ( ring->len, INTELXL_ALIGN );
930  if ( ! ring->desc.raw ) {
931  rc = -ENOMEM;
932  goto err_alloc;
933  }
934  address = virt_to_bus ( ring->desc.raw );
935 
936  /* Initialise descriptor ring */
937  memset ( ring->desc.raw, 0, ring->len );
938 
939  /* Reset tail pointer */
940  writel ( 0, ( intelxl->regs + ring->tail ) );
941 
942  /* Reset counters */
943  ring->prod = 0;
944  ring->cons = 0;
945 
946  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08llx,%08llx)\n",
947  intelxl, ( ring->reg + ring->tail ),
948  ( ( unsigned long long ) address ),
949  ( ( unsigned long long ) address + ring->len ) );
950 
951  return 0;
952 
953  free_dma ( ring->desc.raw, ring->len );
954  err_alloc:
955  return rc;
956 }
void * regs
Registers.
Definition: intelxl.h:1030
size_t len
Length (in bytes)
Definition: intelxl.h:884
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint64_t address
Base address.
Definition: ena.h:24
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:875
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:25
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:877
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void * raw
Raw data.
Definition: intelxl.h:872
unsigned int reg
Register block.
Definition: intelxl.h:880
union intelxl_ring::@64 desc
Descriptors.
unsigned long physaddr_t
Definition: stdint.h:20
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
unsigned int tail
Tail register.
Definition: intelxl.h:882
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
void * memset(void *dest, int character, size_t len) __nonnull

References address, intelxl_ring::cons, DBGC, intelxl_ring::desc, ENOMEM, free_dma(), INTELXL_ALIGN, intelxl_ring::len, malloc_dma(), memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, virt_to_bus(), and writel().

Referenced by intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters
intelxlIntel device

Definition at line 1337 of file intelxl.c.

1337  {
1338  unsigned int i;
1339 
1340  /* Discard any unused receive buffers */
1341  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1342  if ( intelxl->rx_iobuf[i] )
1343  free_iob ( intelxl->rx_iobuf[i] );
1344  intelxl->rx_iobuf[i] = NULL;
1345  }
1346 }
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:1072
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:924
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References free_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by intelxl_close(), and intelxlvf_close().

◆ intelxl_transmit()

int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 1465 of file intelxl.c.

1465  {
1466  struct intelxl_nic *intelxl = netdev->priv;
1468  unsigned int tx_idx;
1469  unsigned int tx_tail;
1471  size_t len;
1472 
1473  /* Get next transmit descriptor */
1474  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1475  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1476  intelxl );
1477  return -ENOBUFS;
1478  }
1479  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1480  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1481  tx = &intelxl->tx.desc.tx[tx_idx].data;
1482 
1483  /* Populate transmit descriptor */
1484  address = virt_to_bus ( iobuf->data );
1485  len = iob_len ( iobuf );
1486  tx->address = cpu_to_le64 ( address );
1487  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1490  wmb();
1491 
1492  /* Notify card that there are packets ready to transmit */
1493  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1494 
1495  DBGC2 ( intelxl, "INTELXL %p TX %d is [%llx,%llx)\n", intelxl, tx_idx,
1496  ( ( unsigned long long ) address ),
1497  ( ( unsigned long long ) address + len ) );
1498  return 0;
1499 }
void * regs
Registers.
Definition: intelxl.h:1030
wmb()
uint64_t address
Base address.
Definition: ena.h:24
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:778
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:775
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:875
#define cpu_to_le64(value)
Definition: byteswap.h:108
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:868
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:794
unsigned int cons
Consumer index.
Definition: intelxl.h:877
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:812
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:915
void * priv
Driver private data.
Definition: netdevice.h:425
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:781
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
union intelxl_ring::@64 desc
Descriptors.
Transmit data descriptor.
Definition: intelxl.h:765
An Intel 40Gigabit network card.
Definition: intelxl.h:1028
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:791
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:1068
unsigned long physaddr_t
Definition: stdint.h:20
uint32_t len
Length.
Definition: ena.h:14
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:44
unsigned int tail
Tail register.
Definition: intelxl.h:882
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:918

References address, intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, virt_to_bus(), wmb(), and writel().

◆ intelxl_poll()

void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters
netdevNetwork device

Definition at line 1587 of file intelxl.c.

1587  {
1588  struct intelxl_nic *intelxl = netdev->priv;
1589 
1590  /* Poll for completed packets */
1591  intelxl_poll_tx ( netdev );
1592 
1593  /* Poll for received packets */
1594  intelxl_poll_rx ( netdev );
1595 
1596  /* Poll for admin events */
1598 
1599  /* Refill RX ring */
1600  intelxl_refill_rx ( intelxl );
1601 
1602  /* Rearm interrupt, since otherwise receive descriptors will
1603  * be written back only after a complete cacheline (four
1604  * packets) have been received.
1605  *
1606  * There is unfortunately no efficient way to determine
1607  * whether or not rearming the interrupt is necessary. If we
1608  * are running inside a hypervisor (e.g. using a VF or PF as a
1609  * passed-through PCI device), then the MSI-X write is
1610  * redirected by the hypervisor to the real host APIC and the
1611  * host ISR then raises an interrupt within the guest. We
1612  * therefore cannot poll the nominal MSI-X target location to
1613  * watch for the value being written. We could read from the
1614  * INT_DYN_CTL register, but this is even less efficient than
1615  * just unconditionally rearming the interrupt.
1616  */
1617  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1618 }
void * regs
Registers.
Definition: intelxl.h:1030
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:941
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1506
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1287
void * priv
Driver private data.
Definition: netdevice.h:425
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:780
unsigned int intr
Interrupt control register.
Definition: intelxl.h:1047
An Intel 40Gigabit network card.
Definition: intelxl.h:1028
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1535

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

◆ intelxlvf_admin_event()

void intelxlvf_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor evt,
union intelxl_admin_buffer buf 
)

Handle virtual function event.

Parameters
netdevNetwork device
evtAdmin queue event descriptor
bufAdmin queue event data buffer

Definition at line 287 of file intelxlvf.c.

289  {
290  struct intelxl_nic *intelxl = netdev->priv;
291  unsigned int vopcode = le32_to_cpu ( evt->vopcode );
292 
293  /* Record command response if applicable */
294  if ( vopcode == intelxl->vopcode ) {
295  memcpy ( &intelxl->vbuf, buf, sizeof ( intelxl->vbuf ) );
296  intelxl->vopcode = 0;
297  intelxl->vret = le32_to_cpu ( evt->vret );
298  if ( intelxl->vret != 0 ) {
299  DBGC ( intelxl, "INTELXL %p admin VF command %#x "
300  "error %d\n", intelxl, vopcode, intelxl->vret );
301  DBGC_HDA ( intelxl, virt_to_bus ( evt ), evt,
302  sizeof ( *evt ) );
303  DBGC_HDA ( intelxl, virt_to_bus ( buf ), buf,
304  le16_to_cpu ( evt->len ) );
305  }
306  return;
307  }
308 
309  /* Handle unsolicited events */
310  switch ( vopcode ) {
313  break;
314  default:
315  DBGC ( intelxl, "INTELXL %p unrecognised VF event %#x:\n",
316  intelxl, vopcode );
317  DBGC_HDA ( intelxl, 0, evt, sizeof ( *evt ) );
318  DBGC_HDA ( intelxl, 0, buf, le16_to_cpu ( evt->len ) );
319  break;
320  }
321 }
#define le32_to_cpu(value)
Definition: byteswap.h:113
int vret
Current VF return value.
Definition: intelxl.h:1063
#define DBGC(...)
Definition: compiler.h:505
static void intelxlvf_admin_status(struct net_device *netdev, struct intelxl_admin_vf_status_buffer *stat)
Handle status change event.
Definition: intelxlvf.c:263
struct intelxl_admin_vf_status_buffer stat
VF Status Change Event data buffer.
Definition: intelxl.h:508
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint16_t len
Data length.
Definition: intelxl.h:528
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
void * priv
Driver private data.
Definition: netdevice.h:425
#define DBGC_HDA(...)
Definition: compiler.h:506
static struct net_device * netdev
Definition: gdbudp.c:52
union intelxl_admin_buffer vbuf
Current VF event data buffer.
Definition: intelxl.h:1065
int32_t vret
VF return value.
Definition: intelxl.h:539
An Intel 40Gigabit network card.
Definition: intelxl.h:1028
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int vopcode
Current VF opcode.
Definition: intelxl.h:1061
uint32_t vopcode
VF opcode.
Definition: intelxl.h:536
#define INTELXL_ADMIN_VF_STATUS
Admin Queue VF Status Change Event opcode.
Definition: intelxl.h:332

References DBGC, DBGC_HDA, INTELXL_ADMIN_VF_STATUS, intelxlvf_admin_status(), le16_to_cpu, le32_to_cpu, intelxl_admin_descriptor::len, memcpy(), netdev, net_device::priv, intelxl_admin_buffer::stat, intelxl_nic::vbuf, virt_to_bus(), intelxl_admin_descriptor::vopcode, intelxl_nic::vopcode, intelxl_admin_descriptor::vret, and intelxl_nic::vret.