Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/pcimsix.h>
#include <ipxe/dma.h>

Data Structures
struct	intelxl_admin_offsets
	Admin queue register offsets. More...

struct	intelxl_admin_buffer_params
	Admin queue data buffer command parameters. More...

struct	intelxl_admin_version
	Admin queue version number. More...

struct	intelxl_admin_version_params
	Admin queue Get Version command parameters. More...

struct	intelxl_admin_driver_params
	Admin queue Driver Version command parameters. More...

struct	intelxl_admin_driver_buffer
	Admin queue Driver Version data buffer. More...

struct	intelxl_admin_shutdown_params
	Admin queue Shutdown command parameters. More...

struct	intelxl_admin_mac_read_params
	Admin queue Manage MAC Address Read command parameters. More...

struct	intelxl_admin_mac_read_buffer
	Admin queue Manage MAC Address Read data buffer. More...

struct	intelxl_admin_mac_write_params
	Admin queue Manage MAC Address Write command parameters. More...

struct	intelxl_admin_clear_pxe_params
	Admin queue Clear PXE Mode command parameters. More...

struct	intelxl_admin_switch_config
	Switching element configuration. More...

struct	intelxl_admin_switch_params
	Admin queue Get Switch Configuration command parameters. More...

struct	intelxl_admin_switch_buffer
	Admin queue Get Switch Configuration data buffer. More...

struct	intelxl_admin_vsi_params
	Admin queue Get VSI Parameters command parameters. More...

struct	intelxl_admin_vsi_buffer
	Admin queue Get VSI Parameters data buffer. More...

struct	intelxl_admin_promisc_params
	Admin queue Set VSI Promiscuous Modes command parameters. More...

struct	intelxl_admin_mac_config_params
	Admin queue Set MAC Configuration command parameters. More...

struct	intelxl_admin_autoneg_params
	Admin queue Restart Autonegotiation command parameters. More...

struct	intelxl_admin_link_params
	Admin queue Get Link Status command parameters. More...

union	intelxl_admin_params
	Admin queue command parameters. More...

union	intelxl_admin_buffer
	Admin queue data buffer. More...

struct	intelxl_admin_descriptor
	Admin queue descriptor. More...

struct	intelxl_admin
	Admin queue. More...

struct	intelxl_context_line
	Queue context line. More...

struct	intelxl_context_tx
	Transmit queue context. More...

struct	intelxl_context_rx
	Receive queue context. More...

struct	intelxl_tx_data_descriptor
	Transmit data descriptor. More...

struct	intelxl_tx_writeback_descriptor
	Transmit writeback descriptor. More...

union	intelxl_tx_descriptor
	Transmit descriptor. More...

struct	intelxl_rx_data_descriptor
	Receive data descriptor. More...

struct	intelxl_rx_writeback_descriptor
	Receive writeback descriptor. More...

union	intelxl_rx_descriptor
	Packet descriptor. More...

struct	intelxl_ring
	Descriptor ring. More...

struct	intelxl_msix
	MSI-X interrupt. More...

struct	intelxl_nic
	An Intel 40 Gigabit network card. More...

Macros
#define	INTELXL_BAR_SIZE 0x200000
	BAR size. More...

#define	INTELXL_ALIGN 256
	Alignment. More...

#define	INTELXL_ADMIN_CMD 0x080000
	PF Admin Command Queue register block. More...

#define	INTELXL_ADMIN_EVT 0x080080
	PF Admin Event Queue register block. More...

#define	INTELXL_ADMIN_BAL 0x000
	Admin Queue Base Address Low Register (offset) More...

#define	INTELXL_ADMIN_BAH 0x100
	Admin Queue Base Address High Register (offset) More...

#define	INTELXL_ADMIN_LEN 0x200
	Admin Queue Length Register (offset) More...

#define	INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 )
	Queue length. More...

#define	INTELXL_ADMIN_LEN_ENABLE 0x80000000UL
	Queue enable. More...

#define	INTELXL_ADMIN_HEAD 0x300
	Admin Queue Head Register (offset) More...

#define	INTELXL_ADMIN_TAIL 0x400
	Admin Queue Tail Register (offset) More...

#define	INTELXL_ADMIN_VERSION 0x0001
	Admin queue Get Version command. More...

#define	INTELXL_ADMIN_DRIVER 0x0002
	Admin queue Driver Version command. More...

#define	INTELXL_ADMIN_SHUTDOWN 0x0003
	Admin queue Shutdown command. More...

#define	INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
	Driver is unloading. More...

#define	INTELXL_ADMIN_MAC_READ 0x0107
	Admin queue Manage MAC Address Read command. More...

#define	INTELXL_ADMIN_MAC_READ_VALID_LAN 0x10
	LAN MAC address is valid. More...

#define	INTELXL_ADMIN_MAC_WRITE 0x0108
	Admin queue Manage MAC Address Write command. More...

#define	INTELXL_ADMIN_CLEAR_PXE 0x0110
	Admin queue Clear PXE Mode command. More...

#define	INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
	Clear PXE Mode magic value. More...

#define	INTELXL_ADMIN_SWITCH 0x0200
	Admin queue Get Switch Configuration command. More...

#define	INTELXL_ADMIN_SWITCH_TYPE_VSI 19
	Virtual Station Inferface element type. More...

#define	INTELXL_ADMIN_VSI 0x0212
	Admin queue Get VSI Parameters command. More...

#define	INTELXL_ADMIN_PROMISC 0x0254
	Admin queue Set VSI Promiscuous Modes command. More...

#define	INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
	Promiscuous unicast mode. More...

#define	INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
	Promiscuous multicast mode. More...

#define	INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
	Promiscuous broadcast mode. More...

#define	INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
	Promiscuous VLAN mode. More...

#define	INTELXL_ADMIN_MAC_CONFIG 0x0603
	Admin queue Set MAC Configuration command. More...

#define	INTELXL_ADMIN_MAC_CONFIG_FL_CRC 0x04
	Append CRC on transmit. More...

#define	INTELXL_ADMIN_AUTONEG 0x0605
	Admin queue Restart Autonegotiation command. More...

#define	INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
	Restart autonegotiation. More...

#define	INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
	Enable link. More...

#define	INTELXL_ADMIN_LINK 0x0607
	Admin queue Get Link Status command. More...

#define	INTELXL_ADMIN_LINK_NOTIFY 0x03
	Notify driver of link status changes. More...

#define	INTELXL_ADMIN_LINK_UP 0x01
	Link is up. More...

#define	INTELXL_ADMIN_BUFFER_SIZE 0x1000
	Maximum size of a data buffer. More...

#define	INTELXL_ADMIN_FL_DD 0x0001
	Admin descriptor done. More...

#define	INTELXL_ADMIN_FL_CMP 0x0002
	Admin descriptor contains a completion. More...

#define	INTELXL_ADMIN_FL_ERR 0x0004
	Admin descriptor completed in error. More...

#define	INTELXL_ADMIN_FL_RD 0x0400
	Admin descriptor uses data buffer for command parameters. More...

#define	INTELXL_ADMIN_FL_BUF 0x1000
	Admin descriptor uses data buffer. More...

#define	INTELXL_ADMIN_EEXIST 13
	Error: attempt to create something that already exists. More...

#define	INTELXL_ADMIN_NUM_DESC 4
	Number of admin queue descriptors. More...

#define	INTELXL_ADMIN_MAX_WAIT_MS 100
	Maximum time to wait for an admin request to complete. More...

#define	INTELXL_ADMIN_API_MAJOR 1
	Admin queue API major version. More...

#define	INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
	CMLAN Context Data Register. More...

#define	INTELXL_PFCM_LANCTXCTL 0x10c300
	CMLAN Context Control Register. More...

#define	INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) ( (x) << 0 )
	Queue number. More...

#define	INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) ( (x) << 12 )
	Sub-line. More...

#define	INTELXL_PFCM_LANCTXCTL_TYPE(x) ( (x) << 15 )
	Queue type. More...

#define	INTELXL_PFCM_LANCTXCTL_TYPE_RX INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )
	RX queue type. More...

#define	INTELXL_PFCM_LANCTXCTL_TYPE_TX INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )
	TX queue type. More...

#define	INTELXL_PFCM_LANCTXCTL_OP_CODE(x) ( (x) << 17 )
	Op code. More...

#define	INTELXL_PFCM_LANCTXCTL_OP_CODE_READ INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )
	Read context. More...

#define	INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )
	Write context. More...

#define	INTELXL_PFCM_LANCTXSTAT 0x10c380
	CMLAN Context Status Register. More...

#define	INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL
	Complete. More...

#define	INTELXL_CTX_TX_FL_NEW 0x4000
	New transmit queue context. More...

#define	INTELXL_CTX_TX_BASE(base) ( (base) >> 7 )
	Transmit queue base address. More...

#define	INTELXL_CTX_TX_COUNT(count) ( (count) << 1 )
	Transmit queue count. More...

#define	INTELXL_CTX_TX_QSET(qset) ( (qset) << 4 )
	Transmit queue set. More...

#define	INTELXL_CTX_RX_BASE_COUNT(base, count) ( ( (base) >> 7 ) \| ( ( ( uint64_t ) (count) ) << 57 ) )
	Receive queue base address and queue count. More...

#define	INTELXL_CTX_RX_LEN(len) ( (len) >> 1 )
	Receive queue data buffer length. More...

#define	INTELXL_CTX_RX_FL_DSIZE 0x10
	Use 32-byte receive descriptors. More...

#define	INTELXL_CTX_RX_FL_CRCSTRIP 0x20
	Strip CRC from received packets. More...

#define	INTELXL_CTX_RX_MFS(mfs) ( (mfs) >> 2 )
	Receive queue maximum frame size. More...

#define	INTELXL_CTX_MAX_WAIT_MS 100
	Maximum time to wait for a context operation to complete. More...

#define	INTELXL_QUEUE_ENABLE_DELAY_US 20
	Time to wait for a queue to become enabled. More...

#define	INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
	Time to wait for a transmit queue to become pre-disabled. More...

#define	INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
	Maximum time to wait for a queue to become disabled. More...

#define	INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
	Global Transmit Queue Head register. More...

#define	INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
	Global Transmit Pre Queue Disable register. More...

#define	INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) ( (x) << 0 )
	Queue index. More...

#define	INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS 0x40000000UL
	Set disable. More...

#define	INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS 0x80000000UL
	Clear disable. More...

#define	INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
	Global Transmit Queue register block. More...

#define	INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
	Global Receive Queue register block. More...

#define	INTELXL_QXX_ENA 0x0000
	Queue Enable Register (offset) More...

#define	INTELXL_QXX_ENA_REQ 0x00000001UL
	Enable request. More...

#define	INTELXL_QXX_ENA_STAT 0x00000004UL
	Enabled status. More...

#define	INTELXL_QXX_CTL 0x4000
	Queue Control Register (offset) More...

#define	INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 )
	PF/VF queue. More...

#define	INTELXL_QXX_CTL_PFVF_Q_PF INTELXL_QXX_CTL_PFVF_Q ( 0x2 )
	PF queue. More...

#define	INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 )
	PF index. More...

#define	INTELXL_QXX_TAIL 0x8000
	Queue Tail Pointer Register (offset) More...

#define	INTELXL_TX_DATA_DTYP 0x0
	Transmit data descriptor type. More...

#define	INTELXL_TX_DATA_EOP 0x10
	Transmit data descriptor end of packet. More...

#define	INTELXL_TX_DATA_RS 0x20
	Transmit data descriptor report status. More...

#define	INTELXL_TX_DATA_JFDI 0x40
	Transmit data descriptor pretty please. More...

#define	INTELXL_TX_DATA_LEN(len) ( (len) << 2 )
	Transmit data descriptor length. More...

#define	INTELXL_TX_WB_FL_DD 0x01
	Transmit writeback descriptor complete. More...

#define	INTELXL_RX_WB_FL_DD 0x00000001UL
	Receive writeback descriptor complete. More...

#define	INTELXL_RX_WB_FL_VLAN 0x00000004UL
	Receive writeback descriptor VLAN tag present. More...

#define	INTELXL_RX_WB_FL_RXE 0x00080000UL
	Receive writeback descriptor error. More...

#define	INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
	Receive writeback descriptor length. More...

#define	INTELXL_TX_NUM_DESC 64
	Number of transmit descriptors. More...

#define	INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
	Transmit descriptor ring maximum fill level. More...

#define	INTELXL_RX_NUM_DESC 64
	Number of receive descriptors. More...

#define	INTELXL_RX_FILL 16
	Receive descriptor ring fill level. More...

#define	INTELXL_MAX_PKT_LEN ( 9728 - 4 /* CRC */ )
	Maximum packet length (excluding CRC) More...

#define	INTELXL_PFINT_DYN_CTL0 0x038480
	PF Interrupt Zero Dynamic Control Register. More...

#define	INTELXL_INT_DYN_CTL_INTENA 0x00000001UL
	Enable. More...

#define	INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL
	Acknowledge. More...

#define	INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL
	Ignore enable. More...

#define	INTELXL_PFINT_LNKLST0 0x038500
	PF Interrupt Zero Linked List Register. More...

#define	INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) ( (x) << 0 )
	Queue index. More...

#define	INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )
	End of list. More...

#define	INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) ( (x) << 11 )
	Queue type. More...

#define	INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )
	Receive queue. More...

#define	INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )
	Transmit queue. More...

#define	INTELXL_PFINT_ICR0_ENA 0x038800
	PF Interrupt Zero Cause Enablement Register. More...

#define	INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL
	Admin event. More...

#define	INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
	Receive Queue Interrupt Cause Control Register. More...

#define	INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 )
	Queue index. More...

#define	INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )
	End of list. More...

#define	INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 )
	Queue type. More...

#define	INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )
	Receive queue. More...

#define	INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )
	Transmit queue. More...

#define	INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL
	Enable. More...

#define	INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
	Transmit Queue Interrupt Cause Control Register. More...

#define	INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 )
	Queue index. More...

#define	INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )
	End of list. More...

#define	INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 )
	Queue type. More...

#define	INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )
	Receive queue. More...

#define	INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )
	Transmit queue. More...

#define	INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL
	Enable. More...

#define	INTELXL_PFFUNC_RID 0x09c000
	Function Requester ID Information Register. More...

#define	INTELXL_PFFUNC_RID_FUNC_NUM(x) ( ( (x) >> 0 ) & 0x7 )
	Function number. More...

#define	INTELXL_PFLAN_QALLOC 0x1c0400
	PF Queue Allocation Register. More...

#define	INTELXL_PFLAN_QALLOC_FIRSTQ(x) ( ( (x) >> 0 ) & 0x7ff )
	First queue. More...

#define	INTELXL_PFLAN_QALLOC_LASTQ(x) ( ( (x) >> 16 ) & 0x7ff )
	Last queue. More...

#define	INTELXL_PFGEN_PORTNUM 0x1c0480
	PF LAN Port Number Register. More...

#define	INTELXL_PFGEN_PORTNUM_PORT_NUM(x) ( ( (x) >> 0 ) & 0x3 )
	Port number. More...

#define	INTELXL_MSIX_VECTOR 0
	MSI-X interrupt vector. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

static void	intelxl_init_admin (struct intelxl_admin admin, unsigned int base, const struct intelxl_admin_offsets regs)
	Initialise admin queue. More...

static void	intelxl_init_ring (struct intelxl_ring ring, unsigned int count, size_t len, int(context)(struct intelxl_nic *intelxl, physaddr_t address))
	Initialise descriptor ring. More...

int	intelxl_msix_enable (struct intelxl_nic intelxl, struct pci_device pci, unsigned int vector)
	Enable MSI-X dummy interrupt. More...

void	intelxl_msix_disable (struct intelxl_nic intelxl, struct pci_device pci, unsigned int vector)
	Disable MSI-X dummy interrupt. More...

struct intelxl_admin_descriptor *	intelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
	Get next admin command queue descriptor. More...

union intelxl_admin_buffer *	intelxl_admin_command_buffer (struct intelxl_nic *intelxl)
	Get next admin command queue data buffer. More...

int	intelxl_admin_command (struct intelxl_nic *intelxl)
	Issue admin queue command. More...

int	intelxl_admin_clear_pxe (struct intelxl_nic *intelxl)
	Clear PXE mode. More...

int	intelxl_admin_mac_config (struct intelxl_nic *intelxl)
	Set MAC configuration. More...

void	intelxl_poll_admin (struct net_device *netdev)
	Poll admin event queue. More...

int	intelxl_open_admin (struct intelxl_nic *intelxl)
	Open admin queues. More...

void	intelxl_reopen_admin (struct intelxl_nic *intelxl)
	Reopen admin queues (after virtual function reset) More...

void	intelxl_close_admin (struct intelxl_nic *intelxl)
	Close admin queues. More...

int	intelxl_alloc_ring (struct intelxl_nic intelxl, struct intelxl_ring ring)
	Allocate descriptor ring. More...

void	intelxl_free_ring (struct intelxl_nic intelxl, struct intelxl_ring ring)

int	intelxl_create_ring (struct intelxl_nic intelxl, struct intelxl_ring ring)
	Create descriptor ring. More...

void	intelxl_destroy_ring (struct intelxl_nic intelxl, struct intelxl_ring ring)
	Destroy descriptor ring. More...

void	intelxl_empty_rx (struct intelxl_nic *intelxl)
	Discard unused receive I/O buffers. More...

int	intelxl_transmit (struct net_device netdev, struct io_buffer iobuf)
	Transmit packet. More...

void	intelxl_poll (struct net_device *netdev)
	Poll for completed and received packets. More...

Variables
const struct intelxl_admin_offsets	intelxl_admin_offsets
	Admin queue register offsets. More...

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.h.

Macro Definition Documentation

◆ INTELXL_BAR_SIZE

#define INTELXL_BAR_SIZE 0x200000

BAR size.

Definition at line 20 of file intelxl.h.

◆ INTELXL_ALIGN

#define INTELXL_ALIGN 256

Alignment.

No data structure requires greater than 256 byte alignment.

Definition at line 26 of file intelxl.h.

◆ INTELXL_ADMIN_CMD

#define INTELXL_ADMIN_CMD 0x080000

PF Admin Command Queue register block.

Definition at line 36 of file intelxl.h.

◆ INTELXL_ADMIN_EVT

#define INTELXL_ADMIN_EVT 0x080080

PF Admin Event Queue register block.

Definition at line 39 of file intelxl.h.

◆ INTELXL_ADMIN_BAL

#define INTELXL_ADMIN_BAL 0x000

Admin Queue Base Address Low Register (offset)

Definition at line 42 of file intelxl.h.

◆ INTELXL_ADMIN_BAH

#define INTELXL_ADMIN_BAH 0x100

Admin Queue Base Address High Register (offset)

Definition at line 45 of file intelxl.h.

◆ INTELXL_ADMIN_LEN

#define INTELXL_ADMIN_LEN 0x200

Admin Queue Length Register (offset)

Definition at line 48 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_LEN

#define INTELXL_ADMIN_LEN_LEN ( x ) ( (x) << 0 )

Queue length.

Definition at line 49 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_ENABLE

#define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL

Queue enable.

Definition at line 50 of file intelxl.h.

◆ INTELXL_ADMIN_HEAD

#define INTELXL_ADMIN_HEAD 0x300

Admin Queue Head Register (offset)

Definition at line 53 of file intelxl.h.

◆ INTELXL_ADMIN_TAIL

#define INTELXL_ADMIN_TAIL 0x400

Admin Queue Tail Register (offset)

Definition at line 56 of file intelxl.h.

◆ INTELXL_ADMIN_VERSION

#define INTELXL_ADMIN_VERSION 0x0001

Admin queue Get Version command.

Definition at line 87 of file intelxl.h.

◆ INTELXL_ADMIN_DRIVER

#define INTELXL_ADMIN_DRIVER 0x0002

Admin queue Driver Version command.

Definition at line 110 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN

#define INTELXL_ADMIN_SHUTDOWN 0x0003

Admin queue Shutdown command.

Definition at line 135 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN_UNLOADING

#define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01

Driver is unloading.

Definition at line 146 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_READ

#define INTELXL_ADMIN_MAC_READ 0x0107

Admin queue Manage MAC Address Read command.

Definition at line 149 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_READ_VALID_LAN

#define INTELXL_ADMIN_MAC_READ_VALID_LAN 0x10

LAN MAC address is valid.

Definition at line 160 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_WRITE

#define INTELXL_ADMIN_MAC_WRITE 0x0108

Admin queue Manage MAC Address Write command.

Definition at line 175 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE

#define INTELXL_ADMIN_CLEAR_PXE 0x0110

Admin queue Clear PXE Mode command.

Definition at line 192 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE_MAGIC

#define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02

Clear PXE Mode magic value.

Definition at line 203 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH

#define INTELXL_ADMIN_SWITCH 0x0200

Admin queue Get Switch Configuration command.

Definition at line 206 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH_TYPE_VSI

#define INTELXL_ADMIN_SWITCH_TYPE_VSI 19

Virtual Station Inferface element type.

Definition at line 231 of file intelxl.h.

◆ INTELXL_ADMIN_VSI

#define INTELXL_ADMIN_VSI 0x0212

Admin queue Get VSI Parameters command.

Definition at line 256 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC

#define INTELXL_ADMIN_PROMISC 0x0254

Admin queue Set VSI Promiscuous Modes command.

Definition at line 283 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_UNICAST

#define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001

Promiscuous unicast mode.

Definition at line 298 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_MULTICAST

#define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002

Promiscuous multicast mode.

Definition at line 301 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_BROADCAST

#define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004

Promiscuous broadcast mode.

Definition at line 304 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_VLAN

#define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010

Promiscuous VLAN mode.

Definition at line 307 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_CONFIG

#define INTELXL_ADMIN_MAC_CONFIG 0x0603

Admin queue Set MAC Configuration command.

Definition at line 310 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_CONFIG_FL_CRC

#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC 0x04

Append CRC on transmit.

Definition at line 323 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG

#define INTELXL_ADMIN_AUTONEG 0x0605

Admin queue Restart Autonegotiation command.

Definition at line 326 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_RESTART

#define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02

Restart autonegotiation.

Definition at line 337 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_ENABLE

#define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04

Enable link.

Definition at line 340 of file intelxl.h.

◆ INTELXL_ADMIN_LINK

#define INTELXL_ADMIN_LINK 0x0607

Admin queue Get Link Status command.

Definition at line 343 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_NOTIFY

#define INTELXL_ADMIN_LINK_NOTIFY 0x03

Notify driver of link status changes.

Definition at line 362 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_UP

#define INTELXL_ADMIN_LINK_UP 0x01

Link is up.

Definition at line 365 of file intelxl.h.

◆ INTELXL_ADMIN_BUFFER_SIZE

#define INTELXL_ADMIN_BUFFER_SIZE 0x1000

Maximum size of a data buffer.

Definition at line 398 of file intelxl.h.

◆ INTELXL_ADMIN_FL_DD

#define INTELXL_ADMIN_FL_DD 0x0001

Admin descriptor done.

Definition at line 433 of file intelxl.h.

◆ INTELXL_ADMIN_FL_CMP

#define INTELXL_ADMIN_FL_CMP 0x0002

Admin descriptor contains a completion.

Definition at line 436 of file intelxl.h.

◆ INTELXL_ADMIN_FL_ERR

#define INTELXL_ADMIN_FL_ERR 0x0004

Admin descriptor completed in error.

Definition at line 439 of file intelxl.h.

◆ INTELXL_ADMIN_FL_RD

#define INTELXL_ADMIN_FL_RD 0x0400

Admin descriptor uses data buffer for command parameters.

Definition at line 442 of file intelxl.h.

◆ INTELXL_ADMIN_FL_BUF

#define INTELXL_ADMIN_FL_BUF 0x1000

Admin descriptor uses data buffer.

Definition at line 445 of file intelxl.h.

◆ INTELXL_ADMIN_EEXIST

#define INTELXL_ADMIN_EEXIST 13

Error: attempt to create something that already exists.

Definition at line 448 of file intelxl.h.

◆ INTELXL_ADMIN_NUM_DESC

#define INTELXL_ADMIN_NUM_DESC 4

Number of admin queue descriptors.

Definition at line 483 of file intelxl.h.

◆ INTELXL_ADMIN_MAX_WAIT_MS

#define INTELXL_ADMIN_MAX_WAIT_MS 100

Maximum time to wait for an admin request to complete.

Definition at line 486 of file intelxl.h.

◆ INTELXL_ADMIN_API_MAJOR

#define INTELXL_ADMIN_API_MAJOR 1

Admin queue API major version.

Definition at line 489 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXDATA

#define INTELXL_PFCM_LANCTXDATA ( x ) ( 0x10c100 + ( 0x80 * (x) ) )

CMLAN Context Data Register.

Definition at line 499 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL

#define INTELXL_PFCM_LANCTXCTL 0x10c300

CMLAN Context Control Register.

Definition at line 502 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_QUEUE_NUM

#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( x ) ( (x) << 0 )

Queue number.

Definition at line 503 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_SUB_LINE

#define INTELXL_PFCM_LANCTXCTL_SUB_LINE ( x ) ( (x) << 12 )

Sub-line.

Definition at line 506 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE

#define INTELXL_PFCM_LANCTXCTL_TYPE ( x ) ( (x) << 15 )

Queue type.

Definition at line 509 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_RX

#define INTELXL_PFCM_LANCTXCTL_TYPE_RX INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )

RX queue type.

Definition at line 512 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_TX

#define INTELXL_PFCM_LANCTXCTL_TYPE_TX INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )

TX queue type.

Definition at line 514 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE ( x ) ( (x) << 17 )

Op code.

Definition at line 516 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_READ

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )

Read context.

Definition at line 519 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )

Write context.

Definition at line 521 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT

#define INTELXL_PFCM_LANCTXSTAT 0x10c380

CMLAN Context Status Register.

Definition at line 525 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT_DONE

#define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL

Complete.

Definition at line 526 of file intelxl.h.

◆ INTELXL_CTX_TX_FL_NEW

#define INTELXL_CTX_TX_FL_NEW 0x4000

New transmit queue context.

Definition at line 555 of file intelxl.h.

◆ INTELXL_CTX_TX_BASE

#define INTELXL_CTX_TX_BASE ( base ) ( (base) >> 7 )

Transmit queue base address.

Definition at line 558 of file intelxl.h.

◆ INTELXL_CTX_TX_COUNT

#define INTELXL_CTX_TX_COUNT ( count ) ( (count) << 1 )

Transmit queue count.

Definition at line 561 of file intelxl.h.

◆ INTELXL_CTX_TX_QSET

#define INTELXL_CTX_TX_QSET ( qset ) ( (qset) << 4 )

Transmit queue set.

Definition at line 564 of file intelxl.h.

◆ INTELXL_CTX_RX_BASE_COUNT

#define INTELXL_CTX_RX_BASE_COUNT	(	base,
		count
	)	( ( (base) >> 7 ) \| ( ( ( uint64_t ) (count) ) << 57 ) )

Receive queue base address and queue count.

Definition at line 587 of file intelxl.h.

◆ INTELXL_CTX_RX_LEN

#define INTELXL_CTX_RX_LEN ( len ) ( (len) >> 1 )

Receive queue data buffer length.

Definition at line 591 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_DSIZE

#define INTELXL_CTX_RX_FL_DSIZE 0x10

Use 32-byte receive descriptors.

Definition at line 594 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_CRCSTRIP

#define INTELXL_CTX_RX_FL_CRCSTRIP 0x20

Strip CRC from received packets.

Definition at line 597 of file intelxl.h.

◆ INTELXL_CTX_RX_MFS

#define INTELXL_CTX_RX_MFS ( mfs ) ( (mfs) >> 2 )

Receive queue maximum frame size.

Definition at line 600 of file intelxl.h.

◆ INTELXL_CTX_MAX_WAIT_MS

#define INTELXL_CTX_MAX_WAIT_MS 100

Maximum time to wait for a context operation to complete.

Definition at line 603 of file intelxl.h.

◆ INTELXL_QUEUE_ENABLE_DELAY_US

#define INTELXL_QUEUE_ENABLE_DELAY_US 20

Time to wait for a queue to become enabled.

Definition at line 606 of file intelxl.h.

◆ INTELXL_QUEUE_PRE_DISABLE_DELAY_US

#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400

Time to wait for a transmit queue to become pre-disabled.

Definition at line 609 of file intelxl.h.

◆ INTELXL_QUEUE_DISABLE_MAX_WAIT_MS

#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000

Maximum time to wait for a queue to become disabled.

Definition at line 612 of file intelxl.h.

◆ INTELXL_QTX_HEAD

#define INTELXL_QTX_HEAD ( x ) ( 0x0e4000 + ( 0x4 * (x) ) )

Global Transmit Queue Head register.

Definition at line 622 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS ( x ) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )

Global Transmit Pre Queue Disable register.

Definition at line 625 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_QINDX

#define INTELXL_GLLAN_TXPRE_QDIS_QINDX ( x ) ( (x) << 0 )

Queue index.

Definition at line 626 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS 0x40000000UL

Set disable.

Definition at line 629 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS 0x80000000UL

Clear disable.

Definition at line 631 of file intelxl.h.

◆ INTELXL_QTX

#define INTELXL_QTX ( x ) ( 0x100000 + ( 0x4 * (x) ) )

Global Transmit Queue register block.

Definition at line 635 of file intelxl.h.

◆ INTELXL_QRX

#define INTELXL_QRX ( x ) ( 0x120000 + ( 0x4 * (x) ) )

Global Receive Queue register block.

Definition at line 638 of file intelxl.h.

◆ INTELXL_QXX_ENA

#define INTELXL_QXX_ENA 0x0000

Queue Enable Register (offset)

Definition at line 641 of file intelxl.h.

◆ INTELXL_QXX_ENA_REQ

#define INTELXL_QXX_ENA_REQ 0x00000001UL

Enable request.

Definition at line 642 of file intelxl.h.

◆ INTELXL_QXX_ENA_STAT

#define INTELXL_QXX_ENA_STAT 0x00000004UL

Enabled status.

Definition at line 643 of file intelxl.h.

◆ INTELXL_QXX_CTL

#define INTELXL_QXX_CTL 0x4000

Queue Control Register (offset)

Definition at line 646 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q

#define INTELXL_QXX_CTL_PFVF_Q ( x ) ( (x) << 0 )

PF/VF queue.

Definition at line 647 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q_PF

#define INTELXL_QXX_CTL_PFVF_Q_PF INTELXL_QXX_CTL_PFVF_Q ( 0x2 )

PF queue.

Definition at line 648 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_PF_INDX

#define INTELXL_QXX_CTL_PFVF_PF_INDX ( x ) ( (x) << 2 )

PF index.

Definition at line 650 of file intelxl.h.

◆ INTELXL_QXX_TAIL

#define INTELXL_QXX_TAIL 0x8000

Queue Tail Pointer Register (offset)

Definition at line 653 of file intelxl.h.

◆ INTELXL_TX_DATA_DTYP

#define INTELXL_TX_DATA_DTYP 0x0

Transmit data descriptor type.

Definition at line 666 of file intelxl.h.

◆ INTELXL_TX_DATA_EOP

#define INTELXL_TX_DATA_EOP 0x10

Transmit data descriptor end of packet.

Definition at line 669 of file intelxl.h.

◆ INTELXL_TX_DATA_RS

#define INTELXL_TX_DATA_RS 0x20

Transmit data descriptor report status.

Definition at line 672 of file intelxl.h.

◆ INTELXL_TX_DATA_JFDI

#define INTELXL_TX_DATA_JFDI 0x40

Transmit data descriptor pretty please.

This bit is completely missing from older versions of the XL710 datasheet. Later versions describe it innocuously as "reserved, must be 1". Without this bit, everything will appear to work (up to and including the port "transmit good octets" counter), but no packet will actually be sent.

Definition at line 682 of file intelxl.h.

◆ INTELXL_TX_DATA_LEN

#define INTELXL_TX_DATA_LEN ( len ) ( (len) << 2 )

Transmit data descriptor length.

Definition at line 685 of file intelxl.h.

◆ INTELXL_TX_WB_FL_DD

#define INTELXL_TX_WB_FL_DD 0x01

Transmit writeback descriptor complete.

Definition at line 698 of file intelxl.h.

◆ INTELXL_RX_WB_FL_DD

#define INTELXL_RX_WB_FL_DD 0x00000001UL

Receive writeback descriptor complete.

Definition at line 735 of file intelxl.h.

◆ INTELXL_RX_WB_FL_VLAN

#define INTELXL_RX_WB_FL_VLAN 0x00000004UL

Receive writeback descriptor VLAN tag present.

Definition at line 738 of file intelxl.h.

◆ INTELXL_RX_WB_FL_RXE

#define INTELXL_RX_WB_FL_RXE 0x00080000UL

Receive writeback descriptor error.

Definition at line 741 of file intelxl.h.

◆ INTELXL_RX_WB_LEN

#define INTELXL_RX_WB_LEN ( len ) ( ( (len) >> 6 ) & 0x3fff )

Receive writeback descriptor length.

Definition at line 744 of file intelxl.h.

◆ INTELXL_TX_NUM_DESC

#define INTELXL_TX_NUM_DESC 64

Number of transmit descriptors.

Chosen to exceed the receive ring fill level, in order to avoid running out of transmit descriptors when sending TCP ACKs.

Definition at line 808 of file intelxl.h.

◆ INTELXL_TX_FILL

#define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 811 of file intelxl.h.

◆ INTELXL_RX_NUM_DESC

#define INTELXL_RX_NUM_DESC 64

Number of receive descriptors.

Must be a multiple of 32 and greater than or equal to 64.

Definition at line 817 of file intelxl.h.

◆ INTELXL_RX_FILL

#define INTELXL_RX_FILL 16

Receive descriptor ring fill level.

Must be a multiple of 8 and greater than 8.

Definition at line 823 of file intelxl.h.

◆ INTELXL_MAX_PKT_LEN

#define INTELXL_MAX_PKT_LEN ( 9728 - 4 /* CRC */ )

Maximum packet length (excluding CRC)

Definition at line 826 of file intelxl.h.

◆ INTELXL_PFINT_DYN_CTL0

#define INTELXL_PFINT_DYN_CTL0 0x038480

PF Interrupt Zero Dynamic Control Register.

Definition at line 836 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA

#define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL

Enable.

Definition at line 837 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_CLEARPBA

#define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL

Acknowledge.

Definition at line 838 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA_MASK

#define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL

Ignore enable.

Definition at line 839 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0

#define INTELXL_PFINT_LNKLST0 0x038500

PF Interrupt Zero Linked List Register.

Definition at line 842 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( x ) ( (x) << 0 )

Queue index.

Definition at line 843 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )

End of list.

Definition at line 846 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( x ) ( (x) << 11 )

Queue type.

Definition at line 848 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 851 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 853 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA

#define INTELXL_PFINT_ICR0_ENA 0x038800

PF Interrupt Zero Cause Enablement Register.

Definition at line 857 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA_ADMINQ

#define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL

Admin event.

Definition at line 858 of file intelxl.h.

◆ INTELXL_QINT_RQCTL

#define INTELXL_QINT_RQCTL ( x ) ( 0x03a000 + ( 0x4 * (x) ) )

Receive Queue Interrupt Cause Control Register.

Definition at line 861 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX

#define INTELXL_QINT_RQCTL_NEXTQ_INDX ( x ) ( (x) << 16 )

Queue index.

Definition at line 862 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 863 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE ( x ) ( (x) << 27 )

Queue type.

Definition at line 865 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 866 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 868 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_CAUSE_ENA

#define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL

Enable.

Definition at line 870 of file intelxl.h.

◆ INTELXL_QINT_TQCTL

#define INTELXL_QINT_TQCTL ( x ) ( 0x03c000 + ( 0x4 * (x) ) )

Transmit Queue Interrupt Cause Control Register.

Definition at line 873 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX

#define INTELXL_QINT_TQCTL_NEXTQ_INDX ( x ) ( (x) << 16 )

Queue index.

Definition at line 874 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 875 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE ( x ) ( (x) << 27 )

Queue type.

Definition at line 877 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 878 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 880 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_CAUSE_ENA

#define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL

Enable.

Definition at line 882 of file intelxl.h.

◆ INTELXL_PFFUNC_RID

#define INTELXL_PFFUNC_RID 0x09c000

Function Requester ID Information Register.

Definition at line 885 of file intelxl.h.

◆ INTELXL_PFFUNC_RID_FUNC_NUM

#define INTELXL_PFFUNC_RID_FUNC_NUM ( x ) ( ( (x) >> 0 ) & 0x7 )

Function number.

Definition at line 886 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC

#define INTELXL_PFLAN_QALLOC 0x1c0400

PF Queue Allocation Register.

Definition at line 891 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_FIRSTQ

#define INTELXL_PFLAN_QALLOC_FIRSTQ ( x ) ( ( (x) >> 0 ) & 0x7ff )

First queue.

Definition at line 892 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_LASTQ

#define INTELXL_PFLAN_QALLOC_LASTQ ( x ) ( ( (x) >> 16 ) & 0x7ff )

Last queue.

Definition at line 895 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM

#define INTELXL_PFGEN_PORTNUM 0x1c0480

PF LAN Port Number Register.

Definition at line 900 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM_PORT_NUM

#define INTELXL_PFGEN_PORTNUM_PORT_NUM ( x ) ( ( (x) >> 0 ) & 0x3 )

Port number.

Definition at line 901 of file intelxl.h.

◆ INTELXL_MSIX_VECTOR

#define INTELXL_MSIX_VECTOR 0

MSI-X interrupt vector.

Definition at line 916 of file intelxl.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

◆ intelxl_init_admin()

static void intelxl_init_admin	(	struct intelxl_admin *	admin,
		unsigned int	base,
		const struct intelxl_admin_offsets *	regs
	)

inlinestatic

Initialise admin queue.

Parameters

admin	Admin queue
base	Register block base
regs	Register offsets

Definition at line 475 of file intelxl.h.

                                                                 {
 
         admin->base = base;
         admin->regs = regs;
 }

References base, intelxl_admin::base, regs, and intelxl_admin::regs.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_init_ring()

static void intelxl_init_ring	(	struct intelxl_ring *	ring,
		unsigned int	count,
		size_t	len,
		int()(struct intelxl_nic intelxl, physaddr_t address)	context
	)

inlinestatic

Initialise descriptor ring.

Parameters

ring	Descriptor ring
count	Number of descriptors
len	Length of a single descriptor
context	Method to program queue context

Definition at line 795 of file intelxl.h.

895 {

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_msix_enable()

int intelxl_msix_enable	(	struct intelxl_nic *	intelxl,
		struct pci_device *	pci,
		unsigned int	vector
	)

Enable MSI-X dummy interrupt.

Parameters

intelxl	Intel device
pci	PCI device
vector	MSI-X vector

Return values

rc	Return status code

Definition at line 62 of file intelxl.c.

                                                                         {
         int rc;
 
         /* Map dummy target location */
         if ( ( rc = dma_map ( intelxl->dma, &intelxl->msix.map,
                               virt_to_phys ( &intelxl->msix.msg ),
                               sizeof ( intelxl->msix.msg ), DMA_RX ) ) != 0 ) {
                 DBGC ( intelxl, "INTELXL %p could not map MSI-X target: %s\n",
                        intelxl, strerror ( rc ) );
                 goto err_map;
         }
 
         /* Enable MSI-X capability */
         if ( ( rc = pci_msix_enable ( pci, &intelxl->msix.cap ) ) != 0 ) {
                 DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
                        intelxl, strerror ( rc ) );
                 goto err_enable;
         }
 
         /* Configure interrupt to write to dummy location */
         pci_msix_map ( &intelxl->msix.cap, vector,
                        dma ( &intelxl->msix.map, &intelxl->msix.msg ), 0 );
 
         /* Enable dummy interrupt */
         pci_msix_unmask ( &intelxl->msix.cap, vector );
 
         return 0;
 
         pci_msix_disable ( pci, &intelxl->msix.cap );
  err_enable:
         dma_unmap ( &intelxl->msix.map );
  err_map:
         return rc;
 }

References intelxl_msix::cap, DBGC, dma(), intelxl_nic::dma, DMA_RX, dma_unmap(), intelxl_msix::map, intelxl_msix::msg, intelxl_nic::msix, pci_msix_disable(), pci_msix_enable(), pci_msix_map(), pci_msix_unmask(), rc, strerror(), vector, and virt_to_phys().

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable	(	struct intelxl_nic *	intelxl,
		struct pci_device *	pci,
		unsigned int	vector
	)

Disable MSI-X dummy interrupt.

Parameters

intelxl	Intel device
pci	PCI device
vector	MSI-X vector

Definition at line 105 of file intelxl.c.

                                                                           {
 
         /* Disable dummy interrupts */
         pci_msix_mask ( &intelxl->msix.cap, vector );
 
         /* Disable MSI-X capability */
         pci_msix_disable ( pci, &intelxl->msix.cap );
 
         /* Unmap dummy target location */
         dma_unmap ( &intelxl->msix.map );
 }

References intelxl_msix::cap, dma_unmap(), intelxl_msix::map, intelxl_nic::msix, pci_msix_disable(), pci_msix_mask(), and vector.

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic * intelxl )

Get next admin command queue descriptor.

Parameters

intelxl Intel device

Return values

cmd	Command descriptor

Definition at line 239 of file intelxl.c.

                                                                  {
         struct intelxl_admin *admin = &intelxl->command;
         struct intelxl_admin_descriptor *cmd;
 
         /* Get and initialise next descriptor */
         cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
         memset ( cmd, 0, sizeof ( *cmd ) );
         return cmd;
 }

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_descriptor(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), and intelxlvf_admin_command_descriptor().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic * intelxl )

Get next admin command queue data buffer.

Parameters

intelxl Intel device

Return values

buf	Data buffer

Definition at line 256 of file intelxl.c.

                                                              {
         struct intelxl_admin *admin = &intelxl->command;
         union intelxl_admin_buffer *buf;
 
         /* Get next data buffer */
         buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
         memset ( buf, 0, sizeof ( *buf ) );
         return buf;
 }

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_buffer(), intelxl_admin_driver(), intelxl_admin_mac_read(), intelxl_admin_switch(), intelxl_admin_vsi(), and intelxlvf_admin_command_buffer().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic * intelxl )

Issue admin queue command.

Parameters

intelxl Intel device

Return values

rc	Return status code

Definition at line 295 of file intelxl.c.

                                                           {
         struct intelxl_admin *admin = &intelxl->command;
         const struct intelxl_admin_offsets *regs = admin->regs;
         void *admin_regs = ( intelxl->regs + admin->base );
         struct intelxl_admin_descriptor *cmd;
         union intelxl_admin_buffer *buf;
         uint64_t address;
         uint32_t cookie;
         uint16_t silence;
         unsigned int index;
         unsigned int tail;
         unsigned int i;
         int rc;
 
         /* Get next queue entry */
         index = admin->index++;
         tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
         cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
         buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
         DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
                 intelxl, index, le16_to_cpu ( cmd->opcode ) );
         if ( cmd->cookie )
                 DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
         DBGC2 ( intelxl, ":\n" );
 
         /* Allow expected errors to be silenced */
         silence = cmd->ret;
         cmd->ret = 0;
 
         /* Sanity checks */
         assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
         assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
         assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
 
         /* Populate data buffer address if applicable */
         if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                 address = dma ( &admin->map, buf );
                 cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
                 cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
         }
 
         /* Populate cookie, if not being (ab)used for VF opcode */
         if ( ! cmd->cookie )
                 cmd->cookie = cpu_to_le32 ( index );
 
         /* Record cookie */
         cookie = cmd->cookie;
 
         /* Post command descriptor */
         DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
         if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
                 DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
                             le16_to_cpu ( cmd->len ) );
         }
         wmb();
         writel ( tail, admin_regs + regs->tail );
 
         /* Wait for completion */
         for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
 
                 /* If response is not complete, delay 1ms and retry */
                 if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
                         mdelay ( 1 );
                         continue;
                 }
                 DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
                         intelxl, index );
                 DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
                             sizeof ( *cmd ) );
                 if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                         DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
                                     le16_to_cpu ( cmd->len ) );
                 }
 
                 /* Check for cookie mismatch */
                 if ( cmd->cookie != cookie ) {
                         DBGC ( intelxl, "INTELXL %p admin command %#x bad "
                                "cookie %#x\n", intelxl, index,
                                le32_to_cpu ( cmd->cookie ) );
                         rc = -EPROTO;
                         goto err;
                 }
 
                 /* Check for unexpected errors */
                 if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
                         DBGC ( intelxl, "INTELXL %p admin command %#x error "
                                "%d\n", intelxl, index,
                                le16_to_cpu ( cmd->ret ) );
                         rc = -EIO;
                         goto err;
                 }
 
                 /* Success */
                 return 0;
         }
 
         rc = -ETIMEDOUT;
         DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
                intelxl, index );
  err:
         DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
         return rc;
 }

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, dma(), EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_FL_RD, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin::map, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, virt_to_phys(), wmb(), and writel().

Referenced by ice_admin_add_txq(), ice_admin_autoneg(), ice_admin_disable_txq(), ice_admin_link(), ice_admin_mac_read(), ice_admin_mac_write(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ice_admin_version(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), intelxlvf_admin_request_qps(), and intelxlvf_reset_admin().

◆ intelxl_admin_clear_pxe()

int intelxl_admin_clear_pxe ( struct intelxl_nic * intelxl )

Clear PXE mode.

Parameters

intelxl Intel device

Return values

rc	Return status code

Definition at line 578 of file intelxl.c.

                                                             {
         struct intelxl_admin_descriptor *cmd;
         struct intelxl_admin_clear_pxe_params *pxe;
         int rc;
 
         /* Populate descriptor */
         cmd = intelxl_admin_command_descriptor ( intelxl );
         cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_CLEAR_PXE );
         cmd->ret = cpu_to_le16 ( INTELXL_ADMIN_EEXIST );
         pxe = &cmd->params.pxe;
         pxe->magic = INTELXL_ADMIN_CLEAR_PXE_MAGIC;
 
         /* Issue command */
         if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
                 return rc;
 
         /* Check for expected errors */
         if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
                 DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
                        intelxl );
                 return 0;
         }
 
         return 0;
 }

References cmd, cpu_to_le16, DBGC, INTELXL_ADMIN_CLEAR_PXE, INTELXL_ADMIN_CLEAR_PXE_MAGIC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_EEXIST, intelxl_admin_clear_pxe_params::magic, and rc.

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_admin_mac_config()

int intelxl_admin_mac_config ( struct intelxl_nic * intelxl )

Set MAC configuration.

Parameters

intelxl Intel device

Return values

rc	Return status code

Definition at line 729 of file intelxl.c.

                                                              {
         struct intelxl_admin_descriptor *cmd;
         struct intelxl_admin_mac_config_params *config;
         int rc;
 
         /* Populate descriptor */
         cmd = intelxl_admin_command_descriptor ( intelxl );
         cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_CONFIG );
         config = &cmd->params.mac_config;
         config->mfs = cpu_to_le16 ( intelxl->mfs );
         config->flags = INTELXL_ADMIN_MAC_CONFIG_FL_CRC;
 
         /* Issue command */
         if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
                 return rc;
 
         return 0;
 }

References cmd, cpu_to_le16, intelxl_admin_mac_config_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_CONFIG, INTELXL_ADMIN_MAC_CONFIG_FL_CRC, intelxl_admin_mac_config_params::mfs, intelxl_nic::mfs, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device * netdev )

Poll admin event queue.

Parameters

netdev Network device

Definition at line 853 of file intelxl.c.

                                                       {
         struct intelxl_nic *intelxl = netdev->priv;
         struct intelxl_admin *admin = &intelxl->event;
         struct intelxl_admin_descriptor *evt;
         union intelxl_admin_buffer *buf;
 
         /* Check for events */
         while ( 1 ) {
 
                 /* Get next event descriptor and data buffer */
                 evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
                 buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
 
                 /* Stop if descriptor is not yet completed */
                 if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
                         return;
                 DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
                         intelxl, admin->index );
                 DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
                             sizeof ( *evt ) );
                 if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
                         DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
                                     le16_to_cpu ( evt->len ) );
                 }
 
                 /* Handle event */
                 intelxl->handle ( netdev, evt, buf );
 
                 /* Reset descriptor and refill queue */
                 intelxl_admin_event_init ( intelxl, admin->index );
                 admin->index++;
                 intelxl_refill_admin ( intelxl );
         }
 }

References intelxl_admin::buf, cpu_to_le16, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_nic::handle, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_NUM_DESC, intelxl_refill_admin(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, net_device::priv, and virt_to_phys().

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic * intelxl )

Open admin queues.

Parameters

intelxl Intel device

Return values

rc	Return status code

Definition at line 894 of file intelxl.c.

                                                        {
         int rc;
 
         /* Allocate admin event queue */
         if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
                 goto err_alloc_event;
 
         /* Allocate admin command queue */
         if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
                 goto err_alloc_command;
 
         /* (Re)open admin queues */
         intelxl_reopen_admin ( intelxl );
 
         return 0;
 
         intelxl_disable_admin ( intelxl, &intelxl->command );
         intelxl_disable_admin ( intelxl, &intelxl->event );
         intelxl_free_admin ( intelxl, &intelxl->command );
  err_alloc_command:
         intelxl_free_admin ( intelxl, &intelxl->event );
  err_alloc_event:
         return rc;
 }

References intelxl_nic::command, intelxl_nic::event, intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic * intelxl )

Reopen admin queues (after virtual function reset)

Parameters

intelxl Intel device

Definition at line 924 of file intelxl.c.

                                                           {
         unsigned int i;
 
         /* Enable admin event queue */
         intelxl_enable_admin ( intelxl, &intelxl->event );
 
         /* Enable admin command queue */
         intelxl_enable_admin ( intelxl, &intelxl->command );
 
         /* Initialise all admin event queue descriptors */
         for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
                 intelxl_admin_event_init ( intelxl, i );
 
         /* Post all descriptors to event queue */
         intelxl_refill_admin ( intelxl );
 }

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_wait().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic * intelxl )

Close admin queues.

Parameters

intelxl Intel device

Definition at line 946 of file intelxl.c.

                                                          {
 
         /* Shut down admin queues */
         intelxl_admin_shutdown ( intelxl );
 
         /* Disable admin queues */
         intelxl_disable_admin ( intelxl, &intelxl->command );
         intelxl_disable_admin ( intelxl, &intelxl->event );
 
         /* Free admin queues */
         intelxl_free_admin ( intelxl, &intelxl->command );
         intelxl_free_admin ( intelxl, &intelxl->event );
 }

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring	(	struct intelxl_nic *	intelxl,
		struct intelxl_ring *	ring
	)

Allocate descriptor ring.

Parameters

intelxl	Intel device
ring	Descriptor ring

Return values

rc	Return status code

Definition at line 974 of file intelxl.c.

                                                      {
         int rc;
 
         /* Allocate descriptor ring */
         ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
                                      INTELXL_ALIGN );
         if ( ! ring->desc.raw ) {
                 rc = -ENOMEM;
                 goto err_alloc;
         }
 
         /* Initialise descriptor ring */
         memset ( ring->desc.raw, 0, ring->len );
 
         /* Reset tail pointer */
         writel ( 0, ( intelxl->regs + ring->tail ) );
 
         /* Reset counters */
         ring->prod = 0;
         ring->cons = 0;
 
         DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
                intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
                ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
 
         return 0;
 
         dma_free ( &ring->map, ring->desc.raw, ring->len );
  err_alloc:
         return rc;
 }

References intelxl_ring::cons, DBGC, intelxl_ring::desc, intelxl_nic::dma, dma_alloc(), dma_free(), ENOMEM, INTELXL_ALIGN, intelxl_ring::len, intelxl_ring::map, memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_nic::regs, intelxl_ring::tail, virt_to_phys(), and writel().

Referenced by ice_create_tx(), intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring	(	struct intelxl_nic *	intelxl,
		struct intelxl_ring *	ring
	)

◆ intelxl_create_ring()

int intelxl_create_ring	(	struct intelxl_nic *	intelxl,
		struct intelxl_ring *	ring
	)

Create descriptor ring.

Parameters

intelxl	Intel device
ring	Descriptor ring

Return values

rc	Return status code

Definition at line 1283 of file intelxl.c.

                                                       {
         physaddr_t address;
         int rc;
 
         /* Allocate descriptor ring */
         if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
                 goto err_alloc;
 
         /* Program queue context */
         address = dma ( &ring->map, ring->desc.raw );
         if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
                 goto err_context;
 
         /* Enable ring */
         if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
                 goto err_enable;
 
         return 0;
 
         intelxl_disable_ring ( intelxl, ring );
  err_enable:
  err_context:
         intelxl_free_ring ( intelxl, ring );
  err_alloc:
         return rc;
 }

References address, intelxl_ring::context, intelxl_ring::desc, dma(), intelxl_alloc_ring(), intelxl_disable_ring(), intelxl_enable_ring(), intelxl_free_ring(), intelxl_ring::map, intelxl_ring::raw, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_destroy_ring()

void intelxl_destroy_ring	(	struct intelxl_nic *	intelxl,
		struct intelxl_ring *	ring
	)

Destroy descriptor ring.

Parameters

intelxl	Intel device
ring	Descriptor ring

Definition at line 1317 of file intelxl.c.

                                                         {
         int rc;
 
         /* Disable ring */
         if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
                 /* Leak memory; there's nothing else we can do */
                 return;
         }
 
         /* Free descriptor ring */
         intelxl_free_ring ( intelxl, ring );
 }

References intelxl_disable_ring(), intelxl_free_ring(), and rc.

Referenced by ice_close(), ice_open(), intelxl_close(), and intelxl_open().

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic * intelxl )

Discard unused receive I/O buffers.

Parameters

intelxl Intel device

Definition at line 1384 of file intelxl.c.

                                                       {
         unsigned int i;
 
         /* Discard any unused receive buffers */
         for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
                 if ( intelxl->rx_iobuf[i] )
                         free_rx_iob ( intelxl->rx_iobuf[i] );
                 intelxl->rx_iobuf[i] = NULL;
         }
 }

References free_rx_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by ice_close(), intelxl_close(), and intelxlvf_close().

◆ intelxl_transmit()

int intelxl_transmit	(	struct net_device *	netdev,
		struct io_buffer *	iobuf
	)

Transmit packet.

Parameters

netdev	Network device
iobuf	I/O buffer

Return values

rc	Return status code

Definition at line 1510 of file intelxl.c.

                                                                             {
         struct intelxl_nic *intelxl = netdev->priv;
         struct intelxl_tx_data_descriptor *tx;
         unsigned int tx_idx;
         unsigned int tx_tail;
         size_t len;
 
         /* Get next transmit descriptor */
         if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
                 DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
                        intelxl );
                 return -ENOBUFS;
         }
         tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
         tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
         tx = &intelxl->tx.desc.tx[tx_idx].data;
 
         /* Populate transmit descriptor */
         len = iob_len ( iobuf );
         tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
         tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
         tx->flags = cpu_to_le32 ( INTELXL_TX_DATA_DTYP | INTELXL_TX_DATA_EOP |
                                   INTELXL_TX_DATA_RS | INTELXL_TX_DATA_JFDI );
         wmb();
 
         /* Notify card that there are packets ready to transmit */
         writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
 
         DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
                 intelxl, tx_idx, virt_to_phys ( iobuf->data ),
                 ( virt_to_phys ( iobuf->data ) + len ) );
         return 0;
 }

References intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_dma(), iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, virt_to_phys(), wmb(), and writel().

◆ intelxl_poll()

void intelxl_poll ( struct net_device * netdev )

Poll for completed and received packets.

Parameters

netdev Network device

Definition at line 1630 of file intelxl.c.

                                                 {
         struct intelxl_nic *intelxl = netdev->priv;
 
         /* Poll for completed packets */
         intelxl_poll_tx ( netdev );
 
         /* Poll for received packets */
         intelxl_poll_rx ( netdev );
 
         /* Poll for admin events */
         intelxl_poll_admin ( netdev );
 
         /* Refill RX ring */
         intelxl_refill_rx ( intelxl );
 
         /* Rearm interrupt, since otherwise receive descriptors will
          * be written back only after a complete cacheline (four
          * packets) have been received.
          *
          * There is unfortunately no efficient way to determine
          * whether or not rearming the interrupt is necessary.  If we
          * are running inside a hypervisor (e.g. using a VF or PF as a
          * passed-through PCI device), then the MSI-X write is
          * redirected by the hypervisor to the real host APIC and the
          * host ISR then raises an interrupt within the guest.  We
          * therefore cannot poll the nominal MSI-X target location to
          * watch for the value being written.  We could read from the
          * INT_DYN_CTL register, but this is even less efficient than
          * just unconditionally rearming the interrupt.
          */
         writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
 }

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

Variable Documentation

◆ intelxl_admin_offsets

const struct intelxl_admin_offsets intelxl_admin_offsets

Admin queue register offsets.

Definition at line 126 of file intelxl.c.

Data Structures

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ INTELXL_BAR_SIZE

◆ INTELXL_ALIGN

◆ INTELXL_ADMIN_CMD

◆ INTELXL_ADMIN_EVT

◆ INTELXL_ADMIN_BAL

◆ INTELXL_ADMIN_BAH

◆ INTELXL_ADMIN_LEN

◆ INTELXL_ADMIN_LEN_LEN

◆ INTELXL_ADMIN_LEN_ENABLE

◆ INTELXL_ADMIN_HEAD

◆ INTELXL_ADMIN_TAIL

◆ INTELXL_ADMIN_VERSION

◆ INTELXL_ADMIN_DRIVER

◆ INTELXL_ADMIN_SHUTDOWN

◆ INTELXL_ADMIN_SHUTDOWN_UNLOADING

◆ INTELXL_ADMIN_MAC_READ

◆ INTELXL_ADMIN_MAC_READ_VALID_LAN

◆ INTELXL_ADMIN_MAC_WRITE

◆ INTELXL_ADMIN_CLEAR_PXE

◆ INTELXL_ADMIN_CLEAR_PXE_MAGIC

◆ INTELXL_ADMIN_SWITCH

◆ INTELXL_ADMIN_SWITCH_TYPE_VSI

◆ INTELXL_ADMIN_VSI

◆ INTELXL_ADMIN_PROMISC

◆ INTELXL_ADMIN_PROMISC_FL_UNICAST

◆ INTELXL_ADMIN_PROMISC_FL_MULTICAST

◆ INTELXL_ADMIN_PROMISC_FL_BROADCAST

◆ INTELXL_ADMIN_PROMISC_FL_VLAN

◆ INTELXL_ADMIN_MAC_CONFIG

◆ INTELXL_ADMIN_MAC_CONFIG_FL_CRC

◆ INTELXL_ADMIN_AUTONEG

◆ INTELXL_ADMIN_AUTONEG_FL_RESTART

◆ INTELXL_ADMIN_AUTONEG_FL_ENABLE

◆ INTELXL_ADMIN_LINK

◆ INTELXL_ADMIN_LINK_NOTIFY

◆ INTELXL_ADMIN_LINK_UP

◆ INTELXL_ADMIN_BUFFER_SIZE

◆ INTELXL_ADMIN_FL_DD

◆ INTELXL_ADMIN_FL_CMP

◆ INTELXL_ADMIN_FL_ERR

◆ INTELXL_ADMIN_FL_RD

◆ INTELXL_ADMIN_FL_BUF

◆ INTELXL_ADMIN_EEXIST

◆ INTELXL_ADMIN_NUM_DESC

◆ INTELXL_ADMIN_MAX_WAIT_MS

◆ INTELXL_ADMIN_API_MAJOR

◆ INTELXL_PFCM_LANCTXDATA

◆ INTELXL_PFCM_LANCTXCTL

◆ INTELXL_PFCM_LANCTXCTL_QUEUE_NUM

◆ INTELXL_PFCM_LANCTXCTL_SUB_LINE

◆ INTELXL_PFCM_LANCTXCTL_TYPE

◆ INTELXL_PFCM_LANCTXCTL_TYPE_RX

◆ INTELXL_PFCM_LANCTXCTL_TYPE_TX

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_READ

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE

◆ INTELXL_PFCM_LANCTXSTAT

◆ INTELXL_PFCM_LANCTXSTAT_DONE

◆ INTELXL_CTX_TX_FL_NEW

◆ INTELXL_CTX_TX_BASE

◆ INTELXL_CTX_TX_COUNT

◆ INTELXL_CTX_TX_QSET

◆ INTELXL_CTX_RX_BASE_COUNT

◆ INTELXL_CTX_RX_LEN

◆ INTELXL_CTX_RX_FL_DSIZE

◆ INTELXL_CTX_RX_FL_CRCSTRIP

◆ INTELXL_CTX_RX_MFS

◆ INTELXL_CTX_MAX_WAIT_MS

◆ INTELXL_QUEUE_ENABLE_DELAY_US

◆ INTELXL_QUEUE_PRE_DISABLE_DELAY_US

◆ INTELXL_QUEUE_DISABLE_MAX_WAIT_MS

◆ INTELXL_QTX_HEAD

◆ INTELXL_GLLAN_TXPRE_QDIS

◆ INTELXL_GLLAN_TXPRE_QDIS_QINDX