iPXE
Data Structures | Macros | Functions | Variables
intelxl.h File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/pcimsix.h>
#include <ipxe/dma.h>

Go to the source code of this file.

Data Structures

struct  intelxl_admin_offsets
 Admin queue register offsets. More...
 
struct  intelxl_admin_buffer_params
 Admin queue data buffer command parameters. More...
 
struct  intelxl_admin_version
 Admin queue version number. More...
 
struct  intelxl_admin_version_params
 Admin queue Get Version command parameters. More...
 
struct  intelxl_admin_driver_params
 Admin queue Driver Version command parameters. More...
 
struct  intelxl_admin_driver_buffer
 Admin queue Driver Version data buffer. More...
 
struct  intelxl_admin_shutdown_params
 Admin queue Shutdown command parameters. More...
 
struct  intelxl_admin_mac_read_params
 Admin queue Manage MAC Address Read command parameters. More...
 
struct  intelxl_admin_mac_read_buffer
 Admin queue Manage MAC Address Read data buffer. More...
 
struct  intelxl_admin_mac_write_params
 Admin queue Manage MAC Address Write command parameters. More...
 
struct  intelxl_admin_clear_pxe_params
 Admin queue Clear PXE Mode command parameters. More...
 
struct  intelxl_admin_switch_config
 Switching element configuration. More...
 
struct  intelxl_admin_switch_params
 Admin queue Get Switch Configuration command parameters. More...
 
struct  intelxl_admin_switch_buffer
 Admin queue Get Switch Configuration data buffer. More...
 
struct  intelxl_admin_vsi_params
 Admin queue Get VSI Parameters command parameters. More...
 
struct  intelxl_admin_vsi_buffer
 Admin queue Get VSI Parameters data buffer. More...
 
struct  intelxl_admin_promisc_params
 Admin queue Set VSI Promiscuous Modes command parameters. More...
 
struct  intelxl_admin_mac_config_params
 Admin queue Set MAC Configuration command parameters. More...
 
struct  intelxl_admin_autoneg_params
 Admin queue Restart Autonegotiation command parameters. More...
 
struct  intelxl_admin_link_params
 Admin queue Get Link Status command parameters. More...
 
union  intelxl_admin_params
 Admin queue command parameters. More...
 
union  intelxl_admin_buffer
 Admin queue data buffer. More...
 
struct  intelxl_admin_descriptor
 Admin queue descriptor. More...
 
struct  intelxl_admin
 Admin queue. More...
 
struct  intelxl_context_line
 Queue context line. More...
 
struct  intelxl_context_tx
 Transmit queue context. More...
 
struct  intelxl_context_rx
 Receive queue context. More...
 
struct  intelxl_tx_data_descriptor
 Transmit data descriptor. More...
 
struct  intelxl_tx_writeback_descriptor
 Transmit writeback descriptor. More...
 
union  intelxl_tx_descriptor
 Transmit descriptor. More...
 
struct  intelxl_rx_data_descriptor
 Receive data descriptor. More...
 
struct  intelxl_rx_writeback_descriptor
 Receive writeback descriptor. More...
 
union  intelxl_rx_descriptor
 Packet descriptor. More...
 
struct  intelxl_ring
 Descriptor ring. More...
 
struct  intelxl_msix
 MSI-X interrupt. More...
 
struct  intelxl_nic
 An Intel 40 Gigabit network card. More...
 

Macros

#define INTELXL_BAR_SIZE   0x200000
 BAR size. More...
 
#define INTELXL_ALIGN   256
 Alignment. More...
 
#define INTELXL_ADMIN_CMD   0x080000
 PF Admin Command Queue register block. More...
 
#define INTELXL_ADMIN_EVT   0x080080
 PF Admin Event Queue register block. More...
 
#define INTELXL_ADMIN_BAL   0x000
 Admin Queue Base Address Low Register (offset) More...
 
#define INTELXL_ADMIN_BAH   0x100
 Admin Queue Base Address High Register (offset) More...
 
#define INTELXL_ADMIN_LEN   0x200
 Admin Queue Length Register (offset) More...
 
#define INTELXL_ADMIN_LEN_LEN(x)   ( (x) << 0 )
 Queue length. More...
 
#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL
 Queue enable. More...
 
#define INTELXL_ADMIN_HEAD   0x300
 Admin Queue Head Register (offset) More...
 
#define INTELXL_ADMIN_TAIL   0x400
 Admin Queue Tail Register (offset) More...
 
#define INTELXL_ADMIN_VERSION   0x0001
 Admin queue Get Version command. More...
 
#define INTELXL_ADMIN_DRIVER   0x0002
 Admin queue Driver Version command. More...
 
#define INTELXL_ADMIN_SHUTDOWN   0x0003
 Admin queue Shutdown command. More...
 
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING   0x01
 Driver is unloading. More...
 
#define INTELXL_ADMIN_MAC_READ   0x0107
 Admin queue Manage MAC Address Read command. More...
 
#define INTELXL_ADMIN_MAC_READ_VALID_LAN   0x10
 LAN MAC address is valid. More...
 
#define INTELXL_ADMIN_MAC_WRITE   0x0108
 Admin queue Manage MAC Address Write command. More...
 
#define INTELXL_ADMIN_CLEAR_PXE   0x0110
 Admin queue Clear PXE Mode command. More...
 
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02
 Clear PXE Mode magic value. More...
 
#define INTELXL_ADMIN_SWITCH   0x0200
 Admin queue Get Switch Configuration command. More...
 
#define INTELXL_ADMIN_SWITCH_TYPE_VSI   19
 Virtual Station Inferface element type. More...
 
#define INTELXL_ADMIN_VSI   0x0212
 Admin queue Get VSI Parameters command. More...
 
#define INTELXL_ADMIN_PROMISC   0x0254
 Admin queue Set VSI Promiscuous Modes command. More...
 
#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001
 Promiscuous unicast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST   0x0002
 Promiscuous multicast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST   0x0004
 Promiscuous broadcast mode. More...
 
#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010
 Promiscuous VLAN mode. More...
 
#define INTELXL_ADMIN_MAC_CONFIG   0x0603
 Admin queue Set MAC Configuration command. More...
 
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC   0x04
 Append CRC on transmit. More...
 
#define INTELXL_ADMIN_AUTONEG   0x0605
 Admin queue Restart Autonegotiation command. More...
 
#define INTELXL_ADMIN_AUTONEG_FL_RESTART   0x02
 Restart autonegotiation. More...
 
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE   0x04
 Enable link. More...
 
#define INTELXL_ADMIN_LINK   0x0607
 Admin queue Get Link Status command. More...
 
#define INTELXL_ADMIN_LINK_NOTIFY   0x03
 Notify driver of link status changes. More...
 
#define INTELXL_ADMIN_LINK_UP   0x01
 Link is up. More...
 
#define INTELXL_ADMIN_BUFFER_SIZE   0x1000
 Maximum size of a data buffer. More...
 
#define INTELXL_ADMIN_FL_DD   0x0001
 Admin descriptor done. More...
 
#define INTELXL_ADMIN_FL_CMP   0x0002
 Admin descriptor contains a completion. More...
 
#define INTELXL_ADMIN_FL_ERR   0x0004
 Admin descriptor completed in error. More...
 
#define INTELXL_ADMIN_FL_RD   0x0400
 Admin descriptor uses data buffer for command parameters. More...
 
#define INTELXL_ADMIN_FL_BUF   0x1000
 Admin descriptor uses data buffer. More...
 
#define INTELXL_ADMIN_EEXIST   13
 Error: attempt to create something that already exists. More...
 
#define INTELXL_ADMIN_NUM_DESC   4
 Number of admin queue descriptors. More...
 
#define INTELXL_ADMIN_MAX_WAIT_MS   100
 Maximum time to wait for an admin request to complete. More...
 
#define INTELXL_ADMIN_API_MAJOR   1
 Admin queue API major version. More...
 
#define INTELXL_PFCM_LANCTXDATA(x)   ( 0x10c100 + ( 0x80 * (x) ) )
 CMLAN Context Data Register. More...
 
#define INTELXL_PFCM_LANCTXCTL   0x10c300
 CMLAN Context Control Register. More...
 
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)   ( (x) << 0 )
 Queue number. More...
 
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)   ( (x) << 12 )
 Sub-line. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE(x)   ( (x) << 15 )
 Queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )
 RX queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )
 TX queue type. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE(x)   ( (x) << 17 )
 Op code. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )
 Read context. More...
 
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )
 Write context. More...
 
#define INTELXL_PFCM_LANCTXSTAT   0x10c380
 CMLAN Context Status Register. More...
 
#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL
 Complete. More...
 
#define INTELXL_CTX_TX_FL_NEW   0x4000
 New transmit queue context. More...
 
#define INTELXL_CTX_TX_BASE(base)   ( (base) >> 7 )
 Transmit queue base address. More...
 
#define INTELXL_CTX_TX_COUNT(count)   ( (count) << 1 )
 Transmit queue count. More...
 
#define INTELXL_CTX_TX_QSET(qset)   ( (qset) << 4 )
 Transmit queue set. More...
 
#define INTELXL_CTX_RX_BASE_COUNT(base, count)   ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
 Receive queue base address and queue count. More...
 
#define INTELXL_CTX_RX_LEN(len)   ( (len) >> 1 )
 Receive queue data buffer length. More...
 
#define INTELXL_CTX_RX_FL_DSIZE   0x10
 Use 32-byte receive descriptors. More...
 
#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20
 Strip CRC from received packets. More...
 
#define INTELXL_CTX_RX_MFS(mfs)   ( (mfs) >> 2 )
 Receive queue maximum frame size. More...
 
#define INTELXL_CTX_MAX_WAIT_MS   100
 Maximum time to wait for a context operation to complete. More...
 
#define INTELXL_QUEUE_ENABLE_DELAY_US   20
 Time to wait for a queue to become enabled. More...
 
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US   400
 Time to wait for a transmit queue to become pre-disabled. More...
 
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS   1000
 Maximum time to wait for a queue to become disabled. More...
 
#define INTELXL_QTX_HEAD(x)   ( 0x0e4000 + ( 0x4 * (x) ) )
 Global Transmit Queue Head register. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS(x)   ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
 Global Transmit Pre Queue Disable register. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)   ( (x) << 0 )
 Queue index. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL
 Set disable. More...
 
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL
 Clear disable. More...
 
#define INTELXL_QTX(x)   ( 0x100000 + ( 0x4 * (x) ) )
 Global Transmit Queue register block. More...
 
#define INTELXL_QRX(x)   ( 0x120000 + ( 0x4 * (x) ) )
 Global Receive Queue register block. More...
 
#define INTELXL_QXX_ENA   0x0000
 Queue Enable Register (offset) More...
 
#define INTELXL_QXX_ENA_REQ   0x00000001UL
 Enable request. More...
 
#define INTELXL_QXX_ENA_STAT   0x00000004UL
 Enabled status. More...
 
#define INTELXL_QXX_CTL   0x4000
 Queue Control Register (offset) More...
 
#define INTELXL_QXX_CTL_PFVF_Q(x)   ( (x) << 0 )
 PF/VF queue. More...
 
#define INTELXL_QXX_CTL_PFVF_Q_PF   INTELXL_QXX_CTL_PFVF_Q ( 0x2 )
 PF queue. More...
 
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)   ( (x) << 2 )
 PF index. More...
 
#define INTELXL_QXX_TAIL   0x8000
 Queue Tail Pointer Register (offset) More...
 
#define INTELXL_TX_DATA_DTYP   0x0
 Transmit data descriptor type. More...
 
#define INTELXL_TX_DATA_EOP   0x10
 Transmit data descriptor end of packet. More...
 
#define INTELXL_TX_DATA_RS   0x20
 Transmit data descriptor report status. More...
 
#define INTELXL_TX_DATA_JFDI   0x40
 Transmit data descriptor pretty please. More...
 
#define INTELXL_TX_DATA_LEN(len)   ( (len) << 2 )
 Transmit data descriptor length. More...
 
#define INTELXL_TX_WB_FL_DD   0x01
 Transmit writeback descriptor complete. More...
 
#define INTELXL_RX_WB_FL_DD   0x00000001UL
 Receive writeback descriptor complete. More...
 
#define INTELXL_RX_WB_FL_VLAN   0x00000004UL
 Receive writeback descriptor VLAN tag present. More...
 
#define INTELXL_RX_WB_FL_RXE   0x00080000UL
 Receive writeback descriptor error. More...
 
#define INTELXL_RX_WB_LEN(len)   ( ( (len) >> 6 ) & 0x3fff )
 Receive writeback descriptor length. More...
 
#define INTELXL_TX_NUM_DESC   64
 Number of transmit descriptors. More...
 
#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )
 Transmit descriptor ring maximum fill level. More...
 
#define INTELXL_RX_NUM_DESC   64
 Number of receive descriptors. More...
 
#define INTELXL_RX_FILL   16
 Receive descriptor ring fill level. More...
 
#define INTELXL_MAX_PKT_LEN   ( 9728 - 4 /* CRC */ )
 Maximum packet length (excluding CRC) More...
 
#define INTELXL_PFINT_DYN_CTL0   0x038480
 PF Interrupt Zero Dynamic Control Register. More...
 
#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL
 Enable. More...
 
#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL
 Acknowledge. More...
 
#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL
 Ignore enable. More...
 
#define INTELXL_PFINT_LNKLST0   0x038500
 PF Interrupt Zero Linked List Register. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)   ( (x) << 0 )
 Queue index. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE   INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x)   ( (x) << 11 )
 Queue type. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_PFINT_ICR0_ENA   0x038800
 PF Interrupt Zero Cause Enablement Register. More...
 
#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL
 Admin event. More...
 
#define INTELXL_QINT_RQCTL(x)   ( 0x03a000 + ( 0x4 * (x) ) )
 Receive Queue Interrupt Cause Control Register. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL
 Enable. More...
 
#define INTELXL_QINT_TQCTL(x)   ( 0x03c000 + ( 0x4 * (x) ) )
 Transmit Queue Interrupt Cause Control Register. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_INDX(x)   ( (x) << 16 )
 Queue index. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )
 End of list. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x)   ( (x) << 27 )
 Queue type. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )
 Receive queue. More...
 
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )
 Transmit queue. More...
 
#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL
 Enable. More...
 
#define INTELXL_PFFUNC_RID   0x09c000
 Function Requester ID Information Register. More...
 
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)   ( ( (x) >> 0 ) & 0x7 )
 Function number. More...
 
#define INTELXL_PFLAN_QALLOC   0x1c0400
 PF Queue Allocation Register. More...
 
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)   ( ( (x) >> 0 ) & 0x7ff )
 First queue. More...
 
#define INTELXL_PFLAN_QALLOC_LASTQ(x)   ( ( (x) >> 16 ) & 0x7ff )
 Last queue. More...
 
#define INTELXL_PFGEN_PORTNUM   0x1c0480
 PF LAN Port Number Register. More...
 
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)   ( ( (x) >> 0 ) & 0x3 )
 Port number. More...
 
#define INTELXL_MSIX_VECTOR   0
 MSI-X interrupt vector. More...
 

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
static void intelxl_init_admin (struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
 Initialise admin queue. More...
 
static void intelxl_init_ring (struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
 Initialise descriptor ring. More...
 
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Enable MSI-X dummy interrupt. More...
 
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Disable MSI-X dummy interrupt. More...
 
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor. More...
 
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer. More...
 
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command. More...
 
int intelxl_admin_clear_pxe (struct intelxl_nic *intelxl)
 Clear PXE mode. More...
 
int intelxl_admin_mac_config (struct intelxl_nic *intelxl)
 Set MAC configuration. More...
 
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue. More...
 
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues. More...
 
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset) More...
 
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues. More...
 
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring. More...
 
void intelxl_free_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 
int intelxl_create_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Create descriptor ring. More...
 
void intelxl_destroy_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Destroy descriptor ring. More...
 
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers. More...
 
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets. More...
 

Variables

const struct intelxl_admin_offsets intelxl_admin_offsets
 Admin queue register offsets. More...
 

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.h.

Macro Definition Documentation

◆ INTELXL_BAR_SIZE

#define INTELXL_BAR_SIZE   0x200000

BAR size.

Definition at line 20 of file intelxl.h.

◆ INTELXL_ALIGN

#define INTELXL_ALIGN   256

Alignment.

No data structure requires greater than 256 byte alignment.

Definition at line 26 of file intelxl.h.

◆ INTELXL_ADMIN_CMD

#define INTELXL_ADMIN_CMD   0x080000

PF Admin Command Queue register block.

Definition at line 36 of file intelxl.h.

◆ INTELXL_ADMIN_EVT

#define INTELXL_ADMIN_EVT   0x080080

PF Admin Event Queue register block.

Definition at line 39 of file intelxl.h.

◆ INTELXL_ADMIN_BAL

#define INTELXL_ADMIN_BAL   0x000

Admin Queue Base Address Low Register (offset)

Definition at line 42 of file intelxl.h.

◆ INTELXL_ADMIN_BAH

#define INTELXL_ADMIN_BAH   0x100

Admin Queue Base Address High Register (offset)

Definition at line 45 of file intelxl.h.

◆ INTELXL_ADMIN_LEN

#define INTELXL_ADMIN_LEN   0x200

Admin Queue Length Register (offset)

Definition at line 48 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_LEN

#define INTELXL_ADMIN_LEN_LEN (   x)    ( (x) << 0 )

Queue length.

Definition at line 49 of file intelxl.h.

◆ INTELXL_ADMIN_LEN_ENABLE

#define INTELXL_ADMIN_LEN_ENABLE   0x80000000UL

Queue enable.

Definition at line 50 of file intelxl.h.

◆ INTELXL_ADMIN_HEAD

#define INTELXL_ADMIN_HEAD   0x300

Admin Queue Head Register (offset)

Definition at line 53 of file intelxl.h.

◆ INTELXL_ADMIN_TAIL

#define INTELXL_ADMIN_TAIL   0x400

Admin Queue Tail Register (offset)

Definition at line 56 of file intelxl.h.

◆ INTELXL_ADMIN_VERSION

#define INTELXL_ADMIN_VERSION   0x0001

Admin queue Get Version command.

Definition at line 87 of file intelxl.h.

◆ INTELXL_ADMIN_DRIVER

#define INTELXL_ADMIN_DRIVER   0x0002

Admin queue Driver Version command.

Definition at line 110 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN

#define INTELXL_ADMIN_SHUTDOWN   0x0003

Admin queue Shutdown command.

Definition at line 135 of file intelxl.h.

◆ INTELXL_ADMIN_SHUTDOWN_UNLOADING

#define INTELXL_ADMIN_SHUTDOWN_UNLOADING   0x01

Driver is unloading.

Definition at line 146 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_READ

#define INTELXL_ADMIN_MAC_READ   0x0107

Admin queue Manage MAC Address Read command.

Definition at line 149 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_READ_VALID_LAN

#define INTELXL_ADMIN_MAC_READ_VALID_LAN   0x10

LAN MAC address is valid.

Definition at line 160 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_WRITE

#define INTELXL_ADMIN_MAC_WRITE   0x0108

Admin queue Manage MAC Address Write command.

Definition at line 175 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE

#define INTELXL_ADMIN_CLEAR_PXE   0x0110

Admin queue Clear PXE Mode command.

Definition at line 192 of file intelxl.h.

◆ INTELXL_ADMIN_CLEAR_PXE_MAGIC

#define INTELXL_ADMIN_CLEAR_PXE_MAGIC   0x02

Clear PXE Mode magic value.

Definition at line 203 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH

#define INTELXL_ADMIN_SWITCH   0x0200

Admin queue Get Switch Configuration command.

Definition at line 206 of file intelxl.h.

◆ INTELXL_ADMIN_SWITCH_TYPE_VSI

#define INTELXL_ADMIN_SWITCH_TYPE_VSI   19

Virtual Station Inferface element type.

Definition at line 231 of file intelxl.h.

◆ INTELXL_ADMIN_VSI

#define INTELXL_ADMIN_VSI   0x0212

Admin queue Get VSI Parameters command.

Definition at line 256 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC

#define INTELXL_ADMIN_PROMISC   0x0254

Admin queue Set VSI Promiscuous Modes command.

Definition at line 283 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_UNICAST

#define INTELXL_ADMIN_PROMISC_FL_UNICAST   0x0001

Promiscuous unicast mode.

Definition at line 298 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_MULTICAST

#define INTELXL_ADMIN_PROMISC_FL_MULTICAST   0x0002

Promiscuous multicast mode.

Definition at line 301 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_BROADCAST

#define INTELXL_ADMIN_PROMISC_FL_BROADCAST   0x0004

Promiscuous broadcast mode.

Definition at line 304 of file intelxl.h.

◆ INTELXL_ADMIN_PROMISC_FL_VLAN

#define INTELXL_ADMIN_PROMISC_FL_VLAN   0x0010

Promiscuous VLAN mode.

Definition at line 307 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_CONFIG

#define INTELXL_ADMIN_MAC_CONFIG   0x0603

Admin queue Set MAC Configuration command.

Definition at line 310 of file intelxl.h.

◆ INTELXL_ADMIN_MAC_CONFIG_FL_CRC

#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC   0x04

Append CRC on transmit.

Definition at line 323 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG

#define INTELXL_ADMIN_AUTONEG   0x0605

Admin queue Restart Autonegotiation command.

Definition at line 326 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_RESTART

#define INTELXL_ADMIN_AUTONEG_FL_RESTART   0x02

Restart autonegotiation.

Definition at line 337 of file intelxl.h.

◆ INTELXL_ADMIN_AUTONEG_FL_ENABLE

#define INTELXL_ADMIN_AUTONEG_FL_ENABLE   0x04

Enable link.

Definition at line 340 of file intelxl.h.

◆ INTELXL_ADMIN_LINK

#define INTELXL_ADMIN_LINK   0x0607

Admin queue Get Link Status command.

Definition at line 343 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_NOTIFY

#define INTELXL_ADMIN_LINK_NOTIFY   0x03

Notify driver of link status changes.

Definition at line 362 of file intelxl.h.

◆ INTELXL_ADMIN_LINK_UP

#define INTELXL_ADMIN_LINK_UP   0x01

Link is up.

Definition at line 365 of file intelxl.h.

◆ INTELXL_ADMIN_BUFFER_SIZE

#define INTELXL_ADMIN_BUFFER_SIZE   0x1000

Maximum size of a data buffer.

Definition at line 398 of file intelxl.h.

◆ INTELXL_ADMIN_FL_DD

#define INTELXL_ADMIN_FL_DD   0x0001

Admin descriptor done.

Definition at line 433 of file intelxl.h.

◆ INTELXL_ADMIN_FL_CMP

#define INTELXL_ADMIN_FL_CMP   0x0002

Admin descriptor contains a completion.

Definition at line 436 of file intelxl.h.

◆ INTELXL_ADMIN_FL_ERR

#define INTELXL_ADMIN_FL_ERR   0x0004

Admin descriptor completed in error.

Definition at line 439 of file intelxl.h.

◆ INTELXL_ADMIN_FL_RD

#define INTELXL_ADMIN_FL_RD   0x0400

Admin descriptor uses data buffer for command parameters.

Definition at line 442 of file intelxl.h.

◆ INTELXL_ADMIN_FL_BUF

#define INTELXL_ADMIN_FL_BUF   0x1000

Admin descriptor uses data buffer.

Definition at line 445 of file intelxl.h.

◆ INTELXL_ADMIN_EEXIST

#define INTELXL_ADMIN_EEXIST   13

Error: attempt to create something that already exists.

Definition at line 448 of file intelxl.h.

◆ INTELXL_ADMIN_NUM_DESC

#define INTELXL_ADMIN_NUM_DESC   4

Number of admin queue descriptors.

Definition at line 483 of file intelxl.h.

◆ INTELXL_ADMIN_MAX_WAIT_MS

#define INTELXL_ADMIN_MAX_WAIT_MS   100

Maximum time to wait for an admin request to complete.

Definition at line 486 of file intelxl.h.

◆ INTELXL_ADMIN_API_MAJOR

#define INTELXL_ADMIN_API_MAJOR   1

Admin queue API major version.

Definition at line 489 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXDATA

#define INTELXL_PFCM_LANCTXDATA (   x)    ( 0x10c100 + ( 0x80 * (x) ) )

CMLAN Context Data Register.

Definition at line 499 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL

#define INTELXL_PFCM_LANCTXCTL   0x10c300

CMLAN Context Control Register.

Definition at line 502 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_QUEUE_NUM

#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM (   x)    ( (x) << 0 )

Queue number.

Definition at line 503 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_SUB_LINE

#define INTELXL_PFCM_LANCTXCTL_SUB_LINE (   x)    ( (x) << 12 )

Sub-line.

Definition at line 506 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE

#define INTELXL_PFCM_LANCTXCTL_TYPE (   x)    ( (x) << 15 )

Queue type.

Definition at line 509 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_RX

#define INTELXL_PFCM_LANCTXCTL_TYPE_RX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 )

RX queue type.

Definition at line 512 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_TYPE_TX

#define INTELXL_PFCM_LANCTXCTL_TYPE_TX   INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 )

TX queue type.

Definition at line 514 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE (   x)    ( (x) << 17 )

Op code.

Definition at line 516 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_READ

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 )

Read context.

Definition at line 519 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE

#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE   INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 )

Write context.

Definition at line 521 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT

#define INTELXL_PFCM_LANCTXSTAT   0x10c380

CMLAN Context Status Register.

Definition at line 525 of file intelxl.h.

◆ INTELXL_PFCM_LANCTXSTAT_DONE

#define INTELXL_PFCM_LANCTXSTAT_DONE   0x00000001UL

Complete.

Definition at line 526 of file intelxl.h.

◆ INTELXL_CTX_TX_FL_NEW

#define INTELXL_CTX_TX_FL_NEW   0x4000

New transmit queue context.

Definition at line 555 of file intelxl.h.

◆ INTELXL_CTX_TX_BASE

#define INTELXL_CTX_TX_BASE (   base)    ( (base) >> 7 )

Transmit queue base address.

Definition at line 558 of file intelxl.h.

◆ INTELXL_CTX_TX_COUNT

#define INTELXL_CTX_TX_COUNT (   count)    ( (count) << 1 )

Transmit queue count.

Definition at line 561 of file intelxl.h.

◆ INTELXL_CTX_TX_QSET

#define INTELXL_CTX_TX_QSET (   qset)    ( (qset) << 4 )

Transmit queue set.

Definition at line 564 of file intelxl.h.

◆ INTELXL_CTX_RX_BASE_COUNT

#define INTELXL_CTX_RX_BASE_COUNT (   base,
  count 
)    ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )

Receive queue base address and queue count.

Definition at line 587 of file intelxl.h.

◆ INTELXL_CTX_RX_LEN

#define INTELXL_CTX_RX_LEN (   len)    ( (len) >> 1 )

Receive queue data buffer length.

Definition at line 591 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_DSIZE

#define INTELXL_CTX_RX_FL_DSIZE   0x10

Use 32-byte receive descriptors.

Definition at line 594 of file intelxl.h.

◆ INTELXL_CTX_RX_FL_CRCSTRIP

#define INTELXL_CTX_RX_FL_CRCSTRIP   0x20

Strip CRC from received packets.

Definition at line 597 of file intelxl.h.

◆ INTELXL_CTX_RX_MFS

#define INTELXL_CTX_RX_MFS (   mfs)    ( (mfs) >> 2 )

Receive queue maximum frame size.

Definition at line 600 of file intelxl.h.

◆ INTELXL_CTX_MAX_WAIT_MS

#define INTELXL_CTX_MAX_WAIT_MS   100

Maximum time to wait for a context operation to complete.

Definition at line 603 of file intelxl.h.

◆ INTELXL_QUEUE_ENABLE_DELAY_US

#define INTELXL_QUEUE_ENABLE_DELAY_US   20

Time to wait for a queue to become enabled.

Definition at line 606 of file intelxl.h.

◆ INTELXL_QUEUE_PRE_DISABLE_DELAY_US

#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US   400

Time to wait for a transmit queue to become pre-disabled.

Definition at line 609 of file intelxl.h.

◆ INTELXL_QUEUE_DISABLE_MAX_WAIT_MS

#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS   1000

Maximum time to wait for a queue to become disabled.

Definition at line 612 of file intelxl.h.

◆ INTELXL_QTX_HEAD

#define INTELXL_QTX_HEAD (   x)    ( 0x0e4000 + ( 0x4 * (x) ) )

Global Transmit Queue Head register.

Definition at line 622 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS (   x)    ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )

Global Transmit Pre Queue Disable register.

Definition at line 625 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_QINDX

#define INTELXL_GLLAN_TXPRE_QDIS_QINDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 626 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS   0x40000000UL

Set disable.

Definition at line 629 of file intelxl.h.

◆ INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS

#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS   0x80000000UL

Clear disable.

Definition at line 631 of file intelxl.h.

◆ INTELXL_QTX

#define INTELXL_QTX (   x)    ( 0x100000 + ( 0x4 * (x) ) )

Global Transmit Queue register block.

Definition at line 635 of file intelxl.h.

◆ INTELXL_QRX

#define INTELXL_QRX (   x)    ( 0x120000 + ( 0x4 * (x) ) )

Global Receive Queue register block.

Definition at line 638 of file intelxl.h.

◆ INTELXL_QXX_ENA

#define INTELXL_QXX_ENA   0x0000

Queue Enable Register (offset)

Definition at line 641 of file intelxl.h.

◆ INTELXL_QXX_ENA_REQ

#define INTELXL_QXX_ENA_REQ   0x00000001UL

Enable request.

Definition at line 642 of file intelxl.h.

◆ INTELXL_QXX_ENA_STAT

#define INTELXL_QXX_ENA_STAT   0x00000004UL

Enabled status.

Definition at line 643 of file intelxl.h.

◆ INTELXL_QXX_CTL

#define INTELXL_QXX_CTL   0x4000

Queue Control Register (offset)

Definition at line 646 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q

#define INTELXL_QXX_CTL_PFVF_Q (   x)    ( (x) << 0 )

PF/VF queue.

Definition at line 647 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_Q_PF

#define INTELXL_QXX_CTL_PFVF_Q_PF   INTELXL_QXX_CTL_PFVF_Q ( 0x2 )

PF queue.

Definition at line 648 of file intelxl.h.

◆ INTELXL_QXX_CTL_PFVF_PF_INDX

#define INTELXL_QXX_CTL_PFVF_PF_INDX (   x)    ( (x) << 2 )

PF index.

Definition at line 650 of file intelxl.h.

◆ INTELXL_QXX_TAIL

#define INTELXL_QXX_TAIL   0x8000

Queue Tail Pointer Register (offset)

Definition at line 653 of file intelxl.h.

◆ INTELXL_TX_DATA_DTYP

#define INTELXL_TX_DATA_DTYP   0x0

Transmit data descriptor type.

Definition at line 666 of file intelxl.h.

◆ INTELXL_TX_DATA_EOP

#define INTELXL_TX_DATA_EOP   0x10

Transmit data descriptor end of packet.

Definition at line 669 of file intelxl.h.

◆ INTELXL_TX_DATA_RS

#define INTELXL_TX_DATA_RS   0x20

Transmit data descriptor report status.

Definition at line 672 of file intelxl.h.

◆ INTELXL_TX_DATA_JFDI

#define INTELXL_TX_DATA_JFDI   0x40

Transmit data descriptor pretty please.

This bit is completely missing from older versions of the XL710 datasheet. Later versions describe it innocuously as "reserved, must be 1". Without this bit, everything will appear to work (up to and including the port "transmit good octets" counter), but no packet will actually be sent.

Definition at line 682 of file intelxl.h.

◆ INTELXL_TX_DATA_LEN

#define INTELXL_TX_DATA_LEN (   len)    ( (len) << 2 )

Transmit data descriptor length.

Definition at line 685 of file intelxl.h.

◆ INTELXL_TX_WB_FL_DD

#define INTELXL_TX_WB_FL_DD   0x01

Transmit writeback descriptor complete.

Definition at line 698 of file intelxl.h.

◆ INTELXL_RX_WB_FL_DD

#define INTELXL_RX_WB_FL_DD   0x00000001UL

Receive writeback descriptor complete.

Definition at line 735 of file intelxl.h.

◆ INTELXL_RX_WB_FL_VLAN

#define INTELXL_RX_WB_FL_VLAN   0x00000004UL

Receive writeback descriptor VLAN tag present.

Definition at line 738 of file intelxl.h.

◆ INTELXL_RX_WB_FL_RXE

#define INTELXL_RX_WB_FL_RXE   0x00080000UL

Receive writeback descriptor error.

Definition at line 741 of file intelxl.h.

◆ INTELXL_RX_WB_LEN

#define INTELXL_RX_WB_LEN (   len)    ( ( (len) >> 6 ) & 0x3fff )

Receive writeback descriptor length.

Definition at line 744 of file intelxl.h.

◆ INTELXL_TX_NUM_DESC

#define INTELXL_TX_NUM_DESC   64

Number of transmit descriptors.

Chosen to exceed the receive ring fill level, in order to avoid running out of transmit descriptors when sending TCP ACKs.

Definition at line 808 of file intelxl.h.

◆ INTELXL_TX_FILL

#define INTELXL_TX_FILL   ( INTELXL_TX_NUM_DESC - 1 )

Transmit descriptor ring maximum fill level.

Definition at line 811 of file intelxl.h.

◆ INTELXL_RX_NUM_DESC

#define INTELXL_RX_NUM_DESC   64

Number of receive descriptors.

Must be a multiple of 32 and greater than or equal to 64.

Definition at line 817 of file intelxl.h.

◆ INTELXL_RX_FILL

#define INTELXL_RX_FILL   16

Receive descriptor ring fill level.

Must be a multiple of 8 and greater than 8.

Definition at line 823 of file intelxl.h.

◆ INTELXL_MAX_PKT_LEN

#define INTELXL_MAX_PKT_LEN   ( 9728 - 4 /* CRC */ )

Maximum packet length (excluding CRC)

Definition at line 826 of file intelxl.h.

◆ INTELXL_PFINT_DYN_CTL0

#define INTELXL_PFINT_DYN_CTL0   0x038480

PF Interrupt Zero Dynamic Control Register.

Definition at line 836 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA

#define INTELXL_INT_DYN_CTL_INTENA   0x00000001UL

Enable.

Definition at line 837 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_CLEARPBA

#define INTELXL_INT_DYN_CTL_CLEARPBA   0x00000002UL

Acknowledge.

Definition at line 838 of file intelxl.h.

◆ INTELXL_INT_DYN_CTL_INTENA_MASK

#define INTELXL_INT_DYN_CTL_INTENA_MASK   0x80000000UL

Ignore enable.

Definition at line 839 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0

#define INTELXL_PFINT_LNKLST0   0x038500

PF Interrupt Zero Linked List Register.

Definition at line 842 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX (   x)    ( (x) << 0 )

Queue index.

Definition at line 843 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE   INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff )

End of list.

Definition at line 846 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE (   x)    ( (x) << 11 )

Queue type.

Definition at line 848 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 851 of file intelxl.h.

◆ INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX

#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX   INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 853 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA

#define INTELXL_PFINT_ICR0_ENA   0x038800

PF Interrupt Zero Cause Enablement Register.

Definition at line 857 of file intelxl.h.

◆ INTELXL_PFINT_ICR0_ENA_ADMINQ

#define INTELXL_PFINT_ICR0_ENA_ADMINQ   0x40000000UL

Admin event.

Definition at line 858 of file intelxl.h.

◆ INTELXL_QINT_RQCTL

#define INTELXL_QINT_RQCTL (   x)    ( 0x03a000 + ( 0x4 * (x) ) )

Receive Queue Interrupt Cause Control Register.

Definition at line 861 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX

#define INTELXL_QINT_RQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 862 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 863 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 865 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 866 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 868 of file intelxl.h.

◆ INTELXL_QINT_RQCTL_CAUSE_ENA

#define INTELXL_QINT_RQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 870 of file intelxl.h.

◆ INTELXL_QINT_TQCTL

#define INTELXL_QINT_TQCTL (   x)    ( 0x03c000 + ( 0x4 * (x) ) )

Transmit Queue Interrupt Cause Control Register.

Definition at line 873 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX

#define INTELXL_QINT_TQCTL_NEXTQ_INDX (   x)    ( (x) << 16 )

Queue index.

Definition at line 874 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE

#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE   INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff )

End of list.

Definition at line 875 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE (   x)    ( (x) << 27 )

Queue type.

Definition at line 877 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 )

Receive queue.

Definition at line 878 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX

#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX   INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 )

Transmit queue.

Definition at line 880 of file intelxl.h.

◆ INTELXL_QINT_TQCTL_CAUSE_ENA

#define INTELXL_QINT_TQCTL_CAUSE_ENA   0x40000000UL

Enable.

Definition at line 882 of file intelxl.h.

◆ INTELXL_PFFUNC_RID

#define INTELXL_PFFUNC_RID   0x09c000

Function Requester ID Information Register.

Definition at line 885 of file intelxl.h.

◆ INTELXL_PFFUNC_RID_FUNC_NUM

#define INTELXL_PFFUNC_RID_FUNC_NUM (   x)    ( ( (x) >> 0 ) & 0x7 )

Function number.

Definition at line 886 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC

#define INTELXL_PFLAN_QALLOC   0x1c0400

PF Queue Allocation Register.

Definition at line 891 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_FIRSTQ

#define INTELXL_PFLAN_QALLOC_FIRSTQ (   x)    ( ( (x) >> 0 ) & 0x7ff )

First queue.

Definition at line 892 of file intelxl.h.

◆ INTELXL_PFLAN_QALLOC_LASTQ

#define INTELXL_PFLAN_QALLOC_LASTQ (   x)    ( ( (x) >> 16 ) & 0x7ff )

Last queue.

Definition at line 895 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM

#define INTELXL_PFGEN_PORTNUM   0x1c0480

PF LAN Port Number Register.

Definition at line 900 of file intelxl.h.

◆ INTELXL_PFGEN_PORTNUM_PORT_NUM

#define INTELXL_PFGEN_PORTNUM_PORT_NUM (   x)    ( ( (x) >> 0 ) & 0x3 )

Port number.

Definition at line 901 of file intelxl.h.

◆ INTELXL_MSIX_VECTOR

#define INTELXL_MSIX_VECTOR   0

MSI-X interrupt vector.

Definition at line 916 of file intelxl.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ intelxl_init_admin()

static void intelxl_init_admin ( struct intelxl_admin admin,
unsigned int  base,
const struct intelxl_admin_offsets regs 
)
inlinestatic

Initialise admin queue.

Parameters
adminAdmin queue
baseRegister block base
regsRegister offsets

Definition at line 475 of file intelxl.h.

476  {
477 
478  admin->base = base;
479  admin->regs = regs;
480 }
unsigned int base
Register block base.
Definition: intelxl.h:462
static const void * base
Base address.
Definition: crypto.h:335
struct i386_regs regs
Definition: registers.h:15
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464

References base, intelxl_admin::base, regs, and intelxl_admin::regs.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_init_ring()

static void intelxl_init_ring ( struct intelxl_ring ring,
unsigned int  count,
size_t  len,
int(*)(struct intelxl_nic *intelxl, physaddr_t address context 
)
inlinestatic

Initialise descriptor ring.

Parameters
ringDescriptor ring
countNumber of descriptors
lenLength of a single descriptor
contextMethod to program queue context

Definition at line 795 of file intelxl.h.

895  {

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_msix_enable()

int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Enable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector
Return values
rcReturn status code

Definition at line 62 of file intelxl.c.

63  {
64  int rc;
65 
66  /* Map dummy target location */
67  if ( ( rc = dma_map ( intelxl->dma, &intelxl->msix.map,
68  virt_to_phys ( &intelxl->msix.msg ),
69  sizeof ( intelxl->msix.msg ), DMA_RX ) ) != 0 ) {
70  DBGC ( intelxl, "INTELXL %p could not map MSI-X target: %s\n",
71  intelxl, strerror ( rc ) );
72  goto err_map;
73  }
74 
75  /* Enable MSI-X capability */
76  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix.cap ) ) != 0 ) {
77  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
78  intelxl, strerror ( rc ) );
79  goto err_enable;
80  }
81 
82  /* Configure interrupt to write to dummy location */
83  pci_msix_map ( &intelxl->msix.cap, vector,
84  dma ( &intelxl->msix.map, &intelxl->msix.msg ), 0 );
85 
86  /* Enable dummy interrupt */
87  pci_msix_unmask ( &intelxl->msix.cap, vector );
88 
89  return 0;
90 
91  pci_msix_disable ( pci, &intelxl->msix.cap );
92  err_enable:
93  dma_unmap ( &intelxl->msix.map );
94  err_map:
95  return rc;
96 }
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
struct pci_msix cap
PCI capability.
Definition: intelxl.h:908
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:912
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define DBGC(...)
Definition: compiler.h:505
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:72
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:948
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
#define DMA_RX
Device will write data to host memory.
Definition: dma.h:135
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:104
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:181
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:910

References intelxl_msix::cap, DBGC, dma(), intelxl_nic::dma, DMA_RX, dma_unmap(), intelxl_msix::map, intelxl_msix::msg, intelxl_nic::msix, pci_msix_disable(), pci_msix_enable(), pci_msix_map(), pci_msix_unmask(), rc, strerror(), vector, and virt_to_phys().

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Disable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector

Definition at line 105 of file intelxl.c.

106  {
107 
108  /* Disable dummy interrupts */
109  pci_msix_mask ( &intelxl->msix.cap, vector );
110 
111  /* Disable MSI-X capability */
112  pci_msix_disable ( pci, &intelxl->msix.cap );
113 
114  /* Unmap dummy target location */
115  dma_unmap ( &intelxl->msix.map );
116 }
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
struct pci_msix cap
PCI capability.
Definition: intelxl.h:908
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:912
uint32_t vector
MSI-X vector.
Definition: ena.h:20
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:60
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:948

References intelxl_msix::cap, dma_unmap(), intelxl_msix::map, intelxl_nic::msix, pci_msix_disable(), pci_msix_mask(), and vector.

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic intelxl)

Get next admin command queue descriptor.

Parameters
intelxlIntel device
Return values
cmdCommand descriptor

Definition at line 239 of file intelxl.c.

239  {
240  struct intelxl_admin *admin = &intelxl->command;
242 
243  /* Get and initialise next descriptor */
244  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
245  memset ( cmd, 0, sizeof ( *cmd ) );
246  return cmd;
247 }
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
Admin queue descriptor.
Definition: intelxl.h:415
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
void * memset(void *dest, int character, size_t len) __nonnull

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_descriptor(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), and intelxlvf_admin_command_descriptor().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl)

Get next admin command queue data buffer.

Parameters
intelxlIntel device
Return values
bufData buffer

Definition at line 256 of file intelxl.c.

256  {
257  struct intelxl_admin *admin = &intelxl->command;
258  union intelxl_admin_buffer *buf;
259 
260  /* Get next data buffer */
261  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
262  memset ( buf, 0, sizeof ( *buf ) );
263  return buf;
264 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
Admin queue data buffer.
Definition: intelxl.h:401
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_buffer(), intelxl_admin_driver(), intelxl_admin_mac_read(), intelxl_admin_switch(), intelxl_admin_vsi(), and intelxlvf_admin_command_buffer().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 295 of file intelxl.c.

295  {
296  struct intelxl_admin *admin = &intelxl->command;
297  const struct intelxl_admin_offsets *regs = admin->regs;
298  void *admin_regs = ( intelxl->regs + admin->base );
300  union intelxl_admin_buffer *buf;
302  uint32_t cookie;
303  uint16_t silence;
304  unsigned int index;
305  unsigned int tail;
306  unsigned int i;
307  int rc;
308 
309  /* Get next queue entry */
310  index = admin->index++;
311  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
312  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
313  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
314  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
315  intelxl, index, le16_to_cpu ( cmd->opcode ) );
316  if ( cmd->cookie )
317  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
318  DBGC2 ( intelxl, ":\n" );
319 
320  /* Allow expected errors to be silenced */
321  silence = cmd->ret;
322  cmd->ret = 0;
323 
324  /* Sanity checks */
325  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
326  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
327  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
328 
329  /* Populate data buffer address if applicable */
330  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
331  address = dma ( &admin->map, buf );
332  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
333  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
334  }
335 
336  /* Populate cookie, if not being (ab)used for VF opcode */
337  if ( ! cmd->cookie )
338  cmd->cookie = cpu_to_le32 ( index );
339 
340  /* Record cookie */
341  cookie = cmd->cookie;
342 
343  /* Post command descriptor */
344  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
345  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
346  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
347  le16_to_cpu ( cmd->len ) );
348  }
349  wmb();
350  writel ( tail, admin_regs + regs->tail );
351 
352  /* Wait for completion */
353  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
354 
355  /* If response is not complete, delay 1ms and retry */
356  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
357  mdelay ( 1 );
358  continue;
359  }
360  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
361  intelxl, index );
362  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
363  sizeof ( *cmd ) );
364  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
365  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
366  le16_to_cpu ( cmd->len ) );
367  }
368 
369  /* Check for cookie mismatch */
370  if ( cmd->cookie != cookie ) {
371  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
372  "cookie %#x\n", intelxl, index,
373  le32_to_cpu ( cmd->cookie ) );
374  rc = -EPROTO;
375  goto err;
376  }
377 
378  /* Check for unexpected errors */
379  if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
380  DBGC ( intelxl, "INTELXL %p admin command %#x error "
381  "%d\n", intelxl, index,
382  le16_to_cpu ( cmd->ret ) );
383  rc = -EIO;
384  goto err;
385  }
386 
387  /* Success */
388  return 0;
389  }
390 
391  rc = -ETIMEDOUT;
392  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
393  intelxl, index );
394  err:
395  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
396  return rc;
397 }
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:439
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define le32_to_cpu(value)
Definition: byteswap.h:113
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue register offsets.
Definition: intelxl.h:63
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:451
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:462
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:436
unsigned int index
Queue index.
Definition: intelxl.h:459
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define DBGC_HDA(...)
Definition: compiler.h:506
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define EPROTO
Protocol error.
Definition: errno.h:624
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
struct i386_regs regs
Definition: registers.h:15
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
#define cpu_to_le16(value)
Definition: byteswap.h:106
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:486
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
Admin queue data buffer.
Definition: intelxl.h:401

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, dma(), EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_FL_RD, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin::map, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, virt_to_phys(), wmb(), and writel().

Referenced by ice_admin_add_txq(), ice_admin_autoneg(), ice_admin_disable_txq(), ice_admin_link(), ice_admin_mac_read(), ice_admin_mac_write(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ice_admin_version(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), intelxlvf_admin_request_qps(), and intelxlvf_reset_admin().

◆ intelxl_admin_clear_pxe()

int intelxl_admin_clear_pxe ( struct intelxl_nic intelxl)

Clear PXE mode.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 578 of file intelxl.c.

578  {
580  struct intelxl_admin_clear_pxe_params *pxe;
581  int rc;
582 
583  /* Populate descriptor */
587  pxe = &cmd->params.pxe;
589 
590  /* Issue command */
591  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
592  return rc;
593 
594  /* Check for expected errors */
595  if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
596  DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
597  intelxl );
598  return 0;
599  }
600 
601  return 0;
602 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:195
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:203
uint8_t magic
Magic value.
Definition: intelxl.h:197
#define INTELXL_ADMIN_EEXIST
Error: attempt to create something that already exists.
Definition: intelxl.h:448
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:192
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, INTELXL_ADMIN_CLEAR_PXE, INTELXL_ADMIN_CLEAR_PXE_MAGIC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_EEXIST, intelxl_admin_clear_pxe_params::magic, and rc.

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_admin_mac_config()

int intelxl_admin_mac_config ( struct intelxl_nic intelxl)

Set MAC configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 729 of file intelxl.c.

729  {
731  struct intelxl_admin_mac_config_params *config;
732  int rc;
733 
734  /* Populate descriptor */
737  config = &cmd->params.mac_config;
738  config->mfs = cpu_to_le16 ( intelxl->mfs );
740 
741  /* Issue command */
742  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
743  return rc;
744 
745  return 0;
746 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
Admin queue Set MAC Configuration command parameters.
Definition: intelxl.h:313
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
#define INTELXL_ADMIN_MAC_CONFIG
Admin queue Set MAC Configuration command.
Definition: intelxl.h:310
Admin queue descriptor.
Definition: intelxl.h:415
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:315
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC
Append CRC on transmit.
Definition: intelxl.h:323
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_mac_config_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_CONFIG, INTELXL_ADMIN_MAC_CONFIG_FL_CRC, intelxl_admin_mac_config_params::mfs, intelxl_nic::mfs, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters
netdevNetwork device

Definition at line 853 of file intelxl.c.

853  {
854  struct intelxl_nic *intelxl = netdev->priv;
855  struct intelxl_admin *admin = &intelxl->event;
856  struct intelxl_admin_descriptor *evt;
857  union intelxl_admin_buffer *buf;
858 
859  /* Check for events */
860  while ( 1 ) {
861 
862  /* Get next event descriptor and data buffer */
863  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
864  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
865 
866  /* Stop if descriptor is not yet completed */
867  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
868  return;
869  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
870  intelxl, admin->index );
871  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
872  sizeof ( *evt ) );
873  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
874  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
875  le16_to_cpu ( evt->len ) );
876  }
877 
878  /* Handle event */
879  intelxl->handle ( netdev, evt, buf );
880 
881  /* Reset descriptor and refill queue */
882  intelxl_admin_event_init ( intelxl, admin->index );
883  admin->index++;
884  intelxl_refill_admin ( intelxl );
885  }
886 }
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:972
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
uint16_t flags
Flags.
Definition: intelxl.h:417
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
uint16_t len
Data length.
Definition: intelxl.h:421
unsigned int index
Queue index.
Definition: intelxl.h:459
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:272
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:835
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define le16_to_cpu(value)
Definition: byteswap.h:112
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
Admin queue data buffer.
Definition: intelxl.h:401

References intelxl_admin::buf, cpu_to_le16, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_nic::handle, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_NUM_DESC, intelxl_refill_admin(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, net_device::priv, and virt_to_phys().

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 894 of file intelxl.c.

894  {
895  int rc;
896 
897  /* Allocate admin event queue */
898  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
899  goto err_alloc_event;
900 
901  /* Allocate admin command queue */
902  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
903  goto err_alloc_command;
904 
905  /* (Re)open admin queues */
906  intelxl_reopen_admin ( intelxl );
907 
908  return 0;
909 
910  intelxl_disable_admin ( intelxl, &intelxl->command );
911  intelxl_disable_admin ( intelxl, &intelxl->event );
912  intelxl_free_admin ( intelxl, &intelxl->command );
913  err_alloc_command:
914  intelxl_free_admin ( intelxl, &intelxl->event );
915  err_alloc_event:
916  return rc;
917 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:141
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:223
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:208
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:924
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters
intelxlIntel device

Definition at line 924 of file intelxl.c.

924  {
925  unsigned int i;
926 
927  /* Enable admin event queue */
928  intelxl_enable_admin ( intelxl, &intelxl->event );
929 
930  /* Enable admin command queue */
931  intelxl_enable_admin ( intelxl, &intelxl->command );
932 
933  /* Initialise all admin event queue descriptors */
934  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
935  intelxl_admin_event_init ( intelxl, i );
936 
937  /* Post all descriptors to event queue */
938  intelxl_refill_admin ( intelxl );
939 }
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:169
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:272
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:835
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_wait().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters
intelxlIntel device

Definition at line 946 of file intelxl.c.

946  {
947 
948  /* Shut down admin queues */
949  intelxl_admin_shutdown ( intelxl );
950 
951  /* Disable admin queues */
952  intelxl_disable_admin ( intelxl, &intelxl->command );
953  intelxl_disable_admin ( intelxl, &intelxl->event );
954 
955  /* Free admin queues */
956  intelxl_free_admin ( intelxl, &intelxl->command );
957  intelxl_free_admin ( intelxl, &intelxl->event );
958 }
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:472
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:223
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:208
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 974 of file intelxl.c.

975  {
976  int rc;
977 
978  /* Allocate descriptor ring */
979  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
980  INTELXL_ALIGN );
981  if ( ! ring->desc.raw ) {
982  rc = -ENOMEM;
983  goto err_alloc;
984  }
985 
986  /* Initialise descriptor ring */
987  memset ( ring->desc.raw, 0, ring->len );
988 
989  /* Reset tail pointer */
990  writel ( 0, ( intelxl->regs + ring->tail ) );
991 
992  /* Reset counters */
993  ring->prod = 0;
994  ring->cons = 0;
995 
996  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
997  intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
998  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
999 
1000  return 0;
1001 
1002  dma_free ( &ring->map, ring->desc.raw, ring->len );
1003  err_alloc:
1004  return rc;
1005 }
void * regs
Registers.
Definition: intelxl.h:921
size_t len
Length (in bytes)
Definition: intelxl.h:777
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:770
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@65 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
unsigned int tail
Tail register.
Definition: intelxl.h:775
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_ring::cons, DBGC, intelxl_ring::desc, intelxl_nic::dma, dma_alloc(), dma_free(), ENOMEM, INTELXL_ALIGN, intelxl_ring::len, intelxl_ring::map, memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_nic::regs, intelxl_ring::tail, virt_to_phys(), and writel().

Referenced by ice_create_tx(), intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

◆ intelxl_create_ring()

int intelxl_create_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Create descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1283 of file intelxl.c.

1284  {
1286  int rc;
1287 
1288  /* Allocate descriptor ring */
1289  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1290  goto err_alloc;
1291 
1292  /* Program queue context */
1293  address = dma ( &ring->map, ring->desc.raw );
1294  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1295  goto err_context;
1296 
1297  /* Enable ring */
1298  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1299  goto err_enable;
1300 
1301  return 0;
1302 
1303  intelxl_disable_ring ( intelxl, ring );
1304  err_enable:
1305  err_context:
1306  intelxl_free_ring ( intelxl, ring );
1307  err_alloc:
1308  return rc;
1309 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:783
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1225
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1250
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@65 desc
Descriptors.
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
unsigned long physaddr_t
Definition: stdint.h:20
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:974

References address, intelxl_ring::context, intelxl_ring::desc, dma(), intelxl_alloc_ring(), intelxl_disable_ring(), intelxl_enable_ring(), intelxl_free_ring(), intelxl_ring::map, intelxl_ring::raw, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_destroy_ring()

void intelxl_destroy_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Destroy descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 1317 of file intelxl.c.

1318  {
1319  int rc;
1320 
1321  /* Disable ring */
1322  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1323  /* Leak memory; there's nothing else we can do */
1324  return;
1325  }
1326 
1327  /* Free descriptor ring */
1328  intelxl_free_ring ( intelxl, ring );
1329 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1250
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013

References intelxl_disable_ring(), intelxl_free_ring(), and rc.

Referenced by ice_close(), ice_open(), intelxl_close(), and intelxl_open().

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters
intelxlIntel device

Definition at line 1384 of file intelxl.c.

1384  {
1385  unsigned int i;
1386 
1387  /* Discard any unused receive buffers */
1388  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1389  if ( intelxl->rx_iobuf[i] )
1390  free_rx_iob ( intelxl->rx_iobuf[i] );
1391  intelxl->rx_iobuf[i] = NULL;
1392  }
1393 }
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:963
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:208
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321

References free_rx_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by ice_close(), intelxl_close(), and intelxlvf_close().

◆ intelxl_transmit()

int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 1510 of file intelxl.c.

1510  {
1511  struct intelxl_nic *intelxl = netdev->priv;
1513  unsigned int tx_idx;
1514  unsigned int tx_tail;
1515  size_t len;
1516 
1517  /* Get next transmit descriptor */
1518  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1519  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1520  intelxl );
1521  return -ENOBUFS;
1522  }
1523  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1524  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1525  tx = &intelxl->tx.desc.tx[tx_idx].data;
1526 
1527  /* Populate transmit descriptor */
1528  len = iob_len ( iobuf );
1529  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1530  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1533  wmb();
1534 
1535  /* Notify card that there are packets ready to transmit */
1536  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1537 
1538  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1539  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1540  ( virt_to_phys ( iobuf->data ) + len ) );
1541  return 0;
1542 }
void * regs
Registers.
Definition: intelxl.h:921
wmb()
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:669
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:666
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define cpu_to_le64(value)
Definition: byteswap.h:108
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:685
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:703
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:264
union intelxl_ring::@65 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:672
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
Transmit data descriptor.
Definition: intelxl.h:656
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:682
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
uint32_t len
Length.
Definition: ena.h:14
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:48
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:811
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_dma(), iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, virt_to_phys(), wmb(), and writel().

◆ intelxl_poll()

void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters
netdevNetwork device

Definition at line 1630 of file intelxl.c.

1630  {
1631  struct intelxl_nic *intelxl = netdev->priv;
1632 
1633  /* Poll for completed packets */
1634  intelxl_poll_tx ( netdev );
1635 
1636  /* Poll for received packets */
1637  intelxl_poll_rx ( netdev );
1638 
1639  /* Poll for admin events */
1641 
1642  /* Refill RX ring */
1643  intelxl_refill_rx ( intelxl );
1644 
1645  /* Rearm interrupt, since otherwise receive descriptors will
1646  * be written back only after a complete cacheline (four
1647  * packets) have been received.
1648  *
1649  * There is unfortunately no efficient way to determine
1650  * whether or not rearming the interrupt is necessary. If we
1651  * are running inside a hypervisor (e.g. using a VF or PF as a
1652  * passed-through PCI device), then the MSI-X write is
1653  * redirected by the hypervisor to the real host APIC and the
1654  * host ISR then raises an interrupt within the guest. We
1655  * therefore cannot poll the nominal MSI-X target location to
1656  * watch for the value being written. We could read from the
1657  * INT_DYN_CTL register, but this is even less efficient than
1658  * just unconditionally rearming the interrupt.
1659  */
1660  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1661 }
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:837
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1549
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1336
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:853
unsigned int intr
Interrupt control register.
Definition: intelxl.h:944
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1578

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

Variable Documentation

◆ intelxl_admin_offsets

Admin queue register offsets.

Definition at line 126 of file intelxl.c.