iPXE
Data Structures | Macros | Functions
pcimsix.h File Reference

PCI MSI-X interrupts. More...

#include <ipxe/pci.h>

Go to the source code of this file.

Data Structures

struct  pci_msix
 PCI MSI-X capability. More...
 

Macros

#define PCI_MSIX_LEN   0x1000
 MSI-X BAR mapped length. More...
 
#define PCI_MSIX_VECTOR(n)   ( (n) * 0x10 )
 MSI-X vector offset. More...
 
#define PCI_MSIX_ADDRESS_LO   0x0
 MSI-X vector address low 32 bits. More...
 
#define PCI_MSIX_ADDRESS_HI   0x4
 MSI-X vector address high 32 bits. More...
 
#define PCI_MSIX_DATA   0x8
 MSI-X vector data. More...
 
#define PCI_MSIX_CONTROL   0xc
 MSI-X vector control. More...
 
#define PCI_MSIX_CONTROL_MASK   0x00000001
 Vector is masked. More...
 

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
int pci_msix_enable (struct pci_device *pci, struct pci_msix *msix)
 Enable MSI-X interrupts. More...
 
void pci_msix_disable (struct pci_device *pci, struct pci_msix *msix)
 Disable MSI-X interrupts. More...
 
void pci_msix_map (struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
 Map MSI-X interrupt vector. More...
 
void pci_msix_control (struct pci_msix *msix, unsigned int vector, uint32_t mask)
 Control MSI-X interrupt vector. More...
 
void pci_msix_dump (struct pci_msix *msix, unsigned int vector)
 Dump MSI-X interrupt state (for debugging) More...
 
static void pci_msix_mask (struct pci_msix *msix, unsigned int vector)
 Mask MSI-X interrupt vector. More...
 
static void pci_msix_unmask (struct pci_msix *msix, unsigned int vector)
 Unmask MSI-X interrupt vector. More...
 

Detailed Description

PCI MSI-X interrupts.

Definition in file pcimsix.h.

Macro Definition Documentation

◆ PCI_MSIX_LEN

#define PCI_MSIX_LEN   0x1000

MSI-X BAR mapped length.

Definition at line 15 of file pcimsix.h.

◆ PCI_MSIX_VECTOR

#define PCI_MSIX_VECTOR (   n)    ( (n) * 0x10 )

MSI-X vector offset.

Definition at line 18 of file pcimsix.h.

◆ PCI_MSIX_ADDRESS_LO

#define PCI_MSIX_ADDRESS_LO   0x0

MSI-X vector address low 32 bits.

Definition at line 21 of file pcimsix.h.

◆ PCI_MSIX_ADDRESS_HI

#define PCI_MSIX_ADDRESS_HI   0x4

MSI-X vector address high 32 bits.

Definition at line 24 of file pcimsix.h.

◆ PCI_MSIX_DATA

#define PCI_MSIX_DATA   0x8

MSI-X vector data.

Definition at line 27 of file pcimsix.h.

◆ PCI_MSIX_CONTROL

#define PCI_MSIX_CONTROL   0xc

MSI-X vector control.

Definition at line 30 of file pcimsix.h.

◆ PCI_MSIX_CONTROL_MASK

#define PCI_MSIX_CONTROL_MASK   0x00000001

Vector is masked.

Definition at line 31 of file pcimsix.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ pci_msix_enable()

int pci_msix_enable ( struct pci_device pci,
struct pci_msix msix 
)

Enable MSI-X interrupts.

Parameters
pciPCI device
msixMSI-X capability
Return values
rcReturn status code

Definition at line 136 of file pcimsix.c.

136  {
137  uint16_t ctrl;
138  physaddr_t msg;
139  unsigned int i;
140  int rc;
141 
142  /* Locate capability */
144  if ( ! msix->cap ) {
145  DBGC ( msix, "MSI-X %p found no MSI-X capability in "
146  PCI_FMT "\n", msix, PCI_ARGS ( pci ) );
147  rc = -ENOENT;
148  goto err_cap;
149  }
150 
151  /* Extract interrupt count */
152  pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
153  msix->count = ( PCI_MSIX_CTRL_SIZE ( ctrl ) + 1 );
154  DBGC ( msix, "MSI-X %p has %d vectors for " PCI_FMT "\n",
155  msix, msix->count, PCI_ARGS ( pci ) );
156 
157  /* Map MSI-X table */
158  msix->table = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_TABLE );
159  if ( ! msix->table ) {
160  rc = -ENOENT;
161  goto err_table;
162  }
163 
164  /* Map pending bit array */
165  msix->pba = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_PBA );
166  if ( ! msix->pba ) {
167  rc = -ENOENT;
168  goto err_pba;
169  }
170 
171  /* Allocate dummy target */
172  msix->msg = dma_alloc ( &pci->dma, &msix->map, sizeof ( *msix->msg ),
173  sizeof ( *msix->msg ) );
174  if ( ! msix->msg ) {
175  rc = -ENOMEM;
176  goto err_msg;
177  }
178 
179  /* Map all interrupts to dummy target by default */
180  msg = dma ( &msix->map, msix->msg );
181  for ( i = 0 ; i < msix->count ; i++ )
182  pci_msix_map ( msix, i, msg, 0 );
183 
184  /* Enable MSI-X */
187  pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
188 
189  return 0;
190 
191  dma_free ( &msix->map, msix->msg, sizeof ( *msix->msg ) );
192  err_msg:
193  iounmap ( msix->pba );
194  err_pba:
195  iounmap ( msix->table );
196  err_table:
197  err_cap:
198  return rc;
199 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
struct dma_device dma
DMA device.
Definition: pci.h:214
void msg(unsigned int row, const char *fmt,...)
Print message centred on specified row.
Definition: message.c:61
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:514
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
#define ENOMEM
Not enough space.
Definition: errno.h:534
struct pci_device * pci
PCI device.
Definition: pcibridge.h:19
#define PCI_MSIX_CTRL
MSI-X interrupts.
Definition: pci.h:115
unsigned int cap
Capability offset.
Definition: pcimsix.h:36
uint32_t * msg
Dummy message target.
Definition: pcimsix.h:44
#define PCI_MSIX_CTRL_SIZE(x)
Table size.
Definition: pci.h:118
#define PCI_MSIX_CTRL_MASK
Mask all interrupts.
Definition: pci.h:117
#define PCI_FMT
PCI device debug message format.
Definition: pci.h:311
void * table
MSI-X table.
Definition: pcimsix.h:40
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
unsigned long physaddr_t
Definition: stdint.h:20
static void * pci_msix_ioremap(struct pci_device *pci, struct pci_msix *msix, unsigned int cfg)
Map MSI-X BAR portion.
Definition: pcimsix.c:93
#define PCI_CAP_ID_MSIX
MSI-X.
Definition: pci.h:98
#define PCI_ARGS(pci)
PCI device debug message arguments.
Definition: pci.h:314
uint8_t ctrl
Ring control.
Definition: dwmac.h:18
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define PCI_MSIX_CTRL_ENABLE
Enable MSI-X.
Definition: pci.h:116
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:233
#define PCI_MSIX_DESC_PBA
Definition: pci.h:120
struct dma_mapping map
Dummy message target mapping.
Definition: pcimsix.h:46
void * pba
Pending bit array.
Definition: pcimsix.h:42
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
unsigned int count
Number of vectors.
Definition: pcimsix.h:38
#define PCI_MSIX_DESC_TABLE
Definition: pci.h:119

References pci_msix::cap, pci_msix::count, ctrl, DBGC, pci_device::dma, dma(), dma_alloc(), dma_free(), ENOENT, ENOMEM, iounmap(), pci_msix::map, pci_msix::msg, msg(), pci_msix::pba, PCI_ARGS, PCI_CAP_ID_MSIX, pci_find_capability(), PCI_FMT, PCI_MSIX_CTRL, PCI_MSIX_CTRL_ENABLE, PCI_MSIX_CTRL_MASK, PCI_MSIX_CTRL_SIZE, PCI_MSIX_DESC_PBA, PCI_MSIX_DESC_TABLE, pci_msix_ioremap(), pci_msix_map(), pci_read_config_word(), pci_write_config_word(), rc, and pci_msix::table.

Referenced by gve_probe(), and intelxl_msix_enable().

◆ pci_msix_disable()

void pci_msix_disable ( struct pci_device pci,
struct pci_msix msix 
)

Disable MSI-X interrupts.

Parameters
pciPCI device
msixMSI-X capability

Definition at line 207 of file pcimsix.c.

207  {
208  uint16_t ctrl;
209 
210  /* Disable MSI-X */
211  pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
213  pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
214 
215  /* Free dummy target */
216  dma_free ( &msix->map, msix->msg, sizeof ( *msix->msg ) );
217 
218  /* Unmap pending bit array */
219  iounmap ( msix->pba );
220 
221  /* Unmap MSI-X table */
222  iounmap ( msix->table );
223 }
unsigned short uint16_t
Definition: stdint.h:11
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
struct pci_device * pci
PCI device.
Definition: pcibridge.h:19
#define PCI_MSIX_CTRL
MSI-X interrupts.
Definition: pci.h:115
unsigned int cap
Capability offset.
Definition: pcimsix.h:36
uint32_t * msg
Dummy message target.
Definition: pcimsix.h:44
void * table
MSI-X table.
Definition: pcimsix.h:40
uint8_t ctrl
Ring control.
Definition: dwmac.h:18
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define PCI_MSIX_CTRL_ENABLE
Enable MSI-X.
Definition: pci.h:116
struct dma_mapping map
Dummy message target mapping.
Definition: pcimsix.h:46
void * pba
Pending bit array.
Definition: pcimsix.h:42

References pci_msix::cap, ctrl, dma_free(), iounmap(), pci_msix::map, pci_msix::msg, pci_msix::pba, PCI_MSIX_CTRL, PCI_MSIX_CTRL_ENABLE, pci_read_config_word(), pci_write_config_word(), and pci_msix::table.

Referenced by gve_probe(), gve_remove(), intelxl_msix_disable(), and intelxl_msix_enable().

◆ pci_msix_map()

void pci_msix_map ( struct pci_msix msix,
unsigned int  vector,
physaddr_t  address,
uint32_t  data 
)

Map MSI-X interrupt vector.

Parameters
msixMSI-X capability
vectorMSI-X vector
addressMessage address
dataMessage data

Definition at line 233 of file pcimsix.c.

234  {
235  void *base;
236 
237  /* Sanity check */
238  assert ( vector < msix->count );
239 
240  /* Map interrupt vector */
241  base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
242  writel ( ( address & 0xffffffffUL ), ( base + PCI_MSIX_ADDRESS_LO ) );
243  if ( sizeof ( address ) > sizeof ( uint32_t ) ) {
244  writel ( ( ( ( uint64_t ) address ) >> 32 ),
245  ( base + PCI_MSIX_ADDRESS_HI ) );
246  } else {
247  writel ( 0, ( base + PCI_MSIX_ADDRESS_HI ) );
248  }
249  writel ( data, ( base + PCI_MSIX_DATA ) );
250 }
uint32_t base
Base.
Definition: librm.h:138
uint32_t vector
MSI-X vector.
Definition: ena.h:20
uint64_t address
Base address.
Definition: ena.h:24
unsigned long long uint64_t
Definition: stdint.h:13
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static unsigned int count
Number of entries.
Definition: dwmac.h:225
#define PCI_MSIX_VECTOR(n)
MSI-X vector offset.
Definition: pcimsix.h:18
void * table
MSI-X table.
Definition: pcimsix.h:40
unsigned int uint32_t
Definition: stdint.h:12
#define PCI_MSIX_ADDRESS_LO
MSI-X vector address low 32 bits.
Definition: pcimsix.h:21
#define PCI_MSIX_DATA
MSI-X vector data.
Definition: pcimsix.h:27
uint8_t data[48]
Additional event data.
Definition: ena.h:22
#define PCI_MSIX_ADDRESS_HI
MSI-X vector address high 32 bits.
Definition: pcimsix.h:24

References address, assert(), base, count, data, PCI_MSIX_ADDRESS_HI, PCI_MSIX_ADDRESS_LO, PCI_MSIX_DATA, PCI_MSIX_VECTOR, pci_msix::table, vector, and writel().

Referenced by pci_msix_enable().

◆ pci_msix_control()

void pci_msix_control ( struct pci_msix msix,
unsigned int  vector,
uint32_t  mask 
)

Control MSI-X interrupt vector.

Parameters
msixMSI-X capability
vectorMSI-X vector
maskControl mask

Definition at line 259 of file pcimsix.c.

260  {
261  void *base;
262  uint32_t ctrl;
263 
264  /* Mask/unmask interrupt vector */
265  base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
268  ctrl |= mask;
269  writel ( ctrl, ( base + PCI_MSIX_CONTROL ) );
270 }
uint32_t base
Base.
Definition: librm.h:138
uint32_t vector
MSI-X vector.
Definition: ena.h:20
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define PCI_MSIX_CONTROL
MSI-X vector control.
Definition: pcimsix.h:30
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define PCI_MSIX_VECTOR(n)
MSI-X vector offset.
Definition: pcimsix.h:18
void * table
MSI-X table.
Definition: pcimsix.h:40
unsigned int uint32_t
Definition: stdint.h:12
#define PCI_MSIX_CONTROL_MASK
Vector is masked.
Definition: pcimsix.h:31
uint8_t ctrl
Ring control.
Definition: dwmac.h:18

References base, ctrl, PCI_MSIX_CONTROL, PCI_MSIX_CONTROL_MASK, PCI_MSIX_VECTOR, readl(), pci_msix::table, vector, and writel().

Referenced by pci_msix_mask(), and pci_msix_unmask().

◆ pci_msix_dump()

void pci_msix_dump ( struct pci_msix msix,
unsigned int  vector 
)

Dump MSI-X interrupt state (for debugging)

Parameters
msixMSI-X capability
vectorMSI-X vector

Definition at line 278 of file pcimsix.c.

278  {
279  void *base;
280  uint32_t address_hi;
281  uint32_t address_lo;
283  uint32_t data;
284  uint32_t ctrl;
285  uint32_t pba;
286 
287  /* Do nothing in non-debug builds */
288  if ( ! DBG_LOG )
289  return;
290 
291  /* Mask/unmask interrupt vector */
292  base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
293  address_hi = readl ( base + PCI_MSIX_ADDRESS_HI );
294  address_lo = readl ( base + PCI_MSIX_ADDRESS_LO );
295  data = readl ( base + PCI_MSIX_DATA );
297  pba = readl ( msix->pba );
298  address = ( ( ( ( uint64_t ) address_hi ) << 32 ) | address_lo );
299  DBGC ( msix, "MSI-X %p vector %d %#08x => %#08lx%s%s\n",
300  msix, vector, data, address,
301  ( ( ctrl & PCI_MSIX_CONTROL_MASK ) ? " (masked)" : "" ),
302  ( ( pba & ( 1 << vector ) ) ? " (pending)" : "" ) );
303 }
uint32_t base
Base.
Definition: librm.h:138
uint32_t vector
MSI-X vector.
Definition: ena.h:20
uint64_t address
Base address.
Definition: ena.h:24
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
unsigned long long uint64_t
Definition: stdint.h:13
#define PCI_MSIX_CONTROL
MSI-X vector control.
Definition: pcimsix.h:30
#define PCI_MSIX_VECTOR(n)
MSI-X vector offset.
Definition: pcimsix.h:18
void * table
MSI-X table.
Definition: pcimsix.h:40
unsigned int uint32_t
Definition: stdint.h:12
#define PCI_MSIX_ADDRESS_LO
MSI-X vector address low 32 bits.
Definition: pcimsix.h:21
unsigned long physaddr_t
Definition: stdint.h:20
#define PCI_MSIX_DATA
MSI-X vector data.
Definition: pcimsix.h:27
#define PCI_MSIX_CONTROL_MASK
Vector is masked.
Definition: pcimsix.h:31
uint8_t ctrl
Ring control.
Definition: dwmac.h:18
uint8_t data[48]
Additional event data.
Definition: ena.h:22
#define DBG_LOG
Definition: compiler.h:317
#define PCI_MSIX_ADDRESS_HI
MSI-X vector address high 32 bits.
Definition: pcimsix.h:24
void * pba
Pending bit array.
Definition: pcimsix.h:42

References address, base, ctrl, data, DBG_LOG, DBGC, pci_msix::pba, PCI_MSIX_ADDRESS_HI, PCI_MSIX_ADDRESS_LO, PCI_MSIX_CONTROL, PCI_MSIX_CONTROL_MASK, PCI_MSIX_DATA, PCI_MSIX_VECTOR, readl(), pci_msix::table, and vector.

◆ pci_msix_mask()

static void pci_msix_mask ( struct pci_msix msix,
unsigned int  vector 
)
inlinestatic

Mask MSI-X interrupt vector.

Parameters
msixMSI-X capability
vectorMSI-X vector

Definition at line 64 of file pcimsix.h.

64  {
65 
67 }
void pci_msix_control(struct pci_msix *msix, unsigned int vector, uint32_t mask)
Control MSI-X interrupt vector.
Definition: pcimsix.c:259
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define PCI_MSIX_CONTROL_MASK
Vector is masked.
Definition: pcimsix.h:31

References pci_msix_control(), PCI_MSIX_CONTROL_MASK, and vector.

Referenced by gve_destroy_queue(), and intelxl_msix_disable().

◆ pci_msix_unmask()

static void pci_msix_unmask ( struct pci_msix msix,
unsigned int  vector 
)
inlinestatic

Unmask MSI-X interrupt vector.

Parameters
msixMSI-X capability
vectorMSI-X vector

Definition at line 76 of file pcimsix.h.

76  {
77 
78  pci_msix_control ( msix, vector, 0 );
79 }
void pci_msix_control(struct pci_msix *msix, unsigned int vector, uint32_t mask)
Control MSI-X interrupt vector.
Definition: pcimsix.c:259
uint32_t vector
MSI-X vector.
Definition: ena.h:20

References pci_msix_control(), and vector.

Referenced by gve_create_queue(), and intelxl_msix_enable().