iPXE
intelxl.c
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1 /*
2  * Copyright (C) 2018 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  * You can also choose to distribute this program under the terms of
20  * the Unmodified Binary Distribution Licence (as given in the file
21  * COPYING.UBDL), provided that you have satisfied its requirements.
22  */
23 
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25 
26 #include <stdint.h>
27 #include <string.h>
28 #include <stdio.h>
29 #include <unistd.h>
30 #include <errno.h>
31 #include <byteswap.h>
32 #include <ipxe/netdevice.h>
33 #include <ipxe/ethernet.h>
34 #include <ipxe/if_ether.h>
35 #include <ipxe/vlan.h>
36 #include <ipxe/iobuf.h>
37 #include <ipxe/pci.h>
38 #include <ipxe/version.h>
39 #include "intelxl.h"
40 
41 /** @file
42  *
43  * Intel 40 Gigabit Ethernet network card driver
44  *
45  */
46 
47 /******************************************************************************
48  *
49  * Device reset
50  *
51  ******************************************************************************
52  */
53 
54 /**
55  * Reset hardware
56  *
57  * @v intelxl Intel device
58  * @ret rc Return status code
59  */
60 static int intelxl_reset ( struct intelxl_nic *intelxl ) {
61  uint32_t pfgen_ctrl;
62 
63  /* Perform a global software reset */
64  pfgen_ctrl = readl ( intelxl->regs + INTELXL_PFGEN_CTRL );
65  writel ( ( pfgen_ctrl | INTELXL_PFGEN_CTRL_PFSWR ),
66  intelxl->regs + INTELXL_PFGEN_CTRL );
68 
69  return 0;
70 }
71 
72 /******************************************************************************
73  *
74  * MAC address
75  *
76  ******************************************************************************
77  */
78 
79 /**
80  * Fetch initial MAC address and maximum frame size
81  *
82  * @v intelxl Intel device
83  * @v netdev Network device
84  * @ret rc Return status code
85  */
86 static int intelxl_fetch_mac ( struct intelxl_nic *intelxl,
87  struct net_device *netdev ) {
89  uint32_t prtpm_sal;
90  uint32_t prtpm_sah;
91  uint32_t prtgl_sah;
92  size_t mfs;
93 
94  /* Read NVM-loaded address */
95  prtpm_sal = readl ( intelxl->regs + INTELXL_PRTPM_SAL );
96  prtpm_sah = readl ( intelxl->regs + INTELXL_PRTPM_SAH );
97  mac.reg.low = cpu_to_le32 ( prtpm_sal );
98  mac.reg.high = cpu_to_le32 ( prtpm_sah );
99 
100  /* Check that address is valid */
101  if ( ! is_valid_ether_addr ( mac.raw ) ) {
102  DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
103  intelxl, eth_ntoa ( mac.raw ) );
104  return -ENOENT;
105  }
106 
107  /* Copy MAC address */
108  DBGC ( intelxl, "INTELXL %p has autoloaded MAC address %s\n",
109  intelxl, eth_ntoa ( mac.raw ) );
110  memcpy ( netdev->hw_addr, mac.raw, ETH_ALEN );
111 
112  /* Get maximum frame size */
113  prtgl_sah = readl ( intelxl->regs + INTELXL_PRTGL_SAH );
114  mfs = INTELXL_PRTGL_SAH_MFS_GET ( prtgl_sah );
115  netdev->max_pkt_len = ( mfs - 4 /* CRC */ );
116 
117  return 0;
118 }
119 
120 /******************************************************************************
121  *
122  * MSI-X interrupts
123  *
124  ******************************************************************************
125  */
126 
127 /**
128  * Enable MSI-X dummy interrupt
129  *
130  * @v intelxl Intel device
131  * @v pci PCI device
132  * @ret rc Return status code
133  */
134 int intelxl_msix_enable ( struct intelxl_nic *intelxl,
135  struct pci_device *pci ) {
136  int rc;
137 
138  /* Map dummy target location */
139  if ( ( rc = dma_map ( intelxl->dma, &intelxl->msix.map,
140  virt_to_phys ( &intelxl->msix.msg ),
141  sizeof ( intelxl->msix.msg ), DMA_RX ) ) != 0 ) {
142  DBGC ( intelxl, "INTELXL %p could not map MSI-X target: %s\n",
143  intelxl, strerror ( rc ) );
144  goto err_map;
145  }
146 
147  /* Enable MSI-X capability */
148  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix.cap ) ) != 0 ) {
149  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
150  intelxl, strerror ( rc ) );
151  goto err_enable;
152  }
153 
154  /* Configure interrupt zero to write to dummy location */
155  pci_msix_map ( &intelxl->msix.cap, 0,
156  dma ( &intelxl->msix.map, &intelxl->msix.msg ), 0 );
157 
158  /* Enable dummy interrupt zero */
159  pci_msix_unmask ( &intelxl->msix.cap, 0 );
160 
161  return 0;
162 
163  pci_msix_disable ( pci, &intelxl->msix.cap );
164  err_enable:
165  dma_unmap ( &intelxl->msix.map );
166  err_map:
167  return rc;
168 }
169 
170 /**
171  * Disable MSI-X dummy interrupt
172  *
173  * @v intelxl Intel device
174  * @v pci PCI device
175  */
176 void intelxl_msix_disable ( struct intelxl_nic *intelxl,
177  struct pci_device *pci ) {
178 
179  /* Disable dummy interrupt zero */
180  pci_msix_mask ( &intelxl->msix.cap, 0 );
181 
182  /* Disable MSI-X capability */
183  pci_msix_disable ( pci, &intelxl->msix.cap );
184 
185  /* Unmap dummy target location */
186  dma_unmap ( &intelxl->msix.map );
187 }
188 
189 /******************************************************************************
190  *
191  * Admin queue
192  *
193  ******************************************************************************
194  */
195 
196 /** Admin queue register offsets */
199  .bah = INTELXL_ADMIN_BAH,
200  .len = INTELXL_ADMIN_LEN,
201  .head = INTELXL_ADMIN_HEAD,
202  .tail = INTELXL_ADMIN_TAIL,
203 };
204 
205 /**
206  * Allocate admin queue
207  *
208  * @v intelxl Intel device
209  * @v admin Admin queue
210  * @ret rc Return status code
211  */
212 static int intelxl_alloc_admin ( struct intelxl_nic *intelxl,
213  struct intelxl_admin *admin ) {
214  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
215  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
216 
217  /* Allocate admin queue */
218  admin->buf = dma_alloc ( intelxl->dma, &admin->map, ( buf_len + len ),
219  INTELXL_ALIGN );
220  if ( ! admin->buf )
221  return -ENOMEM;
222  admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
223 
224  DBGC ( intelxl, "INTELXL %p A%cQ is at [%08lx,%08lx) buf "
225  "[%08lx,%08lx)\n", intelxl,
226  ( ( admin == &intelxl->command ) ? 'T' : 'R' ),
227  virt_to_phys ( admin->desc ),
228  ( virt_to_phys ( admin->desc ) + len ),
229  virt_to_phys ( admin->buf ),
230  ( virt_to_phys ( admin->buf ) + buf_len ) );
231  return 0;
232 }
233 
234 /**
235  * Enable admin queue
236  *
237  * @v intelxl Intel device
238  * @v admin Admin queue
239  */
240 static void intelxl_enable_admin ( struct intelxl_nic *intelxl,
241  struct intelxl_admin *admin ) {
242  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
243  const struct intelxl_admin_offsets *regs = admin->regs;
244  void *admin_regs = ( intelxl->regs + admin->base );
246 
247  /* Initialise admin queue */
248  memset ( admin->desc, 0, len );
249 
250  /* Reset head and tail registers */
251  writel ( 0, admin_regs + regs->head );
252  writel ( 0, admin_regs + regs->tail );
253 
254  /* Reset queue index */
255  admin->index = 0;
256 
257  /* Program queue address */
258  address = dma ( &admin->map, admin->desc );
259  writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
260  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
261  writel ( ( ( ( uint64_t ) address ) >> 32 ),
262  admin_regs + regs->bah );
263  } else {
264  writel ( 0, admin_regs + regs->bah );
265  }
266 
267  /* Program queue length and enable queue */
270  admin_regs + regs->len );
271 }
272 
273 /**
274  * Disable admin queue
275  *
276  * @v intelxl Intel device
277  * @v admin Admin queue
278  */
279 static void intelxl_disable_admin ( struct intelxl_nic *intelxl,
280  struct intelxl_admin *admin ) {
281  const struct intelxl_admin_offsets *regs = admin->regs;
282  void *admin_regs = ( intelxl->regs + admin->base );
283 
284  /* Disable queue */
285  writel ( 0, admin_regs + regs->len );
286 }
287 
288 /**
289  * Free admin queue
290  *
291  * @v intelxl Intel device
292  * @v admin Admin queue
293  */
294 static void intelxl_free_admin ( struct intelxl_nic *intelxl __unused,
295  struct intelxl_admin *admin ) {
296  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
297  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
298 
299  /* Free queue */
300  dma_free ( &admin->map, admin->buf, ( buf_len + len ) );
301 }
302 
303 /**
304  * Get next admin command queue descriptor
305  *
306  * @v intelxl Intel device
307  * @ret cmd Command descriptor
308  */
311  struct intelxl_admin *admin = &intelxl->command;
313 
314  /* Get and initialise next descriptor */
315  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
316  memset ( cmd, 0, sizeof ( *cmd ) );
317  return cmd;
318 }
319 
320 /**
321  * Get next admin command queue data buffer
322  *
323  * @v intelxl Intel device
324  * @ret buf Data buffer
325  */
326 union intelxl_admin_buffer *
328  struct intelxl_admin *admin = &intelxl->command;
329  union intelxl_admin_buffer *buf;
330 
331  /* Get next data buffer */
332  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
333  memset ( buf, 0, sizeof ( *buf ) );
334  return buf;
335 }
336 
337 /**
338  * Initialise admin event queue descriptor
339  *
340  * @v intelxl Intel device
341  * @v index Event queue index
342  */
343 static void intelxl_admin_event_init ( struct intelxl_nic *intelxl,
344  unsigned int index ) {
345  struct intelxl_admin *admin = &intelxl->event;
346  struct intelxl_admin_descriptor *evt;
347  union intelxl_admin_buffer *buf;
349 
350  /* Initialise descriptor */
351  evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
352  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
353  address = dma ( &admin->map, buf );
355  evt->len = cpu_to_le16 ( sizeof ( *buf ) );
356  evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
357  evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
358 }
359 
360 /**
361  * Issue admin queue command
362  *
363  * @v intelxl Intel device
364  * @ret rc Return status code
365  */
366 int intelxl_admin_command ( struct intelxl_nic *intelxl ) {
367  struct intelxl_admin *admin = &intelxl->command;
368  const struct intelxl_admin_offsets *regs = admin->regs;
369  void *admin_regs = ( intelxl->regs + admin->base );
371  union intelxl_admin_buffer *buf;
373  uint32_t cookie;
374  unsigned int index;
375  unsigned int tail;
376  unsigned int i;
377  int rc;
378 
379  /* Get next queue entry */
380  index = admin->index++;
381  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
382  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
383  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
384  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
385  intelxl, index, le16_to_cpu ( cmd->opcode ) );
386  if ( cmd->vopcode )
387  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->vopcode ) );
388  DBGC2 ( intelxl, ":\n" );
389 
390  /* Sanity checks */
391  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
392  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
393  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
394  assert ( cmd->ret == 0 );
395 
396  /* Populate data buffer address if applicable */
397  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
398  address = dma ( &admin->map, buf );
399  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
400  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
401  }
402 
403  /* Populate cookie, if not being (ab)used for VF opcode */
404  if ( ! cmd->vopcode )
405  cmd->cookie = cpu_to_le32 ( index );
406 
407  /* Record cookie */
408  cookie = cmd->cookie;
409 
410  /* Post command descriptor */
411  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
412  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
413  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
414  le16_to_cpu ( cmd->len ) );
415  }
416  wmb();
417  writel ( tail, admin_regs + regs->tail );
418 
419  /* Wait for completion */
420  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
421 
422  /* If response is not complete, delay 1ms and retry */
423  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
424  mdelay ( 1 );
425  continue;
426  }
427  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
428  intelxl, index );
429  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
430  sizeof ( *cmd ) );
431 
432  /* Check for cookie mismatch */
433  if ( cmd->cookie != cookie ) {
434  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
435  "cookie %#x\n", intelxl, index,
436  le32_to_cpu ( cmd->cookie ) );
437  rc = -EPROTO;
438  goto err;
439  }
440 
441  /* Check for errors */
442  if ( cmd->ret != 0 ) {
443  DBGC ( intelxl, "INTELXL %p admin command %#x error "
444  "%d\n", intelxl, index,
445  le16_to_cpu ( cmd->ret ) );
446  rc = -EIO;
447  goto err;
448  }
449 
450  /* Success */
451  return 0;
452  }
453 
454  rc = -ETIMEDOUT;
455  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
456  intelxl, index );
457  err:
458  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
459  return rc;
460 }
461 
462 /**
463  * Get firmware version
464  *
465  * @v intelxl Intel device
466  * @ret rc Return status code
467  */
468 static int intelxl_admin_version ( struct intelxl_nic *intelxl ) {
471  unsigned int api;
472  int rc;
473 
474  /* Populate descriptor */
476  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
477  version = &cmd->params.version;
478 
479  /* Issue command */
480  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
481  return rc;
482  api = le16_to_cpu ( version->api.major );
483  DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
484  intelxl, le16_to_cpu ( version->firmware.major ),
485  le16_to_cpu ( version->firmware.minor ),
486  api, le16_to_cpu ( version->api.minor ) );
487 
488  /* Check for API compatibility */
489  if ( api > INTELXL_ADMIN_API_MAJOR ) {
490  DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
491  intelxl, api );
492  return -ENOTSUP;
493  }
494 
495  return 0;
496 }
497 
498 /**
499  * Report driver version
500  *
501  * @v intelxl Intel device
502  * @ret rc Return status code
503  */
504 static int intelxl_admin_driver ( struct intelxl_nic *intelxl ) {
506  struct intelxl_admin_driver_params *driver;
507  union intelxl_admin_buffer *buf;
508  int rc;
509 
510  /* Populate descriptor */
512  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
514  cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
515  driver = &cmd->params.driver;
516  driver->major = product_major_version;
517  driver->minor = product_minor_version;
518  buf = intelxl_admin_command_buffer ( intelxl );
519  snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
521 
522  /* Issue command */
523  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
524  return rc;
525 
526  return 0;
527 }
528 
529 /**
530  * Shutdown admin queues
531  *
532  * @v intelxl Intel device
533  * @ret rc Return status code
534  */
535 static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
538  int rc;
539 
540  /* Populate descriptor */
542  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
543  shutdown = &cmd->params.shutdown;
545 
546  /* Issue command */
547  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
548  return rc;
549 
550  return 0;
551 }
552 
553 /**
554  * Clear PXE mode
555  *
556  * @v intelxl Intel device
557  * @ret rc Return status code
558  */
559 static int intelxl_admin_clear_pxe ( struct intelxl_nic *intelxl ) {
561  struct intelxl_admin_clear_pxe_params *pxe;
562  uint32_t gllan_rctl_0;
563  int rc;
564 
565  /* Do nothing if device is already out of PXE mode */
566  gllan_rctl_0 = readl ( intelxl->regs + INTELXL_GLLAN_RCTL_0 );
567  if ( ! ( gllan_rctl_0 & INTELXL_GLLAN_RCTL_0_PXE_MODE ) ) {
568  DBGC2 ( intelxl, "INTELXL %p already in non-PXE mode\n",
569  intelxl );
570  return 0;
571  }
572 
573  /* Populate descriptor */
576  pxe = &cmd->params.pxe;
578 
579  /* Issue command */
580  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
581  return rc;
582 
583  return 0;
584 }
585 
586 /**
587  * Get switch configuration
588  *
589  * @v intelxl Intel device
590  * @ret rc Return status code
591  */
592 static int intelxl_admin_switch ( struct intelxl_nic *intelxl ) {
594  struct intelxl_admin_switch_params *sw;
595  union intelxl_admin_buffer *buf;
596  int rc;
597 
598  /* Populate descriptor */
600  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
601  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
602  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
603  sw = &cmd->params.sw;
604  buf = intelxl_admin_command_buffer ( intelxl );
605 
606  /* Get each configuration in turn */
607  do {
608  /* Issue command */
609  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
610  return rc;
611 
612  /* Dump raw configuration */
613  DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
614  intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
615  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
616 
617  /* Parse response */
618  if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
619  intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
620  DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
621  "downlink %#04x conn %#02x\n", intelxl,
622  intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
623  le16_to_cpu ( buf->sw.cfg.downlink ),
624  buf->sw.cfg.connection );
625  }
626 
627  } while ( sw->next );
628 
629  /* Check that we found a VSI */
630  if ( ! intelxl->vsi ) {
631  DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
632  return -ENOENT;
633  }
634 
635  return 0;
636 }
637 
638 /**
639  * Get VSI parameters
640  *
641  * @v intelxl Intel device
642  * @ret rc Return status code
643  */
644 static int intelxl_admin_vsi ( struct intelxl_nic *intelxl ) {
647  union intelxl_admin_buffer *buf;
648  int rc;
649 
650  /* Populate descriptor */
652  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
653  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
654  cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
655  vsi = &cmd->params.vsi;
656  vsi->vsi = cpu_to_le16 ( intelxl->vsi );
657  buf = intelxl_admin_command_buffer ( intelxl );
658 
659  /* Issue command */
660  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
661  return rc;
662 
663  /* Parse response */
664  intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
665  intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
666  DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
667  intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
668 
669  return 0;
670 }
671 
672 /**
673  * Set VSI promiscuous modes
674  *
675  * @v intelxl Intel device
676  * @ret rc Return status code
677  */
678 static int intelxl_admin_promisc ( struct intelxl_nic *intelxl ) {
680  struct intelxl_admin_promisc_params *promisc;
681  uint16_t flags;
682  int rc;
683 
684  /* Populate descriptor */
686  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
691  promisc = &cmd->params.promisc;
692  promisc->flags = cpu_to_le16 ( flags );
693  promisc->valid = cpu_to_le16 ( flags );
694  promisc->vsi = cpu_to_le16 ( intelxl->vsi );
695 
696  /* Issue command */
697  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
698  return rc;
699 
700  return 0;
701 }
702 
703 /**
704  * Restart autonegotiation
705  *
706  * @v intelxl Intel device
707  * @ret rc Return status code
708  */
709 static int intelxl_admin_autoneg ( struct intelxl_nic *intelxl ) {
711  struct intelxl_admin_autoneg_params *autoneg;
712  int rc;
713 
714  /* Populate descriptor */
716  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
717  autoneg = &cmd->params.autoneg;
720 
721  /* Issue command */
722  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
723  return rc;
724 
725  return 0;
726 }
727 
728 /**
729  * Get link status
730  *
731  * @v netdev Network device
732  * @ret rc Return status code
733  */
734 static int intelxl_admin_link ( struct net_device *netdev ) {
735  struct intelxl_nic *intelxl = netdev->priv;
738  int rc;
739 
740  /* Populate descriptor */
742  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
743  link = &cmd->params.link;
745 
746  /* Issue command */
747  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
748  return rc;
749  DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
750  intelxl, link->phy, link->speed, link->status );
751 
752  /* Update network device */
753  if ( link->status & INTELXL_ADMIN_LINK_UP ) {
755  } else {
757  }
758 
759  return 0;
760 }
761 
762 /**
763  * Handle virtual function event (when VF driver is not present)
764  *
765  * @v netdev Network device
766  * @v evt Admin queue event descriptor
767  * @v buf Admin queue event data buffer
768  */
769 __weak void
772  union intelxl_admin_buffer *buf __unused ) {
773 
774  /* Nothing to do */
775 }
776 
777 /**
778  * Refill admin event queue
779  *
780  * @v intelxl Intel device
781  */
782 static void intelxl_refill_admin ( struct intelxl_nic *intelxl ) {
783  struct intelxl_admin *admin = &intelxl->event;
784  const struct intelxl_admin_offsets *regs = admin->regs;
785  void *admin_regs = ( intelxl->regs + admin->base );
786  unsigned int tail;
787 
788  /* Update tail pointer */
789  tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
791  wmb();
792  writel ( tail, admin_regs + regs->tail );
793 }
794 
795 /**
796  * Poll admin event queue
797  *
798  * @v netdev Network device
799  */
801  struct intelxl_nic *intelxl = netdev->priv;
802  struct intelxl_admin *admin = &intelxl->event;
803  struct intelxl_admin_descriptor *evt;
804  union intelxl_admin_buffer *buf;
805 
806  /* Check for events */
807  while ( 1 ) {
808 
809  /* Get next event descriptor and data buffer */
810  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
811  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
812 
813  /* Stop if descriptor is not yet completed */
814  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
815  return;
816  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
817  intelxl, admin->index );
818  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
819  sizeof ( *evt ) );
820  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
821  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
822  le16_to_cpu ( evt->len ) );
823  }
824 
825  /* Handle event */
826  switch ( evt->opcode ) {
829  break;
831  intelxlvf_admin_event ( netdev, evt, buf );
832  break;
833  default:
834  DBGC ( intelxl, "INTELXL %p admin event %#x "
835  "unrecognised opcode %#04x\n", intelxl,
836  admin->index, le16_to_cpu ( evt->opcode ) );
837  break;
838  }
839 
840  /* Reset descriptor and refill queue */
841  intelxl_admin_event_init ( intelxl, admin->index );
842  admin->index++;
843  intelxl_refill_admin ( intelxl );
844  }
845 }
846 
847 /**
848  * Open admin queues
849  *
850  * @v intelxl Intel device
851  * @ret rc Return status code
852  */
853 int intelxl_open_admin ( struct intelxl_nic *intelxl ) {
854  int rc;
855 
856  /* Allocate admin event queue */
857  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
858  goto err_alloc_event;
859 
860  /* Allocate admin command queue */
861  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
862  goto err_alloc_command;
863 
864  /* (Re)open admin queues */
865  intelxl_reopen_admin ( intelxl );
866 
867  /* Get firmware version */
868  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
869  goto err_version;
870 
871  /* Report driver version */
872  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
873  goto err_driver;
874 
875  return 0;
876 
877  err_driver:
878  err_version:
879  intelxl_disable_admin ( intelxl, &intelxl->command );
880  intelxl_disable_admin ( intelxl, &intelxl->event );
881  intelxl_free_admin ( intelxl, &intelxl->command );
882  err_alloc_command:
883  intelxl_free_admin ( intelxl, &intelxl->event );
884  err_alloc_event:
885  return rc;
886 }
887 
888 /**
889  * Reopen admin queues (after virtual function reset)
890  *
891  * @v intelxl Intel device
892  */
893 void intelxl_reopen_admin ( struct intelxl_nic *intelxl ) {
894  unsigned int i;
895 
896  /* Enable admin event queue */
897  intelxl_enable_admin ( intelxl, &intelxl->event );
898 
899  /* Enable admin command queue */
900  intelxl_enable_admin ( intelxl, &intelxl->command );
901 
902  /* Initialise all admin event queue descriptors */
903  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
904  intelxl_admin_event_init ( intelxl, i );
905 
906  /* Post all descriptors to event queue */
907  intelxl_refill_admin ( intelxl );
908 }
909 
910 /**
911  * Close admin queues
912  *
913  * @v intelxl Intel device
914  */
915 void intelxl_close_admin ( struct intelxl_nic *intelxl ) {
916 
917  /* Shut down admin queues */
918  intelxl_admin_shutdown ( intelxl );
919 
920  /* Disable admin queues */
921  intelxl_disable_admin ( intelxl, &intelxl->command );
922  intelxl_disable_admin ( intelxl, &intelxl->event );
923 
924  /* Free admin queues */
925  intelxl_free_admin ( intelxl, &intelxl->command );
926  intelxl_free_admin ( intelxl, &intelxl->event );
927 }
928 
929 /******************************************************************************
930  *
931  * Descriptor rings
932  *
933  ******************************************************************************
934  */
935 
936 /**
937  * Allocate descriptor ring
938  *
939  * @v intelxl Intel device
940  * @v ring Descriptor ring
941  * @ret rc Return status code
942  */
943 int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
944  struct intelxl_ring *ring ) {
945  int rc;
946 
947  /* Allocate descriptor ring */
948  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
949  INTELXL_ALIGN );
950  if ( ! ring->desc.raw ) {
951  rc = -ENOMEM;
952  goto err_alloc;
953  }
954 
955  /* Initialise descriptor ring */
956  memset ( ring->desc.raw, 0, ring->len );
957 
958  /* Reset tail pointer */
959  writel ( 0, ( intelxl->regs + ring->tail ) );
960 
961  /* Reset counters */
962  ring->prod = 0;
963  ring->cons = 0;
964 
965  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
966  intelxl, ( ring->reg + ring->tail ),
967  virt_to_phys ( ring->desc.raw ),
968  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
969 
970  return 0;
971 
972  dma_free ( &ring->map, ring->desc.raw, ring->len );
973  err_alloc:
974  return rc;
975 }
976 
977 /**
978  * Free descriptor ring
979  *
980  * @v intelxl Intel device
981  * @v ring Descriptor ring
982  */
983 void intelxl_free_ring ( struct intelxl_nic *intelxl __unused,
984  struct intelxl_ring *ring ) {
985 
986  /* Free descriptor ring */
987  dma_free ( &ring->map, ring->desc.raw, ring->len );
988  ring->desc.raw = NULL;
989 }
990 
991 /**
992  * Dump queue context (for debugging)
993  *
994  * @v intelxl Intel device
995  * @v op Context operation
996  * @v len Size of context
997  */
998 static __attribute__ (( unused )) void
999 intelxl_context_dump ( struct intelxl_nic *intelxl, uint32_t op, size_t len ) {
1000  struct intelxl_context_line line;
1001  uint32_t pfcm_lanctxctl;
1002  uint32_t pfcm_lanctxstat;
1003  unsigned int queue;
1004  unsigned int index;
1005  unsigned int i;
1006 
1007  /* Do nothing unless debug output is enabled */
1008  if ( ! DBG_EXTRA )
1009  return;
1010 
1011  /* Dump context */
1012  DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
1013  for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
1014 
1015  /* Start context operation */
1016  queue = ( intelxl->base + intelxl->queue );
1017  pfcm_lanctxctl =
1021  writel ( pfcm_lanctxctl,
1022  intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1023 
1024  /* Wait for operation to complete */
1025  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1026 
1027  /* Check if operation is complete */
1028  pfcm_lanctxstat = readl ( intelxl->regs +
1030  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1031  break;
1032 
1033  /* Delay */
1034  mdelay ( 1 );
1035  }
1036 
1037  /* Read context data */
1038  for ( i = 0 ; i < ( sizeof ( line ) /
1039  sizeof ( line.raw[0] ) ) ; i++ ) {
1040  line.raw[i] = readl ( intelxl->regs +
1041  INTELXL_PFCM_LANCTXDATA ( i ) );
1042  }
1043  DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
1044  &line, sizeof ( line ) );
1045  }
1046 }
1047 
1048 /**
1049  * Program queue context line
1050  *
1051  * @v intelxl Intel device
1052  * @v line Queue context line
1053  * @v index Line number
1054  * @v op Context operation
1055  * @ret rc Return status code
1056  */
1057 static int intelxl_context_line ( struct intelxl_nic *intelxl,
1058  struct intelxl_context_line *line,
1059  unsigned int index, uint32_t op ) {
1060  uint32_t pfcm_lanctxctl;
1061  uint32_t pfcm_lanctxstat;
1062  unsigned int queue;
1063  unsigned int i;
1064 
1065  /* Write context data */
1066  for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
1067  writel ( le32_to_cpu ( line->raw[i] ),
1068  intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
1069  }
1070 
1071  /* Start context operation */
1072  queue = ( intelxl->base + intelxl->queue );
1073  pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
1076  writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1077 
1078  /* Wait for operation to complete */
1079  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1080 
1081  /* Check if operation is complete */
1082  pfcm_lanctxstat = readl ( intelxl->regs +
1084  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1085  return 0;
1086 
1087  /* Delay */
1088  mdelay ( 1 );
1089  }
1090 
1091  DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
1092  intelxl, pfcm_lanctxctl );
1093  return -ETIMEDOUT;
1094 }
1095 
1096 /**
1097  * Program queue context
1098  *
1099  * @v intelxl Intel device
1100  * @v line Queue context lines
1101  * @v len Size of context
1102  * @v op Context operation
1103  * @ret rc Return status code
1104  */
1105 static int intelxl_context ( struct intelxl_nic *intelxl,
1106  struct intelxl_context_line *line,
1107  size_t len, uint32_t op ) {
1108  unsigned int index;
1109  int rc;
1110 
1111  DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
1112  intelxl, op, len );
1113  DBGC2_HDA ( intelxl, 0, line, len );
1114 
1115  /* Program one line at a time */
1116  for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
1117  if ( ( rc = intelxl_context_line ( intelxl, line++, index,
1118  op ) ) != 0 )
1119  return rc;
1120  }
1121 
1122  return 0;
1123 }
1124 
1125 /**
1126  * Program transmit queue context
1127  *
1128  * @v intelxl Intel device
1129  * @v address Descriptor ring base address
1130  * @ret rc Return status code
1131  */
1132 static int intelxl_context_tx ( struct intelxl_nic *intelxl,
1133  physaddr_t address ) {
1134  union {
1135  struct intelxl_context_tx tx;
1136  struct intelxl_context_line line;
1137  } ctx;
1138  int rc;
1139 
1140  /* Initialise context */
1141  memset ( &ctx, 0, sizeof ( ctx ) );
1142  ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
1143  ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
1144  ctx.tx.count =
1146  ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
1147 
1148  /* Program context */
1149  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1151  return rc;
1152 
1153  return 0;
1154 }
1155 
1156 /**
1157  * Program receive queue context
1158  *
1159  * @v intelxl Intel device
1160  * @v address Descriptor ring base address
1161  * @ret rc Return status code
1162  */
1163 static int intelxl_context_rx ( struct intelxl_nic *intelxl,
1164  physaddr_t address ) {
1165  union {
1166  struct intelxl_context_rx rx;
1167  struct intelxl_context_line line;
1168  } ctx;
1169  uint64_t base_count;
1170  int rc;
1171 
1172  /* Initialise context */
1173  memset ( &ctx, 0, sizeof ( ctx ) );
1175  ctx.rx.base_count = cpu_to_le64 ( base_count );
1176  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
1178  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
1179 
1180  /* Program context */
1181  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1183  return rc;
1184 
1185  return 0;
1186 }
1187 
1188 /**
1189  * Enable descriptor ring
1190  *
1191  * @v intelxl Intel device
1192  * @v ring Descriptor ring
1193  * @ret rc Return status code
1194  */
1195 static int intelxl_enable_ring ( struct intelxl_nic *intelxl,
1196  struct intelxl_ring *ring ) {
1197  void *ring_regs = ( intelxl->regs + ring->reg );
1198  uint32_t qxx_ena;
1199 
1200  /* Enable ring */
1201  writel ( INTELXL_QXX_ENA_REQ, ( ring_regs + INTELXL_QXX_ENA ) );
1203  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1204  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) ) {
1205  DBGC ( intelxl, "INTELXL %p ring %06x failed to enable: "
1206  "%#08x\n", intelxl, ring->reg, qxx_ena );
1207  return -EIO;
1208  }
1209 
1210  return 0;
1211 }
1212 
1213 /**
1214  * Disable descriptor ring
1215  *
1216  * @v intelxl Intel device
1217  * @v ring Descriptor ring
1218  * @ret rc Return status code
1219  */
1220 static int intelxl_disable_ring ( struct intelxl_nic *intelxl,
1221  struct intelxl_ring *ring ) {
1222  void *ring_regs = ( intelxl->regs + ring->reg );
1223  uint32_t qxx_ena;
1224  unsigned int i;
1225 
1226  /* Disable ring */
1227  writel ( 0, ( ring_regs + INTELXL_QXX_ENA ) );
1228 
1229  /* Wait for ring to be disabled */
1230  for ( i = 0 ; i < INTELXL_QUEUE_DISABLE_MAX_WAIT_MS ; i++ ) {
1231 
1232  /* Check if ring is disabled */
1233  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1234  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) )
1235  return 0;
1236 
1237  /* Delay */
1238  mdelay ( 1 );
1239  }
1240 
1241  DBGC ( intelxl, "INTELXL %p ring %06x timed out waiting for disable: "
1242  "%#08x\n", intelxl, ring->reg, qxx_ena );
1243  return -ETIMEDOUT;
1244 }
1245 
1246 /**
1247  * Create descriptor ring
1248  *
1249  * @v intelxl Intel device
1250  * @v ring Descriptor ring
1251  * @ret rc Return status code
1252  */
1253 static int intelxl_create_ring ( struct intelxl_nic *intelxl,
1254  struct intelxl_ring *ring ) {
1256  int rc;
1257 
1258  /* Allocate descriptor ring */
1259  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1260  goto err_alloc;
1261 
1262  /* Program queue context */
1263  address = dma ( &ring->map, ring->desc.raw );
1264  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1265  goto err_context;
1266 
1267  /* Enable ring */
1268  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1269  goto err_enable;
1270 
1271  return 0;
1272 
1273  intelxl_disable_ring ( intelxl, ring );
1274  err_enable:
1275  err_context:
1276  intelxl_free_ring ( intelxl, ring );
1277  err_alloc:
1278  return rc;
1279 }
1280 
1281 /**
1282  * Destroy descriptor ring
1283  *
1284  * @v intelxl Intel device
1285  * @v ring Descriptor ring
1286  */
1287 static void intelxl_destroy_ring ( struct intelxl_nic *intelxl,
1288  struct intelxl_ring *ring ) {
1289  int rc;
1290 
1291  /* Disable ring */
1292  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1293  /* Leak memory; there's nothing else we can do */
1294  return;
1295  }
1296 
1297  /* Free descriptor ring */
1298  intelxl_free_ring ( intelxl, ring );
1299 }
1300 
1301 /**
1302  * Refill receive descriptor ring
1303  *
1304  * @v intelxl Intel device
1305  */
1306 static void intelxl_refill_rx ( struct intelxl_nic *intelxl ) {
1308  struct io_buffer *iobuf;
1309  unsigned int rx_idx;
1310  unsigned int rx_tail;
1311  unsigned int refilled = 0;
1312 
1313  /* Refill ring */
1314  while ( ( intelxl->rx.prod - intelxl->rx.cons ) < INTELXL_RX_FILL ) {
1315 
1316  /* Allocate I/O buffer */
1317  iobuf = alloc_rx_iob ( intelxl->mfs, intelxl->dma );
1318  if ( ! iobuf ) {
1319  /* Wait for next refill */
1320  break;
1321  }
1322 
1323  /* Get next receive descriptor */
1324  rx_idx = ( intelxl->rx.prod++ % INTELXL_RX_NUM_DESC );
1325  rx = &intelxl->rx.desc.rx[rx_idx].data;
1326 
1327  /* Populate receive descriptor */
1328  rx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1329  rx->flags = 0;
1330 
1331  /* Record I/O buffer */
1332  assert ( intelxl->rx_iobuf[rx_idx] == NULL );
1333  intelxl->rx_iobuf[rx_idx] = iobuf;
1334 
1335  DBGC2 ( intelxl, "INTELXL %p RX %d is [%08lx,%08lx)\n",
1336  intelxl, rx_idx, virt_to_phys ( iobuf->data ),
1337  ( virt_to_phys ( iobuf->data ) + intelxl->mfs ) );
1338  refilled++;
1339  }
1340 
1341  /* Push descriptors to card, if applicable */
1342  if ( refilled ) {
1343  wmb();
1344  rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1345  writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1346  }
1347 }
1348 
1349 /**
1350  * Discard unused receive I/O buffers
1351  *
1352  * @v intelxl Intel device
1353  */
1354 void intelxl_empty_rx ( struct intelxl_nic *intelxl ) {
1355  unsigned int i;
1356 
1357  /* Discard any unused receive buffers */
1358  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1359  if ( intelxl->rx_iobuf[i] )
1360  free_rx_iob ( intelxl->rx_iobuf[i] );
1361  intelxl->rx_iobuf[i] = NULL;
1362  }
1363 }
1364 
1365 /******************************************************************************
1366  *
1367  * Network device interface
1368  *
1369  ******************************************************************************
1370  */
1371 
1372 /**
1373  * Open network device
1374  *
1375  * @v netdev Network device
1376  * @ret rc Return status code
1377  */
1378 static int intelxl_open ( struct net_device *netdev ) {
1379  struct intelxl_nic *intelxl = netdev->priv;
1381  unsigned int queue;
1382  uint32_t prtgl_sal;
1383  uint32_t prtgl_sah;
1384  int rc;
1385 
1386  /* Calculate maximum frame size */
1387  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
1388  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
1389 
1390  /* Program MAC address and maximum frame size */
1391  memset ( &mac, 0, sizeof ( mac ) );
1392  memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
1393  prtgl_sal = le32_to_cpu ( mac.reg.low );
1394  prtgl_sah = ( le32_to_cpu ( mac.reg.high ) |
1395  INTELXL_PRTGL_SAH_MFS_SET ( intelxl->mfs ) );
1396  writel ( prtgl_sal, intelxl->regs + INTELXL_PRTGL_SAL );
1397  writel ( prtgl_sah, intelxl->regs + INTELXL_PRTGL_SAH );
1398 
1399  /* Associate transmit queue to PF */
1401  INTELXL_QXX_CTL_PFVF_PF_INDX ( intelxl->pf ) ),
1402  ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_CTL ) );
1403 
1404  /* Clear transmit pre queue disable */
1405  queue = ( intelxl->base + intelxl->queue );
1408  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1409 
1410  /* Reset transmit queue head */
1411  writel ( 0, ( intelxl->regs + INTELXL_QTX_HEAD ( intelxl->queue ) ) );
1412 
1413  /* Create receive descriptor ring */
1414  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
1415  goto err_create_rx;
1416 
1417  /* Create transmit descriptor ring */
1418  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->tx ) ) != 0 )
1419  goto err_create_tx;
1420 
1421  /* Fill receive ring */
1422  intelxl_refill_rx ( intelxl );
1423 
1424  /* Restart autonegotiation */
1425  intelxl_admin_autoneg ( intelxl );
1426 
1427  /* Update link state */
1429 
1430  return 0;
1431 
1434  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1436  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1437  err_create_tx:
1438  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1439  err_create_rx:
1440  return rc;
1441 }
1442 
1443 /**
1444  * Close network device
1445  *
1446  * @v netdev Network device
1447  */
1448 static void intelxl_close ( struct net_device *netdev ) {
1449  struct intelxl_nic *intelxl = netdev->priv;
1450  unsigned int queue;
1451 
1452  /* Dump contexts (for debugging) */
1454  sizeof ( struct intelxl_context_tx ) );
1456  sizeof ( struct intelxl_context_rx ) );
1457 
1458  /* Pre-disable transmit queue */
1459  queue = ( intelxl->base + intelxl->queue );
1462  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1464 
1465  /* Destroy transmit descriptor ring */
1466  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1467 
1468  /* Destroy receive descriptor ring */
1469  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1470 
1471  /* Discard any unused receive buffers */
1472  intelxl_empty_rx ( intelxl );
1473 }
1474 
1475 /**
1476  * Transmit packet
1477  *
1478  * @v netdev Network device
1479  * @v iobuf I/O buffer
1480  * @ret rc Return status code
1481  */
1482 int intelxl_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
1483  struct intelxl_nic *intelxl = netdev->priv;
1485  unsigned int tx_idx;
1486  unsigned int tx_tail;
1487  size_t len;
1488 
1489  /* Get next transmit descriptor */
1490  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1491  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1492  intelxl );
1493  return -ENOBUFS;
1494  }
1495  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1496  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1497  tx = &intelxl->tx.desc.tx[tx_idx].data;
1498 
1499  /* Populate transmit descriptor */
1500  len = iob_len ( iobuf );
1501  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1502  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1505  wmb();
1506 
1507  /* Notify card that there are packets ready to transmit */
1508  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1509 
1510  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1511  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1512  ( virt_to_phys ( iobuf->data ) + len ) );
1513  return 0;
1514 }
1515 
1516 /**
1517  * Poll for completed packets
1518  *
1519  * @v netdev Network device
1520  */
1521 static void intelxl_poll_tx ( struct net_device *netdev ) {
1522  struct intelxl_nic *intelxl = netdev->priv;
1523  struct intelxl_tx_writeback_descriptor *tx_wb;
1524  unsigned int tx_idx;
1525 
1526  /* Check for completed packets */
1527  while ( intelxl->tx.cons != intelxl->tx.prod ) {
1528 
1529  /* Get next transmit descriptor */
1530  tx_idx = ( intelxl->tx.cons % INTELXL_TX_NUM_DESC );
1531  tx_wb = &intelxl->tx.desc.tx[tx_idx].wb;
1532 
1533  /* Stop if descriptor is still in use */
1534  if ( ! ( tx_wb->flags & INTELXL_TX_WB_FL_DD ) )
1535  return;
1536  DBGC2 ( intelxl, "INTELXL %p TX %d complete\n",
1537  intelxl, tx_idx );
1538 
1539  /* Complete TX descriptor */
1541  intelxl->tx.cons++;
1542  }
1543 }
1544 
1545 /**
1546  * Poll for received packets
1547  *
1548  * @v netdev Network device
1549  */
1550 static void intelxl_poll_rx ( struct net_device *netdev ) {
1551  struct intelxl_nic *intelxl = netdev->priv;
1552  struct intelxl_rx_writeback_descriptor *rx_wb;
1553  struct io_buffer *iobuf;
1554  unsigned int rx_idx;
1555  unsigned int tag;
1556  size_t len;
1557 
1558  /* Check for received packets */
1559  while ( intelxl->rx.cons != intelxl->rx.prod ) {
1560 
1561  /* Get next receive descriptor */
1562  rx_idx = ( intelxl->rx.cons % INTELXL_RX_NUM_DESC );
1563  rx_wb = &intelxl->rx.desc.rx[rx_idx].wb;
1564 
1565  /* Stop if descriptor is still in use */
1566  if ( ! ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_DD ) ) )
1567  return;
1568 
1569  /* Populate I/O buffer */
1570  iobuf = intelxl->rx_iobuf[rx_idx];
1571  intelxl->rx_iobuf[rx_idx] = NULL;
1572  len = INTELXL_RX_WB_LEN ( le32_to_cpu ( rx_wb->len ) );
1573  iob_put ( iobuf, len );
1574 
1575  /* Find VLAN device, if applicable */
1576  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_VLAN ) ) {
1577  tag = VLAN_TAG ( le16_to_cpu ( rx_wb->vlan ) );
1578  } else {
1579  tag = 0;
1580  }
1581 
1582  /* Hand off to network stack */
1583  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_RXE ) ) {
1584  DBGC ( intelxl, "INTELXL %p RX %d error (length %zd, "
1585  "flags %08x)\n", intelxl, rx_idx, len,
1586  le32_to_cpu ( rx_wb->flags ) );
1587  vlan_netdev_rx_err ( netdev, tag, iobuf, -EIO );
1588  } else {
1589  DBGC2 ( intelxl, "INTELXL %p RX %d complete (length "
1590  "%zd)\n", intelxl, rx_idx, len );
1591  vlan_netdev_rx ( netdev, tag, iobuf );
1592  }
1593  intelxl->rx.cons++;
1594  }
1595 }
1596 
1597 /**
1598  * Poll for completed and received packets
1599  *
1600  * @v netdev Network device
1601  */
1602 void intelxl_poll ( struct net_device *netdev ) {
1603  struct intelxl_nic *intelxl = netdev->priv;
1604 
1605  /* Poll for completed packets */
1606  intelxl_poll_tx ( netdev );
1607 
1608  /* Poll for received packets */
1609  intelxl_poll_rx ( netdev );
1610 
1611  /* Poll for admin events */
1613 
1614  /* Refill RX ring */
1615  intelxl_refill_rx ( intelxl );
1616 
1617  /* Rearm interrupt, since otherwise receive descriptors will
1618  * be written back only after a complete cacheline (four
1619  * packets) have been received.
1620  *
1621  * There is unfortunately no efficient way to determine
1622  * whether or not rearming the interrupt is necessary. If we
1623  * are running inside a hypervisor (e.g. using a VF or PF as a
1624  * passed-through PCI device), then the MSI-X write is
1625  * redirected by the hypervisor to the real host APIC and the
1626  * host ISR then raises an interrupt within the guest. We
1627  * therefore cannot poll the nominal MSI-X target location to
1628  * watch for the value being written. We could read from the
1629  * INT_DYN_CTL register, but this is even less efficient than
1630  * just unconditionally rearming the interrupt.
1631  */
1632  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1633 }
1634 
1635 /** Network device operations */
1637  .open = intelxl_open,
1638  .close = intelxl_close,
1639  .transmit = intelxl_transmit,
1640  .poll = intelxl_poll,
1641 };
1642 
1643 /******************************************************************************
1644  *
1645  * PCI interface
1646  *
1647  ******************************************************************************
1648  */
1649 
1650 /**
1651  * Probe PCI device
1652  *
1653  * @v pci PCI device
1654  * @ret rc Return status code
1655  */
1656 static int intelxl_probe ( struct pci_device *pci ) {
1657  struct net_device *netdev;
1658  struct intelxl_nic *intelxl;
1659  uint32_t pffunc_rid;
1660  uint32_t pfgen_portnum;
1661  uint32_t pflan_qalloc;
1662  int rc;
1663 
1664  /* Allocate and initialise net device */
1665  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
1666  if ( ! netdev ) {
1667  rc = -ENOMEM;
1668  goto err_alloc;
1669  }
1671  intelxl = netdev->priv;
1672  pci_set_drvdata ( pci, netdev );
1673  netdev->dev = &pci->dev;
1674  memset ( intelxl, 0, sizeof ( *intelxl ) );
1675  intelxl->intr = INTELXL_PFINT_DYN_CTL0;
1681  sizeof ( intelxl->tx.desc.tx[0] ),
1684  sizeof ( intelxl->rx.desc.rx[0] ),
1686 
1687  /* Fix up PCI device */
1688  adjust_pci_device ( pci );
1689 
1690  /* Map registers */
1691  intelxl->regs = pci_ioremap ( pci, pci->membase, INTELXL_BAR_SIZE );
1692  if ( ! intelxl->regs ) {
1693  rc = -ENODEV;
1694  goto err_ioremap;
1695  }
1696 
1697  /* Configure DMA */
1698  intelxl->dma = &pci->dma;
1699  dma_set_mask_64bit ( intelxl->dma );
1700  netdev->dma = intelxl->dma;
1701 
1702  /* Reset the NIC */
1703  if ( ( rc = intelxl_reset ( intelxl ) ) != 0 )
1704  goto err_reset;
1705 
1706  /* Get function number, port number and base queue number */
1707  pffunc_rid = readl ( intelxl->regs + INTELXL_PFFUNC_RID );
1708  intelxl->pf = INTELXL_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
1709  pfgen_portnum = readl ( intelxl->regs + INTELXL_PFGEN_PORTNUM );
1710  intelxl->port = INTELXL_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
1711  pflan_qalloc = readl ( intelxl->regs + INTELXL_PFLAN_QALLOC );
1712  intelxl->base = INTELXL_PFLAN_QALLOC_FIRSTQ ( pflan_qalloc );
1713  DBGC ( intelxl, "INTELXL %p PF %d using port %d queues [%#04x-%#04x]\n",
1714  intelxl, intelxl->pf, intelxl->port, intelxl->base,
1715  INTELXL_PFLAN_QALLOC_LASTQ ( pflan_qalloc ) );
1716 
1717  /* Fetch MAC address and maximum frame size */
1718  if ( ( rc = intelxl_fetch_mac ( intelxl, netdev ) ) != 0 )
1719  goto err_fetch_mac;
1720 
1721  /* Enable MSI-X dummy interrupt */
1722  if ( ( rc = intelxl_msix_enable ( intelxl, pci ) ) != 0 )
1723  goto err_msix;
1724 
1725  /* Open admin queues */
1726  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
1727  goto err_open_admin;
1728 
1729  /* Clear PXE mode */
1730  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
1731  goto err_admin_clear_pxe;
1732 
1733  /* Get switch configuration */
1734  if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
1735  goto err_admin_switch;
1736 
1737  /* Get VSI configuration */
1738  if ( ( rc = intelxl_admin_vsi ( intelxl ) ) != 0 )
1739  goto err_admin_vsi;
1740 
1741  /* Configure switch for promiscuous mode */
1742  if ( ( rc = intelxl_admin_promisc ( intelxl ) ) != 0 )
1743  goto err_admin_promisc;
1744 
1745  /* Configure queue register addresses */
1746  intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1747  intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1748  intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1749  intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1750 
1751  /* Configure interrupt causes */
1754  intelxl->regs + INTELXL_QINT_TQCTL ( intelxl->queue ) );
1755  writel ( ( INTELXL_QINT_RQCTL_NEXTQ_INDX ( intelxl->queue ) |
1758  intelxl->regs + INTELXL_QINT_RQCTL ( intelxl->queue ) );
1761  intelxl->regs + INTELXL_PFINT_LNKLST0 );
1763  intelxl->regs + INTELXL_PFINT_ICR0_ENA );
1764 
1765  /* Register network device */
1766  if ( ( rc = register_netdev ( netdev ) ) != 0 )
1767  goto err_register_netdev;
1768 
1769  /* Set initial link state */
1771 
1772  return 0;
1773 
1775  err_register_netdev:
1776  err_admin_promisc:
1777  err_admin_vsi:
1778  err_admin_switch:
1779  err_admin_clear_pxe:
1780  intelxl_close_admin ( intelxl );
1781  err_open_admin:
1782  intelxl_msix_disable ( intelxl, pci );
1783  err_msix:
1784  err_fetch_mac:
1785  intelxl_reset ( intelxl );
1786  err_reset:
1787  iounmap ( intelxl->regs );
1788  err_ioremap:
1789  netdev_nullify ( netdev );
1790  netdev_put ( netdev );
1791  err_alloc:
1792  return rc;
1793 }
1794 
1795 /**
1796  * Remove PCI device
1797  *
1798  * @v pci PCI device
1799  */
1800 static void intelxl_remove ( struct pci_device *pci ) {
1801  struct net_device *netdev = pci_get_drvdata ( pci );
1802  struct intelxl_nic *intelxl = netdev->priv;
1803 
1804  /* Unregister network device */
1806 
1807  /* Close admin queues */
1808  intelxl_close_admin ( intelxl );
1809 
1810  /* Disable MSI-X dummy interrupt */
1811  intelxl_msix_disable ( intelxl, pci );
1812 
1813  /* Reset the NIC */
1814  intelxl_reset ( intelxl );
1815 
1816  /* Free network device */
1817  iounmap ( intelxl->regs );
1818  netdev_nullify ( netdev );
1819  netdev_put ( netdev );
1820 }
1821 
1822 /** PCI device IDs */
1823 static struct pci_device_id intelxl_nics[] = {
1824  PCI_ROM ( 0x8086, 0x1572, "x710-sfp", "X710 10GbE SFP+", 0 ),
1825  PCI_ROM ( 0x8086, 0x1574, "xl710-qemu", "Virtual XL710", 0 ),
1826  PCI_ROM ( 0x8086, 0x1580, "xl710-kx-b", "XL710 40GbE backplane", 0 ),
1827  PCI_ROM ( 0x8086, 0x1581, "xl710-kx-c", "XL710 10GbE backplane", 0 ),
1828  PCI_ROM ( 0x8086, 0x1583, "xl710-qda2", "XL710 40GbE QSFP+", 0 ),
1829  PCI_ROM ( 0x8086, 0x1584, "xl710-qda1", "XL710 40GbE QSFP+", 0 ),
1830  PCI_ROM ( 0x8086, 0x1585, "x710-qsfp", "X710 10GbE QSFP+", 0 ),
1831  PCI_ROM ( 0x8086, 0x1586, "x710-10gt", "X710 10GBASE-T", 0 ),
1832  PCI_ROM ( 0x8086, 0x1587, "x710-kr2", "XL710 20GbE backplane", 0 ),
1833  PCI_ROM ( 0x8086, 0x1588, "x710-kr2-a", "XL710 20GbE backplane", 0 ),
1834  PCI_ROM ( 0x8086, 0x1589, "x710-10gt4", "X710 10GBASE-T4", 0 ),
1835  PCI_ROM ( 0x8086, 0x158a, "xxv710", "XXV710 25GbE backplane", 0 ),
1836  PCI_ROM ( 0x8086, 0x158b, "xxv710-sfp28", "XXV710 25GbE SFP28", 0 ),
1837  PCI_ROM ( 0x8086, 0x37ce, "x722-kx", "X722 10GbE backplane", 0 ),
1838  PCI_ROM ( 0x8086, 0x37cf, "x722-qsfp", "X722 10GbE QSFP+", 0 ),
1839  PCI_ROM ( 0x8086, 0x37d0, "x722-sfp", "X722 10GbE SFP+", 0 ),
1840  PCI_ROM ( 0x8086, 0x37d1, "x722-1gt", "X722 1GBASE-T", 0 ),
1841  PCI_ROM ( 0x8086, 0x37d2, "x722-10gt", "X722 10GBASE-T", 0 ),
1842  PCI_ROM ( 0x8086, 0x37d3, "x722-sfp-i", "X722 10GbE SFP+", 0 ),
1843 };
1844 
1845 /** PCI driver */
1846 struct pci_driver intelxl_driver __pci_driver = {
1847  .ids = intelxl_nics,
1848  .id_count = ( sizeof ( intelxl_nics ) / sizeof ( intelxl_nics[0] ) ),
1849  .probe = intelxl_probe,
1851 };
#define INTELXL_RESET_DELAY_MS
Time to delay for device reset, in milliseconds.
Definition: intelxl.h:998
#define INTELXL_PFGEN_CTRL_PFSWR
Software Reset.
Definition: intelxl.h:995
const char product_short_name[]
Product short name string.
Definition: version.c:76
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:310
static int intelxl_admin_promisc(struct intelxl_nic *intelxl)
Set VSI promiscuous modes.
Definition: intelxl.c:678
Receive queue context.
Definition: intelxl.h:677
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)
First queue.
Definition: intelxl.h:1008
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:733
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1482
#define __attribute__(x)
Definition: compiler.h:10
void * regs
Registers.
Definition: intelxl.h:1057
#define VLAN_TAG(tci)
Extract VLAN tag from tag control information.
Definition: vlan.h:29
#define INTELXL_ADMIN_PROMISC_FL_VLAN
Promiscuous VLAN mode.
Definition: intelxl.h:264
#define INTELXL_QRX(x)
Global Receive Queue register block.
Definition: intelxl.h:746
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:278
unsigned long membase
Memory base.
Definition: pci.h:200
#define INTELXL_ADMIN_SHUTDOWN
Admin queue Shutdown command.
Definition: intelxl.h:135
size_t len
Length (in bytes)
Definition: intelxl.h:889
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:552
struct dma_device * dma
DMA device.
Definition: intelxl.h:1059
#define INTELXL_PFLAN_QALLOC_LASTQ(x)
Last queue.
Definition: intelxl.h:1011
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:699
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_PRTPM_SAH
Physical Function MAC Address High Register.
Definition: intelxl.h:1033
wmb()
#define INTELXL_ADMIN_BAH
Admin Queue Base Address High Register (offset)
Definition: intelxl.h:45
#define iob_put(iobuf, len)
Definition: iobuf.h:120
struct dma_device dma
DMA device.
Definition: pci.h:195
#define INTELXL_PFFUNC_RID
Function Requester ID Information Register.
Definition: intelxl.h:1001
struct pci_msix cap
PCI capability.
Definition: intelxl.h:1047
uint32_t raw[4]
Raw data.
Definition: intelxl.h:641
A PCI driver.
Definition: pci.h:230
static int intelxl_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: intelxl.c:592
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:39
#define INTELXL_PFLAN_QALLOC
PF Queue Allocation Register.
Definition: intelxl.h:1007
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:1051
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:895
#define INTELXL_QXX_CTL_PFVF_Q_PF
PF queue.
Definition: intelxl.h:756
static void intelxl_context_dump(struct intelxl_nic *intelxl, uint32_t op, size_t len)
Dump queue context (for debugging)
Definition: intelxl.c:999
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:734
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:284
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
static int intelxl_context_tx(struct intelxl_nic *intelxl, physaddr_t address)
Program transmit queue context.
Definition: intelxl.c:1132
static int intelxl_open(struct net_device *netdev)
Open network device.
Definition: intelxl.c:1378
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:163
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:267
Error codes.
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)
Queue index.
Definition: intelxl.h:971
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE
Write context.
Definition: intelxl.h:631
#define INTELXL_ADMIN_LEN_ENABLE
Queue enable.
Definition: intelxl.h:50
#define INTELXL_GLLAN_RCTL_0
Global RLAN Control 0 register.
Definition: intelxl.h:764
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:230
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE
End of list.
Definition: intelxl.h:984
#define INTELXL_PRTGL_SAL
Port MAC Address Low Register.
Definition: intelxl.h:1022
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:36
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:565
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:176
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:234
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:505
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:770
#define INTELXL_PRTGL_SAH
Port MAC Address High Register.
Definition: intelxl.h:1025
Admin queue register offsets.
Definition: intelxl.h:63
I/O buffers.
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:270
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1195
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:232
uint16_t vlan
VLAN tag.
Definition: intelxl.h:835
uint8_t type
Switching element type.
Definition: intelxl.h:168
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:535
uint16_t opcode
Opcode.
Definition: intelxl.h:527
Queue context line.
Definition: intelxl.h:639
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:415
Admin queue.
Definition: intelxl.h:561
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:781
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:216
unsigned int qset
Queue set handle.
Definition: intelxl.h:1074
#define INTELXL_RX_WB_FL_DD
Receive writeback descriptor complete.
Definition: intelxl.h:847
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:778
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_PFINT_ICR0_ENA
PF Interrupt Zero Cause Enablement Register.
Definition: intelxl.h:966
unsigned int prod
Producer index.
Definition: intelxl.h:880
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:1083
Admin queue Shutdown command parameters.
Definition: intelxl.h:138
#define ENOENT
No such file or directory.
Definition: errno.h:514
char name[32]
Driver name.
Definition: intelxl.h:131
uint16_t flags
Flags.
Definition: intelxl.h:525
static int intelxl_context_rx(struct intelxl_nic *intelxl, physaddr_t address)
Program receive queue context.
Definition: intelxl.c:1163
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:474
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:327
#define INTELXL_PRTGL_SAH_MFS_GET(x)
Max frame size.
Definition: intelxl.h:1026
unsigned long long uint64_t
Definition: stdint.h:13
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:946
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:240
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:501
struct dma_device * dma
DMA device.
Definition: netdevice.h:366
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1521
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
#define cpu_to_le64(value)
Definition: byteswap.h:108
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:708
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:751
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:863
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1220
unsigned int bal
Base Address Low Register offset.
Definition: intelxl.h:65
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_PFINT_ICR0_ENA_ADMINQ
Admin event.
Definition: intelxl.h:967
size_t mfs
Maximum frame size.
Definition: intelxl.h:1061
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:503
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: intelxl.h:1017
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:853
unsigned int base
Register block base.
Definition: intelxl.h:572
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:871
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
struct intelxl_admin_version api
API version.
Definition: intelxl.h:106
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:702
#define INTELXL_ADMIN_VSI
Admin queue Get VSI Parameters command.
Definition: intelxl.h:213
struct device dev
Generic device.
Definition: pci.h:193
unsigned int queue
Queue number.
Definition: intelxl.h:1070
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:152
#define INTELXL_ADMIN_PROMISC
Admin queue Set VSI Promiscuous Modes command.
Definition: intelxl.h:240
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:593
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:749
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:797
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:134
Intel 40 Gigabit Ethernet network card driver.
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:510
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:622
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1306
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:624
static struct pci_device_id intelxl_nics[]
PCI device IDs.
Definition: intelxl.c:1823
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:344
#define INTELXL_PFGEN_CTRL
PF Control Register.
Definition: intelxl.h:994
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:882
#define INTELXL_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: intelxl.h:1016
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1105
uint16_t len
Data length.
Definition: intelxl.h:529
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:1097
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:585
#define INTELXL_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:991
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:549
u32 version
Version number.
Definition: ath9k_hw.c:1983
unsigned int index
Queue index.
Definition: intelxl.h:569
static void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1287
Transmit writeback descriptor.
Definition: intelxl.h:800
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:160
#define ETH_HLEN
Definition: if_ether.h:9
static int intelxl_reset(struct intelxl_nic *intelxl)
Reset hardware.
Definition: intelxl.c:60
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:1099
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX
Receive queue.
Definition: intelxl.h:960
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:343
#define INTELXL_PFINT_DYN_CTL0
PF Interrupt Zero Dynamic Control Register.
Definition: intelxl.h:945
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
uint8_t magic
Magic value.
Definition: intelxl.h:154
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:567
Ethernet protocol.
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)
PF index.
Definition: intelxl.h:758
#define INTELXL_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:979
Admin queue version number.
Definition: intelxl.h:90
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:60
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:1072
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX
Transmit queue.
Definition: intelxl.h:977
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:815
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:920
void * priv
Driver private data.
Definition: netdevice.h:431
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:613
#define DBGC_HDA(...)
Definition: compiler.h:506
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:780
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
void * raw
Raw data.
Definition: intelxl.h:875
uint16_t flags
Flags.
Definition: intelxl.h:245
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:635
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:264
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:929
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:782
#define INTELXL_QXX_ENA_REQ
Enable request.
Definition: intelxl.h:750
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:72
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:87
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
#define INTELXL_CTX_TX_FL_NEW
New transmit queue context.
Definition: intelxl.h:665
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:800
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:899
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:176
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:1080
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:599
union intelxl_ring::@65 desc
Descriptors.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:567
unsigned int reg
Register block.
Definition: intelxl.h:885
#define cpu_to_le32(value)
Definition: byteswap.h:107
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:983
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:212
#define EPROTO
Protocol error.
Definition: errno.h:624
#define INTELXL_PRTPM_SAL
Physical Function MAC Address Low Register.
Definition: intelxl.h:1030
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS
Maximum time to wait for a queue to become disabled.
Definition: intelxl.h:720
Receive data descriptor.
Definition: intelxl.h:821
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:784
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
Admin queue Driver Version command parameters.
Definition: intelxl.h:113
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:181
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:873
PCI bus.
A PCI device.
Definition: pci.h:191
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:722
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
unsigned int intr
Interrupt control register.
Definition: intelxl.h:1076
static int intelxl_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: intelxl.c:709
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:616
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:563
A network device.
Definition: netdevice.h:352
#define INTELXL_QTX(x)
Global Transmit Queue register block.
Definition: intelxl.h:743
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:523
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:294
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:878
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:279
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:558
unsigned int port
Port number.
Definition: intelxl.h:1068
#define INTELXL_ADMIN_BAL
Admin Queue Base Address Low Register (offset)
Definition: intelxl.h:42
Admin queue Get Version command parameters.
Definition: intelxl.h:98
Transmit data descriptor.
Definition: intelxl.h:768
#define INTELXL_ADMIN_SEND_TO_VF
Admin queue Send Message to VF command.
Definition: intelxl.h:312
#define INTELXL_CTX_TX_QSET(qset)
Transmit queue set.
Definition: intelxl.h:674
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:717
An Intel 40Gigabit network card.
Definition: intelxl.h:1055
#define INTELXL_PFINT_LNKLST0
PF Interrupt Zero Linked List Register.
Definition: intelxl.h:951
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:794
#define ETH_ALEN
Definition: if_ether.h:8
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:218
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:542
uint8_t connection
Connection type.
Definition: intelxl.h:180
A PCI device ID list entry.
Definition: pci.h:155
Version number.
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
Receive address.
Definition: intelxl.h:1036
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:907
#define INTELXL_ADMIN_LEN_LEN(x)
Queue length.
Definition: intelxl.h:49
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
uint32_t high
Buffer address high.
Definition: intelxl.h:81
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:1095
static void intelxl_close(struct net_device *netdev)
Close network device.
Definition: intelxl.c:1448
#define INTELXL_PRTGL_SAH_MFS_SET(x)
Max frame size.
Definition: intelxl.h:1027
struct i386_regs regs
Definition: registers.h:15
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:366
struct pci_driver intelxl_driver __pci_driver
PCI driver.
Definition: intelxl.c:1846
Network device operations.
Definition: netdevice.h:213
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:249
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
static int intelxl_admin_version(struct intelxl_nic *intelxl)
Get firmware version.
Definition: intelxl.c:468
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:243
#define DMA_RX
Device will write data to host memory.
Definition: dma.h:135
#define INTELXL_CTX_TX_BASE(base)
Transmit queue base address.
Definition: intelxl.h:668
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:705
Network device management.
unsigned long physaddr_t
Definition: stdint.h:20
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define INTELXL_QINT_TQCTL(x)
Transmit Queue Interrupt Cause Control Register.
Definition: intelxl.h:982
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:354
const int product_major_version
Product major version.
Definition: version.c:64
#define INTELXL_TX_WB_FL_DD
Transmit writeback descriptor complete.
Definition: intelxl.h:810
unsigned int pf
Physical function number.
Definition: intelxl.h:1064
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define INTELXL_GLLAN_RCTL_0_PXE_MODE
PXE mode.
Definition: intelxl.h:765
Admin queue descriptor.
Definition: intelxl.h:523
uint32_t low
Buffer address low.
Definition: intelxl.h:83
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:174
#define INTELXL_ADMIN_TAIL
Admin Queue Tail Register (offset)
Definition: intelxl.h:56
#define INTELXL_QXX_TAIL
Queue Tail Pointer Register (offset)
Definition: intelxl.h:761
#define INTELXL_RX_WB_LEN(len)
Receive writeback descriptor length.
Definition: intelxl.h:856
__weak void vlan_netdev_rx(struct net_device *netdev, unsigned int tag, struct io_buffer *iobuf)
Add VLAN tag-stripped packet to queue (when VLAN support is not present)
Definition: netdevice.c:1190
uint32_t len
Length.
Definition: ena.h:14
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:737
uint8_t unused[32]
Unused.
Definition: eltorito.h:15
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:208
static int intelxl_probe(struct pci_device *pci)
Probe PCI device.
Definition: intelxl.c:1656
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define INTELXL_QUEUE_ENABLE_DELAY_US
Time to wait for a queue to become enabled.
Definition: intelxl.h:714
#define DBGC2(...)
Definition: compiler.h:522
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:243
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:306
static int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:559
__weak void intelxlvf_admin_event(struct net_device *netdev __unused, struct intelxl_admin_descriptor *evt __unused, union intelxl_admin_buffer *buf __unused)
Handle virtual function event (when VF driver is not present)
Definition: intelxl.c:770
void * data
Start of data.
Definition: iobuf.h:48
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:303
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)
Queue index.
Definition: intelxl.h:952
static int intelxl_context_line(struct intelxl_nic *intelxl, struct intelxl_context_line *line, unsigned int index, uint32_t op)
Program queue context line.
Definition: intelxl.c:1057
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:104
#define EIO
Input/output error.
Definition: errno.h:433
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:636
__weak void vlan_netdev_rx_err(struct net_device *netdev, unsigned int tag __unused, struct io_buffer *iobuf, int rc)
Discard received VLAN tag-stripped packet (when VLAN support is not present)
Definition: netdevice.c:1208
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS
Clear disable.
Definition: intelxl.h:739
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST
Promiscuous broadcast mode.
Definition: intelxl.h:261
unsigned int base
Absolute queue number base.
Definition: intelxl.h:1066
void iounmap(volatile const void *io_addr)
Unmap I/O address.
Descriptor ring.
Definition: intelxl.h:867
Virtual LANs.
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:209
#define __weak
Declare a function as weak (use before the definition)
Definition: compiler.h:219
unsigned int tail
Tail register.
Definition: intelxl.h:887
Receive writeback descriptor.
Definition: intelxl.h:831
unsigned int tail
Tail Register offset.
Definition: intelxl.h:73
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:281
#define INTELXL_QINT_RQCTL(x)
Receive Queue Interrupt Cause Control Register.
Definition: intelxl.h:970
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:477
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:574
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:893
#define INTELXL_BAR_SIZE
BAR size.
Definition: intelxl.h:20
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:191
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING
Driver is unloading.
Definition: intelxl.h:146
uint16_t valid
Valid flags.
Definition: intelxl.h:247
static int intelxl_admin_vsi(struct intelxl_nic *intelxl)
Get VSI parameters.
Definition: intelxl.c:644
void shutdown(int flags)
Shut down iPXE.
Definition: init.c:98
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:817
#define INTELXL_ADMIN_PROMISC_FL_UNICAST
Promiscuous unicast mode.
Definition: intelxl.h:255
static int intelxl_fetch_mac(struct intelxl_nic *intelxl, struct net_device *netdev)
Fetch initial MAC address and maximum frame size.
Definition: intelxl.c:86
const char product_name[]
Product name string.
Definition: version.c:73
#define DBG_EXTRA
Definition: compiler.h:319
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:387
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:409
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
static struct net_device_operations intelxl_operations
Network device operations.
Definition: intelxl.c:1636
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:915
#define INTELXL_ADMIN_DRIVER
Admin queue Driver Version command.
Definition: intelxl.h:110
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:181
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: intelxl.h:1002
#define INTELXL_CTX_TX_COUNT(count)
Transmit queue count.
Definition: intelxl.h:671
#define INTELXL_ADMIN_SWITCH_TYPE_VSI
Virtual Station Inferface element type.
Definition: intelxl.h:188
#define INTELXL_RX_FILL
Receive descriptor ring fill level.
Definition: intelxl.h:935
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:734
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:504
uint64_t tag
Identity tag.
Definition: edd.h:30
uint16_t queue
Queue ID.
Definition: ena.h:22
Transmit queue context.
Definition: intelxl.h:645
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:149
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:711
uint16_t seid
Switching element ID.
Definition: intelxl.h:172
#define INTELXL_RX_WB_FL_RXE
Receive writeback descriptor error.
Definition: intelxl.h:853
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:555
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:695
static void intelxl_remove(struct pci_device *pci)
Remove PCI device.
Definition: intelxl.c:1800
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:381
static int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1253
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:596
#define INTELXL_ADMIN_LEN
Admin Queue Length Register (offset)
Definition: intelxl.h:48
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST
Promiscuous multicast mode.
Definition: intelxl.h:258
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:1085
#define INTELXL_QXX_CTL
Queue Control Register (offset)
Definition: intelxl.h:754
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_QTX_HEAD(x)
Global Transmit Queue Head register.
Definition: intelxl.h:730
String functions.
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:546
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:289
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:612
const int product_minor_version
Product minor version.
Definition: version.c:67
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1354
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:923
#define INTELXL_ADMIN_HEAD
Admin Queue Head Register (offset)
Definition: intelxl.h:53
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:609
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1602
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:943
Admin queue data buffer.
Definition: intelxl.h:499
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:1049
#define INTELXL_RX_WB_FL_VLAN
Receive writeback descriptor VLAN tag present.
Definition: intelxl.h:850
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:861
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1550
void * memset(void *dest, int character, size_t len) __nonnull
A persistent I/O buffer.
Definition: iobuf.h:33
uint8_t flags
Flags.
Definition: ena.h:18
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ
Read context.
Definition: intelxl.h:629