iPXE
intelxl.c
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2018 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  * You can also choose to distribute this program under the terms of
20  * the Unmodified Binary Distribution Licence (as given in the file
21  * COPYING.UBDL), provided that you have satisfied its requirements.
22  */
23 
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25 
26 #include <stdint.h>
27 #include <string.h>
28 #include <stdio.h>
29 #include <unistd.h>
30 #include <errno.h>
31 #include <byteswap.h>
32 #include <ipxe/netdevice.h>
33 #include <ipxe/ethernet.h>
34 #include <ipxe/if_ether.h>
35 #include <ipxe/vlan.h>
36 #include <ipxe/iobuf.h>
37 #include <ipxe/pci.h>
38 #include <ipxe/version.h>
39 #include "intelxl.h"
40 
41 /** @file
42  *
43  * Intel 40 Gigabit Ethernet network card driver
44  *
45  */
46 
47 /******************************************************************************
48  *
49  * MSI-X interrupts
50  *
51  ******************************************************************************
52  */
53 
54 /**
55  * Enable MSI-X dummy interrupt
56  *
57  * @v intelxl Intel device
58  * @v pci PCI device
59  * @v vector MSI-X vector
60  * @ret rc Return status code
61  */
62 int intelxl_msix_enable ( struct intelxl_nic *intelxl,
63  struct pci_device *pci, unsigned int vector ) {
64  int rc;
65 
66  /* Map dummy target location */
67  if ( ( rc = dma_map ( intelxl->dma, &intelxl->msix.map,
68  virt_to_phys ( &intelxl->msix.msg ),
69  sizeof ( intelxl->msix.msg ), DMA_RX ) ) != 0 ) {
70  DBGC ( intelxl, "INTELXL %p could not map MSI-X target: %s\n",
71  intelxl, strerror ( rc ) );
72  goto err_map;
73  }
74 
75  /* Enable MSI-X capability */
76  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix.cap ) ) != 0 ) {
77  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
78  intelxl, strerror ( rc ) );
79  goto err_enable;
80  }
81 
82  /* Configure interrupt to write to dummy location */
83  pci_msix_map ( &intelxl->msix.cap, vector,
84  dma ( &intelxl->msix.map, &intelxl->msix.msg ), 0 );
85 
86  /* Enable dummy interrupt */
87  pci_msix_unmask ( &intelxl->msix.cap, vector );
88 
89  return 0;
90 
91  pci_msix_disable ( pci, &intelxl->msix.cap );
92  err_enable:
93  dma_unmap ( &intelxl->msix.map );
94  err_map:
95  return rc;
96 }
97 
98 /**
99  * Disable MSI-X dummy interrupt
100  *
101  * @v intelxl Intel device
102  * @v pci PCI device
103  * @v vector MSI-X vector
104  */
105 void intelxl_msix_disable ( struct intelxl_nic *intelxl,
106  struct pci_device *pci, unsigned int vector ) {
107 
108  /* Disable dummy interrupts */
109  pci_msix_mask ( &intelxl->msix.cap, vector );
110 
111  /* Disable MSI-X capability */
112  pci_msix_disable ( pci, &intelxl->msix.cap );
113 
114  /* Unmap dummy target location */
115  dma_unmap ( &intelxl->msix.map );
116 }
117 
118 /******************************************************************************
119  *
120  * Admin queue
121  *
122  ******************************************************************************
123  */
124 
125 /** Admin queue register offsets */
128  .bah = INTELXL_ADMIN_BAH,
129  .len = INTELXL_ADMIN_LEN,
130  .head = INTELXL_ADMIN_HEAD,
131  .tail = INTELXL_ADMIN_TAIL,
132 };
133 
134 /**
135  * Allocate admin queue
136  *
137  * @v intelxl Intel device
138  * @v admin Admin queue
139  * @ret rc Return status code
140  */
141 static int intelxl_alloc_admin ( struct intelxl_nic *intelxl,
142  struct intelxl_admin *admin ) {
143  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
144  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
145 
146  /* Allocate admin queue */
147  admin->buf = dma_alloc ( intelxl->dma, &admin->map, ( buf_len + len ),
148  INTELXL_ALIGN );
149  if ( ! admin->buf )
150  return -ENOMEM;
151  admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
152 
153  DBGC ( intelxl, "INTELXL %p A%cQ is at [%08lx,%08lx) buf "
154  "[%08lx,%08lx)\n", intelxl,
155  ( ( admin == &intelxl->command ) ? 'T' : 'R' ),
156  virt_to_phys ( admin->desc ),
157  ( virt_to_phys ( admin->desc ) + len ),
158  virt_to_phys ( admin->buf ),
159  ( virt_to_phys ( admin->buf ) + buf_len ) );
160  return 0;
161 }
162 
163 /**
164  * Enable admin queue
165  *
166  * @v intelxl Intel device
167  * @v admin Admin queue
168  */
169 static void intelxl_enable_admin ( struct intelxl_nic *intelxl,
170  struct intelxl_admin *admin ) {
171  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
172  const struct intelxl_admin_offsets *regs = admin->regs;
173  void *admin_regs = ( intelxl->regs + admin->base );
175 
176  /* Initialise admin queue */
177  memset ( admin->desc, 0, len );
178 
179  /* Reset head and tail registers */
180  writel ( 0, admin_regs + regs->head );
181  writel ( 0, admin_regs + regs->tail );
182 
183  /* Reset queue index */
184  admin->index = 0;
185 
186  /* Program queue address */
187  address = dma ( &admin->map, admin->desc );
188  writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
189  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
190  writel ( ( ( ( uint64_t ) address ) >> 32 ),
191  admin_regs + regs->bah );
192  } else {
193  writel ( 0, admin_regs + regs->bah );
194  }
195 
196  /* Program queue length and enable queue */
199  admin_regs + regs->len );
200 }
201 
202 /**
203  * Disable admin queue
204  *
205  * @v intelxl Intel device
206  * @v admin Admin queue
207  */
208 static void intelxl_disable_admin ( struct intelxl_nic *intelxl,
209  struct intelxl_admin *admin ) {
210  const struct intelxl_admin_offsets *regs = admin->regs;
211  void *admin_regs = ( intelxl->regs + admin->base );
212 
213  /* Disable queue */
214  writel ( 0, admin_regs + regs->len );
215 }
216 
217 /**
218  * Free admin queue
219  *
220  * @v intelxl Intel device
221  * @v admin Admin queue
222  */
223 static void intelxl_free_admin ( struct intelxl_nic *intelxl __unused,
224  struct intelxl_admin *admin ) {
225  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
226  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
227 
228  /* Free queue */
229  dma_free ( &admin->map, admin->buf, ( buf_len + len ) );
230 }
231 
232 /**
233  * Get next admin command queue descriptor
234  *
235  * @v intelxl Intel device
236  * @ret cmd Command descriptor
237  */
240  struct intelxl_admin *admin = &intelxl->command;
242 
243  /* Get and initialise next descriptor */
244  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
245  memset ( cmd, 0, sizeof ( *cmd ) );
246  return cmd;
247 }
248 
249 /**
250  * Get next admin command queue data buffer
251  *
252  * @v intelxl Intel device
253  * @ret buf Data buffer
254  */
255 union intelxl_admin_buffer *
257  struct intelxl_admin *admin = &intelxl->command;
258  union intelxl_admin_buffer *buf;
259 
260  /* Get next data buffer */
261  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
262  memset ( buf, 0, sizeof ( *buf ) );
263  return buf;
264 }
265 
266 /**
267  * Initialise admin event queue descriptor
268  *
269  * @v intelxl Intel device
270  * @v index Event queue index
271  */
272 static void intelxl_admin_event_init ( struct intelxl_nic *intelxl,
273  unsigned int index ) {
274  struct intelxl_admin *admin = &intelxl->event;
275  struct intelxl_admin_descriptor *evt;
276  union intelxl_admin_buffer *buf;
278 
279  /* Initialise descriptor */
280  evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
281  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
282  address = dma ( &admin->map, buf );
284  evt->len = cpu_to_le16 ( sizeof ( *buf ) );
285  evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
286  evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
287 }
288 
289 /**
290  * Issue admin queue command
291  *
292  * @v intelxl Intel device
293  * @ret rc Return status code
294  */
295 int intelxl_admin_command ( struct intelxl_nic *intelxl ) {
296  struct intelxl_admin *admin = &intelxl->command;
297  const struct intelxl_admin_offsets *regs = admin->regs;
298  void *admin_regs = ( intelxl->regs + admin->base );
300  union intelxl_admin_buffer *buf;
302  uint32_t cookie;
303  uint16_t silence;
304  unsigned int index;
305  unsigned int tail;
306  unsigned int i;
307  int rc;
308 
309  /* Get next queue entry */
310  index = admin->index++;
311  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
312  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
313  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
314  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
315  intelxl, index, le16_to_cpu ( cmd->opcode ) );
316  if ( cmd->cookie )
317  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
318  DBGC2 ( intelxl, ":\n" );
319 
320  /* Allow expected errors to be silenced */
321  silence = cmd->ret;
322  cmd->ret = 0;
323 
324  /* Sanity checks */
325  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
326  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
327  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
328 
329  /* Populate data buffer address if applicable */
330  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
331  address = dma ( &admin->map, buf );
332  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
333  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
334  }
335 
336  /* Populate cookie, if not being (ab)used for VF opcode */
337  if ( ! cmd->cookie )
338  cmd->cookie = cpu_to_le32 ( index );
339 
340  /* Record cookie */
341  cookie = cmd->cookie;
342 
343  /* Post command descriptor */
344  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
345  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
346  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
347  le16_to_cpu ( cmd->len ) );
348  }
349  wmb();
350  writel ( tail, admin_regs + regs->tail );
351 
352  /* Wait for completion */
353  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
354 
355  /* If response is not complete, delay 1ms and retry */
356  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
357  mdelay ( 1 );
358  continue;
359  }
360  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
361  intelxl, index );
362  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
363  sizeof ( *cmd ) );
364  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
365  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
366  le16_to_cpu ( cmd->len ) );
367  }
368 
369  /* Check for cookie mismatch */
370  if ( cmd->cookie != cookie ) {
371  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
372  "cookie %#x\n", intelxl, index,
373  le32_to_cpu ( cmd->cookie ) );
374  rc = -EPROTO;
375  goto err;
376  }
377 
378  /* Check for unexpected errors */
379  if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
380  DBGC ( intelxl, "INTELXL %p admin command %#x error "
381  "%d\n", intelxl, index,
382  le16_to_cpu ( cmd->ret ) );
383  rc = -EIO;
384  goto err;
385  }
386 
387  /* Success */
388  return 0;
389  }
390 
391  rc = -ETIMEDOUT;
392  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
393  intelxl, index );
394  err:
395  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
396  return rc;
397 }
398 
399 /**
400  * Get firmware version
401  *
402  * @v intelxl Intel device
403  * @ret rc Return status code
404  */
405 static int intelxl_admin_version ( struct intelxl_nic *intelxl ) {
408  unsigned int api;
409  int rc;
410 
411  /* Populate descriptor */
413  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
414  version = &cmd->params.version;
415 
416  /* Issue command */
417  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
418  return rc;
419  api = le16_to_cpu ( version->api.major );
420  DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
421  intelxl, le16_to_cpu ( version->firmware.major ),
422  le16_to_cpu ( version->firmware.minor ),
423  api, le16_to_cpu ( version->api.minor ) );
424 
425  /* Check for API compatibility */
426  if ( api > INTELXL_ADMIN_API_MAJOR ) {
427  DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
428  intelxl, api );
429  return -ENOTSUP;
430  }
431 
432  return 0;
433 }
434 
435 /**
436  * Report driver version
437  *
438  * @v intelxl Intel device
439  * @ret rc Return status code
440  */
441 static int intelxl_admin_driver ( struct intelxl_nic *intelxl ) {
443  struct intelxl_admin_driver_params *driver;
444  union intelxl_admin_buffer *buf;
445  int rc;
446 
447  /* Populate descriptor */
449  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
451  cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
452  driver = &cmd->params.driver;
453  driver->major = product_major_version;
454  driver->minor = product_minor_version;
455  buf = intelxl_admin_command_buffer ( intelxl );
456  snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
458 
459  /* Issue command */
460  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
461  return rc;
462 
463  return 0;
464 }
465 
466 /**
467  * Shutdown admin queues
468  *
469  * @v intelxl Intel device
470  * @ret rc Return status code
471  */
472 static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
475  int rc;
476 
477  /* Populate descriptor */
479  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
480  shutdown = &cmd->params.shutdown;
482 
483  /* Issue command */
484  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
485  return rc;
486 
487  return 0;
488 }
489 
490 /**
491  * Get MAC address
492  *
493  * @v netdev Network device
494  * @ret rc Return status code
495  */
496 static int intelxl_admin_mac_read ( struct net_device *netdev ) {
497  struct intelxl_nic *intelxl = netdev->priv;
500  union intelxl_admin_buffer *buf;
501  uint8_t *mac;
502  int rc;
503 
504  /* Populate descriptor */
506  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
507  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
508  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
509  read = &cmd->params.mac_read;
510  buf = intelxl_admin_command_buffer ( intelxl );
511  mac = buf->mac_read.pf;
512 
513  /* Issue command */
514  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
515  return rc;
516 
517  /* Check that MAC address is present in response */
518  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
519  DBGC ( intelxl, "INTELXL %p has no MAC address\n", intelxl );
520  return -ENOENT;
521  }
522 
523  /* Check that address is valid */
524  if ( ! is_valid_ether_addr ( mac ) ) {
525  DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
526  intelxl, eth_ntoa ( mac ) );
527  return -ENOENT;
528  }
529 
530  /* Copy MAC address */
531  DBGC ( intelxl, "INTELXL %p has MAC address %s\n",
532  intelxl, eth_ntoa ( mac ) );
534 
535  return 0;
536 }
537 
538 /**
539  * Set MAC address
540  *
541  * @v netdev Network device
542  * @ret rc Return status code
543  */
544 static int intelxl_admin_mac_write ( struct net_device *netdev ) {
545  struct intelxl_nic *intelxl = netdev->priv;
548  union {
550  struct {
551  uint16_t high;
552  uint32_t low;
553  } __attribute__ (( packed ));
554  } mac;
555  int rc;
556 
557  /* Populate descriptor */
560  write = &cmd->params.mac_write;
561  memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
562  write->high = bswap_16 ( mac.high );
563  write->low = bswap_32 ( mac.low );
564 
565  /* Issue command */
566  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
567  return rc;
568 
569  return 0;
570 }
571 
572 /**
573  * Clear PXE mode
574  *
575  * @v intelxl Intel device
576  * @ret rc Return status code
577  */
578 int intelxl_admin_clear_pxe ( struct intelxl_nic *intelxl ) {
580  struct intelxl_admin_clear_pxe_params *pxe;
581  int rc;
582 
583  /* Populate descriptor */
587  pxe = &cmd->params.pxe;
589 
590  /* Issue command */
591  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
592  return rc;
593 
594  /* Check for expected errors */
595  if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
596  DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
597  intelxl );
598  return 0;
599  }
600 
601  return 0;
602 }
603 
604 /**
605  * Get switch configuration
606  *
607  * @v intelxl Intel device
608  * @ret rc Return status code
609  */
610 static int intelxl_admin_switch ( struct intelxl_nic *intelxl ) {
612  struct intelxl_admin_switch_params *sw;
613  union intelxl_admin_buffer *buf;
614  uint16_t next = 0;
615  int rc;
616 
617  /* Get each configuration in turn */
618  do {
619  /* Populate descriptor */
621  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
622  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
623  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
624  sw = &cmd->params.sw;
625  sw->next = next;
626  buf = intelxl_admin_command_buffer ( intelxl );
627 
628  /* Issue command */
629  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
630  return rc;
631 
632  /* Dump raw configuration */
633  DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
634  intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
635  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
636 
637  /* Parse response */
638  if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
639  intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
640  DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
641  "downlink %#04x conn %#02x\n", intelxl,
642  intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
643  le16_to_cpu ( buf->sw.cfg.downlink ),
644  buf->sw.cfg.connection );
645  }
646 
647  } while ( ( next = sw->next ) );
648 
649  /* Check that we found a VSI */
650  if ( ! intelxl->vsi ) {
651  DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
652  return -ENOENT;
653  }
654 
655  return 0;
656 }
657 
658 /**
659  * Get VSI parameters
660  *
661  * @v intelxl Intel device
662  * @ret rc Return status code
663  */
664 static int intelxl_admin_vsi ( struct intelxl_nic *intelxl ) {
667  union intelxl_admin_buffer *buf;
668  int rc;
669 
670  /* Populate descriptor */
672  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
673  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
674  cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
675  vsi = &cmd->params.vsi;
676  vsi->vsi = cpu_to_le16 ( intelxl->vsi );
677  buf = intelxl_admin_command_buffer ( intelxl );
678 
679  /* Issue command */
680  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
681  return rc;
682 
683  /* Parse response */
684  intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
685  intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
686  DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
687  intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
688 
689  return 0;
690 }
691 
692 /**
693  * Set VSI promiscuous modes
694  *
695  * @v intelxl Intel device
696  * @ret rc Return status code
697  */
698 static int intelxl_admin_promisc ( struct intelxl_nic *intelxl ) {
700  struct intelxl_admin_promisc_params *promisc;
701  uint16_t flags;
702  int rc;
703 
704  /* Populate descriptor */
706  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
711  promisc = &cmd->params.promisc;
712  promisc->flags = cpu_to_le16 ( flags );
713  promisc->valid = cpu_to_le16 ( flags );
714  promisc->vsi = cpu_to_le16 ( intelxl->vsi );
715 
716  /* Issue command */
717  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
718  return rc;
719 
720  return 0;
721 }
722 
723 /**
724  * Set MAC configuration
725  *
726  * @v intelxl Intel device
727  * @ret rc Return status code
728  */
729 int intelxl_admin_mac_config ( struct intelxl_nic *intelxl ) {
731  struct intelxl_admin_mac_config_params *config;
732  int rc;
733 
734  /* Populate descriptor */
737  config = &cmd->params.mac_config;
738  config->mfs = cpu_to_le16 ( intelxl->mfs );
740 
741  /* Issue command */
742  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
743  return rc;
744 
745  return 0;
746 }
747 
748 /**
749  * Restart autonegotiation
750  *
751  * @v intelxl Intel device
752  * @ret rc Return status code
753  */
754 static int intelxl_admin_autoneg ( struct intelxl_nic *intelxl ) {
756  struct intelxl_admin_autoneg_params *autoneg;
757  int rc;
758 
759  /* Populate descriptor */
761  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
762  autoneg = &cmd->params.autoneg;
765 
766  /* Issue command */
767  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
768  return rc;
769 
770  return 0;
771 }
772 
773 /**
774  * Get link status
775  *
776  * @v netdev Network device
777  * @ret rc Return status code
778  */
779 static int intelxl_admin_link ( struct net_device *netdev ) {
780  struct intelxl_nic *intelxl = netdev->priv;
783  int rc;
784 
785  /* Populate descriptor */
787  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
788  link = &cmd->params.link;
790 
791  /* Issue command */
792  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
793  return rc;
794  DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
795  intelxl, link->phy, link->speed, link->status );
796 
797  /* Update network device */
798  if ( link->status & INTELXL_ADMIN_LINK_UP ) {
800  } else {
802  }
803 
804  return 0;
805 }
806 
807 /**
808  * Handle admin event
809  *
810  * @v netdev Network device
811  * @v evt Event descriptor
812  * @v buf Data buffer
813  */
814 static void intelxl_admin_event ( struct net_device *netdev,
815  struct intelxl_admin_descriptor *evt,
816  union intelxl_admin_buffer *buf __unused ) {
817  struct intelxl_nic *intelxl = netdev->priv;
818 
819  /* Ignore unrecognised events */
820  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
821  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
822  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
823  return;
824  }
825 
826  /* Update link status */
828 }
829 
830 /**
831  * Refill admin event queue
832  *
833  * @v intelxl Intel device
834  */
835 static void intelxl_refill_admin ( struct intelxl_nic *intelxl ) {
836  struct intelxl_admin *admin = &intelxl->event;
837  const struct intelxl_admin_offsets *regs = admin->regs;
838  void *admin_regs = ( intelxl->regs + admin->base );
839  unsigned int tail;
840 
841  /* Update tail pointer */
842  tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
844  wmb();
845  writel ( tail, admin_regs + regs->tail );
846 }
847 
848 /**
849  * Poll admin event queue
850  *
851  * @v netdev Network device
852  */
854  struct intelxl_nic *intelxl = netdev->priv;
855  struct intelxl_admin *admin = &intelxl->event;
856  struct intelxl_admin_descriptor *evt;
857  union intelxl_admin_buffer *buf;
858 
859  /* Check for events */
860  while ( 1 ) {
861 
862  /* Get next event descriptor and data buffer */
863  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
864  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
865 
866  /* Stop if descriptor is not yet completed */
867  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
868  return;
869  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
870  intelxl, admin->index );
871  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
872  sizeof ( *evt ) );
873  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
874  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
875  le16_to_cpu ( evt->len ) );
876  }
877 
878  /* Handle event */
879  intelxl->handle ( netdev, evt, buf );
880 
881  /* Reset descriptor and refill queue */
882  intelxl_admin_event_init ( intelxl, admin->index );
883  admin->index++;
884  intelxl_refill_admin ( intelxl );
885  }
886 }
887 
888 /**
889  * Open admin queues
890  *
891  * @v intelxl Intel device
892  * @ret rc Return status code
893  */
894 int intelxl_open_admin ( struct intelxl_nic *intelxl ) {
895  int rc;
896 
897  /* Allocate admin event queue */
898  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
899  goto err_alloc_event;
900 
901  /* Allocate admin command queue */
902  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
903  goto err_alloc_command;
904 
905  /* (Re)open admin queues */
906  intelxl_reopen_admin ( intelxl );
907 
908  return 0;
909 
910  intelxl_disable_admin ( intelxl, &intelxl->command );
911  intelxl_disable_admin ( intelxl, &intelxl->event );
912  intelxl_free_admin ( intelxl, &intelxl->command );
913  err_alloc_command:
914  intelxl_free_admin ( intelxl, &intelxl->event );
915  err_alloc_event:
916  return rc;
917 }
918 
919 /**
920  * Reopen admin queues (after virtual function reset)
921  *
922  * @v intelxl Intel device
923  */
924 void intelxl_reopen_admin ( struct intelxl_nic *intelxl ) {
925  unsigned int i;
926 
927  /* Enable admin event queue */
928  intelxl_enable_admin ( intelxl, &intelxl->event );
929 
930  /* Enable admin command queue */
931  intelxl_enable_admin ( intelxl, &intelxl->command );
932 
933  /* Initialise all admin event queue descriptors */
934  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
935  intelxl_admin_event_init ( intelxl, i );
936 
937  /* Post all descriptors to event queue */
938  intelxl_refill_admin ( intelxl );
939 }
940 
941 /**
942  * Close admin queues
943  *
944  * @v intelxl Intel device
945  */
946 void intelxl_close_admin ( struct intelxl_nic *intelxl ) {
947 
948  /* Shut down admin queues */
949  intelxl_admin_shutdown ( intelxl );
950 
951  /* Disable admin queues */
952  intelxl_disable_admin ( intelxl, &intelxl->command );
953  intelxl_disable_admin ( intelxl, &intelxl->event );
954 
955  /* Free admin queues */
956  intelxl_free_admin ( intelxl, &intelxl->command );
957  intelxl_free_admin ( intelxl, &intelxl->event );
958 }
959 
960 /******************************************************************************
961  *
962  * Descriptor rings
963  *
964  ******************************************************************************
965  */
966 
967 /**
968  * Allocate descriptor ring
969  *
970  * @v intelxl Intel device
971  * @v ring Descriptor ring
972  * @ret rc Return status code
973  */
974 int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
975  struct intelxl_ring *ring ) {
976  int rc;
977 
978  /* Allocate descriptor ring */
979  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
980  INTELXL_ALIGN );
981  if ( ! ring->desc.raw ) {
982  rc = -ENOMEM;
983  goto err_alloc;
984  }
985 
986  /* Initialise descriptor ring */
987  memset ( ring->desc.raw, 0, ring->len );
988 
989  /* Reset tail pointer */
990  writel ( 0, ( intelxl->regs + ring->tail ) );
991 
992  /* Reset counters */
993  ring->prod = 0;
994  ring->cons = 0;
995 
996  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
997  intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
998  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
999 
1000  return 0;
1001 
1002  dma_free ( &ring->map, ring->desc.raw, ring->len );
1003  err_alloc:
1004  return rc;
1005 }
1006 
1007 /**
1008  * Free descriptor ring
1009  *
1010  * @v intelxl Intel device
1011  * @v ring Descriptor ring
1012  */
1013 void intelxl_free_ring ( struct intelxl_nic *intelxl __unused,
1014  struct intelxl_ring *ring ) {
1015 
1016  /* Free descriptor ring */
1017  dma_free ( &ring->map, ring->desc.raw, ring->len );
1018  ring->desc.raw = NULL;
1019 }
1020 
1021 /**
1022  * Dump queue context (for debugging)
1023  *
1024  * @v intelxl Intel device
1025  * @v op Context operation
1026  * @v len Size of context
1027  */
1028 static __attribute__ (( unused )) void
1029 intelxl_context_dump ( struct intelxl_nic *intelxl, uint32_t op, size_t len ) {
1030  struct intelxl_context_line line;
1031  uint32_t pfcm_lanctxctl;
1032  uint32_t pfcm_lanctxstat;
1033  unsigned int queue;
1034  unsigned int index;
1035  unsigned int i;
1036 
1037  /* Do nothing unless debug output is enabled */
1038  if ( ! DBG_EXTRA )
1039  return;
1040 
1041  /* Dump context */
1042  DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
1043  for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
1044 
1045  /* Start context operation */
1046  queue = ( intelxl->base + intelxl->queue );
1047  pfcm_lanctxctl =
1051  writel ( pfcm_lanctxctl,
1052  intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1053 
1054  /* Wait for operation to complete */
1055  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1056 
1057  /* Check if operation is complete */
1058  pfcm_lanctxstat = readl ( intelxl->regs +
1060  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1061  break;
1062 
1063  /* Delay */
1064  mdelay ( 1 );
1065  }
1066 
1067  /* Read context data */
1068  for ( i = 0 ; i < ( sizeof ( line ) /
1069  sizeof ( line.raw[0] ) ) ; i++ ) {
1070  line.raw[i] = readl ( intelxl->regs +
1071  INTELXL_PFCM_LANCTXDATA ( i ) );
1072  }
1073  DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
1074  &line, sizeof ( line ) );
1075  }
1076 }
1077 
1078 /**
1079  * Program queue context line
1080  *
1081  * @v intelxl Intel device
1082  * @v line Queue context line
1083  * @v index Line number
1084  * @v op Context operation
1085  * @ret rc Return status code
1086  */
1087 static int intelxl_context_line ( struct intelxl_nic *intelxl,
1088  struct intelxl_context_line *line,
1089  unsigned int index, uint32_t op ) {
1090  uint32_t pfcm_lanctxctl;
1091  uint32_t pfcm_lanctxstat;
1092  unsigned int queue;
1093  unsigned int i;
1094 
1095  /* Write context data */
1096  for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
1097  writel ( le32_to_cpu ( line->raw[i] ),
1098  intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
1099  }
1100 
1101  /* Start context operation */
1102  queue = ( intelxl->base + intelxl->queue );
1103  pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
1106  writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1107 
1108  /* Wait for operation to complete */
1109  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1110 
1111  /* Check if operation is complete */
1112  pfcm_lanctxstat = readl ( intelxl->regs +
1114  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1115  return 0;
1116 
1117  /* Delay */
1118  mdelay ( 1 );
1119  }
1120 
1121  DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
1122  intelxl, pfcm_lanctxctl );
1123  return -ETIMEDOUT;
1124 }
1125 
1126 /**
1127  * Program queue context
1128  *
1129  * @v intelxl Intel device
1130  * @v line Queue context lines
1131  * @v len Size of context
1132  * @v op Context operation
1133  * @ret rc Return status code
1134  */
1135 static int intelxl_context ( struct intelxl_nic *intelxl,
1136  struct intelxl_context_line *line,
1137  size_t len, uint32_t op ) {
1138  unsigned int index;
1139  int rc;
1140 
1141  DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
1142  intelxl, op, len );
1143  DBGC2_HDA ( intelxl, 0, line, len );
1144 
1145  /* Program one line at a time */
1146  for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
1147  if ( ( rc = intelxl_context_line ( intelxl, line++, index,
1148  op ) ) != 0 )
1149  return rc;
1150  }
1151 
1152  return 0;
1153 }
1154 
1155 /**
1156  * Program transmit queue context
1157  *
1158  * @v intelxl Intel device
1159  * @v address Descriptor ring base address
1160  * @ret rc Return status code
1161  */
1162 static int intelxl_context_tx ( struct intelxl_nic *intelxl,
1163  physaddr_t address ) {
1164  union {
1165  struct intelxl_context_tx tx;
1166  struct intelxl_context_line line;
1167  } ctx;
1168  int rc;
1169 
1170  /* Initialise context */
1171  memset ( &ctx, 0, sizeof ( ctx ) );
1172  ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
1173  ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
1174  ctx.tx.count =
1176  ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
1177 
1178  /* Program context */
1179  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1181  return rc;
1182 
1183  return 0;
1184 }
1185 
1186 /**
1187  * Program receive queue context
1188  *
1189  * @v intelxl Intel device
1190  * @v address Descriptor ring base address
1191  * @ret rc Return status code
1192  */
1193 static int intelxl_context_rx ( struct intelxl_nic *intelxl,
1194  physaddr_t address ) {
1195  union {
1196  struct intelxl_context_rx rx;
1197  struct intelxl_context_line line;
1198  } ctx;
1199  uint64_t base_count;
1200  int rc;
1201 
1202  /* Initialise context */
1203  memset ( &ctx, 0, sizeof ( ctx ) );
1205  ctx.rx.base_count = cpu_to_le64 ( base_count );
1206  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
1208  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
1209 
1210  /* Program context */
1211  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1213  return rc;
1214 
1215  return 0;
1216 }
1217 
1218 /**
1219  * Enable descriptor ring
1220  *
1221  * @v intelxl Intel device
1222  * @v ring Descriptor ring
1223  * @ret rc Return status code
1224  */
1225 static int intelxl_enable_ring ( struct intelxl_nic *intelxl,
1226  struct intelxl_ring *ring ) {
1227  void *ring_regs = ( intelxl->regs + ring->reg );
1228  uint32_t qxx_ena;
1229 
1230  /* Enable ring */
1231  writel ( INTELXL_QXX_ENA_REQ, ( ring_regs + INTELXL_QXX_ENA ) );
1233  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1234  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) ) {
1235  DBGC ( intelxl, "INTELXL %p ring %06x failed to enable: "
1236  "%#08x\n", intelxl, ring->tail, qxx_ena );
1237  return -EIO;
1238  }
1239 
1240  return 0;
1241 }
1242 
1243 /**
1244  * Disable descriptor ring
1245  *
1246  * @v intelxl Intel device
1247  * @v ring Descriptor ring
1248  * @ret rc Return status code
1249  */
1250 static int intelxl_disable_ring ( struct intelxl_nic *intelxl,
1251  struct intelxl_ring *ring ) {
1252  void *ring_regs = ( intelxl->regs + ring->reg );
1253  uint32_t qxx_ena;
1254  unsigned int i;
1255 
1256  /* Disable ring */
1257  writel ( 0, ( ring_regs + INTELXL_QXX_ENA ) );
1258 
1259  /* Wait for ring to be disabled */
1260  for ( i = 0 ; i < INTELXL_QUEUE_DISABLE_MAX_WAIT_MS ; i++ ) {
1261 
1262  /* Check if ring is disabled */
1263  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1264  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) )
1265  return 0;
1266 
1267  /* Delay */
1268  mdelay ( 1 );
1269  }
1270 
1271  DBGC ( intelxl, "INTELXL %p ring %06x timed out waiting for disable: "
1272  "%#08x\n", intelxl, ring->tail, qxx_ena );
1273  return -ETIMEDOUT;
1274 }
1275 
1276 /**
1277  * Create descriptor ring
1278  *
1279  * @v intelxl Intel device
1280  * @v ring Descriptor ring
1281  * @ret rc Return status code
1282  */
1283 int intelxl_create_ring ( struct intelxl_nic *intelxl,
1284  struct intelxl_ring *ring ) {
1286  int rc;
1287 
1288  /* Allocate descriptor ring */
1289  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1290  goto err_alloc;
1291 
1292  /* Program queue context */
1293  address = dma ( &ring->map, ring->desc.raw );
1294  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1295  goto err_context;
1296 
1297  /* Enable ring */
1298  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1299  goto err_enable;
1300 
1301  return 0;
1302 
1303  intelxl_disable_ring ( intelxl, ring );
1304  err_enable:
1305  err_context:
1306  intelxl_free_ring ( intelxl, ring );
1307  err_alloc:
1308  return rc;
1309 }
1310 
1311 /**
1312  * Destroy descriptor ring
1313  *
1314  * @v intelxl Intel device
1315  * @v ring Descriptor ring
1316  */
1317 void intelxl_destroy_ring ( struct intelxl_nic *intelxl,
1318  struct intelxl_ring *ring ) {
1319  int rc;
1320 
1321  /* Disable ring */
1322  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1323  /* Leak memory; there's nothing else we can do */
1324  return;
1325  }
1326 
1327  /* Free descriptor ring */
1328  intelxl_free_ring ( intelxl, ring );
1329 }
1330 
1331 /**
1332  * Refill receive descriptor ring
1333  *
1334  * @v intelxl Intel device
1335  */
1336 static void intelxl_refill_rx ( struct intelxl_nic *intelxl ) {
1338  struct io_buffer *iobuf;
1339  unsigned int rx_idx;
1340  unsigned int rx_tail;
1341  unsigned int refilled = 0;
1342 
1343  /* Refill ring */
1344  while ( ( intelxl->rx.prod - intelxl->rx.cons ) < INTELXL_RX_FILL ) {
1345 
1346  /* Allocate I/O buffer */
1347  iobuf = alloc_rx_iob ( intelxl->mfs, intelxl->dma );
1348  if ( ! iobuf ) {
1349  /* Wait for next refill */
1350  break;
1351  }
1352 
1353  /* Get next receive descriptor */
1354  rx_idx = ( intelxl->rx.prod++ % INTELXL_RX_NUM_DESC );
1355  rx = &intelxl->rx.desc.rx[rx_idx].data;
1356 
1357  /* Populate receive descriptor */
1358  rx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1359  rx->flags = 0;
1360 
1361  /* Record I/O buffer */
1362  assert ( intelxl->rx_iobuf[rx_idx] == NULL );
1363  intelxl->rx_iobuf[rx_idx] = iobuf;
1364 
1365  DBGC2 ( intelxl, "INTELXL %p RX %d is [%08lx,%08lx)\n",
1366  intelxl, rx_idx, virt_to_phys ( iobuf->data ),
1367  ( virt_to_phys ( iobuf->data ) + intelxl->mfs ) );
1368  refilled++;
1369  }
1370 
1371  /* Push descriptors to card, if applicable */
1372  if ( refilled ) {
1373  wmb();
1374  rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1375  writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1376  }
1377 }
1378 
1379 /**
1380  * Discard unused receive I/O buffers
1381  *
1382  * @v intelxl Intel device
1383  */
1384 void intelxl_empty_rx ( struct intelxl_nic *intelxl ) {
1385  unsigned int i;
1386 
1387  /* Discard any unused receive buffers */
1388  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1389  if ( intelxl->rx_iobuf[i] )
1390  free_rx_iob ( intelxl->rx_iobuf[i] );
1391  intelxl->rx_iobuf[i] = NULL;
1392  }
1393 }
1394 
1395 /******************************************************************************
1396  *
1397  * Network device interface
1398  *
1399  ******************************************************************************
1400  */
1401 
1402 /**
1403  * Open network device
1404  *
1405  * @v netdev Network device
1406  * @ret rc Return status code
1407  */
1408 static int intelxl_open ( struct net_device *netdev ) {
1409  struct intelxl_nic *intelxl = netdev->priv;
1410  unsigned int queue;
1411  int rc;
1412 
1413  /* Calculate maximum frame size */
1414  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
1415  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
1416 
1417  /* Set MAC address */
1418  if ( ( rc = intelxl_admin_mac_write ( netdev ) ) != 0 )
1419  goto err_mac_write;
1420 
1421  /* Set maximum frame size */
1422  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
1423  goto err_mac_config;
1424 
1425  /* Associate transmit queue to PF */
1427  INTELXL_QXX_CTL_PFVF_PF_INDX ( intelxl->pf ) ),
1428  ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_CTL ) );
1429 
1430  /* Clear transmit pre queue disable */
1431  queue = ( intelxl->base + intelxl->queue );
1434  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1435 
1436  /* Reset transmit queue head */
1437  writel ( 0, ( intelxl->regs + INTELXL_QTX_HEAD ( intelxl->queue ) ) );
1438 
1439  /* Create receive descriptor ring */
1440  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
1441  goto err_create_rx;
1442 
1443  /* Create transmit descriptor ring */
1444  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->tx ) ) != 0 )
1445  goto err_create_tx;
1446 
1447  /* Fill receive ring */
1448  intelxl_refill_rx ( intelxl );
1449 
1450  /* Restart autonegotiation */
1451  intelxl_admin_autoneg ( intelxl );
1452 
1453  /* Update link state */
1455 
1456  return 0;
1457 
1460  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1462  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1463  err_create_tx:
1464  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1465  err_create_rx:
1466  err_mac_config:
1467  err_mac_write:
1468  return rc;
1469 }
1470 
1471 /**
1472  * Close network device
1473  *
1474  * @v netdev Network device
1475  */
1476 static void intelxl_close ( struct net_device *netdev ) {
1477  struct intelxl_nic *intelxl = netdev->priv;
1478  unsigned int queue;
1479 
1480  /* Dump contexts (for debugging) */
1482  sizeof ( struct intelxl_context_tx ) );
1484  sizeof ( struct intelxl_context_rx ) );
1485 
1486  /* Pre-disable transmit queue */
1487  queue = ( intelxl->base + intelxl->queue );
1490  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1492 
1493  /* Destroy transmit descriptor ring */
1494  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1495 
1496  /* Destroy receive descriptor ring */
1497  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1498 
1499  /* Discard any unused receive buffers */
1500  intelxl_empty_rx ( intelxl );
1501 }
1502 
1503 /**
1504  * Transmit packet
1505  *
1506  * @v netdev Network device
1507  * @v iobuf I/O buffer
1508  * @ret rc Return status code
1509  */
1510 int intelxl_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
1511  struct intelxl_nic *intelxl = netdev->priv;
1513  unsigned int tx_idx;
1514  unsigned int tx_tail;
1515  size_t len;
1516 
1517  /* Get next transmit descriptor */
1518  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1519  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1520  intelxl );
1521  return -ENOBUFS;
1522  }
1523  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1524  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1525  tx = &intelxl->tx.desc.tx[tx_idx].data;
1526 
1527  /* Populate transmit descriptor */
1528  len = iob_len ( iobuf );
1529  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1530  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1533  wmb();
1534 
1535  /* Notify card that there are packets ready to transmit */
1536  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1537 
1538  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1539  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1540  ( virt_to_phys ( iobuf->data ) + len ) );
1541  return 0;
1542 }
1543 
1544 /**
1545  * Poll for completed packets
1546  *
1547  * @v netdev Network device
1548  */
1549 static void intelxl_poll_tx ( struct net_device *netdev ) {
1550  struct intelxl_nic *intelxl = netdev->priv;
1551  struct intelxl_tx_writeback_descriptor *tx_wb;
1552  unsigned int tx_idx;
1553 
1554  /* Check for completed packets */
1555  while ( intelxl->tx.cons != intelxl->tx.prod ) {
1556 
1557  /* Get next transmit descriptor */
1558  tx_idx = ( intelxl->tx.cons % INTELXL_TX_NUM_DESC );
1559  tx_wb = &intelxl->tx.desc.tx[tx_idx].wb;
1560 
1561  /* Stop if descriptor is still in use */
1562  if ( ! ( tx_wb->flags & INTELXL_TX_WB_FL_DD ) )
1563  return;
1564  DBGC2 ( intelxl, "INTELXL %p TX %d complete\n",
1565  intelxl, tx_idx );
1566 
1567  /* Complete TX descriptor */
1569  intelxl->tx.cons++;
1570  }
1571 }
1572 
1573 /**
1574  * Poll for received packets
1575  *
1576  * @v netdev Network device
1577  */
1578 static void intelxl_poll_rx ( struct net_device *netdev ) {
1579  struct intelxl_nic *intelxl = netdev->priv;
1580  struct intelxl_rx_writeback_descriptor *rx_wb;
1581  struct io_buffer *iobuf;
1582  unsigned int rx_idx;
1583  unsigned int tag;
1584  size_t len;
1585 
1586  /* Check for received packets */
1587  while ( intelxl->rx.cons != intelxl->rx.prod ) {
1588 
1589  /* Get next receive descriptor */
1590  rx_idx = ( intelxl->rx.cons % INTELXL_RX_NUM_DESC );
1591  rx_wb = &intelxl->rx.desc.rx[rx_idx].wb;
1592 
1593  /* Stop if descriptor is still in use */
1594  if ( ! ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_DD ) ) )
1595  return;
1596 
1597  /* Populate I/O buffer */
1598  iobuf = intelxl->rx_iobuf[rx_idx];
1599  intelxl->rx_iobuf[rx_idx] = NULL;
1600  len = INTELXL_RX_WB_LEN ( le32_to_cpu ( rx_wb->len ) );
1601  iob_put ( iobuf, len );
1602 
1603  /* Find VLAN device, if applicable */
1604  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_VLAN ) ) {
1605  tag = VLAN_TAG ( le16_to_cpu ( rx_wb->vlan ) );
1606  } else {
1607  tag = 0;
1608  }
1609 
1610  /* Hand off to network stack */
1611  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_RXE ) ) {
1612  DBGC ( intelxl, "INTELXL %p RX %d error (length %zd, "
1613  "flags %08x)\n", intelxl, rx_idx, len,
1614  le32_to_cpu ( rx_wb->flags ) );
1615  vlan_netdev_rx_err ( netdev, tag, iobuf, -EIO );
1616  } else {
1617  DBGC2 ( intelxl, "INTELXL %p RX %d complete (length "
1618  "%zd)\n", intelxl, rx_idx, len );
1619  vlan_netdev_rx ( netdev, tag, iobuf );
1620  }
1621  intelxl->rx.cons++;
1622  }
1623 }
1624 
1625 /**
1626  * Poll for completed and received packets
1627  *
1628  * @v netdev Network device
1629  */
1630 void intelxl_poll ( struct net_device *netdev ) {
1631  struct intelxl_nic *intelxl = netdev->priv;
1632 
1633  /* Poll for completed packets */
1634  intelxl_poll_tx ( netdev );
1635 
1636  /* Poll for received packets */
1637  intelxl_poll_rx ( netdev );
1638 
1639  /* Poll for admin events */
1641 
1642  /* Refill RX ring */
1643  intelxl_refill_rx ( intelxl );
1644 
1645  /* Rearm interrupt, since otherwise receive descriptors will
1646  * be written back only after a complete cacheline (four
1647  * packets) have been received.
1648  *
1649  * There is unfortunately no efficient way to determine
1650  * whether or not rearming the interrupt is necessary. If we
1651  * are running inside a hypervisor (e.g. using a VF or PF as a
1652  * passed-through PCI device), then the MSI-X write is
1653  * redirected by the hypervisor to the real host APIC and the
1654  * host ISR then raises an interrupt within the guest. We
1655  * therefore cannot poll the nominal MSI-X target location to
1656  * watch for the value being written. We could read from the
1657  * INT_DYN_CTL register, but this is even less efficient than
1658  * just unconditionally rearming the interrupt.
1659  */
1660  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1661 }
1662 
1663 /** Network device operations */
1665  .open = intelxl_open,
1666  .close = intelxl_close,
1667  .transmit = intelxl_transmit,
1668  .poll = intelxl_poll,
1669 };
1670 
1671 /******************************************************************************
1672  *
1673  * PCI interface
1674  *
1675  ******************************************************************************
1676  */
1677 
1678 /**
1679  * Probe PCI device
1680  *
1681  * @v pci PCI device
1682  * @ret rc Return status code
1683  */
1684 static int intelxl_probe ( struct pci_device *pci ) {
1685  struct net_device *netdev;
1686  struct intelxl_nic *intelxl;
1687  uint32_t pffunc_rid;
1688  uint32_t pfgen_portnum;
1689  uint32_t pflan_qalloc;
1690  int rc;
1691 
1692  /* Allocate and initialise net device */
1693  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
1694  if ( ! netdev ) {
1695  rc = -ENOMEM;
1696  goto err_alloc;
1697  }
1700  intelxl = netdev->priv;
1701  pci_set_drvdata ( pci, netdev );
1702  netdev->dev = &pci->dev;
1703  memset ( intelxl, 0, sizeof ( *intelxl ) );
1704  intelxl->intr = INTELXL_PFINT_DYN_CTL0;
1705  intelxl->handle = intelxl_admin_event;
1711  sizeof ( intelxl->tx.desc.tx[0] ),
1714  sizeof ( intelxl->rx.desc.rx[0] ),
1716 
1717  /* Fix up PCI device */
1718  adjust_pci_device ( pci );
1719 
1720  /* Map registers */
1721  intelxl->regs = pci_ioremap ( pci, pci->membase, INTELXL_BAR_SIZE );
1722  if ( ! intelxl->regs ) {
1723  rc = -ENODEV;
1724  goto err_ioremap;
1725  }
1726 
1727  /* Configure DMA */
1728  intelxl->dma = &pci->dma;
1729  dma_set_mask_64bit ( intelxl->dma );
1730  netdev->dma = intelxl->dma;
1731 
1732  /* Locate PCI Express capability */
1733  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
1734  if ( ! intelxl->exp ) {
1735  DBGC ( intelxl, "INTELXL %p missing PCIe capability\n",
1736  intelxl );
1737  rc = -ENXIO;
1738  goto err_exp;
1739  }
1740 
1741  /* Reset the function via PCIe FLR */
1742  pci_reset ( pci, intelxl->exp );
1743 
1744  /* Get function number, port number and base queue number */
1745  pffunc_rid = readl ( intelxl->regs + INTELXL_PFFUNC_RID );
1746  intelxl->pf = INTELXL_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
1747  pfgen_portnum = readl ( intelxl->regs + INTELXL_PFGEN_PORTNUM );
1748  intelxl->port = INTELXL_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
1749  pflan_qalloc = readl ( intelxl->regs + INTELXL_PFLAN_QALLOC );
1750  intelxl->base = INTELXL_PFLAN_QALLOC_FIRSTQ ( pflan_qalloc );
1751  DBGC ( intelxl, "INTELXL %p PF %d using port %d queues [%#04x-%#04x]\n",
1752  intelxl, intelxl->pf, intelxl->port, intelxl->base,
1753  INTELXL_PFLAN_QALLOC_LASTQ ( pflan_qalloc ) );
1754 
1755  /* Enable MSI-X dummy interrupt */
1756  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
1757  INTELXL_MSIX_VECTOR ) ) != 0 )
1758  goto err_msix;
1759 
1760  /* Open admin queues */
1761  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
1762  goto err_open_admin;
1763 
1764  /* Get firmware version */
1765  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
1766  goto err_admin_version;
1767 
1768  /* Report driver version */
1769  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
1770  goto err_admin_driver;
1771 
1772  /* Clear PXE mode */
1773  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
1774  goto err_admin_clear_pxe;
1775 
1776  /* Get switch configuration */
1777  if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
1778  goto err_admin_switch;
1779 
1780  /* Get VSI configuration */
1781  if ( ( rc = intelxl_admin_vsi ( intelxl ) ) != 0 )
1782  goto err_admin_vsi;
1783 
1784  /* Configure switch for promiscuous mode */
1785  if ( ( rc = intelxl_admin_promisc ( intelxl ) ) != 0 )
1786  goto err_admin_promisc;
1787 
1788  /* Get MAC address */
1789  if ( ( rc = intelxl_admin_mac_read ( netdev ) ) != 0 )
1790  goto err_admin_mac_read;
1791 
1792  /* Configure queue register addresses */
1793  intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1794  intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1795  intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1796  intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1797 
1798  /* Configure interrupt causes */
1801  intelxl->regs + INTELXL_QINT_TQCTL ( intelxl->queue ) );
1802  writel ( ( INTELXL_QINT_RQCTL_NEXTQ_INDX ( intelxl->queue ) |
1805  intelxl->regs + INTELXL_QINT_RQCTL ( intelxl->queue ) );
1808  intelxl->regs + INTELXL_PFINT_LNKLST0 );
1810  intelxl->regs + INTELXL_PFINT_ICR0_ENA );
1811 
1812  /* Register network device */
1813  if ( ( rc = register_netdev ( netdev ) ) != 0 )
1814  goto err_register_netdev;
1815 
1816  /* Set initial link state */
1818 
1819  return 0;
1820 
1822  err_register_netdev:
1823  err_admin_mac_read:
1824  err_admin_promisc:
1825  err_admin_vsi:
1826  err_admin_switch:
1827  err_admin_clear_pxe:
1828  err_admin_driver:
1829  err_admin_version:
1830  intelxl_close_admin ( intelxl );
1831  err_open_admin:
1832  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1833  err_msix:
1834  pci_reset ( pci, intelxl->exp );
1835  err_exp:
1836  iounmap ( intelxl->regs );
1837  err_ioremap:
1838  netdev_nullify ( netdev );
1839  netdev_put ( netdev );
1840  err_alloc:
1841  return rc;
1842 }
1843 
1844 /**
1845  * Remove PCI device
1846  *
1847  * @v pci PCI device
1848  */
1849 static void intelxl_remove ( struct pci_device *pci ) {
1850  struct net_device *netdev = pci_get_drvdata ( pci );
1851  struct intelxl_nic *intelxl = netdev->priv;
1852 
1853  /* Unregister network device */
1855 
1856  /* Close admin queues */
1857  intelxl_close_admin ( intelxl );
1858 
1859  /* Disable MSI-X dummy interrupt */
1860  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1861 
1862  /* Reset the NIC */
1863  pci_reset ( pci, intelxl->exp );
1864 
1865  /* Free network device */
1866  iounmap ( intelxl->regs );
1867  netdev_nullify ( netdev );
1868  netdev_put ( netdev );
1869 }
1870 
1871 /** PCI device IDs */
1872 static struct pci_device_id intelxl_nics[] = {
1873  PCI_ROM ( 0x8086, 0x0cf8, "x710-n3000", "X710 FPGA N3000", 0 ),
1874  PCI_ROM ( 0x8086, 0x0d58, "xxv710-n3000", "XXV710 FPGA N3000", 0 ),
1875  PCI_ROM ( 0x8086, 0x104e, "x710-sfp-b", "X710 10GbE SFP+", 0 ),
1876  PCI_ROM ( 0x8086, 0x104f, "x710-kx-b", "X710 10GbE backplane", 0 ),
1877  PCI_ROM ( 0x8086, 0x1572, "x710-sfp", "X710 10GbE SFP+", 0 ),
1878  PCI_ROM ( 0x8086, 0x1574, "xl710-qemu", "Virtual XL710", 0 ),
1879  PCI_ROM ( 0x8086, 0x1580, "xl710-kx-b", "XL710 40GbE backplane", 0 ),
1880  PCI_ROM ( 0x8086, 0x1581, "xl710-kx-c", "XL710 10GbE backplane", 0 ),
1881  PCI_ROM ( 0x8086, 0x1583, "xl710-qda2", "XL710 40GbE QSFP+", 0 ),
1882  PCI_ROM ( 0x8086, 0x1584, "xl710-qda1", "XL710 40GbE QSFP+", 0 ),
1883  PCI_ROM ( 0x8086, 0x1585, "x710-qsfp", "X710 10GbE QSFP+", 0 ),
1884  PCI_ROM ( 0x8086, 0x1586, "x710-10gt", "X710 10GBASE-T", 0 ),
1885  PCI_ROM ( 0x8086, 0x1587, "x710-kr2", "XL710 20GbE backplane", 0 ),
1886  PCI_ROM ( 0x8086, 0x1588, "x710-kr2-a", "XL710 20GbE backplane", 0 ),
1887  PCI_ROM ( 0x8086, 0x1589, "x710-10gt4", "X710 10GBASE-T4", 0 ),
1888  PCI_ROM ( 0x8086, 0x158a, "xxv710", "XXV710 25GbE backplane", 0 ),
1889  PCI_ROM ( 0x8086, 0x158b, "xxv710-sfp28", "XXV710 25GbE SFP28", 0 ),
1890  PCI_ROM ( 0x8086, 0x15ff, "x710-10gt-b", "X710 10GBASE-T", 0 ),
1891  PCI_ROM ( 0x8086, 0x37ce, "x722-kx", "X722 10GbE backplane", 0 ),
1892  PCI_ROM ( 0x8086, 0x37cf, "x722-qsfp", "X722 10GbE QSFP+", 0 ),
1893  PCI_ROM ( 0x8086, 0x37d0, "x722-sfp", "X722 10GbE SFP+", 0 ),
1894  PCI_ROM ( 0x8086, 0x37d1, "x722-1gt", "X722 1GBASE-T", 0 ),
1895  PCI_ROM ( 0x8086, 0x37d2, "x722-10gt", "X722 10GBASE-T", 0 ),
1896  PCI_ROM ( 0x8086, 0x37d3, "x722-sfp-i", "X722 10GbE SFP+", 0 ),
1897 };
1898 
1899 /** PCI driver */
1900 struct pci_driver intelxl_driver __pci_driver = {
1901  .ids = intelxl_nics,
1902  .id_count = ( sizeof ( intelxl_nics ) / sizeof ( intelxl_nics[0] ) ),
1903  .probe = intelxl_probe,
1905 };
const char product_short_name[]
Product short name string.
Definition: version.c:76
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
static int intelxl_admin_promisc(struct intelxl_nic *intelxl)
Set VSI promiscuous modes.
Definition: intelxl.c:698
Receive queue context.
Definition: intelxl.h:567
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)
First queue.
Definition: intelxl.h:892
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:625
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1510
#define __attribute__(x)
Definition: compiler.h:10
void * regs
Registers.
Definition: intelxl.h:921
#define VLAN_TAG(tci)
Extract VLAN tag from tag control information.
Definition: vlan.h:29
#define INTELXL_ADMIN_PROMISC_FL_VLAN
Promiscuous VLAN mode.
Definition: intelxl.h:307
#define INTELXL_QRX(x)
Global Receive Queue register block.
Definition: intelxl.h:638
struct option_descriptor read[1]
Definition: nvo_cmd.c:115
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:337
unsigned long membase
Memory base.
Definition: pci.h:215
#define INTELXL_ADMIN_SHUTDOWN
Admin queue Shutdown command.
Definition: intelxl.h:135
size_t len
Length (in bytes)
Definition: intelxl.h:777
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:439
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
#define INTELXL_PFLAN_QALLOC_LASTQ(x)
Last queue.
Definition: intelxl.h:895
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:591
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define INTELXL_ADMIN_BAH
Admin Queue Base Address High Register (offset)
Definition: intelxl.h:45
#define iob_put(iobuf, len)
Definition: iobuf.h:120
struct dma_device dma
DMA device.
Definition: pci.h:210
#define INTELXL_PFFUNC_RID
Function Requester ID Information Register.
Definition: intelxl.h:885
struct pci_msix cap
PCI capability.
Definition: intelxl.h:908
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1317
uint32_t raw[4]
Raw data.
Definition: intelxl.h:531
A PCI driver.
Definition: pci.h:245
static int intelxl_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: intelxl.c:610
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:39
#define INTELXL_PFLAN_QALLOC
PF Queue Allocation Register.
Definition: intelxl.h:891
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:912
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:783
#define INTELXL_QXX_CTL_PFVF_Q_PF
PF queue.
Definition: intelxl.h:648
static void intelxl_context_dump(struct intelxl_nic *intelxl, uint32_t op, size_t len)
Dump queue context (for debugging)
Definition: intelxl.c:1029
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:626
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
static int intelxl_context_tx(struct intelxl_nic *intelxl, physaddr_t address)
Program transmit queue context.
Definition: intelxl.c:1162
static int intelxl_open(struct net_device *netdev)
Open network device.
Definition: intelxl.c:1408
uint32_t next
Next descriptor address.
Definition: myson.h:18
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:206
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:326
Error codes.
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)
Queue index.
Definition: intelxl.h:862
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:972
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE
Write context.
Definition: intelxl.h:521
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define INTELXL_ADMIN_LEN_ENABLE
Queue enable.
Definition: intelxl.h:50
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:273
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE
End of list.
Definition: intelxl.h:875
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:36
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:277
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:409
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:768
Admin queue register offsets.
Definition: intelxl.h:63
I/O buffers.
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:329
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1225
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:247
uint16_t vlan
VLAN tag.
Definition: intelxl.h:723
uint8_t type
Switching element type.
Definition: intelxl.h:211
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:472
uint16_t opcode
Opcode.
Definition: intelxl.h:419
Queue context line.
Definition: intelxl.h:529
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:415
Admin queue.
Definition: intelxl.h:451
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:669
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:259
unsigned int qset
Queue set handle.
Definition: intelxl.h:938
#define INTELXL_RX_WB_FL_DD
Receive writeback descriptor complete.
Definition: intelxl.h:735
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:666
#define DBGC(...)
Definition: compiler.h:505
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:578
#define INTELXL_PFINT_ICR0_ENA
PF Interrupt Zero Cause Enablement Register.
Definition: intelxl.h:857
unsigned int prod
Producer index.
Definition: intelxl.h:768
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
Admin queue Shutdown command parameters.
Definition: intelxl.h:138
#define ENOENT
No such file or directory.
Definition: errno.h:514
char name[32]
Driver name.
Definition: intelxl.h:131
uint16_t flags
Flags.
Definition: intelxl.h:417
static int intelxl_context_rx(struct intelxl_nic *intelxl, physaddr_t address)
Program receive queue context.
Definition: intelxl.c:1193
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:474
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:256
unsigned long long uint64_t
Definition: stdint.h:13
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:837
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:169
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:403
struct dma_device * dma
DMA device.
Definition: netdevice.h:366
static int intelxl_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: intelxl.c:496
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1549
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
#define cpu_to_le64(value)
Definition: byteswap.h:108
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:183
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:600
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:643
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:751
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1250
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
unsigned int bal
Base Address Low Register offset.
Definition: intelxl.h:65
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_PFINT_ICR0_ENA_ADMINQ
Admin event.
Definition: intelxl.h:858
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:407
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: intelxl.h:901
Admin queue Set MAC Configuration command parameters.
Definition: intelxl.h:313
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:894
unsigned int base
Register block base.
Definition: intelxl.h:462
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:124
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
struct intelxl_admin_version api
API version.
Definition: intelxl.h:106
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:594
#define INTELXL_ADMIN_VSI
Admin queue Get VSI Parameters command.
Definition: intelxl.h:256
struct device dev
Generic device.
Definition: pci.h:208
unsigned int queue
Queue number.
Definition: intelxl.h:934
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:195
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:946
#define INTELXL_ADMIN_PROMISC
Admin queue Set VSI Promiscuous Modes command.
Definition: intelxl.h:283
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:641
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:685
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:160
Intel 40 Gigabit Ethernet network card driver.
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:510
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:512
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1336
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:514
static struct pci_device_id intelxl_nics[]
PCI device IDs.
Definition: intelxl.c:1872
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:357
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:770
#define INTELXL_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: intelxl.h:900
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint8_t pf[ETH_ALEN]
Physical function MAC address.
Definition: intelxl.h:165
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1135
uint16_t len
Data length.
Definition: intelxl.h:421
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:475
#define INTELXL_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:882
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:436
u32 version
Driver version.
Definition: ath9k_hw.c:1983
unsigned int index
Queue index.
Definition: intelxl.h:459
Transmit writeback descriptor.
Definition: intelxl.h:688
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:203
#define ETH_HLEN
Definition: if_ether.h:9
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:963
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX
Receive queue.
Definition: intelxl.h:851
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:272
#define INTELXL_PFINT_DYN_CTL0
PF Interrupt Zero Dynamic Control Register.
Definition: intelxl.h:836
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:826
uint8_t magic
Magic value.
Definition: intelxl.h:197
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:567
Ethernet protocol.
static void intelxl_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
Handle admin event.
Definition: intelxl.c:814
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)
PF index.
Definition: intelxl.h:650
#define INTELXL_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:870
Admin queue version number.
Definition: intelxl.h:90
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:60
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:936
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX
Transmit queue.
Definition: intelxl.h:868
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:703
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
#define bswap_16(value)
Definition: byteswap.h:58
uint16_t high
MAC address first 16 bits, byte-swapped.
Definition: intelxl.h:184
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:503
#define DBGC_HDA(...)
Definition: compiler.h:506
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:778
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
void * raw
Raw data.
Definition: intelxl.h:763
uint16_t flags
Flags.
Definition: intelxl.h:288
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:525
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:264
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:835
#define INTELXL_QXX_ENA_REQ
Enable request.
Definition: intelxl.h:642
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:72
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:87
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
#define INTELXL_CTX_TX_FL_NEW
New transmit queue context.
Definition: intelxl.h:555
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1283
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:853
uint32_t low
MAC address last 32 bits, byte-swapped.
Definition: intelxl.h:186
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:894
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:219
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:948
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:489
union intelxl_ring::@65 desc
Descriptors.
#define INTELXL_ADMIN_EEXIST
Error: attempt to create something that already exists.
Definition: intelxl.h:448
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define bswap_32(value)
Definition: byteswap.h:70
unsigned int reg
Register block.
Definition: intelxl.h:773
#define cpu_to_le32(value)
Definition: byteswap.h:107
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:141
#define EPROTO
Protocol error.
Definition: errno.h:624
struct intelxl_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: intelxl.h:405
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS
Maximum time to wait for a queue to become disabled.
Definition: intelxl.h:612
Receive data descriptor.
Definition: intelxl.h:709
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:672
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:149
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
Admin queue Driver Version command parameters.
Definition: intelxl.h:113
Admin queue Manage MAC Address Read command parameters.
Definition: intelxl.h:152
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:181
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
PCI bus.
A PCI device.
Definition: pci.h:206
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:719
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
device nvs write
Definition: threewire.h:61
unsigned int intr
Interrupt control register.
Definition: intelxl.h:944
static int intelxl_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: intelxl.c:754
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:506
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
A network device.
Definition: netdevice.h:352
#define INTELXL_QTX(x)
Global Transmit Queue register block.
Definition: intelxl.h:635
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:523
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:223
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:175
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
unsigned char uint8_t
Definition: stdint.h:10
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:208
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:105
unsigned int port
Port number.
Definition: intelxl.h:932
#define INTELXL_ADMIN_BAL
Admin Queue Base Address Low Register (offset)
Definition: intelxl.h:42
Admin queue Get Version command parameters.
Definition: intelxl.h:98
Transmit data descriptor.
Definition: intelxl.h:656
#define INTELXL_CTX_TX_QSET(qset)
Transmit queue set.
Definition: intelxl.h:564
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:609
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define INTELXL_PFINT_LNKLST0
PF Interrupt Zero Linked List Register.
Definition: intelxl.h:842
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:682
#define ETH_ALEN
Definition: if_ether.h:8
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:261
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:429
uint8_t connection
Connection type.
Definition: intelxl.h:223
A PCI device ID list entry.
Definition: pci.h:170
Version number.
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:795
#define INTELXL_ADMIN_LEN_LEN(x)
Queue length.
Definition: intelxl.h:49
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
uint32_t high
Buffer address high.
Definition: intelxl.h:81
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
static void intelxl_close(struct net_device *netdev)
Close network device.
Definition: intelxl.c:1476
struct i386_regs regs
Definition: registers.h:15
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:97
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
struct pci_driver intelxl_driver __pci_driver
PCI driver.
Definition: intelxl.c:1900
Network device operations.
Definition: netdevice.h:213
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:916
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:292
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
static int intelxl_admin_version(struct intelxl_nic *intelxl)
Get firmware version.
Definition: intelxl.c:405
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:286
#define DMA_RX
Device will write data to host memory.
Definition: dma.h:135
#define INTELXL_CTX_TX_BASE(base)
Transmit queue base address.
Definition: intelxl.h:558
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:597
#define INTELXL_ADMIN_MAC_CONFIG
Admin queue Set MAC Configuration command.
Definition: intelxl.h:310
Network device management.
unsigned long physaddr_t
Definition: stdint.h:20
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define INTELXL_QINT_TQCTL(x)
Transmit Queue Interrupt Cause Control Register.
Definition: intelxl.h:873
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:367
const int product_major_version
Product major version.
Definition: version.c:64
#define INTELXL_TX_WB_FL_DD
Transmit writeback descriptor complete.
Definition: intelxl.h:698
unsigned int pf
Physical function number.
Definition: intelxl.h:928
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
Admin queue descriptor.
Definition: intelxl.h:415
#define ENXIO
No such device or address.
Definition: errno.h:599
uint32_t low
Buffer address low.
Definition: intelxl.h:83
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:217
static int intelxl_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: intelxl.c:544
#define INTELXL_ADMIN_TAIL
Admin Queue Tail Register (offset)
Definition: intelxl.h:56
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:315
#define INTELXL_QXX_TAIL
Queue Tail Pointer Register (offset)
Definition: intelxl.h:653
#define INTELXL_RX_WB_LEN(len)
Receive writeback descriptor length.
Definition: intelxl.h:744
__weak void vlan_netdev_rx(struct net_device *netdev, unsigned int tag, struct io_buffer *iobuf)
Add VLAN tag-stripped packet to queue (when VLAN support is not present)
Definition: netdevice.c:1160
uint32_t len
Length.
Definition: ena.h:14
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:629
uint8_t unused[32]
Unused.
Definition: eltorito.h:15
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:208
static int intelxl_probe(struct pci_device *pci)
Probe PCI device.
Definition: intelxl.c:1684
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define INTELXL_QUEUE_ENABLE_DELAY_US
Time to wait for a queue to become enabled.
Definition: intelxl.h:606
#define DBGC2(...)
Definition: compiler.h:522
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:258
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:365
Admin queue Manage MAC Address Write command parameters.
Definition: intelxl.h:178
void * data
Start of data.
Definition: iobuf.h:48
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:362
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)
Queue index.
Definition: intelxl.h:843
static int intelxl_context_line(struct intelxl_nic *intelxl, struct intelxl_context_line *line, unsigned int index, uint32_t op)
Program queue context line.
Definition: intelxl.c:1087
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:104
#define EIO
Input/output error.
Definition: errno.h:433
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:526
__weak void vlan_netdev_rx_err(struct net_device *netdev, unsigned int tag __unused, struct io_buffer *iobuf, int rc)
Discard received VLAN tag-stripped packet (when VLAN support is not present)
Definition: netdevice.c:1178
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS
Clear disable.
Definition: intelxl.h:631
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST
Promiscuous broadcast mode.
Definition: intelxl.h:304
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
void iounmap(volatile const void *io_addr)
Unmap I/O address.
Descriptor ring.
Definition: intelxl.h:755
Virtual LANs.
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:252
unsigned int tail
Tail register.
Definition: intelxl.h:775
Receive writeback descriptor.
Definition: intelxl.h:719
unsigned int tail
Tail Register offset.
Definition: intelxl.h:73
__be32 raw[7]
Definition: CIB_PRM.h:28
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:340
#define INTELXL_QINT_RQCTL(x)
Receive Queue Interrupt Cause Control Register.
Definition: intelxl.h:861
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:370
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:924
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC
Append CRC on transmit.
Definition: intelxl.h:323
#define INTELXL_BAR_SIZE
BAR size.
Definition: intelxl.h:20
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:234
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING
Driver is unloading.
Definition: intelxl.h:146
uint16_t valid
Valid flags.
Definition: intelxl.h:290
static int intelxl_admin_vsi(struct intelxl_nic *intelxl)
Get VSI parameters.
Definition: intelxl.c:664
void shutdown(int flags)
Shut down iPXE.
Definition: init.c:98
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:705
#define INTELXL_ADMIN_PROMISC_FL_UNICAST
Promiscuous unicast mode.
Definition: intelxl.h:298
const char product_name[]
Product name string.
Definition: version.c:73
#define DBG_EXTRA
Definition: compiler.h:319
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:387
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:409
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
static struct net_device_operations intelxl_operations
Network device operations.
Definition: intelxl.c:1664
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:946
#define INTELXL_ADMIN_DRIVER
Admin queue Driver Version command.
Definition: intelxl.h:110
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:181
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: intelxl.h:886
#define INTELXL_CTX_TX_COUNT(count)
Transmit queue count.
Definition: intelxl.h:561
#define INTELXL_ADMIN_SWITCH_TYPE_VSI
Virtual Station Inferface element type.
Definition: intelxl.h:231
#define INTELXL_RX_FILL
Receive descriptor ring fill level.
Definition: intelxl.h:823
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:779
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:441
uint64_t tag
Identity tag.
Definition: edd.h:30
uint16_t queue
Queue ID.
Definition: ena.h:22
Transmit queue context.
Definition: intelxl.h:535
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:192
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
uint16_t seid
Switching element ID.
Definition: intelxl.h:215
#define INTELXL_RX_WB_FL_RXE
Receive writeback descriptor error.
Definition: intelxl.h:741
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:587
static void intelxl_remove(struct pci_device *pci)
Remove PCI device.
Definition: intelxl.c:1849
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:381
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:486
#define INTELXL_ADMIN_LEN
Admin Queue Length Register (offset)
Definition: intelxl.h:48
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST
Promiscuous multicast mode.
Definition: intelxl.h:301
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
#define INTELXL_QXX_CTL
Queue Control Register (offset)
Definition: intelxl.h:646
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_QTX_HEAD(x)
Global Transmit Queue Head register.
Definition: intelxl.h:622
String functions.
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:301
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:502
const int product_minor_version
Product minor version.
Definition: version.c:67
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1384
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:811
#define INTELXL_ADMIN_HEAD
Admin Queue Head Register (offset)
Definition: intelxl.h:53
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:729
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:499
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1630
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:974
Admin queue data buffer.
Definition: intelxl.h:401
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:910
#define INTELXL_RX_WB_FL_VLAN
Receive writeback descriptor VLAN tag present.
Definition: intelxl.h:738
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:749
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1578
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:62
A persistent I/O buffer.
Definition: iobuf.h:33
uint8_t flags
Flags.
Definition: ena.h:18
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ
Read context.
Definition: intelxl.h:519