iPXE
intelxlvf.h
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1 #ifndef _INTELXLVF_H
2 #define _INTELXLVF_H
3 
4 /** @file
5  *
6  * Intel 40 Gigabit Ethernet virtual function network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include "intelxl.h"
13 
14 /** BAR size */
15 #define INTELXLVF_BAR_SIZE 0x10000
16 
17 /** Transmit Queue Tail Register */
18 #define INTELXLVF_QTX_TAIL 0x00000
19 
20 /** Receive Queue Tail Register */
21 #define INTELXLVF_QRX_TAIL 0x02000
22 
23 /** VF Interrupt Zero Dynamic Control Register */
24 #define INTELXLVF_VFINT_DYN_CTL0 0x5c00
25 
26 /** VF Admin Queue register block */
27 #define INTELXLVF_ADMIN 0x6000
28 
29 /** Admin Command Queue Base Address Low Register (offset) */
30 #define INTELXLVF_ADMIN_CMD_BAL 0x1c00
31 
32 /** Admin Command Queue Base Address High Register (offset) */
33 #define INTELXLVF_ADMIN_CMD_BAH 0x1800
34 
35 /** Admin Command Queue Length Register (offset) */
36 #define INTELXLVF_ADMIN_CMD_LEN 0x0800
37 
38 /** Admin Command Queue Head Register (offset) */
39 #define INTELXLVF_ADMIN_CMD_HEAD 0x0400
40 
41 /** Admin Command Queue Tail Register (offset) */
42 #define INTELXLVF_ADMIN_CMD_TAIL 0x2400
43 
44 /** Admin Event Queue Base Address Low Register (offset) */
45 #define INTELXLVF_ADMIN_EVT_BAL 0x0c00
46 
47 /** Admin Event Queue Base Address High Register (offset) */
48 #define INTELXLVF_ADMIN_EVT_BAH 0x0000
49 
50 /** Admin Event Queue Length Register (offset) */
51 #define INTELXLVF_ADMIN_EVT_LEN 0x2000
52 
53 /** Admin Event Queue Head Register (offset) */
54 #define INTELXLVF_ADMIN_EVT_HEAD 0x1400
55 
56 /** Admin Event Queue Tail Register (offset) */
57 #define INTELXLVF_ADMIN_EVT_TAIL 0x1000
58 
59 /** Maximum time to wait for a VF admin request to complete */
60 #define INTELXLVF_ADMIN_MAX_WAIT_MS 2000
61 
62 /** VF Reset Status Register */
63 #define INTELXLVF_VFGEN_RSTAT 0x8800
64 #define INTELXLVF_VFGEN_RSTAT_VFR_STATE(x) ( (x) & 0x3 )
65 #define INTELXLVF_VFGEN_RSTAT_VFR_STATE_ACTIVE 0x2
66 
67 /** Maximum time to wait for reset to complete */
68 #define INTELXLVF_RESET_MAX_WAIT_MS 1000
69 
70 /**
71  * Initialise descriptor ring
72  *
73  * @v ring Descriptor ring
74  * @v count Number of descriptors
75  * @v len Length of a single descriptor
76  * @v tail Tail register offset
77  */
78 static inline __attribute__ (( always_inline)) void
79 intelxlvf_init_ring ( struct intelxl_ring *ring, unsigned int count,
80  size_t len, unsigned int tail ) {
81 
82  ring->len = ( count * len );
83  ring->tail = tail;
84 }
85 
86 #endif /* _INTELXLVF_H */
#define __attribute__(x)
Definition: compiler.h:10
size_t len
Length (in bytes)
Definition: intelxl.h:884
Intel 40 Gigabit Ethernet network card driver.
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
uint32_t len
Length.
Definition: ena.h:14
uint16_t count
Number of entries.
Definition: ena.h:22
static void intelxlvf_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, unsigned int tail)
Initialise descriptor ring.
Definition: intelxlvf.h:79
Descriptor ring.
Definition: intelxl.h:864
unsigned int tail
Tail register.
Definition: intelxl.h:882