iPXE
Functions | Variables
intelxl.c File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/vlan.h>
#include <ipxe/iobuf.h>
#include <ipxe/pci.h>
#include <ipxe/version.h>
#include "intelxl.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Enable MSI-X dummy interrupt. More...
 
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Disable MSI-X dummy interrupt. More...
 
static int intelxl_alloc_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Allocate admin queue. More...
 
static void intelxl_enable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Enable admin queue. More...
 
static void intelxl_disable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Disable admin queue. More...
 
static void intelxl_free_admin (struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
 Free admin queue. More...
 
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor. More...
 
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer. More...
 
static void intelxl_admin_event_init (struct intelxl_nic *intelxl, unsigned int index)
 Initialise admin event queue descriptor. More...
 
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command. More...
 
static int intelxl_admin_version (struct intelxl_nic *intelxl)
 Get firmware version. More...
 
static int intelxl_admin_driver (struct intelxl_nic *intelxl)
 Report driver version. More...
 
static int intelxl_admin_shutdown (struct intelxl_nic *intelxl)
 Shutdown admin queues. More...
 
static int intelxl_admin_mac_read (struct net_device *netdev)
 Get MAC address. More...
 
static int intelxl_admin_mac_write (struct net_device *netdev)
 Set MAC address. More...
 
int intelxl_admin_clear_pxe (struct intelxl_nic *intelxl)
 Clear PXE mode. More...
 
static int intelxl_admin_switch (struct intelxl_nic *intelxl)
 Get switch configuration. More...
 
static int intelxl_admin_vsi (struct intelxl_nic *intelxl)
 Get VSI parameters. More...
 
static int intelxl_admin_promisc (struct intelxl_nic *intelxl)
 Set VSI promiscuous modes. More...
 
int intelxl_admin_mac_config (struct intelxl_nic *intelxl)
 Set MAC configuration. More...
 
static int intelxl_admin_autoneg (struct intelxl_nic *intelxl)
 Restart autonegotiation. More...
 
static int intelxl_admin_link (struct net_device *netdev)
 Get link status. More...
 
static void intelxl_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
 Handle admin event. More...
 
static void intelxl_refill_admin (struct intelxl_nic *intelxl)
 Refill admin event queue. More...
 
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue. More...
 
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues. More...
 
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset) More...
 
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues. More...
 
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring. More...
 
void intelxl_free_ring (struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
 Free descriptor ring. More...
 
static void intelxl_context_dump (struct intelxl_nic *intelxl, uint32_t op, size_t len)
 Dump queue context (for debugging) More...
 
static int intelxl_context_line (struct intelxl_nic *intelxl, struct intelxl_context_line *line, unsigned int index, uint32_t op)
 Program queue context line. More...
 
static int intelxl_context (struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
 Program queue context. More...
 
static int intelxl_context_tx (struct intelxl_nic *intelxl, physaddr_t address)
 Program transmit queue context. More...
 
static int intelxl_context_rx (struct intelxl_nic *intelxl, physaddr_t address)
 Program receive queue context. More...
 
static int intelxl_enable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Enable descriptor ring. More...
 
static int intelxl_disable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Disable descriptor ring. More...
 
int intelxl_create_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Create descriptor ring. More...
 
void intelxl_destroy_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Destroy descriptor ring. More...
 
static void intelxl_refill_rx (struct intelxl_nic *intelxl)
 Refill receive descriptor ring. More...
 
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers. More...
 
static int intelxl_open (struct net_device *netdev)
 Open network device. More...
 
static void intelxl_close (struct net_device *netdev)
 Close network device. More...
 
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
static void intelxl_poll_tx (struct net_device *netdev)
 Poll for completed packets. More...
 
static void intelxl_poll_rx (struct net_device *netdev)
 Poll for received packets. More...
 
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets. More...
 
static int intelxl_probe (struct pci_device *pci)
 Probe PCI device. More...
 
static void intelxl_remove (struct pci_device *pci)
 Remove PCI device. More...
 

Variables

const struct intelxl_admin_offsets intelxl_admin_offsets
 Admin queue register offsets. More...
 
static struct net_device_operations intelxl_operations
 Network device operations. More...
 
static struct pci_device_id intelxl_nics []
 PCI device IDs. More...
 
struct pci_driver intelxl_driver __pci_driver
 PCI driver. More...
 

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ intelxl_msix_enable()

int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Enable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector
Return values
rcReturn status code

Definition at line 62 of file intelxl.c.

63  {
64  int rc;
65 
66  /* Map dummy target location */
67  if ( ( rc = dma_map ( intelxl->dma, &intelxl->msix.map,
68  virt_to_phys ( &intelxl->msix.msg ),
69  sizeof ( intelxl->msix.msg ), DMA_RX ) ) != 0 ) {
70  DBGC ( intelxl, "INTELXL %p could not map MSI-X target: %s\n",
71  intelxl, strerror ( rc ) );
72  goto err_map;
73  }
74 
75  /* Enable MSI-X capability */
76  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix.cap ) ) != 0 ) {
77  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
78  intelxl, strerror ( rc ) );
79  goto err_enable;
80  }
81 
82  /* Configure interrupt to write to dummy location */
83  pci_msix_map ( &intelxl->msix.cap, vector,
84  dma ( &intelxl->msix.map, &intelxl->msix.msg ), 0 );
85 
86  /* Enable dummy interrupt */
87  pci_msix_unmask ( &intelxl->msix.cap, vector );
88 
89  return 0;
90 
91  pci_msix_disable ( pci, &intelxl->msix.cap );
92  err_enable:
93  dma_unmap ( &intelxl->msix.map );
94  err_map:
95  return rc;
96 }
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
struct pci_msix cap
PCI capability.
Definition: intelxl.h:908
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:912
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define DBGC(...)
Definition: compiler.h:505
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:72
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:948
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
#define DMA_RX
Device will write data to host memory.
Definition: dma.h:135
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:104
void pci_msix_map(struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
Map MSI-X interrupt vector.
Definition: pcimsix.c:181
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
uint32_t msg
MSI-X dummy interrupt target.
Definition: intelxl.h:910

References intelxl_msix::cap, DBGC, dma(), intelxl_nic::dma, DMA_RX, dma_unmap(), intelxl_msix::map, intelxl_msix::msg, intelxl_nic::msix, pci_msix_disable(), pci_msix_enable(), pci_msix_map(), pci_msix_unmask(), rc, strerror(), vector, and virt_to_phys().

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Disable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector

Definition at line 105 of file intelxl.c.

106  {
107 
108  /* Disable dummy interrupts */
109  pci_msix_mask ( &intelxl->msix.cap, vector );
110 
111  /* Disable MSI-X capability */
112  pci_msix_disable ( pci, &intelxl->msix.cap );
113 
114  /* Unmap dummy target location */
115  dma_unmap ( &intelxl->msix.map );
116 }
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:158
struct pci_msix cap
PCI capability.
Definition: intelxl.h:908
struct dma_mapping map
DMA mapping for dummy interrupt target.
Definition: intelxl.h:912
uint32_t vector
MSI-X vector.
Definition: ena.h:20
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:60
void dma_unmap(struct dma_mapping *map)
Unmap buffer.
struct intelxl_msix msix
MSI-X interrupt.
Definition: intelxl.h:948

References intelxl_msix::cap, dma_unmap(), intelxl_msix::map, intelxl_nic::msix, pci_msix_disable(), pci_msix_mask(), and vector.

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_admin()

static int intelxl_alloc_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Allocate admin queue.

Parameters
intelxlIntel device
adminAdmin queue
Return values
rcReturn status code

Definition at line 141 of file intelxl.c.

142  {
143  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
144  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
145 
146  /* Allocate admin queue */
147  admin->buf = dma_alloc ( intelxl->dma, &admin->map, ( buf_len + len ),
148  INTELXL_ALIGN );
149  if ( ! admin->buf )
150  return -ENOMEM;
151  admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
152 
153  DBGC ( intelxl, "INTELXL %p A%cQ is at [%08lx,%08lx) buf "
154  "[%08lx,%08lx)\n", intelxl,
155  ( ( admin == &intelxl->command ) ? 'T' : 'R' ),
156  virt_to_phys ( admin->desc ),
157  ( virt_to_phys ( admin->desc ) + len ),
158  virt_to_phys ( admin->buf ),
159  ( virt_to_phys ( admin->buf ) + buf_len ) );
160  return 0;
161 }
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define ENOMEM
Not enough space.
Definition: errno.h:534
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
uint32_t len
Length.
Definition: ena.h:14

References intelxl_admin::buf, intelxl_nic::command, DBGC, intelxl_admin::desc, intelxl_nic::dma, dma_alloc(), ENOMEM, INTELXL_ADMIN_NUM_DESC, INTELXL_ALIGN, len, intelxl_admin::map, and virt_to_phys().

Referenced by intelxl_open_admin().

◆ intelxl_enable_admin()

static void intelxl_enable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Enable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 169 of file intelxl.c.

170  {
171  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
172  const struct intelxl_admin_offsets *regs = admin->regs;
173  void *admin_regs = ( intelxl->regs + admin->base );
175 
176  /* Initialise admin queue */
177  memset ( admin->desc, 0, len );
178 
179  /* Reset head and tail registers */
180  writel ( 0, admin_regs + regs->head );
181  writel ( 0, admin_regs + regs->tail );
182 
183  /* Reset queue index */
184  admin->index = 0;
185 
186  /* Program queue address */
187  address = dma ( &admin->map, admin->desc );
188  writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
189  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
190  writel ( ( ( ( uint64_t ) address ) >> 32 ),
191  admin_regs + regs->bah );
192  } else {
193  writel ( 0, admin_regs + regs->bah );
194  }
195 
196  /* Program queue length and enable queue */
199  admin_regs + regs->len );
200 }
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_ADMIN_LEN_ENABLE
Queue enable.
Definition: intelxl.h:50
Admin queue register offsets.
Definition: intelxl.h:63
uint64_t address
Base address.
Definition: ena.h:24
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:462
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_ADMIN_LEN_LEN(x)
Queue length.
Definition: intelxl.h:49
struct i386_regs regs
Definition: registers.h:15
unsigned long physaddr_t
Definition: stdint.h:20
uint32_t len
Length.
Definition: ena.h:14
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
void * memset(void *dest, int character, size_t len) __nonnull

References address, intelxl_admin::base, intelxl_admin::desc, dma(), intelxl_admin::index, INTELXL_ADMIN_LEN_ENABLE, INTELXL_ADMIN_LEN_LEN, INTELXL_ADMIN_NUM_DESC, len, intelxl_admin::map, memset(), regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_reopen_admin().

◆ intelxl_disable_admin()

static void intelxl_disable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Disable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 208 of file intelxl.c.

209  {
210  const struct intelxl_admin_offsets *regs = admin->regs;
211  void *admin_regs = ( intelxl->regs + admin->base );
212 
213  /* Disable queue */
214  writel ( 0, admin_regs + regs->len );
215 }
void * regs
Registers.
Definition: intelxl.h:921
Admin queue register offsets.
Definition: intelxl.h:63
unsigned int base
Register block base.
Definition: intelxl.h:462
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464

References intelxl_admin::base, regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_free_admin()

static void intelxl_free_admin ( struct intelxl_nic *intelxl  __unused,
struct intelxl_admin admin 
)
static

Free admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 223 of file intelxl.c.

224  {
225  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
226  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
227 
228  /* Free queue */
229  dma_free ( &admin->map, admin->buf, ( buf_len + len ) );
230 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
uint32_t len
Length.
Definition: ena.h:14

References intelxl_admin::buf, intelxl_admin::desc, dma_free(), INTELXL_ADMIN_NUM_DESC, len, and intelxl_admin::map.

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic intelxl)

Get next admin command queue descriptor.

Parameters
intelxlIntel device
Return values
cmdCommand descriptor

Definition at line 239 of file intelxl.c.

239  {
240  struct intelxl_admin *admin = &intelxl->command;
242 
243  /* Get and initialise next descriptor */
244  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
245  memset ( cmd, 0, sizeof ( *cmd ) );
246  return cmd;
247 }
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
Admin queue descriptor.
Definition: intelxl.h:415
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
void * memset(void *dest, int character, size_t len) __nonnull

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_descriptor(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), and intelxlvf_admin_command_descriptor().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl)

Get next admin command queue data buffer.

Parameters
intelxlIntel device
Return values
bufData buffer

Definition at line 256 of file intelxl.c.

256  {
257  struct intelxl_admin *admin = &intelxl->command;
258  union intelxl_admin_buffer *buf;
259 
260  /* Get next data buffer */
261  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
262  memset ( buf, 0, sizeof ( *buf ) );
263  return buf;
264 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
Admin queue data buffer.
Definition: intelxl.h:401
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_buffer(), intelxl_admin_driver(), intelxl_admin_mac_read(), intelxl_admin_switch(), intelxl_admin_vsi(), and intelxlvf_admin_command_buffer().

◆ intelxl_admin_event_init()

static void intelxl_admin_event_init ( struct intelxl_nic intelxl,
unsigned int  index 
)
static

Initialise admin event queue descriptor.

Parameters
intelxlIntel device
indexEvent queue index

Definition at line 272 of file intelxl.c.

273  {
274  struct intelxl_admin *admin = &intelxl->event;
275  struct intelxl_admin_descriptor *evt;
276  union intelxl_admin_buffer *buf;
278 
279  /* Initialise descriptor */
280  evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
281  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
282  address = dma ( &admin->map, buf );
284  evt->len = cpu_to_le16 ( sizeof ( *buf ) );
285  evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
286  evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
287 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:451
uint16_t flags
Flags.
Definition: intelxl.h:417
unsigned long long uint64_t
Definition: stdint.h:13
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
uint16_t len
Data length.
Definition: intelxl.h:421
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define cpu_to_le32(value)
Definition: byteswap.h:107
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:429
uint32_t high
Buffer address high.
Definition: intelxl.h:81
Admin queue descriptor.
Definition: intelxl.h:415
uint32_t low
Buffer address low.
Definition: intelxl.h:83
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:370
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
Admin queue data buffer.
Definition: intelxl.h:401

References address, intelxl_admin::buf, intelxl_admin_params::buffer, cpu_to_le16, cpu_to_le32, intelxl_admin::desc, dma(), intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_admin_buffer_params::high, index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_NUM_DESC, intelxl_admin_descriptor::len, intelxl_admin_buffer_params::low, intelxl_admin::map, and intelxl_admin_descriptor::params.

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 295 of file intelxl.c.

295  {
296  struct intelxl_admin *admin = &intelxl->command;
297  const struct intelxl_admin_offsets *regs = admin->regs;
298  void *admin_regs = ( intelxl->regs + admin->base );
300  union intelxl_admin_buffer *buf;
302  uint32_t cookie;
303  uint16_t silence;
304  unsigned int index;
305  unsigned int tail;
306  unsigned int i;
307  int rc;
308 
309  /* Get next queue entry */
310  index = admin->index++;
311  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
312  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
313  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
314  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
315  intelxl, index, le16_to_cpu ( cmd->opcode ) );
316  if ( cmd->cookie )
317  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
318  DBGC2 ( intelxl, ":\n" );
319 
320  /* Allow expected errors to be silenced */
321  silence = cmd->ret;
322  cmd->ret = 0;
323 
324  /* Sanity checks */
325  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
326  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
327  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
328 
329  /* Populate data buffer address if applicable */
330  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
331  address = dma ( &admin->map, buf );
332  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
333  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
334  }
335 
336  /* Populate cookie, if not being (ab)used for VF opcode */
337  if ( ! cmd->cookie )
338  cmd->cookie = cpu_to_le32 ( index );
339 
340  /* Record cookie */
341  cookie = cmd->cookie;
342 
343  /* Post command descriptor */
344  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
345  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
346  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
347  le16_to_cpu ( cmd->len ) );
348  }
349  wmb();
350  writel ( tail, admin_regs + regs->tail );
351 
352  /* Wait for completion */
353  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
354 
355  /* If response is not complete, delay 1ms and retry */
356  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
357  mdelay ( 1 );
358  continue;
359  }
360  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
361  intelxl, index );
362  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
363  sizeof ( *cmd ) );
364  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
365  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
366  le16_to_cpu ( cmd->len ) );
367  }
368 
369  /* Check for cookie mismatch */
370  if ( cmd->cookie != cookie ) {
371  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
372  "cookie %#x\n", intelxl, index,
373  le32_to_cpu ( cmd->cookie ) );
374  rc = -EPROTO;
375  goto err;
376  }
377 
378  /* Check for unexpected errors */
379  if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
380  DBGC ( intelxl, "INTELXL %p admin command %#x error "
381  "%d\n", intelxl, index,
382  le16_to_cpu ( cmd->ret ) );
383  rc = -EIO;
384  goto err;
385  }
386 
387  /* Success */
388  return 0;
389  }
390 
391  rc = -ETIMEDOUT;
392  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
393  intelxl, index );
394  err:
395  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
396  return rc;
397 }
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:439
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define le32_to_cpu(value)
Definition: byteswap.h:113
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue register offsets.
Definition: intelxl.h:63
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:451
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:462
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:436
unsigned int index
Queue index.
Definition: intelxl.h:459
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define DBGC_HDA(...)
Definition: compiler.h:506
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define EPROTO
Protocol error.
Definition: errno.h:624
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
struct i386_regs regs
Definition: registers.h:15
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
#define cpu_to_le16(value)
Definition: byteswap.h:106
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:486
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
Admin queue data buffer.
Definition: intelxl.h:401

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, dma(), EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_FL_RD, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin::map, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, virt_to_phys(), wmb(), and writel().

Referenced by ice_admin_add_txq(), ice_admin_autoneg(), ice_admin_disable_txq(), ice_admin_link(), ice_admin_mac_read(), ice_admin_mac_write(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ice_admin_version(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), intelxlvf_admin_request_qps(), and intelxlvf_reset_admin().

◆ intelxl_admin_version()

static int intelxl_admin_version ( struct intelxl_nic intelxl)
static

Get firmware version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 405 of file intelxl.c.

405  {
408  unsigned int api;
409  int rc;
410 
411  /* Populate descriptor */
413  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
414  version = &cmd->params.version;
415 
416  /* Issue command */
417  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
418  return rc;
419  api = le16_to_cpu ( version->api.major );
420  DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
421  intelxl, le16_to_cpu ( version->firmware.major ),
422  le16_to_cpu ( version->firmware.minor ),
423  api, le16_to_cpu ( version->api.minor ) );
424 
425  /* Check for API compatibility */
426  if ( api > INTELXL_ADMIN_API_MAJOR ) {
427  DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
428  intelxl, api );
429  return -ENOTSUP;
430  }
431 
432  return 0;
433 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin_version api
API version.
Definition: intelxl.h:106
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:87
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:489
Admin queue Get Version command parameters.
Definition: intelxl.h:98
#define le16_to_cpu(value)
Definition: byteswap.h:112
u32 version
Driver version.
Definition: ath9k_hw.c:1983
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References intelxl_admin_version_params::api, cmd, cpu_to_le16, DBGC, ENOTSUP, INTELXL_ADMIN_API_MAJOR, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_VERSION, le16_to_cpu, rc, and version.

◆ intelxl_admin_driver()

static int intelxl_admin_driver ( struct intelxl_nic intelxl)
static

Report driver version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 441 of file intelxl.c.

441  {
443  struct intelxl_admin_driver_params *driver;
444  union intelxl_admin_buffer *buf;
445  int rc;
446 
447  /* Populate descriptor */
449  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
451  cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
452  driver = &cmd->params.driver;
453  driver->major = product_major_version;
454  driver->minor = product_minor_version;
455  buf = intelxl_admin_command_buffer ( intelxl );
456  snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
458 
459  /* Issue command */
460  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
461  return rc;
462 
463  return 0;
464 }
const char product_short_name[]
Product short name string.
Definition: version.c:76
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
char name[32]
Driver name.
Definition: intelxl.h:131
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:256
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:403
Admin queue Driver Version command parameters.
Definition: intelxl.h:113
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
const int product_major_version
Product major version.
Definition: version.c:64
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
const char product_name[]
Product name string.
Definition: version.c:73
#define INTELXL_ADMIN_DRIVER
Admin queue Driver Version command.
Definition: intelxl.h:110
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
const int product_minor_version
Product minor version.
Definition: version.c:67
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, intelxl_admin_buffer::driver, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_DRIVER, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, intelxl_admin_driver_buffer::name, product_major_version, product_minor_version, product_name, product_short_name, rc, and snprintf().

Referenced by intelxl_probe().

◆ intelxl_admin_shutdown()

static int intelxl_admin_shutdown ( struct intelxl_nic intelxl)
static

Shutdown admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 472 of file intelxl.c.

472  {
475  int rc;
476 
477  /* Populate descriptor */
479  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
480  shutdown = &cmd->params.shutdown;
482 
483  /* Issue command */
484  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
485  return rc;
486 
487  return 0;
488 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
#define INTELXL_ADMIN_SHUTDOWN
Admin queue Shutdown command.
Definition: intelxl.h:135
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Admin queue Shutdown command parameters.
Definition: intelxl.h:138
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING
Driver is unloading.
Definition: intelxl.h:146
void shutdown(int flags)
Shut down iPXE.
Definition: init.c:98
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_SHUTDOWN, INTELXL_ADMIN_SHUTDOWN_UNLOADING, rc, and shutdown().

Referenced by intelxl_close_admin().

◆ intelxl_admin_mac_read()

static int intelxl_admin_mac_read ( struct net_device netdev)
static

Get MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 496 of file intelxl.c.

496  {
497  struct intelxl_nic *intelxl = netdev->priv;
500  union intelxl_admin_buffer *buf;
501  uint8_t *mac;
502  int rc;
503 
504  /* Populate descriptor */
506  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
507  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
508  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
509  read = &cmd->params.mac_read;
510  buf = intelxl_admin_command_buffer ( intelxl );
511  mac = buf->mac_read.pf;
512 
513  /* Issue command */
514  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
515  return rc;
516 
517  /* Check that MAC address is present in response */
518  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
519  DBGC ( intelxl, "INTELXL %p has no MAC address\n", intelxl );
520  return -ENOENT;
521  }
522 
523  /* Check that address is valid */
524  if ( ! is_valid_ether_addr ( mac ) ) {
525  DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
526  intelxl, eth_ntoa ( mac ) );
527  return -ENOENT;
528  }
529 
530  /* Copy MAC address */
531  DBGC ( intelxl, "INTELXL %p has MAC address %s\n",
532  intelxl, eth_ntoa ( mac ) );
534 
535  return 0;
536 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct option_descriptor read[1]
Definition: nvo_cmd.c:115
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:514
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:256
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:160
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint8_t pf[ETH_ALEN]
Physical function MAC address.
Definition: intelxl.h:165
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
struct intelxl_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: intelxl.h:405
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:149
Admin queue Manage MAC Address Read command parameters.
Definition: intelxl.h:152
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
unsigned char uint8_t
Definition: stdint.h:10
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define ETH_ALEN
Definition: if_ether.h:8
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:381
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, DBGC, ENOENT, ETH_ALEN, eth_ntoa(), net_device::hw_addr, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_MAC_READ, INTELXL_ADMIN_MAC_READ_VALID_LAN, is_valid_ether_addr(), mac, intelxl_admin_buffer::mac_read, memcpy(), netdev, intelxl_admin_mac_read_buffer::pf, net_device::priv, rc, and read.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_write()

static int intelxl_admin_mac_write ( struct net_device netdev)
static

Set MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 544 of file intelxl.c.

544  {
545  struct intelxl_nic *intelxl = netdev->priv;
548  union {
550  struct {
551  uint16_t high;
552  uint32_t low;
553  } __attribute__ (( packed ));
554  } mac;
555  int rc;
556 
557  /* Populate descriptor */
560  write = &cmd->params.mac_write;
561  memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
562  write->high = bswap_16 ( mac.high );
563  write->low = bswap_32 ( mac.low );
564 
565  /* Issue command */
566  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
567  return rc;
568 
569  return 0;
570 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
#define __attribute__(x)
Definition: compiler.h:10
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
void * memcpy(void *dest, const void *src, size_t len) __nonnull
void * priv
Driver private data.
Definition: netdevice.h:431
#define bswap_16(value)
Definition: byteswap.h:58
uint16_t high
MAC address first 16 bits, byte-swapped.
Definition: intelxl.h:184
static struct net_device * netdev
Definition: gdbudp.c:52
uint32_t low
MAC address last 32 bits, byte-swapped.
Definition: intelxl.h:186
#define bswap_32(value)
Definition: byteswap.h:70
device nvs write
Definition: threewire.h:61
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:175
unsigned char uint8_t
Definition: stdint.h:10
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define ETH_ALEN
Definition: if_ether.h:8
unsigned int uint32_t
Definition: stdint.h:12
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
Admin queue Manage MAC Address Write command parameters.
Definition: intelxl.h:178
#define cpu_to_le16(value)
Definition: byteswap.h:106
__be32 raw[7]
Definition: CIB_PRM.h:28
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:387
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References __attribute__, bswap_16, bswap_32, cmd, cpu_to_le16, ETH_ALEN, intelxl_admin_mac_write_params::high, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_WRITE, net_device::ll_addr, intelxl_admin_mac_write_params::low, mac, memcpy(), netdev, net_device::priv, raw, rc, and write.

Referenced by intelxl_open().

◆ intelxl_admin_clear_pxe()

int intelxl_admin_clear_pxe ( struct intelxl_nic intelxl)

Clear PXE mode.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 578 of file intelxl.c.

578  {
580  struct intelxl_admin_clear_pxe_params *pxe;
581  int rc;
582 
583  /* Populate descriptor */
587  pxe = &cmd->params.pxe;
589 
590  /* Issue command */
591  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
592  return rc;
593 
594  /* Check for expected errors */
595  if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
596  DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
597  intelxl );
598  return 0;
599  }
600 
601  return 0;
602 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:195
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:203
uint8_t magic
Magic value.
Definition: intelxl.h:197
#define INTELXL_ADMIN_EEXIST
Error: attempt to create something that already exists.
Definition: intelxl.h:448
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:192
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, INTELXL_ADMIN_CLEAR_PXE, INTELXL_ADMIN_CLEAR_PXE_MAGIC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_EEXIST, intelxl_admin_clear_pxe_params::magic, and rc.

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_admin_switch()

static int intelxl_admin_switch ( struct intelxl_nic intelxl)
static

Get switch configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 610 of file intelxl.c.

610  {
612  struct intelxl_admin_switch_params *sw;
613  union intelxl_admin_buffer *buf;
614  uint16_t next = 0;
615  int rc;
616 
617  /* Get each configuration in turn */
618  do {
619  /* Populate descriptor */
621  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
622  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
623  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
624  sw = &cmd->params.sw;
625  sw->next = next;
626  buf = intelxl_admin_command_buffer ( intelxl );
627 
628  /* Issue command */
629  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
630  return rc;
631 
632  /* Dump raw configuration */
633  DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
634  intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
635  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
636 
637  /* Parse response */
638  if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
639  intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
640  DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
641  "downlink %#04x conn %#02x\n", intelxl,
642  intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
643  le16_to_cpu ( buf->sw.cfg.downlink ),
644  buf->sw.cfg.connection );
645  }
646 
647  } while ( ( next = sw->next ) );
648 
649  /* Check that we found a VSI */
650  if ( ! intelxl->vsi ) {
651  DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
652  return -ENOENT;
653  }
654 
655  return 0;
656 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
uint32_t next
Next descriptor address.
Definition: myson.h:18
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:206
uint8_t type
Switching element type.
Definition: intelxl.h:211
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:514
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:256
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:407
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:936
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:219
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
uint8_t connection
Connection type.
Definition: intelxl.h:223
#define le16_to_cpu(value)
Definition: byteswap.h:112
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:217
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:252
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:234
#define INTELXL_ADMIN_SWITCH_TYPE_VSI
Virtual Station Inferface element type.
Definition: intelxl.h:231
uint16_t seid
Switching element ID.
Definition: intelxl.h:215
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References intelxl_admin_switch_buffer::cfg, cmd, intelxl_admin_switch_config::connection, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, intelxl_admin_switch_config::downlink, ENOENT, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_SWITCH, INTELXL_ADMIN_SWITCH_TYPE_VSI, le16_to_cpu, next, rc, intelxl_admin_switch_config::seid, intelxl_admin_buffer::sw, intelxl_admin_switch_config::type, intelxl_admin_switch_config::uplink, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_vsi()

static int intelxl_admin_vsi ( struct intelxl_nic intelxl)
static

Get VSI parameters.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 664 of file intelxl.c.

664  {
667  union intelxl_admin_buffer *buf;
668  int rc;
669 
670  /* Populate descriptor */
672  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
673  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
674  cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
675  vsi = &cmd->params.vsi;
676  vsi->vsi = cpu_to_le16 ( intelxl->vsi );
677  buf = intelxl_admin_command_buffer ( intelxl );
678 
679  /* Issue command */
680  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
681  return rc;
682 
683  /* Parse response */
684  intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
685  intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
686  DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
687  intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
688 
689  return 0;
690 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:273
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:277
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:409
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:259
unsigned int qset
Queue set handle.
Definition: intelxl.h:938
#define DBGC(...)
Definition: compiler.h:505
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:256
#define INTELXL_ADMIN_VSI
Admin queue Get VSI Parameters command.
Definition: intelxl.h:256
unsigned int queue
Queue number.
Definition: intelxl.h:934
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:936
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:261
#define le16_to_cpu(value)
Definition: byteswap.h:112
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_VSI, le16_to_cpu, intelxl_admin_vsi_buffer::qset, intelxl_nic::qset, intelxl_admin_vsi_buffer::queue, intelxl_nic::queue, rc, intelxl_admin_vsi_params::vsi, intelxl_admin_buffer::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_promisc()

static int intelxl_admin_promisc ( struct intelxl_nic intelxl)
static

Set VSI promiscuous modes.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 698 of file intelxl.c.

698  {
700  struct intelxl_admin_promisc_params *promisc;
701  uint16_t flags;
702  int rc;
703 
704  /* Populate descriptor */
706  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
711  promisc = &cmd->params.promisc;
712  promisc->flags = cpu_to_le16 ( flags );
713  promisc->valid = cpu_to_le16 ( flags );
714  promisc->vsi = cpu_to_le16 ( intelxl->vsi );
715 
716  /* Issue command */
717  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
718  return rc;
719 
720  return 0;
721 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
#define INTELXL_ADMIN_PROMISC_FL_VLAN
Promiscuous VLAN mode.
Definition: intelxl.h:307
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_PROMISC
Admin queue Set VSI Promiscuous Modes command.
Definition: intelxl.h:283
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:936
uint16_t flags
Flags.
Definition: intelxl.h:288
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:292
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:286
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST
Promiscuous broadcast mode.
Definition: intelxl.h:304
uint16_t valid
Valid flags.
Definition: intelxl.h:290
#define INTELXL_ADMIN_PROMISC_FL_UNICAST
Promiscuous unicast mode.
Definition: intelxl.h:298
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST
Promiscuous multicast mode.
Definition: intelxl.h:301
uint8_t flags
Flags.
Definition: ena.h:18

References cmd, cpu_to_le16, flags, intelxl_admin_promisc_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_PROMISC, INTELXL_ADMIN_PROMISC_FL_BROADCAST, INTELXL_ADMIN_PROMISC_FL_MULTICAST, INTELXL_ADMIN_PROMISC_FL_UNICAST, INTELXL_ADMIN_PROMISC_FL_VLAN, rc, intelxl_admin_promisc_params::valid, intelxl_admin_promisc_params::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_config()

int intelxl_admin_mac_config ( struct intelxl_nic intelxl)

Set MAC configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 729 of file intelxl.c.

729  {
731  struct intelxl_admin_mac_config_params *config;
732  int rc;
733 
734  /* Populate descriptor */
737  config = &cmd->params.mac_config;
738  config->mfs = cpu_to_le16 ( intelxl->mfs );
740 
741  /* Issue command */
742  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
743  return rc;
744 
745  return 0;
746 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
Admin queue Set MAC Configuration command parameters.
Definition: intelxl.h:313
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
#define INTELXL_ADMIN_MAC_CONFIG
Admin queue Set MAC Configuration command.
Definition: intelxl.h:310
Admin queue descriptor.
Definition: intelxl.h:415
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:315
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC
Append CRC on transmit.
Definition: intelxl.h:323
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_mac_config_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_CONFIG, INTELXL_ADMIN_MAC_CONFIG_FL_CRC, intelxl_admin_mac_config_params::mfs, intelxl_nic::mfs, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_admin_autoneg()

static int intelxl_admin_autoneg ( struct intelxl_nic intelxl)
static

Restart autonegotiation.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 754 of file intelxl.c.

754  {
756  struct intelxl_admin_autoneg_params *autoneg;
757  int rc;
758 
759  /* Populate descriptor */
761  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
762  autoneg = &cmd->params.autoneg;
765 
766  /* Issue command */
767  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
768  return rc;
769 
770  return 0;
771 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:337
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:326
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:329
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:340
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_autoneg_params::flags, INTELXL_ADMIN_AUTONEG, INTELXL_ADMIN_AUTONEG_FL_ENABLE, INTELXL_ADMIN_AUTONEG_FL_RESTART, intelxl_admin_command(), intelxl_admin_command_descriptor(), and rc.

Referenced by intelxl_open().

◆ intelxl_admin_link()

static int intelxl_admin_link ( struct net_device netdev)
static

Get link status.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 779 of file intelxl.c.

779  {
780  struct intelxl_nic *intelxl = netdev->priv;
783  int rc;
784 
785  /* Populate descriptor */
787  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
788  link = &cmd->params.link;
790 
791  /* Issue command */
792  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
793  return rc;
794  DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
795  intelxl, link->phy, link->speed, link->status );
796 
797  /* Update network device */
798  if ( link->status & INTELXL_ADMIN_LINK_UP ) {
800  } else {
802  }
803 
804  return 0;
805 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:239
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
#define DBGC(...)
Definition: compiler.h:505
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:230
void * priv
Driver private data.
Definition: netdevice.h:431
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:774
static struct net_device * netdev
Definition: gdbudp.c:52
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Admin queue descriptor.
Definition: intelxl.h:415
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:365
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:362
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_LINK, INTELXL_ADMIN_LINK_NOTIFY, INTELXL_ADMIN_LINK_UP, link, netdev, netdev_link_down(), netdev_link_up(), net_device::priv, and rc.

Referenced by intelxl_admin_event(), intelxl_open(), and intelxl_probe().

◆ intelxl_admin_event()

static void intelxl_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor evt,
union intelxl_admin_buffer *buf  __unused 
)
static

Handle admin event.

Parameters
netdevNetwork device
evtEvent descriptor
bufData buffer

Definition at line 814 of file intelxl.c.

816  {
817  struct intelxl_nic *intelxl = netdev->priv;
818 
819  /* Ignore unrecognised events */
820  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
821  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
822  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
823  return;
824  }
825 
826  /* Update link status */
828 }
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
uint16_t opcode
Opcode.
Definition: intelxl.h:419
#define DBGC(...)
Definition: compiler.h:505
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define cpu_to_le16(value)
Definition: byteswap.h:106
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:779

References cpu_to_le16, DBGC, INTELXL_ADMIN_LINK, intelxl_admin_link(), le16_to_cpu, netdev, intelxl_admin_descriptor::opcode, and net_device::priv.

Referenced by intelxl_probe().

◆ intelxl_refill_admin()

static void intelxl_refill_admin ( struct intelxl_nic intelxl)
static

Refill admin event queue.

Parameters
intelxlIntel device

Definition at line 835 of file intelxl.c.

835  {
836  struct intelxl_admin *admin = &intelxl->event;
837  const struct intelxl_admin_offsets *regs = admin->regs;
838  void *admin_regs = ( intelxl->regs + admin->base );
839  unsigned int tail;
840 
841  /* Update tail pointer */
842  tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
844  wmb();
845  writel ( tail, admin_regs + regs->tail );
846 }
void * regs
Registers.
Definition: intelxl.h:921
wmb()
Admin queue register offsets.
Definition: intelxl.h:63
Admin queue.
Definition: intelxl.h:451
unsigned int base
Register block base.
Definition: intelxl.h:462
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
unsigned int tail
Tail Register offset.
Definition: intelxl.h:73
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_admin::base, intelxl_nic::event, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, regs, intelxl_admin::regs, intelxl_nic::regs, intelxl_admin_offsets::tail, wmb(), and writel().

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters
netdevNetwork device

Definition at line 853 of file intelxl.c.

853  {
854  struct intelxl_nic *intelxl = netdev->priv;
855  struct intelxl_admin *admin = &intelxl->event;
856  struct intelxl_admin_descriptor *evt;
857  union intelxl_admin_buffer *buf;
858 
859  /* Check for events */
860  while ( 1 ) {
861 
862  /* Get next event descriptor and data buffer */
863  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
864  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
865 
866  /* Stop if descriptor is not yet completed */
867  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
868  return;
869  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
870  intelxl, admin->index );
871  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
872  sizeof ( *evt ) );
873  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
874  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
875  le16_to_cpu ( evt->len ) );
876  }
877 
878  /* Handle event */
879  intelxl->handle ( netdev, evt, buf );
880 
881  /* Reset descriptor and refill queue */
882  intelxl_admin_event_init ( intelxl, admin->index );
883  admin->index++;
884  intelxl_refill_admin ( intelxl );
885  }
886 }
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:972
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
uint16_t flags
Flags.
Definition: intelxl.h:417
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
uint16_t len
Data length.
Definition: intelxl.h:421
unsigned int index
Queue index.
Definition: intelxl.h:459
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:272
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:835
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define le16_to_cpu(value)
Definition: byteswap.h:112
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
Admin queue data buffer.
Definition: intelxl.h:401

References intelxl_admin::buf, cpu_to_le16, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_nic::handle, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_NUM_DESC, intelxl_refill_admin(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, net_device::priv, and virt_to_phys().

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 894 of file intelxl.c.

894  {
895  int rc;
896 
897  /* Allocate admin event queue */
898  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
899  goto err_alloc_event;
900 
901  /* Allocate admin command queue */
902  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
903  goto err_alloc_command;
904 
905  /* (Re)open admin queues */
906  intelxl_reopen_admin ( intelxl );
907 
908  return 0;
909 
910  intelxl_disable_admin ( intelxl, &intelxl->command );
911  intelxl_disable_admin ( intelxl, &intelxl->event );
912  intelxl_free_admin ( intelxl, &intelxl->command );
913  err_alloc_command:
914  intelxl_free_admin ( intelxl, &intelxl->event );
915  err_alloc_event:
916  return rc;
917 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:141
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:223
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:208
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:924
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters
intelxlIntel device

Definition at line 924 of file intelxl.c.

924  {
925  unsigned int i;
926 
927  /* Enable admin event queue */
928  intelxl_enable_admin ( intelxl, &intelxl->event );
929 
930  /* Enable admin command queue */
931  intelxl_enable_admin ( intelxl, &intelxl->command );
932 
933  /* Initialise all admin event queue descriptors */
934  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
935  intelxl_admin_event_init ( intelxl, i );
936 
937  /* Post all descriptors to event queue */
938  intelxl_refill_admin ( intelxl );
939 }
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:169
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:272
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:835
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_wait().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters
intelxlIntel device

Definition at line 946 of file intelxl.c.

946  {
947 
948  /* Shut down admin queues */
949  intelxl_admin_shutdown ( intelxl );
950 
951  /* Disable admin queues */
952  intelxl_disable_admin ( intelxl, &intelxl->command );
953  intelxl_disable_admin ( intelxl, &intelxl->event );
954 
955  /* Free admin queues */
956  intelxl_free_admin ( intelxl, &intelxl->command );
957  intelxl_free_admin ( intelxl, &intelxl->event );
958 }
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:472
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:223
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:208
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 974 of file intelxl.c.

975  {
976  int rc;
977 
978  /* Allocate descriptor ring */
979  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
980  INTELXL_ALIGN );
981  if ( ! ring->desc.raw ) {
982  rc = -ENOMEM;
983  goto err_alloc;
984  }
985 
986  /* Initialise descriptor ring */
987  memset ( ring->desc.raw, 0, ring->len );
988 
989  /* Reset tail pointer */
990  writel ( 0, ( intelxl->regs + ring->tail ) );
991 
992  /* Reset counters */
993  ring->prod = 0;
994  ring->cons = 0;
995 
996  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
997  intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
998  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
999 
1000  return 0;
1001 
1002  dma_free ( &ring->map, ring->desc.raw, ring->len );
1003  err_alloc:
1004  return rc;
1005 }
void * regs
Registers.
Definition: intelxl.h:921
size_t len
Length (in bytes)
Definition: intelxl.h:777
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:770
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@65 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
unsigned int tail
Tail register.
Definition: intelxl.h:775
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_ring::cons, DBGC, intelxl_ring::desc, intelxl_nic::dma, dma_alloc(), dma_free(), ENOMEM, INTELXL_ALIGN, intelxl_ring::len, intelxl_ring::map, memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_nic::regs, intelxl_ring::tail, virt_to_phys(), and writel().

Referenced by ice_create_tx(), intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring ( struct intelxl_nic *intelxl  __unused,
struct intelxl_ring ring 
)

Free descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 1013 of file intelxl.c.

1014  {
1015 
1016  /* Free descriptor ring */
1017  dma_free ( &ring->map, ring->desc.raw, ring->len );
1018  ring->desc.raw = NULL;
1019 }
size_t len
Length (in bytes)
Definition: intelxl.h:777
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@65 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321

References intelxl_ring::desc, dma_free(), intelxl_ring::len, intelxl_ring::map, NULL, and intelxl_ring::raw.

Referenced by ice_create_tx(), ice_destroy_tx(), intelxl_create_ring(), intelxl_destroy_ring(), intelxlvf_close(), and intelxlvf_open().

◆ intelxl_context_dump()

static void intelxl_context_dump ( struct intelxl_nic intelxl,
uint32_t  op,
size_t  len 
)
static

Dump queue context (for debugging)

Parameters
intelxlIntel device
opContext operation
lenSize of context

Definition at line 1029 of file intelxl.c.

1029  {
1030  struct intelxl_context_line line;
1031  uint32_t pfcm_lanctxctl;
1032  uint32_t pfcm_lanctxstat;
1033  unsigned int queue;
1034  unsigned int index;
1035  unsigned int i;
1036 
1037  /* Do nothing unless debug output is enabled */
1038  if ( ! DBG_EXTRA )
1039  return;
1040 
1041  /* Dump context */
1042  DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
1043  for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
1044 
1045  /* Start context operation */
1046  queue = ( intelxl->base + intelxl->queue );
1047  pfcm_lanctxctl =
1051  writel ( pfcm_lanctxctl,
1052  intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1053 
1054  /* Wait for operation to complete */
1055  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1056 
1057  /* Check if operation is complete */
1058  pfcm_lanctxstat = readl ( intelxl->regs +
1060  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1061  break;
1062 
1063  /* Delay */
1064  mdelay ( 1 );
1065  }
1066 
1067  /* Read context data */
1068  for ( i = 0 ; i < ( sizeof ( line ) /
1069  sizeof ( line.raw[0] ) ) ; i++ ) {
1070  line.raw[i] = readl ( intelxl->regs +
1071  INTELXL_PFCM_LANCTXDATA ( i ) );
1072  }
1073  DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
1074  &line, sizeof ( line ) );
1075  }
1076 }
void * regs
Registers.
Definition: intelxl.h:921
Queue context line.
Definition: intelxl.h:529
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
unsigned int queue
Queue number.
Definition: intelxl.h:934
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:503
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:525
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:506
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
uint32_t len
Length.
Definition: ena.h:14
#define DBGC2(...)
Definition: compiler.h:522
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:526
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
#define DBG_EXTRA
Definition: compiler.h:319
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:502
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:499
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ
Read context.
Definition: intelxl.h:519

References intelxl_nic::base, DBG_EXTRA, DBGC2, DBGC2_HDA, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_READ, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, len, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

Referenced by intelxl_close().

◆ intelxl_context_line()

static int intelxl_context_line ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
unsigned int  index,
uint32_t  op 
)
static

Program queue context line.

Parameters
intelxlIntel device
lineQueue context line
indexLine number
opContext operation
Return values
rcReturn status code

Definition at line 1087 of file intelxl.c.

1089  {
1090  uint32_t pfcm_lanctxctl;
1091  uint32_t pfcm_lanctxstat;
1092  unsigned int queue;
1093  unsigned int i;
1094 
1095  /* Write context data */
1096  for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
1097  writel ( le32_to_cpu ( line->raw[i] ),
1098  intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
1099  }
1100 
1101  /* Start context operation */
1102  queue = ( intelxl->base + intelxl->queue );
1103  pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
1106  writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1107 
1108  /* Wait for operation to complete */
1109  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1110 
1111  /* Check if operation is complete */
1112  pfcm_lanctxstat = readl ( intelxl->regs +
1114  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1115  return 0;
1116 
1117  /* Delay */
1118  mdelay ( 1 );
1119  }
1120 
1121  DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
1122  intelxl, pfcm_lanctxctl );
1123  return -ETIMEDOUT;
1124 }
void * regs
Registers.
Definition: intelxl.h:921
uint32_t raw[4]
Raw data.
Definition: intelxl.h:531
#define le32_to_cpu(value)
Definition: byteswap.h:113
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE
Write context.
Definition: intelxl.h:521
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
unsigned int queue
Queue number.
Definition: intelxl.h:934
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:503
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:525
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:506
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:526
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:502
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:499

References intelxl_nic::base, DBGC, ETIMEDOUT, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, le32_to_cpu, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

◆ intelxl_context()

static int intelxl_context ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
size_t  len,
uint32_t  op 
)
static

Program queue context.

Parameters
intelxlIntel device
lineQueue context lines
lenSize of context
opContext operation
Return values
rcReturn status code

Definition at line 1135 of file intelxl.c.

1137  {
1138  unsigned int index;
1139  int rc;
1140 
1141  DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
1142  intelxl, op, len );
1143  DBGC2_HDA ( intelxl, 0, line, len );
1144 
1145  /* Program one line at a time */
1146  for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
1147  if ( ( rc = intelxl_context_line ( intelxl, line++, index,
1148  op ) ) != 0 )
1149  return rc;
1150  }
1151 
1152  return 0;
1153 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Queue context line.
Definition: intelxl.h:529
#define DBGC2_HDA(...)
Definition: compiler.h:523
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
uint32_t len
Length.
Definition: ena.h:14
#define DBGC2(...)
Definition: compiler.h:522
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21

References DBGC2, DBGC2_HDA, index, len, op, and rc.

Referenced by intelxl_context_rx(), and intelxl_context_tx().

◆ intelxl_context_tx()

static int intelxl_context_tx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program transmit queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1162 of file intelxl.c.

1163  {
1164  union {
1165  struct intelxl_context_tx tx;
1166  struct intelxl_context_line line;
1167  } ctx;
1168  int rc;
1169 
1170  /* Initialise context */
1171  memset ( &ctx, 0, sizeof ( ctx ) );
1172  ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
1173  ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
1174  ctx.tx.count =
1176  ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
1177 
1178  /* Program context */
1179  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1181  return rc;
1182 
1183  return 0;
1184 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:529
unsigned int qset
Queue set handle.
Definition: intelxl.h:938
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:514
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1135
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
#define INTELXL_CTX_TX_FL_NEW
New transmit queue context.
Definition: intelxl.h:555
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_CTX_TX_QSET(qset)
Transmit queue set.
Definition: intelxl.h:564
#define INTELXL_CTX_TX_BASE(base)
Transmit queue base address.
Definition: intelxl.h:558
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_CTX_TX_COUNT(count)
Transmit queue count.
Definition: intelxl.h:561
Transmit queue context.
Definition: intelxl.h:535
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_TX_BASE, INTELXL_CTX_TX_COUNT, INTELXL_CTX_TX_FL_NEW, INTELXL_CTX_TX_QSET, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_TX_NUM_DESC, memset(), intelxl_nic::qset, rc, and tx.

◆ intelxl_context_rx()

static int intelxl_context_rx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program receive queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1193 of file intelxl.c.

1194  {
1195  union {
1196  struct intelxl_context_rx rx;
1197  struct intelxl_context_line line;
1198  } ctx;
1199  uint64_t base_count;
1200  int rc;
1201 
1202  /* Initialise context */
1203  memset ( &ctx, 0, sizeof ( ctx ) );
1205  ctx.rx.base_count = cpu_to_le64 ( base_count );
1206  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
1208  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
1209 
1210  /* Program context */
1211  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1213  return rc;
1214 
1215  return 0;
1216 }
Receive queue context.
Definition: intelxl.h:567
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:591
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:529
unsigned long long uint64_t
Definition: stdint.h:13
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:600
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:594
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:512
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1135
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:597
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:587
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_RX_BASE_COUNT, INTELXL_CTX_RX_FL_CRCSTRIP, INTELXL_CTX_RX_FL_DSIZE, INTELXL_CTX_RX_LEN, INTELXL_CTX_RX_MFS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_RX_NUM_DESC, memset(), intelxl_nic::mfs, rc, and rx.

◆ intelxl_enable_ring()

static int intelxl_enable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Enable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1225 of file intelxl.c.

1226  {
1227  void *ring_regs = ( intelxl->regs + ring->reg );
1228  uint32_t qxx_ena;
1229 
1230  /* Enable ring */
1231  writel ( INTELXL_QXX_ENA_REQ, ( ring_regs + INTELXL_QXX_ENA ) );
1233  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1234  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) ) {
1235  DBGC ( intelxl, "INTELXL %p ring %06x failed to enable: "
1236  "%#08x\n", intelxl, ring->tail, qxx_ena );
1237  return -EIO;
1238  }
1239 
1240  return 0;
1241 }
void * regs
Registers.
Definition: intelxl.h:921
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:643
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:641
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define INTELXL_QXX_ENA_REQ
Enable request.
Definition: intelxl.h:642
unsigned int reg
Register block.
Definition: intelxl.h:773
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_QUEUE_ENABLE_DELAY_US
Time to wait for a queue to become enabled.
Definition: intelxl.h:606
#define EIO
Input/output error.
Definition: errno.h:433
unsigned int tail
Tail register.
Definition: intelxl.h:775

References DBGC, EIO, INTELXL_QUEUE_ENABLE_DELAY_US, INTELXL_QXX_ENA, INTELXL_QXX_ENA_REQ, INTELXL_QXX_ENA_STAT, readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, udelay(), and writel().

Referenced by intelxl_create_ring().

◆ intelxl_disable_ring()

static int intelxl_disable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Disable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1250 of file intelxl.c.

1251  {
1252  void *ring_regs = ( intelxl->regs + ring->reg );
1253  uint32_t qxx_ena;
1254  unsigned int i;
1255 
1256  /* Disable ring */
1257  writel ( 0, ( ring_regs + INTELXL_QXX_ENA ) );
1258 
1259  /* Wait for ring to be disabled */
1260  for ( i = 0 ; i < INTELXL_QUEUE_DISABLE_MAX_WAIT_MS ; i++ ) {
1261 
1262  /* Check if ring is disabled */
1263  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1264  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) )
1265  return 0;
1266 
1267  /* Delay */
1268  mdelay ( 1 );
1269  }
1270 
1271  DBGC ( intelxl, "INTELXL %p ring %06x timed out waiting for disable: "
1272  "%#08x\n", intelxl, ring->tail, qxx_ena );
1273  return -ETIMEDOUT;
1274 }
void * regs
Registers.
Definition: intelxl.h:921
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:643
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:641
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
unsigned int reg
Register block.
Definition: intelxl.h:773
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS
Maximum time to wait for a queue to become disabled.
Definition: intelxl.h:612
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669

References DBGC, ETIMEDOUT, INTELXL_QUEUE_DISABLE_MAX_WAIT_MS, INTELXL_QXX_ENA, INTELXL_QXX_ENA_STAT, mdelay(), readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, and writel().

Referenced by intelxl_create_ring(), and intelxl_destroy_ring().

◆ intelxl_create_ring()

int intelxl_create_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Create descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1283 of file intelxl.c.

1284  {
1286  int rc;
1287 
1288  /* Allocate descriptor ring */
1289  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1290  goto err_alloc;
1291 
1292  /* Program queue context */
1293  address = dma ( &ring->map, ring->desc.raw );
1294  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1295  goto err_context;
1296 
1297  /* Enable ring */
1298  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1299  goto err_enable;
1300 
1301  return 0;
1302 
1303  intelxl_disable_ring ( intelxl, ring );
1304  err_enable:
1305  err_context:
1306  intelxl_free_ring ( intelxl, ring );
1307  err_alloc:
1308  return rc;
1309 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:783
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1225
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1250
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@65 desc
Descriptors.
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
unsigned long physaddr_t
Definition: stdint.h:20
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:974

References address, intelxl_ring::context, intelxl_ring::desc, dma(), intelxl_alloc_ring(), intelxl_disable_ring(), intelxl_enable_ring(), intelxl_free_ring(), intelxl_ring::map, intelxl_ring::raw, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_destroy_ring()

void intelxl_destroy_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Destroy descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 1317 of file intelxl.c.

1318  {
1319  int rc;
1320 
1321  /* Disable ring */
1322  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1323  /* Leak memory; there's nothing else we can do */
1324  return;
1325  }
1326 
1327  /* Free descriptor ring */
1328  intelxl_free_ring ( intelxl, ring );
1329 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1250
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013

References intelxl_disable_ring(), intelxl_free_ring(), and rc.

Referenced by ice_close(), ice_open(), intelxl_close(), and intelxl_open().

◆ intelxl_refill_rx()

static void intelxl_refill_rx ( struct intelxl_nic intelxl)
static

Refill receive descriptor ring.

Parameters
intelxlIntel device

Definition at line 1336 of file intelxl.c.

1336  {
1338  struct io_buffer *iobuf;
1339  unsigned int rx_idx;
1340  unsigned int rx_tail;
1341  unsigned int refilled = 0;
1342 
1343  /* Refill ring */
1344  while ( ( intelxl->rx.prod - intelxl->rx.cons ) < INTELXL_RX_FILL ) {
1345 
1346  /* Allocate I/O buffer */
1347  iobuf = alloc_rx_iob ( intelxl->mfs, intelxl->dma );
1348  if ( ! iobuf ) {
1349  /* Wait for next refill */
1350  break;
1351  }
1352 
1353  /* Get next receive descriptor */
1354  rx_idx = ( intelxl->rx.prod++ % INTELXL_RX_NUM_DESC );
1355  rx = &intelxl->rx.desc.rx[rx_idx].data;
1356 
1357  /* Populate receive descriptor */
1358  rx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1359  rx->flags = 0;
1360 
1361  /* Record I/O buffer */
1362  assert ( intelxl->rx_iobuf[rx_idx] == NULL );
1363  intelxl->rx_iobuf[rx_idx] = iobuf;
1364 
1365  DBGC2 ( intelxl, "INTELXL %p RX %d is [%08lx,%08lx)\n",
1366  intelxl, rx_idx, virt_to_phys ( iobuf->data ),
1367  ( virt_to_phys ( iobuf->data ) + intelxl->mfs ) );
1368  refilled++;
1369  }
1370 
1371  /* Push descriptors to card, if applicable */
1372  if ( refilled ) {
1373  wmb();
1374  rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1375  writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1376  }
1377 }
void * regs
Registers.
Definition: intelxl.h:921
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
wmb()
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define cpu_to_le64(value)
Definition: byteswap.h:108
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:963
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:264
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
union intelxl_ring::@65 desc
Descriptors.
Receive data descriptor.
Definition: intelxl.h:709
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:181
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:48
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_RX_FILL
Receive descriptor ring fill level.
Definition: intelxl.h:823
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:749
A persistent I/O buffer.
Definition: iobuf.h:33

References alloc_rx_iob(), assert(), intelxl_ring::cons, cpu_to_le64, io_buffer::data, intelxl_rx_descriptor::data, DBGC2, intelxl_ring::desc, intelxl_nic::dma, INTELXL_RX_FILL, INTELXL_RX_NUM_DESC, iob_dma(), intelxl_nic::mfs, NULL, intelxl_ring::prod, intelxl_nic::regs, rx, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, intelxl_ring::tail, virt_to_phys(), wmb(), and writel().

Referenced by intelxl_open(), and intelxl_poll().

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters
intelxlIntel device

Definition at line 1384 of file intelxl.c.

1384  {
1385  unsigned int i;
1386 
1387  /* Discard any unused receive buffers */
1388  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1389  if ( intelxl->rx_iobuf[i] )
1390  free_rx_iob ( intelxl->rx_iobuf[i] );
1391  intelxl->rx_iobuf[i] = NULL;
1392  }
1393 }
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:963
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:208
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321

References free_rx_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by ice_close(), intelxl_close(), and intelxlvf_close().

◆ intelxl_open()

static int intelxl_open ( struct net_device netdev)
static

Open network device.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 1408 of file intelxl.c.

1408  {
1409  struct intelxl_nic *intelxl = netdev->priv;
1410  unsigned int queue;
1411  int rc;
1412 
1413  /* Calculate maximum frame size */
1414  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
1415  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
1416 
1417  /* Set MAC address */
1418  if ( ( rc = intelxl_admin_mac_write ( netdev ) ) != 0 )
1419  goto err_mac_write;
1420 
1421  /* Set maximum frame size */
1422  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
1423  goto err_mac_config;
1424 
1425  /* Associate transmit queue to PF */
1427  INTELXL_QXX_CTL_PFVF_PF_INDX ( intelxl->pf ) ),
1428  ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_CTL ) );
1429 
1430  /* Clear transmit pre queue disable */
1431  queue = ( intelxl->base + intelxl->queue );
1434  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1435 
1436  /* Reset transmit queue head */
1437  writel ( 0, ( intelxl->regs + INTELXL_QTX_HEAD ( intelxl->queue ) ) );
1438 
1439  /* Create receive descriptor ring */
1440  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
1441  goto err_create_rx;
1442 
1443  /* Create transmit descriptor ring */
1444  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->tx ) ) != 0 )
1445  goto err_create_tx;
1446 
1447  /* Fill receive ring */
1448  intelxl_refill_rx ( intelxl );
1449 
1450  /* Restart autonegotiation */
1451  intelxl_admin_autoneg ( intelxl );
1452 
1453  /* Update link state */
1455 
1456  return 0;
1457 
1460  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1462  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1463  err_create_tx:
1464  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1465  err_create_rx:
1466  err_mac_config:
1467  err_mac_write:
1468  return rc;
1469 }
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:625
void * regs
Registers.
Definition: intelxl.h:921
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1317
#define INTELXL_QXX_CTL_PFVF_Q_PF
PF queue.
Definition: intelxl.h:648
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:626
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:415
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
unsigned int queue
Queue number.
Definition: intelxl.h:934
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1336
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
#define ETH_HLEN
Definition: if_ether.h:9
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)
PF index.
Definition: intelxl.h:650
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static struct net_device * netdev
Definition: gdbudp.c:52
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1283
unsigned int reg
Register block.
Definition: intelxl.h:773
static int intelxl_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: intelxl.c:754
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:609
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
unsigned int pf
Physical function number.
Definition: intelxl.h:928
static int intelxl_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: intelxl.c:544
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:629
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS
Clear disable.
Definition: intelxl.h:631
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:779
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_QXX_CTL
Queue Control Register (offset)
Definition: intelxl.h:646
#define INTELXL_QTX_HEAD(x)
Global Transmit Queue Head register.
Definition: intelxl.h:622
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:729

References intelxl_nic::base, ETH_HLEN, intelxl_admin_autoneg(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_write(), INTELXL_ALIGN, intelxl_create_ring(), intelxl_destroy_ring(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_QTX_HEAD, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, INTELXL_QXX_CTL, INTELXL_QXX_CTL_PFVF_PF_INDX, INTELXL_QXX_CTL_PFVF_Q_PF, intelxl_refill_rx(), intelxl_nic::mfs, net_device::mtu, netdev, intelxl_nic::pf, net_device::priv, queue, intelxl_nic::queue, rc, intelxl_ring::reg, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_close()

static void intelxl_close ( struct net_device netdev)
static

Close network device.

Parameters
netdevNetwork device

Definition at line 1476 of file intelxl.c.

1476  {
1477  struct intelxl_nic *intelxl = netdev->priv;
1478  unsigned int queue;
1479 
1480  /* Dump contexts (for debugging) */
1482  sizeof ( struct intelxl_context_tx ) );
1484  sizeof ( struct intelxl_context_rx ) );
1485 
1486  /* Pre-disable transmit queue */
1487  queue = ( intelxl->base + intelxl->queue );
1490  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1492 
1493  /* Destroy transmit descriptor ring */
1494  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1495 
1496  /* Destroy receive descriptor ring */
1497  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1498 
1499  /* Discard any unused receive buffers */
1500  intelxl_empty_rx ( intelxl );
1501 }
Receive queue context.
Definition: intelxl.h:567
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:625
void * regs
Registers.
Definition: intelxl.h:921
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1317
static void intelxl_context_dump(struct intelxl_nic *intelxl, uint32_t op, size_t len)
Dump queue context (for debugging)
Definition: intelxl.c:1029
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:626
unsigned int queue
Queue number.
Definition: intelxl.h:934
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:512
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:514
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:609
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:629
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
uint16_t queue
Queue ID.
Definition: ena.h:22
Transmit queue context.
Definition: intelxl.h:535
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1384

References intelxl_nic::base, intelxl_context_dump(), intelxl_destroy_ring(), intelxl_empty_rx(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, netdev, net_device::priv, queue, intelxl_nic::queue, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_transmit()

int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 1510 of file intelxl.c.

1510  {
1511  struct intelxl_nic *intelxl = netdev->priv;
1513  unsigned int tx_idx;
1514  unsigned int tx_tail;
1515  size_t len;
1516 
1517  /* Get next transmit descriptor */
1518  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1519  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1520  intelxl );
1521  return -ENOBUFS;
1522  }
1523  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1524  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1525  tx = &intelxl->tx.desc.tx[tx_idx].data;
1526 
1527  /* Populate transmit descriptor */
1528  len = iob_len ( iobuf );
1529  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1530  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1533  wmb();
1534 
1535  /* Notify card that there are packets ready to transmit */
1536  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1537 
1538  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1539  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1540  ( virt_to_phys ( iobuf->data ) + len ) );
1541  return 0;
1542 }
void * regs
Registers.
Definition: intelxl.h:921
wmb()
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:669
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:666
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define cpu_to_le64(value)
Definition: byteswap.h:108
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:685
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:703
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:264
union intelxl_ring::@65 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:672
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
Transmit data descriptor.
Definition: intelxl.h:656
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:682
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
uint32_t len
Length.
Definition: ena.h:14
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:48
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:811
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_dma(), iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, virt_to_phys(), wmb(), and writel().

◆ intelxl_poll_tx()

static void intelxl_poll_tx ( struct net_device netdev)
static

Poll for completed packets.

Parameters
netdevNetwork device

Definition at line 1549 of file intelxl.c.

1549  {
1550  struct intelxl_nic *intelxl = netdev->priv;
1551  struct intelxl_tx_writeback_descriptor *tx_wb;
1552  unsigned int tx_idx;
1553 
1554  /* Check for completed packets */
1555  while ( intelxl->tx.cons != intelxl->tx.prod ) {
1556 
1557  /* Get next transmit descriptor */
1558  tx_idx = ( intelxl->tx.cons % INTELXL_TX_NUM_DESC );
1559  tx_wb = &intelxl->tx.desc.tx[tx_idx].wb;
1560 
1561  /* Stop if descriptor is still in use */
1562  if ( ! ( tx_wb->flags & INTELXL_TX_WB_FL_DD ) )
1563  return;
1564  DBGC2 ( intelxl, "INTELXL %p TX %d complete\n",
1565  intelxl, tx_idx );
1566 
1567  /* Complete TX descriptor */
1569  intelxl->tx.cons++;
1570  }
1571 }
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:764
unsigned int prod
Producer index.
Definition: intelxl.h:768
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
unsigned int cons
Consumer index.
Definition: intelxl.h:770
Transmit writeback descriptor.
Definition: intelxl.h:688
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
union intelxl_ring::@65 desc
Descriptors.
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
#define INTELXL_TX_WB_FL_DD
Transmit writeback descriptor complete.
Definition: intelxl.h:698
#define DBGC2(...)
Definition: compiler.h:522
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:705

References intelxl_ring::cons, DBGC2, intelxl_ring::desc, intelxl_tx_writeback_descriptor::flags, INTELXL_TX_NUM_DESC, INTELXL_TX_WB_FL_DD, netdev, netdev_tx_complete_next(), net_device::priv, intelxl_ring::prod, intelxl_ring::tx, intelxl_nic::tx, and intelxl_tx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll_rx()

static void intelxl_poll_rx ( struct net_device netdev)
static

Poll for received packets.

Parameters
netdevNetwork device

Definition at line 1578 of file intelxl.c.

1578  {
1579  struct intelxl_nic *intelxl = netdev->priv;
1580  struct intelxl_rx_writeback_descriptor *rx_wb;
1581  struct io_buffer *iobuf;
1582  unsigned int rx_idx;
1583  unsigned int tag;
1584  size_t len;
1585 
1586  /* Check for received packets */
1587  while ( intelxl->rx.cons != intelxl->rx.prod ) {
1588 
1589  /* Get next receive descriptor */
1590  rx_idx = ( intelxl->rx.cons % INTELXL_RX_NUM_DESC );
1591  rx_wb = &intelxl->rx.desc.rx[rx_idx].wb;
1592 
1593  /* Stop if descriptor is still in use */
1594  if ( ! ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_DD ) ) )
1595  return;
1596 
1597  /* Populate I/O buffer */
1598  iobuf = intelxl->rx_iobuf[rx_idx];
1599  intelxl->rx_iobuf[rx_idx] = NULL;
1600  len = INTELXL_RX_WB_LEN ( le32_to_cpu ( rx_wb->len ) );
1601  iob_put ( iobuf, len );
1602 
1603  /* Find VLAN device, if applicable */
1604  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_VLAN ) ) {
1605  tag = VLAN_TAG ( le16_to_cpu ( rx_wb->vlan ) );
1606  } else {
1607  tag = 0;
1608  }
1609 
1610  /* Hand off to network stack */
1611  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_RXE ) ) {
1612  DBGC ( intelxl, "INTELXL %p RX %d error (length %zd, "
1613  "flags %08x)\n", intelxl, rx_idx, len,
1614  le32_to_cpu ( rx_wb->flags ) );
1615  vlan_netdev_rx_err ( netdev, tag, iobuf, -EIO );
1616  } else {
1617  DBGC2 ( intelxl, "INTELXL %p RX %d complete (length "
1618  "%zd)\n", intelxl, rx_idx, len );
1619  vlan_netdev_rx ( netdev, tag, iobuf );
1620  }
1621  intelxl->rx.cons++;
1622  }
1623 }
#define VLAN_TAG(tci)
Extract VLAN tag from tag control information.
Definition: vlan.h:29
#define iob_put(iobuf, len)
Definition: iobuf.h:120
#define le32_to_cpu(value)
Definition: byteswap.h:113
uint16_t vlan
VLAN tag.
Definition: intelxl.h:723
#define INTELXL_RX_WB_FL_DD
Receive writeback descriptor complete.
Definition: intelxl.h:735
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:751
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:963
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
union intelxl_ring::@65 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:107
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define INTELXL_RX_WB_LEN(len)
Receive writeback descriptor length.
Definition: intelxl.h:744
__weak void vlan_netdev_rx(struct net_device *netdev, unsigned int tag, struct io_buffer *iobuf)
Add VLAN tag-stripped packet to queue (when VLAN support is not present)
Definition: netdevice.c:1209
uint32_t len
Length.
Definition: ena.h:14
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
__weak void vlan_netdev_rx_err(struct net_device *netdev, unsigned int tag __unused, struct io_buffer *iobuf, int rc)
Discard received VLAN tag-stripped packet (when VLAN support is not present)
Definition: netdevice.c:1227
Receive writeback descriptor.
Definition: intelxl.h:719
uint64_t tag
Identity tag.
Definition: edd.h:30
#define INTELXL_RX_WB_FL_RXE
Receive writeback descriptor error.
Definition: intelxl.h:741
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
#define INTELXL_RX_WB_FL_VLAN
Receive writeback descriptor VLAN tag present.
Definition: intelxl.h:738
A persistent I/O buffer.
Definition: iobuf.h:33

References intelxl_ring::cons, cpu_to_le32, DBGC, DBGC2, intelxl_ring::desc, EIO, intelxl_rx_writeback_descriptor::flags, INTELXL_RX_NUM_DESC, INTELXL_RX_WB_FL_DD, INTELXL_RX_WB_FL_RXE, INTELXL_RX_WB_FL_VLAN, INTELXL_RX_WB_LEN, iob_put, le16_to_cpu, le32_to_cpu, len, intelxl_rx_writeback_descriptor::len, netdev, NULL, net_device::priv, intelxl_ring::prod, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, tag, intelxl_rx_writeback_descriptor::vlan, vlan_netdev_rx(), vlan_netdev_rx_err(), VLAN_TAG, and intelxl_rx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll()

void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters
netdevNetwork device

Definition at line 1630 of file intelxl.c.

1630  {
1631  struct intelxl_nic *intelxl = netdev->priv;
1632 
1633  /* Poll for completed packets */
1634  intelxl_poll_tx ( netdev );
1635 
1636  /* Poll for received packets */
1637  intelxl_poll_rx ( netdev );
1638 
1639  /* Poll for admin events */
1641 
1642  /* Refill RX ring */
1643  intelxl_refill_rx ( intelxl );
1644 
1645  /* Rearm interrupt, since otherwise receive descriptors will
1646  * be written back only after a complete cacheline (four
1647  * packets) have been received.
1648  *
1649  * There is unfortunately no efficient way to determine
1650  * whether or not rearming the interrupt is necessary. If we
1651  * are running inside a hypervisor (e.g. using a VF or PF as a
1652  * passed-through PCI device), then the MSI-X write is
1653  * redirected by the hypervisor to the real host APIC and the
1654  * host ISR then raises an interrupt within the guest. We
1655  * therefore cannot poll the nominal MSI-X target location to
1656  * watch for the value being written. We could read from the
1657  * INT_DYN_CTL register, but this is even less efficient than
1658  * just unconditionally rearming the interrupt.
1659  */
1660  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1661 }
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:837
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1549
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1336
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:853
unsigned int intr
Interrupt control register.
Definition: intelxl.h:944
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1578

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

◆ intelxl_probe()

static int intelxl_probe ( struct pci_device pci)
static

Probe PCI device.

Parameters
pciPCI device
Return values
rcReturn status code

Definition at line 1684 of file intelxl.c.

1684  {
1685  struct net_device *netdev;
1686  struct intelxl_nic *intelxl;
1687  uint32_t pffunc_rid;
1688  uint32_t pfgen_portnum;
1689  uint32_t pflan_qalloc;
1690  int rc;
1691 
1692  /* Allocate and initialise net device */
1693  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
1694  if ( ! netdev ) {
1695  rc = -ENOMEM;
1696  goto err_alloc;
1697  }
1700  intelxl = netdev->priv;
1701  pci_set_drvdata ( pci, netdev );
1702  netdev->dev = &pci->dev;
1703  memset ( intelxl, 0, sizeof ( *intelxl ) );
1704  intelxl->intr = INTELXL_PFINT_DYN_CTL0;
1705  intelxl->handle = intelxl_admin_event;
1711  sizeof ( intelxl->tx.desc.tx[0] ),
1714  sizeof ( intelxl->rx.desc.rx[0] ),
1716 
1717  /* Fix up PCI device */
1718  adjust_pci_device ( pci );
1719 
1720  /* Map registers */
1721  intelxl->regs = pci_ioremap ( pci, pci->membase, INTELXL_BAR_SIZE );
1722  if ( ! intelxl->regs ) {
1723  rc = -ENODEV;
1724  goto err_ioremap;
1725  }
1726 
1727  /* Configure DMA */
1728  intelxl->dma = &pci->dma;
1729  dma_set_mask_64bit ( intelxl->dma );
1730  netdev->dma = intelxl->dma;
1731 
1732  /* Locate PCI Express capability */
1733  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
1734  if ( ! intelxl->exp ) {
1735  DBGC ( intelxl, "INTELXL %p missing PCIe capability\n",
1736  intelxl );
1737  rc = -ENXIO;
1738  goto err_exp;
1739  }
1740 
1741  /* Reset the function via PCIe FLR */
1742  pci_reset ( pci, intelxl->exp );
1743 
1744  /* Get function number, port number and base queue number */
1745  pffunc_rid = readl ( intelxl->regs + INTELXL_PFFUNC_RID );
1746  intelxl->pf = INTELXL_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
1747  pfgen_portnum = readl ( intelxl->regs + INTELXL_PFGEN_PORTNUM );
1748  intelxl->port = INTELXL_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
1749  pflan_qalloc = readl ( intelxl->regs + INTELXL_PFLAN_QALLOC );
1750  intelxl->base = INTELXL_PFLAN_QALLOC_FIRSTQ ( pflan_qalloc );
1751  DBGC ( intelxl, "INTELXL %p PF %d using port %d queues [%#04x-%#04x]\n",
1752  intelxl, intelxl->pf, intelxl->port, intelxl->base,
1753  INTELXL_PFLAN_QALLOC_LASTQ ( pflan_qalloc ) );
1754 
1755  /* Enable MSI-X dummy interrupt */
1756  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
1757  INTELXL_MSIX_VECTOR ) ) != 0 )
1758  goto err_msix;
1759 
1760  /* Open admin queues */
1761  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
1762  goto err_open_admin;
1763 
1764  /* Get firmware version */
1765  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
1766  goto err_admin_version;
1767 
1768  /* Report driver version */
1769  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
1770  goto err_admin_driver;
1771 
1772  /* Clear PXE mode */
1773  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
1774  goto err_admin_clear_pxe;
1775 
1776  /* Get switch configuration */
1777  if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
1778  goto err_admin_switch;
1779 
1780  /* Get VSI configuration */
1781  if ( ( rc = intelxl_admin_vsi ( intelxl ) ) != 0 )
1782  goto err_admin_vsi;
1783 
1784  /* Configure switch for promiscuous mode */
1785  if ( ( rc = intelxl_admin_promisc ( intelxl ) ) != 0 )
1786  goto err_admin_promisc;
1787 
1788  /* Get MAC address */
1789  if ( ( rc = intelxl_admin_mac_read ( netdev ) ) != 0 )
1790  goto err_admin_mac_read;
1791 
1792  /* Configure queue register addresses */
1793  intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1794  intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1795  intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1796  intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1797 
1798  /* Configure interrupt causes */
1801  intelxl->regs + INTELXL_QINT_TQCTL ( intelxl->queue ) );
1802  writel ( ( INTELXL_QINT_RQCTL_NEXTQ_INDX ( intelxl->queue ) |
1805  intelxl->regs + INTELXL_QINT_RQCTL ( intelxl->queue ) );
1808  intelxl->regs + INTELXL_PFINT_LNKLST0 );
1810  intelxl->regs + INTELXL_PFINT_ICR0_ENA );
1811 
1812  /* Register network device */
1813  if ( ( rc = register_netdev ( netdev ) ) != 0 )
1814  goto err_register_netdev;
1815 
1816  /* Set initial link state */
1818 
1819  return 0;
1820 
1822  err_register_netdev:
1823  err_admin_mac_read:
1824  err_admin_promisc:
1825  err_admin_vsi:
1826  err_admin_switch:
1827  err_admin_clear_pxe:
1828  err_admin_driver:
1829  err_admin_version:
1830  intelxl_close_admin ( intelxl );
1831  err_open_admin:
1832  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1833  err_msix:
1834  pci_reset ( pci, intelxl->exp );
1835  err_exp:
1836  iounmap ( intelxl->regs );
1837  err_ioremap:
1838  netdev_nullify ( netdev );
1839  netdev_put ( netdev );
1840  err_alloc:
1841  return rc;
1842 }
static int intelxl_admin_promisc(struct intelxl_nic *intelxl)
Set VSI promiscuous modes.
Definition: intelxl.c:698
Receive queue context.
Definition: intelxl.h:567
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)
First queue.
Definition: intelxl.h:892
void * regs
Registers.
Definition: intelxl.h:921
#define INTELXL_QRX(x)
Global Receive Queue register block.
Definition: intelxl.h:638
unsigned long membase
Memory base.
Definition: pci.h:215
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
#define INTELXL_PFLAN_QALLOC_LASTQ(x)
Last queue.
Definition: intelxl.h:895
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct dma_device dma
DMA device.
Definition: pci.h:210
#define INTELXL_PFFUNC_RID
Function Requester ID Information Register.
Definition: intelxl.h:885
static int intelxl_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: intelxl.c:610
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:39
#define INTELXL_PFLAN_QALLOC
PF Queue Allocation Register.
Definition: intelxl.h:891
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)
Queue index.
Definition: intelxl.h:862
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:972
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE
End of list.
Definition: intelxl.h:875
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:36
Admin queue register offsets.
Definition: intelxl.h:63
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:578
#define INTELXL_PFINT_ICR0_ENA
PF Interrupt Zero Cause Enablement Register.
Definition: intelxl.h:857
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:474
struct dma_device * dma
DMA device.
Definition: netdevice.h:366
static int intelxl_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: intelxl.c:496
#define INTELXL_PFINT_ICR0_ENA_ADMINQ
Admin event.
Definition: intelxl.h:858
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: intelxl.h:901
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:894
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:124
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
struct device dev
Generic device.
Definition: pci.h:208
unsigned int queue
Queue number.
Definition: intelxl.h:934
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:946
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:515
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:359
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define INTELXL_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: intelxl.h:900
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:475
#define INTELXL_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:882
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX
Receive queue.
Definition: intelxl.h:851
#define INTELXL_PFINT_DYN_CTL0
PF Interrupt Zero Dynamic Control Register.
Definition: intelxl.h:836
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:826
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:572
static void intelxl_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
Handle admin event.
Definition: intelxl.c:814
#define INTELXL_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:870
Admin queue version number.
Definition: intelxl.h:90
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX
Transmit queue.
Definition: intelxl.h:868
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:941
union intelxl_ring::@65 desc
Descriptors.
unsigned int reg
Register block.
Definition: intelxl.h:773
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:759
unsigned int intr
Interrupt control register.
Definition: intelxl.h:944
A network device.
Definition: netdevice.h:352
#define INTELXL_QTX(x)
Global Transmit Queue register block.
Definition: intelxl.h:635
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:528
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:105
unsigned int port
Port number.
Definition: intelxl.h:932
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define INTELXL_PFINT_LNKLST0
PF Interrupt Zero Linked List Register.
Definition: intelxl.h:842
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:795
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:97
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:916
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
#define INTELXL_QINT_TQCTL(x)
Transmit Queue Interrupt Cause Control Register.
Definition: intelxl.h:873
unsigned int pf
Physical function number.
Definition: intelxl.h:928
#define ENXIO
No such device or address.
Definition: errno.h:599
#define INTELXL_QXX_TAIL
Queue Tail Pointer Register (offset)
Definition: intelxl.h:653
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)
Queue index.
Definition: intelxl.h:843
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
unsigned int base
Absolute queue number base.
Definition: intelxl.h:930
void iounmap(volatile const void *io_addr)
Unmap I/O address.
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_QINT_RQCTL(x)
Receive Queue Interrupt Cause Control Register.
Definition: intelxl.h:861
#define INTELXL_BAR_SIZE
BAR size.
Definition: intelxl.h:20
static int intelxl_admin_vsi(struct intelxl_nic *intelxl)
Get VSI parameters.
Definition: intelxl.c:664
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:409
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:946
static struct net_device_operations intelxl_operations
Network device operations.
Definition: intelxl.c:1664
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: intelxl.h:886
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:779
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:441
Transmit queue context.
Definition: intelxl.h:535
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:62

References adjust_pci_device(), alloc_etherdev(), intelxl_nic::base, intelxl_nic::command, DBGC, intelxl_ring::desc, pci_device::dev, net_device::dev, pci_device::dma, net_device::dma, intelxl_nic::dma, dma_set_mask_64bit(), ENODEV, ENOMEM, ENXIO, intelxl_nic::event, intelxl_nic::exp, intelxl_nic::handle, intelxl_admin_clear_pxe(), INTELXL_ADMIN_CMD, intelxl_admin_driver(), intelxl_admin_event(), INTELXL_ADMIN_EVT, intelxl_admin_link(), intelxl_admin_mac_read(), intelxl_admin_promisc(), intelxl_admin_switch(), intelxl_admin_vsi(), INTELXL_BAR_SIZE, intelxl_close_admin(), intelxl_init_admin(), intelxl_init_ring(), INTELXL_MAX_PKT_LEN, intelxl_msix_disable(), intelxl_msix_enable(), INTELXL_MSIX_VECTOR, intelxl_open_admin(), intelxl_operations, INTELXL_PFFUNC_RID, INTELXL_PFFUNC_RID_FUNC_NUM, INTELXL_PFGEN_PORTNUM, INTELXL_PFGEN_PORTNUM_PORT_NUM, INTELXL_PFINT_DYN_CTL0, INTELXL_PFINT_ICR0_ENA, INTELXL_PFINT_ICR0_ENA_ADMINQ, INTELXL_PFINT_LNKLST0, INTELXL_PFINT_LNKLST0_FIRSTQ_INDX, INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX, INTELXL_PFLAN_QALLOC, INTELXL_PFLAN_QALLOC_FIRSTQ, INTELXL_PFLAN_QALLOC_LASTQ, INTELXL_QINT_RQCTL, INTELXL_QINT_RQCTL_CAUSE_ENA, INTELXL_QINT_RQCTL_NEXTQ_INDX, INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX, INTELXL_QINT_TQCTL, INTELXL_QINT_TQCTL_CAUSE_ENA, INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE, INTELXL_QRX, INTELXL_QTX, INTELXL_QXX_TAIL, INTELXL_RX_NUM_DESC, INTELXL_TX_NUM_DESC, intelxl_nic::intr, iounmap(), net_device::max_pkt_len, pci_device::membase, memset(), netdev, netdev_init(), netdev_nullify(), netdev_put(), PCI_CAP_ID_EXP, pci_find_capability(), pci_ioremap(), pci_reset(), pci_set_drvdata(), intelxl_nic::pf, intelxl_nic::port, net_device::priv, intelxl_nic::queue, rc, readl(), intelxl_ring::reg, register_netdev(), intelxl_nic::regs, intelxl_ring::rx, intelxl_nic::rx, intelxl_ring::tail, intelxl_ring::tx, intelxl_nic::tx, unregister_netdev(), and writel().

◆ intelxl_remove()

static void intelxl_remove ( struct pci_device pci)
static

Remove PCI device.

Parameters
pciPCI device

Definition at line 1849 of file intelxl.c.

1849  {
1850  struct net_device *netdev = pci_get_drvdata ( pci );
1851  struct intelxl_nic *intelxl = netdev->priv;
1852 
1853  /* Unregister network device */
1855 
1856  /* Close admin queues */
1857  intelxl_close_admin ( intelxl );
1858 
1859  /* Disable MSI-X dummy interrupt */
1860  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1861 
1862  /* Reset the NIC */
1863  pci_reset ( pci, intelxl->exp );
1864 
1865  /* Free network device */
1866  iounmap ( intelxl->regs );
1867  netdev_nullify ( netdev );
1868  netdev_put ( netdev );
1869 }
void * regs
Registers.
Definition: intelxl.h:921
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:124
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:946
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:572
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:941
A network device.
Definition: netdevice.h:352
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:528
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:105
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:916
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:369
void iounmap(volatile const void *io_addr)
Unmap I/O address.
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:946

References intelxl_nic::exp, intelxl_close_admin(), intelxl_msix_disable(), INTELXL_MSIX_VECTOR, iounmap(), netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), pci_reset(), net_device::priv, intelxl_nic::regs, and unregister_netdev().

Variable Documentation

◆ intelxl_admin_offsets

Initial value:
= {
}
#define INTELXL_ADMIN_BAH
Admin Queue Base Address High Register (offset)
Definition: intelxl.h:45
#define INTELXL_ADMIN_BAL
Admin Queue Base Address Low Register (offset)
Definition: intelxl.h:42
#define INTELXL_ADMIN_TAIL
Admin Queue Tail Register (offset)
Definition: intelxl.h:56
#define INTELXL_ADMIN_LEN
Admin Queue Length Register (offset)
Definition: intelxl.h:48
#define INTELXL_ADMIN_HEAD
Admin Queue Head Register (offset)
Definition: intelxl.h:53

Admin queue register offsets.

Definition at line 126 of file intelxl.c.

◆ intelxl_operations

struct net_device_operations intelxl_operations
static
Initial value:
= {
.open = intelxl_open,
.close = intelxl_close,
.transmit = intelxl_transmit,
.poll = intelxl_poll,
}
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1510
static int intelxl_open(struct net_device *netdev)
Open network device.
Definition: intelxl.c:1408
static void intelxl_close(struct net_device *netdev)
Close network device.
Definition: intelxl.c:1476
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1630

Network device operations.

Definition at line 1664 of file intelxl.c.

Referenced by intelxl_probe().

◆ intelxl_nics

struct pci_device_id intelxl_nics[]
static
Initial value:
= {
PCI_ROM ( 0x8086, 0x0cf8, "x710-n3000", "X710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x0d58, "xxv710-n3000", "XXV710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x104e, "x710-sfp-b", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x104f, "x710-kx-b", "X710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1572, "x710-sfp", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x1574, "xl710-qemu", "Virtual XL710", 0 ),
PCI_ROM ( 0x8086, 0x1580, "xl710-kx-b", "XL710 40GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1581, "xl710-kx-c", "XL710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1583, "xl710-qda2", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1584, "xl710-qda1", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1585, "x710-qsfp", "X710 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1586, "x710-10gt", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x1587, "x710-kr2", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1588, "x710-kr2-a", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1589, "x710-10gt4", "X710 10GBASE-T4", 0 ),
PCI_ROM ( 0x8086, 0x158a, "xxv710", "XXV710 25GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x158b, "xxv710-sfp28", "XXV710 25GbE SFP28", 0 ),
PCI_ROM ( 0x8086, 0x15ff, "x710-10gt-b", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37ce, "x722-kx", "X722 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x37cf, "x722-qsfp", "X722 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d0, "x722-sfp", "X722 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d1, "x722-1gt", "X722 1GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d2, "x722-10gt", "X722 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d3, "x722-sfp-i", "X722 10GbE SFP+", 0 ),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:303

PCI device IDs.

Definition at line 1872 of file intelxl.c.

◆ __pci_driver

struct pci_driver intelxl_driver __pci_driver
Initial value:
= {
.ids = intelxl_nics,
.id_count = ( sizeof ( intelxl_nics ) / sizeof ( intelxl_nics[0] ) ),
.probe = intelxl_probe,
}
static struct pci_device_id intelxl_nics[]
PCI device IDs.
Definition: intelxl.c:1872
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static int intelxl_probe(struct pci_device *pci)
Probe PCI device.
Definition: intelxl.c:1684
static void intelxl_remove(struct pci_device *pci)
Remove PCI device.
Definition: intelxl.c:1849

PCI driver.

Definition at line 1900 of file intelxl.c.