iPXE
Functions | Variables
intelxl.c File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/vlan.h>
#include <ipxe/iobuf.h>
#include <ipxe/pci.h>
#include <ipxe/version.h>
#include "intelxl.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
 FILE_SECBOOT (PERMITTED)
 
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Enable MSI-X dummy interrupt. More...
 
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Disable MSI-X dummy interrupt. More...
 
static int intelxl_alloc_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Allocate admin queue. More...
 
static void intelxl_enable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Enable admin queue. More...
 
static void intelxl_disable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Disable admin queue. More...
 
static void intelxl_free_admin (struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
 Free admin queue. More...
 
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor. More...
 
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer. More...
 
static void intelxl_admin_event_init (struct intelxl_nic *intelxl, unsigned int index)
 Initialise admin event queue descriptor. More...
 
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command. More...
 
static int intelxl_admin_version (struct intelxl_nic *intelxl)
 Get firmware version. More...
 
static int intelxl_admin_driver (struct intelxl_nic *intelxl)
 Report driver version. More...
 
static int intelxl_admin_shutdown (struct intelxl_nic *intelxl)
 Shutdown admin queues. More...
 
static int intelxl_admin_mac_read (struct net_device *netdev)
 Get MAC address. More...
 
static int intelxl_admin_mac_write (struct net_device *netdev)
 Set MAC address. More...
 
int intelxl_admin_clear_pxe (struct intelxl_nic *intelxl)
 Clear PXE mode. More...
 
static int intelxl_admin_switch (struct intelxl_nic *intelxl)
 Get switch configuration. More...
 
static int intelxl_admin_vsi (struct intelxl_nic *intelxl)
 Get VSI parameters. More...
 
static int intelxl_admin_promisc (struct intelxl_nic *intelxl)
 Set VSI promiscuous modes. More...
 
int intelxl_admin_mac_config (struct intelxl_nic *intelxl)
 Set MAC configuration. More...
 
static int intelxl_admin_autoneg (struct intelxl_nic *intelxl)
 Restart autonegotiation. More...
 
static int intelxl_admin_link (struct net_device *netdev)
 Get link status. More...
 
static void intelxl_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
 Handle admin event. More...
 
static void intelxl_refill_admin (struct intelxl_nic *intelxl)
 Refill admin event queue. More...
 
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue. More...
 
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues. More...
 
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset) More...
 
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues. More...
 
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring. More...
 
void intelxl_free_ring (struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
 Free descriptor ring. More...
 
static void intelxl_context_dump (struct intelxl_nic *intelxl, uint32_t op, size_t len)
 Dump queue context (for debugging) More...
 
static int intelxl_context_line (struct intelxl_nic *intelxl, struct intelxl_context_line *line, unsigned int index, uint32_t op)
 Program queue context line. More...
 
static int intelxl_context (struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
 Program queue context. More...
 
static int intelxl_context_tx (struct intelxl_nic *intelxl, physaddr_t address)
 Program transmit queue context. More...
 
static int intelxl_context_rx (struct intelxl_nic *intelxl, physaddr_t address)
 Program receive queue context. More...
 
static int intelxl_enable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Enable descriptor ring. More...
 
static int intelxl_disable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Disable descriptor ring. More...
 
int intelxl_create_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Create descriptor ring. More...
 
void intelxl_destroy_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Destroy descriptor ring. More...
 
static void intelxl_refill_rx (struct intelxl_nic *intelxl)
 Refill receive descriptor ring. More...
 
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers. More...
 
static int intelxl_open (struct net_device *netdev)
 Open network device. More...
 
static void intelxl_close (struct net_device *netdev)
 Close network device. More...
 
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
static void intelxl_poll_tx (struct net_device *netdev)
 Poll for completed packets. More...
 
static void intelxl_poll_rx (struct net_device *netdev)
 Poll for received packets. More...
 
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets. More...
 
static int intelxl_probe (struct pci_device *pci)
 Probe PCI device. More...
 
static void intelxl_remove (struct pci_device *pci)
 Remove PCI device. More...
 

Variables

const struct intelxl_admin_offsets intelxl_admin_offsets
 Admin queue register offsets. More...
 
static struct net_device_operations intelxl_operations
 Network device operations. More...
 
static struct pci_device_id intelxl_nics []
 PCI device IDs. More...
 
struct pci_driver intelxl_driver __pci_driver
 PCI driver. More...
 

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ FILE_SECBOOT()

FILE_SECBOOT ( PERMITTED  )

◆ intelxl_msix_enable()

int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Enable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector
Return values
rcReturn status code

Definition at line 63 of file intelxl.c.

64  {
65  int rc;
66 
67  /* Enable MSI-X capability */
68  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix ) ) != 0 ) {
69  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
70  intelxl, strerror ( rc ) );
71  goto err_enable;
72  }
73 
74  /* Enable dummy interrupt */
75  pci_msix_unmask ( &intelxl->msix, vector );
76 
77  return 0;
78 
79  pci_msix_disable ( pci, &intelxl->msix );
80  err_enable:
81  return rc;
82 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:208
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define DBGC(...)
Definition: compiler.h:505
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:77
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:79
struct pci_msix msix
MSI-X interrupt.
Definition: intelxl.h:939
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:137

References DBGC, intelxl_nic::msix, pci_msix_disable(), pci_msix_enable(), pci_msix_unmask(), rc, strerror(), and vector.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Disable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector

Definition at line 91 of file intelxl.c.

92  {
93 
94  /* Disable dummy interrupts */
95  pci_msix_mask ( &intelxl->msix, vector );
96 
97  /* Disable MSI-X capability */
98  pci_msix_disable ( pci, &intelxl->msix );
99 }
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:208
uint32_t vector
MSI-X vector.
Definition: ena.h:20
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:65
struct pci_msix msix
MSI-X interrupt.
Definition: intelxl.h:939

References intelxl_nic::msix, pci_msix_disable(), pci_msix_mask(), and vector.

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_admin()

static int intelxl_alloc_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Allocate admin queue.

Parameters
intelxlIntel device
adminAdmin queue
Return values
rcReturn status code

Definition at line 124 of file intelxl.c.

125  {
126  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
127  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
128 
129  /* Allocate admin queue */
130  admin->buf = dma_alloc ( intelxl->dma, &admin->map, ( buf_len + len ),
131  INTELXL_ALIGN );
132  if ( ! admin->buf )
133  return -ENOMEM;
134  admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
135 
136  DBGC ( intelxl, "INTELXL %p A%cQ is at [%08lx,%08lx) buf "
137  "[%08lx,%08lx)\n", intelxl,
138  ( ( admin == &intelxl->command ) ? 'T' : 'R' ),
139  virt_to_phys ( admin->desc ),
140  ( virt_to_phys ( admin->desc ) + len ),
141  virt_to_phys ( admin->buf ),
142  ( virt_to_phys ( admin->buf ) + buf_len ) );
143  return 0;
144 }
struct dma_device * dma
DMA device.
Definition: intelxl.h:914
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:27
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
#define ENOMEM
Not enough space.
Definition: errno.h:535
ring len
Length.
Definition: dwmac.h:231
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:458
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.

References intelxl_admin::buf, intelxl_nic::command, DBGC, intelxl_admin::desc, intelxl_nic::dma, dma_alloc(), ENOMEM, INTELXL_ADMIN_NUM_DESC, INTELXL_ALIGN, len, and intelxl_admin::map.

Referenced by intelxl_open_admin().

◆ intelxl_enable_admin()

static void intelxl_enable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Enable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 152 of file intelxl.c.

153  {
154  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
155  const struct intelxl_admin_offsets *regs = admin->regs;
156  void *admin_regs = ( intelxl->regs + admin->base );
158 
159  /* Initialise admin queue */
160  memset ( admin->desc, 0, len );
161 
162  /* Reset head and tail registers */
163  writel ( 0, admin_regs + regs->head );
164  writel ( 0, admin_regs + regs->tail );
165 
166  /* Reset queue index */
167  admin->index = 0;
168 
169  /* Program queue address */
170  address = dma ( &admin->map, admin->desc );
171  writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
172  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
173  writel ( ( ( ( uint64_t ) address ) >> 32 ),
174  admin_regs + regs->bah );
175  } else {
176  writel ( 0, admin_regs + regs->bah );
177  }
178 
179  /* Program queue length and enable queue */
182  admin_regs + regs->len );
183 }
void * regs
Registers.
Definition: intelxl.h:912
#define INTELXL_ADMIN_LEN_ENABLE
Queue enable.
Definition: intelxl.h:51
Admin queue register offsets.
Definition: intelxl.h:64
uint64_t address
Base address.
Definition: ena.h:24
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:463
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
unsigned int index
Queue index.
Definition: intelxl.h:460
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:458
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_ADMIN_LEN_LEN(x)
Queue length.
Definition: intelxl.h:50
struct i386_regs regs
Definition: registers.h:15
unsigned long physaddr_t
Definition: stdint.h:20
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:465
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
void * memset(void *dest, int character, size_t len) __nonnull

References address, intelxl_admin::base, intelxl_admin::desc, dma(), intelxl_admin::index, INTELXL_ADMIN_LEN_ENABLE, INTELXL_ADMIN_LEN_LEN, INTELXL_ADMIN_NUM_DESC, len, intelxl_admin::map, memset(), regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_reopen_admin().

◆ intelxl_disable_admin()

static void intelxl_disable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Disable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 191 of file intelxl.c.

192  {
193  const struct intelxl_admin_offsets *regs = admin->regs;
194  void *admin_regs = ( intelxl->regs + admin->base );
195 
196  /* Disable queue */
197  writel ( 0, admin_regs + regs->len );
198 }
void * regs
Registers.
Definition: intelxl.h:912
Admin queue register offsets.
Definition: intelxl.h:64
unsigned int base
Register block base.
Definition: intelxl.h:463
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:465

References intelxl_admin::base, regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_free_admin()

static void intelxl_free_admin ( struct intelxl_nic *intelxl  __unused,
struct intelxl_admin admin 
)
static

Free admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 206 of file intelxl.c.

207  {
208  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
209  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
210 
211  /* Free queue */
212  dma_free ( &admin->map, admin->buf, ( buf_len + len ) );
213 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
ring len
Length.
Definition: dwmac.h:231
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:458
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454

References intelxl_admin::buf, intelxl_admin::desc, dma_free(), INTELXL_ADMIN_NUM_DESC, len, and intelxl_admin::map.

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic intelxl)

Get next admin command queue descriptor.

Parameters
intelxlIntel device
Return values
cmdCommand descriptor

Definition at line 222 of file intelxl.c.

222  {
223  struct intelxl_admin *admin = &intelxl->command;
225 
226  /* Get and initialise next descriptor */
227  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
228  memset ( cmd, 0, sizeof ( *cmd ) );
229  return cmd;
230 }
Admin queue.
Definition: intelxl.h:452
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
unsigned int index
Queue index.
Definition: intelxl.h:460
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
Admin queue descriptor.
Definition: intelxl.h:416
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
void * memset(void *dest, int character, size_t len) __nonnull

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_descriptor(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), and intelxlvf_admin_command_descriptor().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl)

Get next admin command queue data buffer.

Parameters
intelxlIntel device
Return values
bufData buffer

Definition at line 239 of file intelxl.c.

239  {
240  struct intelxl_admin *admin = &intelxl->command;
241  union intelxl_admin_buffer *buf;
242 
243  /* Get next data buffer */
244  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
245  memset ( buf, 0, sizeof ( *buf ) );
246  return buf;
247 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
Admin queue.
Definition: intelxl.h:452
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
unsigned int index
Queue index.
Definition: intelxl.h:460
Admin queue data buffer.
Definition: intelxl.h:402
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_buffer(), intelxl_admin_driver(), intelxl_admin_mac_read(), intelxl_admin_switch(), intelxl_admin_vsi(), and intelxlvf_admin_command_buffer().

◆ intelxl_admin_event_init()

static void intelxl_admin_event_init ( struct intelxl_nic intelxl,
unsigned int  index 
)
static

Initialise admin event queue descriptor.

Parameters
intelxlIntel device
indexEvent queue index

Definition at line 255 of file intelxl.c.

256  {
257  struct intelxl_admin *admin = &intelxl->event;
258  struct intelxl_admin_descriptor *evt;
259  union intelxl_admin_buffer *buf;
261 
262  /* Initialise descriptor */
263  evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
264  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
265  address = dma ( &admin->map, buf );
267  evt->len = cpu_to_le16 ( sizeof ( *buf ) );
268  evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
269  evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
270 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:452
long index
Definition: bigint.h:65
uint16_t flags
Flags.
Definition: intelxl.h:418
unsigned long long uint64_t
Definition: stdint.h:13
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
uint16_t len
Data length.
Definition: intelxl.h:422
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:458
#define cpu_to_le32(value)
Definition: byteswap.h:108
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:430
uint32_t high
Buffer address high.
Definition: intelxl.h:82
Admin queue descriptor.
Definition: intelxl.h:416
uint32_t low
Buffer address low.
Definition: intelxl.h:84
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:371
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Admin queue data buffer.
Definition: intelxl.h:402

References address, intelxl_admin::buf, intelxl_admin_params::buffer, cpu_to_le16, cpu_to_le32, intelxl_admin::desc, dma(), intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_admin_buffer_params::high, index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_NUM_DESC, intelxl_admin_descriptor::len, intelxl_admin_buffer_params::low, intelxl_admin::map, and intelxl_admin_descriptor::params.

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 278 of file intelxl.c.

278  {
279  struct intelxl_admin *admin = &intelxl->command;
280  const struct intelxl_admin_offsets *regs = admin->regs;
281  void *admin_regs = ( intelxl->regs + admin->base );
283  union intelxl_admin_buffer *buf;
285  uint32_t cookie;
286  uint16_t silence;
287  unsigned int index;
288  unsigned int tail;
289  unsigned int i;
290  int rc;
291 
292  /* Get next queue entry */
293  index = admin->index++;
294  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
295  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
296  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
297  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
298  intelxl, index, le16_to_cpu ( cmd->opcode ) );
299  if ( cmd->cookie )
300  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
301  DBGC2 ( intelxl, ":\n" );
302 
303  /* Allow expected errors to be silenced */
304  silence = cmd->ret;
305  cmd->ret = 0;
306 
307  /* Sanity checks */
308  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
309  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
310  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
311 
312  /* Populate data buffer address if applicable */
313  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
314  address = dma ( &admin->map, buf );
315  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
316  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
317  }
318 
319  /* Populate cookie, if not being (ab)used for VF opcode */
320  if ( ! cmd->cookie )
321  cmd->cookie = cpu_to_le32 ( index );
322 
323  /* Record cookie */
324  cookie = cmd->cookie;
325 
326  /* Post command descriptor */
327  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
328  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
329  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
330  le16_to_cpu ( cmd->len ) );
331  }
332  wmb();
333  writel ( tail, admin_regs + regs->tail );
334 
335  /* Wait for completion */
336  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
337 
338  /* If response is not complete, delay 1ms and retry */
339  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
340  mdelay ( 1 );
341  continue;
342  }
343  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
344  intelxl, index );
345  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
346  sizeof ( *cmd ) );
347  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
348  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
349  le16_to_cpu ( cmd->len ) );
350  }
351 
352  /* Check for cookie mismatch */
353  if ( cmd->cookie != cookie ) {
354  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
355  "cookie %#x\n", intelxl, index,
356  le32_to_cpu ( cmd->cookie ) );
357  rc = -EPROTO;
358  goto err;
359  }
360 
361  /* Check for unexpected errors */
362  if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
363  DBGC ( intelxl, "INTELXL %p admin command %#x error "
364  "%d\n", intelxl, index,
365  le16_to_cpu ( cmd->ret ) );
366  rc = -EIO;
367  goto err;
368  }
369 
370  /* Success */
371  return 0;
372  }
373 
374  rc = -ETIMEDOUT;
375  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
376  intelxl, index );
377  err:
378  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
379  return rc;
380 }
void * regs
Registers.
Definition: intelxl.h:912
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:440
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define le32_to_cpu(value)
Definition: byteswap.h:114
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
Admin queue register offsets.
Definition: intelxl.h:64
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:452
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
long index
Definition: bigint.h:65
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:463
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:437
unsigned int index
Queue index.
Definition: intelxl.h:460
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define DBGC_HDA(...)
Definition: compiler.h:506
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:458
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define EPROTO
Protocol error.
Definition: errno.h:625
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
#define le16_to_cpu(value)
Definition: byteswap.h:113
unsigned int uint32_t
Definition: stdint.h:12
struct i386_regs regs
Definition: registers.h:15
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:79
Admin queue descriptor.
Definition: intelxl.h:416
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:434
#define cpu_to_le16(value)
Definition: byteswap.h:107
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:465
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:443
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:487
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:670
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:434
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Admin queue data buffer.
Definition: intelxl.h:402

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, dma(), EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_FL_RD, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin::map, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, wmb(), and writel().

Referenced by ice_admin_add_txq(), ice_admin_autoneg(), ice_admin_disable_txq(), ice_admin_link(), ice_admin_mac_read(), ice_admin_mac_write(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ice_admin_version(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), intelxlvf_admin_request_qps(), and intelxlvf_reset_admin().

◆ intelxl_admin_version()

static int intelxl_admin_version ( struct intelxl_nic intelxl)
static

Get firmware version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 388 of file intelxl.c.

388  {
391  unsigned int api;
392  int rc;
393 
394  /* Populate descriptor */
396  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
397  version = &cmd->params.version;
398 
399  /* Issue command */
400  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
401  return rc;
402  api = le16_to_cpu ( version->api.major );
403  DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
404  intelxl, le16_to_cpu ( version->firmware.major ),
405  le16_to_cpu ( version->firmware.minor ),
406  api, le16_to_cpu ( version->api.minor ) );
407 
408  /* Check for API compatibility */
409  if ( api > INTELXL_ADMIN_API_MAJOR ) {
410  DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
411  intelxl, api );
412  return -ENOTSUP;
413  }
414 
415  return 0;
416 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct pci_api * api
API for this bus:dev.fn address.
Definition: pcicloud.c:42
#define DBGC(...)
Definition: compiler.h:505
#define ENOTSUP
Operation not supported.
Definition: errno.h:590
u32 version
Driver version.
Definition: ath9k_hw.c:1985
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:88
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:490
Admin queue Get Version command parameters.
Definition: intelxl.h:99
#define le16_to_cpu(value)
Definition: byteswap.h:113
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References api, cmd, cpu_to_le16, DBGC, ENOTSUP, INTELXL_ADMIN_API_MAJOR, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_VERSION, le16_to_cpu, rc, and version.

◆ intelxl_admin_driver()

static int intelxl_admin_driver ( struct intelxl_nic intelxl)
static

Report driver version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 424 of file intelxl.c.

424  {
426  struct intelxl_admin_driver_params *driver;
427  union intelxl_admin_buffer *buf;
428  int rc;
429 
430  /* Populate descriptor */
432  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
434  cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
435  driver = &cmd->params.driver;
436  driver->major = product_major_version;
437  driver->minor = product_minor_version;
438  buf = intelxl_admin_command_buffer ( intelxl );
439  snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
441 
442  /* Issue command */
443  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
444  return rc;
445 
446  return 0;
447 }
const char product_short_name[]
Product short name string.
Definition: version.c:77
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
char name[32]
Driver name.
Definition: intelxl.h:132
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:239
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:404
Admin queue Driver Version command parameters.
Definition: intelxl.h:114
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
const int product_major_version
Product major version.
Definition: version.c:65
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:383
const char product_name[]
Product name string.
Definition: version.c:74
#define INTELXL_ADMIN_DRIVER
Admin queue Driver Version command.
Definition: intelxl.h:111
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:443
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
const int product_minor_version
Product minor version.
Definition: version.c:68
Admin queue data buffer.
Definition: intelxl.h:402

References cmd, cpu_to_le16, intelxl_admin_buffer::driver, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_DRIVER, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, intelxl_admin_driver_buffer::name, product_major_version, product_minor_version, product_name, product_short_name, rc, and snprintf().

Referenced by intelxl_probe().

◆ intelxl_admin_shutdown()

static int intelxl_admin_shutdown ( struct intelxl_nic intelxl)
static

Shutdown admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 455 of file intelxl.c.

455  {
458  int rc;
459 
460  /* Populate descriptor */
462  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
463  shutdown = &cmd->params.shutdown;
465 
466  /* Issue command */
467  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
468  return rc;
469 
470  return 0;
471 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
#define INTELXL_ADMIN_SHUTDOWN
Admin queue Shutdown command.
Definition: intelxl.h:136
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Admin queue Shutdown command parameters.
Definition: intelxl.h:139
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING
Driver is unloading.
Definition: intelxl.h:147
void shutdown(int flags)
Shut down iPXE.
Definition: init.c:101
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_SHUTDOWN, INTELXL_ADMIN_SHUTDOWN_UNLOADING, rc, and shutdown().

Referenced by intelxl_close_admin().

◆ intelxl_admin_mac_read()

static int intelxl_admin_mac_read ( struct net_device netdev)
static

Get MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 479 of file intelxl.c.

479  {
480  struct intelxl_nic *intelxl = netdev->priv;
483  union intelxl_admin_buffer *buf;
484  uint8_t *mac;
485  int rc;
486 
487  /* Populate descriptor */
489  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
490  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
491  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
492  read = &cmd->params.mac_read;
493  buf = intelxl_admin_command_buffer ( intelxl );
494  mac = buf->mac_read.pf;
495 
496  /* Issue command */
497  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
498  return rc;
499 
500  /* Check that MAC address is present in response */
501  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
502  DBGC ( intelxl, "INTELXL %p has no MAC address\n", intelxl );
503  return -ENOENT;
504  }
505 
506  /* Check that address is valid */
507  if ( ! is_valid_ether_addr ( mac ) ) {
508  DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
509  intelxl, eth_ntoa ( mac ) );
510  return -ENOENT;
511  }
512 
513  /* Copy MAC address */
514  DBGC ( intelxl, "INTELXL %p has MAC address %s\n",
515  intelxl, eth_ntoa ( mac ) );
517 
518  return 0;
519 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct option_descriptor read[1]
Definition: nvo_cmd.c:116
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:515
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:239
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:161
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint8_t pf[ETH_ALEN]
Physical function MAC address.
Definition: intelxl.h:166
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
struct intelxl_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: intelxl.h:406
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:150
Admin queue Manage MAC Address Read command parameters.
Definition: intelxl.h:153
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:176
unsigned char uint8_t
Definition: stdint.h:10
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define ETH_ALEN
Definition: if_ether.h:9
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:78
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:382
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:402

References cmd, cpu_to_le16, DBGC, ENOENT, ETH_ALEN, eth_ntoa(), net_device::hw_addr, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_MAC_READ, INTELXL_ADMIN_MAC_READ_VALID_LAN, is_valid_ether_addr(), mac, intelxl_admin_buffer::mac_read, memcpy(), netdev, intelxl_admin_mac_read_buffer::pf, net_device::priv, rc, and read.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_write()

static int intelxl_admin_mac_write ( struct net_device netdev)
static

Set MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 527 of file intelxl.c.

527  {
528  struct intelxl_nic *intelxl = netdev->priv;
531  union {
533  struct {
534  uint16_t high;
535  uint32_t low;
536  } __attribute__ (( packed ));
537  } mac;
538  int rc;
539 
540  /* Populate descriptor */
543  write = &cmd->params.mac_write;
544  memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
545  write->high = bswap_16 ( mac.high );
546  write->low = bswap_32 ( mac.low );
547 
548  /* Issue command */
549  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
550  return rc;
551 
552  return 0;
553 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
#define __attribute__(x)
Definition: compiler.h:10
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
void * memcpy(void *dest, const void *src, size_t len) __nonnull
void * priv
Driver private data.
Definition: netdevice.h:432
#define bswap_16(value)
Definition: byteswap.h:59
uint16_t high
MAC address first 16 bits, byte-swapped.
Definition: intelxl.h:185
static struct net_device * netdev
Definition: gdbudp.c:52
uint32_t low
MAC address last 32 bits, byte-swapped.
Definition: intelxl.h:187
#define bswap_32(value)
Definition: byteswap.h:71
device nvs write
Definition: threewire.h:61
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:176
unsigned char uint8_t
Definition: stdint.h:10
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define ETH_ALEN
Definition: if_ether.h:9
unsigned int uint32_t
Definition: stdint.h:12
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
Admin queue Manage MAC Address Write command parameters.
Definition: intelxl.h:179
#define cpu_to_le16(value)
Definition: byteswap.h:107
__be32 raw[7]
Definition: CIB_PRM.h:28
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:388
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References __attribute__, bswap_16, bswap_32, cmd, cpu_to_le16, ETH_ALEN, intelxl_admin_mac_write_params::high, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_WRITE, net_device::ll_addr, intelxl_admin_mac_write_params::low, mac, memcpy(), netdev, net_device::priv, raw, rc, and write.

Referenced by intelxl_open().

◆ intelxl_admin_clear_pxe()

int intelxl_admin_clear_pxe ( struct intelxl_nic intelxl)

Clear PXE mode.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 561 of file intelxl.c.

561  {
563  struct intelxl_admin_clear_pxe_params *pxe;
564  int rc;
565 
566  /* Populate descriptor */
570  pxe = &cmd->params.pxe;
572 
573  /* Issue command */
574  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
575  return rc;
576 
577  /* Check for expected errors */
578  if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
579  DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
580  intelxl );
581  return 0;
582  }
583 
584  return 0;
585 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:196
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:204
uint8_t magic
Magic value.
Definition: intelxl.h:198
#define INTELXL_ADMIN_EEXIST
Error: attempt to create something that already exists.
Definition: intelxl.h:449
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:193
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, INTELXL_ADMIN_CLEAR_PXE, INTELXL_ADMIN_CLEAR_PXE_MAGIC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_EEXIST, intelxl_admin_clear_pxe_params::magic, and rc.

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_admin_switch()

static int intelxl_admin_switch ( struct intelxl_nic intelxl)
static

Get switch configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 593 of file intelxl.c.

593  {
595  struct intelxl_admin_switch_params *sw;
596  union intelxl_admin_buffer *buf;
597  uint16_t next = 0;
598  int rc;
599 
600  /* Get each configuration in turn */
601  do {
602  /* Populate descriptor */
604  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
605  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
606  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
607  sw = &cmd->params.sw;
608  sw->next = next;
609  buf = intelxl_admin_command_buffer ( intelxl );
610 
611  /* Issue command */
612  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
613  return rc;
614 
615  /* Dump raw configuration */
616  DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
617  intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
618  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
619 
620  /* Parse response */
621  if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
622  intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
623  DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
624  "downlink %#04x conn %#02x\n", intelxl,
625  intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
626  le16_to_cpu ( buf->sw.cfg.downlink ),
627  buf->sw.cfg.connection );
628  }
629 
630  } while ( ( next = sw->next ) );
631 
632  /* Check that we found a VSI */
633  if ( ! intelxl->vsi ) {
634  DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
635  return -ENOENT;
636  }
637 
638  return 0;
639 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:207
uint8_t type
Switching element type.
Definition: intelxl.h:212
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:515
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:239
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:408
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:220
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
uint8_t connection
Connection type.
Definition: intelxl.h:224
#define le16_to_cpu(value)
Definition: byteswap.h:113
uint32_t next
Next descriptor address.
Definition: dwmac.h:22
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:218
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:253
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:235
#define INTELXL_ADMIN_SWITCH_TYPE_VSI
Virtual Station Inferface element type.
Definition: intelxl.h:232
uint16_t seid
Switching element ID.
Definition: intelxl.h:216
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:402

References intelxl_admin_switch_buffer::cfg, cmd, intelxl_admin_switch_config::connection, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, intelxl_admin_switch_config::downlink, ENOENT, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_SWITCH, INTELXL_ADMIN_SWITCH_TYPE_VSI, le16_to_cpu, next, rc, intelxl_admin_switch_config::seid, intelxl_admin_buffer::sw, intelxl_admin_switch_config::type, intelxl_admin_switch_config::uplink, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_vsi()

static int intelxl_admin_vsi ( struct intelxl_nic intelxl)
static

Get VSI parameters.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 647 of file intelxl.c.

647  {
650  union intelxl_admin_buffer *buf;
651  int rc;
652 
653  /* Populate descriptor */
655  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
656  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
657  cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
658  vsi = &cmd->params.vsi;
659  vsi->vsi = cpu_to_le16 ( intelxl->vsi );
660  buf = intelxl_admin_command_buffer ( intelxl );
661 
662  /* Issue command */
663  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
664  return rc;
665 
666  /* Parse response */
667  intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
668  intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
669  DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
670  intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
671 
672  return 0;
673 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:274
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:278
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:410
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:260
unsigned int qset
Queue set handle.
Definition: intelxl.h:929
#define DBGC(...)
Definition: compiler.h:505
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:239
#define INTELXL_ADMIN_VSI
Admin queue Get VSI Parameters command.
Definition: intelxl.h:257
unsigned int queue
Queue number.
Definition: intelxl.h:925
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:262
#define le16_to_cpu(value)
Definition: byteswap.h:113
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:402

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_VSI, le16_to_cpu, intelxl_admin_vsi_buffer::qset, intelxl_nic::qset, intelxl_admin_vsi_buffer::queue, intelxl_nic::queue, rc, intelxl_admin_vsi_params::vsi, intelxl_admin_buffer::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_promisc()

static int intelxl_admin_promisc ( struct intelxl_nic intelxl)
static

Set VSI promiscuous modes.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 681 of file intelxl.c.

681  {
683  struct intelxl_admin_promisc_params *promisc;
684  uint16_t flags;
685  int rc;
686 
687  /* Populate descriptor */
689  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
694  promisc = &cmd->params.promisc;
695  promisc->flags = cpu_to_le16 ( flags );
696  promisc->valid = cpu_to_le16 ( flags );
697  promisc->vsi = cpu_to_le16 ( intelxl->vsi );
698 
699  /* Issue command */
700  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
701  return rc;
702 
703  return 0;
704 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
#define INTELXL_ADMIN_PROMISC_FL_VLAN
Promiscuous VLAN mode.
Definition: intelxl.h:308
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_PROMISC
Admin queue Set VSI Promiscuous Modes command.
Definition: intelxl.h:284
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
uint16_t flags
Flags.
Definition: intelxl.h:289
uint8_t flags
Flags.
Definition: ena.h:18
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:293
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:287
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST
Promiscuous broadcast mode.
Definition: intelxl.h:305
uint16_t valid
Valid flags.
Definition: intelxl.h:291
#define INTELXL_ADMIN_PROMISC_FL_UNICAST
Promiscuous unicast mode.
Definition: intelxl.h:299
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST
Promiscuous multicast mode.
Definition: intelxl.h:302

References cmd, cpu_to_le16, flags, intelxl_admin_promisc_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_PROMISC, INTELXL_ADMIN_PROMISC_FL_BROADCAST, INTELXL_ADMIN_PROMISC_FL_MULTICAST, INTELXL_ADMIN_PROMISC_FL_UNICAST, INTELXL_ADMIN_PROMISC_FL_VLAN, rc, intelxl_admin_promisc_params::valid, intelxl_admin_promisc_params::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_config()

int intelxl_admin_mac_config ( struct intelxl_nic intelxl)

Set MAC configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 712 of file intelxl.c.

712  {
714  struct intelxl_admin_mac_config_params *config;
715  int rc;
716 
717  /* Populate descriptor */
720  config = &cmd->params.mac_config;
721  config->mfs = cpu_to_le16 ( intelxl->mfs );
723 
724  /* Issue command */
725  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
726  return rc;
727 
728  return 0;
729 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
Admin queue Set MAC Configuration command parameters.
Definition: intelxl.h:314
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
#define INTELXL_ADMIN_MAC_CONFIG
Admin queue Set MAC Configuration command.
Definition: intelxl.h:311
Admin queue descriptor.
Definition: intelxl.h:416
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:316
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC
Append CRC on transmit.
Definition: intelxl.h:324
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_mac_config_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_CONFIG, INTELXL_ADMIN_MAC_CONFIG_FL_CRC, intelxl_admin_mac_config_params::mfs, intelxl_nic::mfs, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_admin_autoneg()

static int intelxl_admin_autoneg ( struct intelxl_nic intelxl)
static

Restart autonegotiation.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 737 of file intelxl.c.

737  {
739  struct intelxl_admin_autoneg_params *autoneg;
740  int rc;
741 
742  /* Populate descriptor */
744  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
745  autoneg = &cmd->params.autoneg;
748 
749  /* Issue command */
750  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
751  return rc;
752 
753  return 0;
754 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:338
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:327
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:330
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:341
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_autoneg_params::flags, INTELXL_ADMIN_AUTONEG, INTELXL_ADMIN_AUTONEG_FL_ENABLE, INTELXL_ADMIN_AUTONEG_FL_RESTART, intelxl_admin_command(), intelxl_admin_command_descriptor(), and rc.

Referenced by intelxl_open().

◆ intelxl_admin_link()

static int intelxl_admin_link ( struct net_device netdev)
static

Get link status.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 762 of file intelxl.c.

762  {
763  struct intelxl_nic *intelxl = netdev->priv;
766  int rc;
767 
768  /* Populate descriptor */
770  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
771  link = &cmd->params.link;
773 
774  /* Issue command */
775  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
776  return rc;
777  DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
778  intelxl, link->phy, link->speed, link->status );
779 
780  /* Update network device */
781  if ( link->status & INTELXL_ADMIN_LINK_UP ) {
783  } else {
785  }
786 
787  return 0;
788 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:222
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:344
#define DBGC(...)
Definition: compiler.h:505
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:231
void * priv
Driver private data.
Definition: netdevice.h:432
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:789
static struct net_device * netdev
Definition: gdbudp.c:52
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:25
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue descriptor.
Definition: intelxl.h:416
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:366
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:363
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_LINK, INTELXL_ADMIN_LINK_NOTIFY, INTELXL_ADMIN_LINK_UP, link, netdev, netdev_link_down(), netdev_link_up(), net_device::priv, and rc.

Referenced by intelxl_admin_event(), intelxl_open(), and intelxl_probe().

◆ intelxl_admin_event()

static void intelxl_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor evt,
union intelxl_admin_buffer *buf  __unused 
)
static

Handle admin event.

Parameters
netdevNetwork device
evtEvent descriptor
bufData buffer

Definition at line 797 of file intelxl.c.

799  {
800  struct intelxl_nic *intelxl = netdev->priv;
801 
802  /* Ignore unrecognised events */
803  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
804  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
805  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
806  return;
807  }
808 
809  /* Update link status */
811 }
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:344
uint16_t opcode
Opcode.
Definition: intelxl.h:420
#define DBGC(...)
Definition: compiler.h:505
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define le16_to_cpu(value)
Definition: byteswap.h:113
#define cpu_to_le16(value)
Definition: byteswap.h:107
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:762

References cpu_to_le16, DBGC, INTELXL_ADMIN_LINK, intelxl_admin_link(), le16_to_cpu, netdev, intelxl_admin_descriptor::opcode, and net_device::priv.

Referenced by intelxl_probe().

◆ intelxl_refill_admin()

static void intelxl_refill_admin ( struct intelxl_nic intelxl)
static

Refill admin event queue.

Parameters
intelxlIntel device

Definition at line 818 of file intelxl.c.

818  {
819  struct intelxl_admin *admin = &intelxl->event;
820  const struct intelxl_admin_offsets *regs = admin->regs;
821  void *admin_regs = ( intelxl->regs + admin->base );
822  unsigned int tail;
823 
824  /* Update tail pointer */
825  tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
827  wmb();
828  writel ( tail, admin_regs + regs->tail );
829 }
void * regs
Registers.
Definition: intelxl.h:912
wmb()
Admin queue register offsets.
Definition: intelxl.h:64
Admin queue.
Definition: intelxl.h:452
unsigned int base
Register block base.
Definition: intelxl.h:463
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
unsigned int index
Queue index.
Definition: intelxl.h:460
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
unsigned int tail
Tail Register offset.
Definition: intelxl.h:74
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:465
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944

References intelxl_admin::base, intelxl_nic::event, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, regs, intelxl_admin::regs, intelxl_nic::regs, intelxl_admin_offsets::tail, wmb(), and writel().

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters
netdevNetwork device

Definition at line 836 of file intelxl.c.

836  {
837  struct intelxl_nic *intelxl = netdev->priv;
838  struct intelxl_admin *admin = &intelxl->event;
839  struct intelxl_admin_descriptor *evt;
840  union intelxl_admin_buffer *buf;
841 
842  /* Check for events */
843  while ( 1 ) {
844 
845  /* Get next event descriptor and data buffer */
846  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
847  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
848 
849  /* Stop if descriptor is not yet completed */
850  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
851  return;
852  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
853  intelxl, admin->index );
854  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
855  sizeof ( *evt ) );
856  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
857  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
858  le16_to_cpu ( evt->len ) );
859  }
860 
861  /* Handle event */
862  intelxl->handle ( netdev, evt, buf );
863 
864  /* Reset descriptor and refill queue */
865  intelxl_admin_event_init ( intelxl, admin->index );
866  admin->index++;
867  intelxl_refill_admin ( intelxl );
868  }
869 }
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:963
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:456
Admin queue.
Definition: intelxl.h:452
uint16_t flags
Flags.
Definition: intelxl.h:418
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
uint16_t len
Data length.
Definition: intelxl.h:422
unsigned int index
Queue index.
Definition: intelxl.h:460
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:255
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:818
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:454
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define le16_to_cpu(value)
Definition: byteswap.h:113
Admin queue descriptor.
Definition: intelxl.h:416
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:434
Admin queue data buffer.
Definition: intelxl.h:402

References intelxl_admin::buf, cpu_to_le16, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_nic::handle, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_NUM_DESC, intelxl_refill_admin(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, and net_device::priv.

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 877 of file intelxl.c.

877  {
878  int rc;
879 
880  /* Allocate admin event queue */
881  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
882  goto err_alloc_event;
883 
884  /* Allocate admin command queue */
885  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
886  goto err_alloc_command;
887 
888  /* (Re)open admin queues */
889  intelxl_reopen_admin ( intelxl );
890 
891  return 0;
892 
893  intelxl_disable_admin ( intelxl, &intelxl->command );
894  intelxl_disable_admin ( intelxl, &intelxl->event );
895  intelxl_free_admin ( intelxl, &intelxl->command );
896  err_alloc_command:
897  intelxl_free_admin ( intelxl, &intelxl->event );
898  err_alloc_event:
899  return rc;
900 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:124
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:206
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:191
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:907
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944

References intelxl_nic::command, intelxl_nic::event, intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters
intelxlIntel device

Definition at line 907 of file intelxl.c.

907  {
908  unsigned int i;
909 
910  /* Enable admin event queue */
911  intelxl_enable_admin ( intelxl, &intelxl->event );
912 
913  /* Enable admin command queue */
914  intelxl_enable_admin ( intelxl, &intelxl->command );
915 
916  /* Initialise all admin event queue descriptors */
917  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
918  intelxl_admin_event_init ( intelxl, i );
919 
920  /* Post all descriptors to event queue */
921  intelxl_refill_admin ( intelxl );
922 }
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:152
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:484
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:255
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:818
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_wait().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters
intelxlIntel device

Definition at line 929 of file intelxl.c.

929  {
930 
931  /* Shut down admin queues */
932  intelxl_admin_shutdown ( intelxl );
933 
934  /* Disable admin queues */
935  intelxl_disable_admin ( intelxl, &intelxl->command );
936  intelxl_disable_admin ( intelxl, &intelxl->event );
937 
938  /* Free admin queues */
939  intelxl_free_admin ( intelxl, &intelxl->command );
940  intelxl_free_admin ( intelxl, &intelxl->event );
941 }
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:455
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:206
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:191
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 957 of file intelxl.c.

958  {
959  int rc;
960 
961  /* Allocate descriptor ring */
962  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
963  INTELXL_ALIGN );
964  if ( ! ring->desc.raw ) {
965  rc = -ENOMEM;
966  goto err_alloc;
967  }
968 
969  /* Initialise descriptor ring */
970  memset ( ring->desc.raw, 0, ring->len );
971 
972  /* Reset tail pointer */
973  writel ( 0, ( intelxl->regs + ring->tail ) );
974 
975  /* Reset counters */
976  ring->prod = 0;
977  ring->cons = 0;
978 
979  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
980  intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
981  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
982 
983  return 0;
984 
985  dma_free ( &ring->map, ring->desc.raw, ring->len );
986  err_alloc:
987  return rc;
988 }
void * regs
Registers.
Definition: intelxl.h:912
size_t len
Length (in bytes)
Definition: intelxl.h:778
struct dma_device * dma
DMA device.
Definition: intelxl.h:914
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:769
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:27
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
#define ENOMEM
Not enough space.
Definition: errno.h:535
unsigned int cons
Consumer index.
Definition: intelxl.h:771
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void * raw
Raw data.
Definition: intelxl.h:764
union intelxl_ring::@79 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:767
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
unsigned int tail
Tail register.
Definition: intelxl.h:776
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_ring::cons, DBGC, intelxl_ring::desc, intelxl_nic::dma, dma_alloc(), dma_free(), ENOMEM, INTELXL_ALIGN, intelxl_ring::len, intelxl_ring::map, memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_nic::regs, intelxl_ring::tail, and writel().

Referenced by ice_create_tx(), intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring ( struct intelxl_nic *intelxl  __unused,
struct intelxl_ring ring 
)

Free descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 996 of file intelxl.c.

997  {
998 
999  /* Free descriptor ring */
1000  dma_free ( &ring->map, ring->desc.raw, ring->len );
1001  ring->desc.raw = NULL;
1002 }
size_t len
Length (in bytes)
Definition: intelxl.h:778
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
void * raw
Raw data.
Definition: intelxl.h:764
union intelxl_ring::@79 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:767
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322

References intelxl_ring::desc, dma_free(), intelxl_ring::len, intelxl_ring::map, NULL, and intelxl_ring::raw.

Referenced by ice_create_tx(), ice_destroy_tx(), intelxl_create_ring(), intelxl_destroy_ring(), intelxlvf_close(), and intelxlvf_open().

◆ intelxl_context_dump()

static void intelxl_context_dump ( struct intelxl_nic intelxl,
uint32_t  op,
size_t  len 
)
static

Dump queue context (for debugging)

Parameters
intelxlIntel device
opContext operation
lenSize of context

Definition at line 1012 of file intelxl.c.

1012  {
1013  struct intelxl_context_line line;
1014  uint32_t pfcm_lanctxctl;
1015  uint32_t pfcm_lanctxstat;
1016  unsigned int queue;
1017  unsigned int index;
1018  unsigned int i;
1019 
1020  /* Do nothing unless debug output is enabled */
1021  if ( ! DBG_EXTRA )
1022  return;
1023 
1024  /* Dump context */
1025  DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
1026  for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
1027 
1028  /* Start context operation */
1029  queue = ( intelxl->base + intelxl->queue );
1030  pfcm_lanctxctl =
1034  writel ( pfcm_lanctxctl,
1035  intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1036 
1037  /* Wait for operation to complete */
1038  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1039 
1040  /* Check if operation is complete */
1041  pfcm_lanctxstat = readl ( intelxl->regs +
1043  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1044  break;
1045 
1046  /* Delay */
1047  mdelay ( 1 );
1048  }
1049 
1050  /* Read context data */
1051  for ( i = 0 ; i < ( sizeof ( line ) /
1052  sizeof ( line.raw[0] ) ) ; i++ ) {
1053  line.raw[i] = readl ( intelxl->regs +
1054  INTELXL_PFCM_LANCTXDATA ( i ) );
1055  }
1056  DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
1057  &line, sizeof ( line ) );
1058  }
1059 }
void * regs
Registers.
Definition: intelxl.h:912
Queue context line.
Definition: intelxl.h:530
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
long index
Definition: bigint.h:65
unsigned int queue
Queue number.
Definition: intelxl.h:925
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:504
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:526
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:507
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:79
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define DBGC2(...)
Definition: compiler.h:522
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:527
unsigned int base
Absolute queue number base.
Definition: intelxl.h:921
#define DBG_EXTRA
Definition: compiler.h:319
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:604
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:503
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:500
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ
Read context.
Definition: intelxl.h:520

References intelxl_nic::base, DBG_EXTRA, DBGC2, DBGC2_HDA, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_READ, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, len, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

Referenced by intelxl_close().

◆ intelxl_context_line()

static int intelxl_context_line ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
unsigned int  index,
uint32_t  op 
)
static

Program queue context line.

Parameters
intelxlIntel device
lineQueue context line
indexLine number
opContext operation
Return values
rcReturn status code

Definition at line 1070 of file intelxl.c.

1072  {
1073  uint32_t pfcm_lanctxctl;
1074  uint32_t pfcm_lanctxstat;
1075  unsigned int queue;
1076  unsigned int i;
1077 
1078  /* Write context data */
1079  for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
1080  writel ( le32_to_cpu ( line->raw[i] ),
1081  intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
1082  }
1083 
1084  /* Start context operation */
1085  queue = ( intelxl->base + intelxl->queue );
1086  pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
1089  writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1090 
1091  /* Wait for operation to complete */
1092  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1093 
1094  /* Check if operation is complete */
1095  pfcm_lanctxstat = readl ( intelxl->regs +
1097  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1098  return 0;
1099 
1100  /* Delay */
1101  mdelay ( 1 );
1102  }
1103 
1104  DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
1105  intelxl, pfcm_lanctxctl );
1106  return -ETIMEDOUT;
1107 }
void * regs
Registers.
Definition: intelxl.h:912
uint32_t raw[4]
Raw data.
Definition: intelxl.h:532
#define le32_to_cpu(value)
Definition: byteswap.h:114
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE
Write context.
Definition: intelxl.h:522
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
long index
Definition: bigint.h:65
unsigned int queue
Queue number.
Definition: intelxl.h:925
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:504
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:526
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:507
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:79
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:527
unsigned int base
Absolute queue number base.
Definition: intelxl.h:921
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:604
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:670
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:503
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:500

References intelxl_nic::base, DBGC, ETIMEDOUT, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, le32_to_cpu, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

◆ intelxl_context()

static int intelxl_context ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
size_t  len,
uint32_t  op 
)
static

Program queue context.

Parameters
intelxlIntel device
lineQueue context lines
lenSize of context
opContext operation
Return values
rcReturn status code

Definition at line 1118 of file intelxl.c.

1120  {
1121  unsigned int index;
1122  int rc;
1123 
1124  DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
1125  intelxl, op, len );
1126  DBGC2_HDA ( intelxl, 0, line, len );
1127 
1128  /* Program one line at a time */
1129  for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
1130  if ( ( rc = intelxl_context_line ( intelxl, line++, index,
1131  op ) ) != 0 )
1132  return rc;
1133  }
1134 
1135  return 0;
1136 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Queue context line.
Definition: intelxl.h:530
long index
Definition: bigint.h:65
ring len
Length.
Definition: dwmac.h:231
#define DBGC2_HDA(...)
Definition: compiler.h:523
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define DBGC2(...)
Definition: compiler.h:522

References DBGC2, DBGC2_HDA, index, len, op, and rc.

Referenced by intelxl_context_rx(), and intelxl_context_tx().

◆ intelxl_context_tx()

static int intelxl_context_tx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program transmit queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1145 of file intelxl.c.

1146  {
1147  union {
1148  struct intelxl_context_tx tx;
1149  struct intelxl_context_line line;
1150  } ctx;
1151  int rc;
1152 
1153  /* Initialise context */
1154  memset ( &ctx, 0, sizeof ( ctx ) );
1155  ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
1156  ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
1157  ctx.tx.count =
1159  ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
1160 
1161  /* Program context */
1162  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1164  return rc;
1165 
1166  return 0;
1167 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:530
unsigned int qset
Queue set handle.
Definition: intelxl.h:929
#define cpu_to_le64(value)
Definition: byteswap.h:109
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:515
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1118
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
#define INTELXL_CTX_TX_FL_NEW
New transmit queue context.
Definition: intelxl.h:556
#define INTELXL_CTX_TX_QSET(qset)
Transmit queue set.
Definition: intelxl.h:565
#define INTELXL_CTX_TX_BASE(base)
Transmit queue base address.
Definition: intelxl.h:559
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_CTX_TX_COUNT(count)
Transmit queue count.
Definition: intelxl.h:562
Transmit queue context.
Definition: intelxl.h:536
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_TX_BASE, INTELXL_CTX_TX_COUNT, INTELXL_CTX_TX_FL_NEW, INTELXL_CTX_TX_QSET, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_TX_NUM_DESC, memset(), intelxl_nic::qset, rc, and tx.

◆ intelxl_context_rx()

static int intelxl_context_rx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program receive queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1176 of file intelxl.c.

1177  {
1178  union {
1179  struct intelxl_context_rx rx;
1180  struct intelxl_context_line line;
1181  } ctx;
1182  uint64_t base_count;
1183  int rc;
1184 
1185  /* Initialise context */
1186  memset ( &ctx, 0, sizeof ( ctx ) );
1188  ctx.rx.base_count = cpu_to_le64 ( base_count );
1189  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
1191  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
1192 
1193  /* Program context */
1194  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1196  return rc;
1197 
1198  return 0;
1199 }
Receive queue context.
Definition: intelxl.h:568
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:592
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:530
unsigned long long uint64_t
Definition: stdint.h:13
#define cpu_to_le64(value)
Definition: byteswap.h:109
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:601
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:595
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:513
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1118
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:598
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:588
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_RX_BASE_COUNT, INTELXL_CTX_RX_FL_CRCSTRIP, INTELXL_CTX_RX_FL_DSIZE, INTELXL_CTX_RX_LEN, INTELXL_CTX_RX_MFS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_RX_NUM_DESC, memset(), intelxl_nic::mfs, rc, and rx.

◆ intelxl_enable_ring()

static int intelxl_enable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Enable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1208 of file intelxl.c.

1209  {
1210  void *ring_regs = ( intelxl->regs + ring->reg );
1211  uint32_t qxx_ena;
1212 
1213  /* Enable ring */
1214  writel ( INTELXL_QXX_ENA_REQ, ( ring_regs + INTELXL_QXX_ENA ) );
1216  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1217  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) ) {
1218  DBGC ( intelxl, "INTELXL %p ring %06x failed to enable: "
1219  "%#08x\n", intelxl, ring->tail, qxx_ena );
1220  return -EIO;
1221  }
1222 
1223  return 0;
1224 }
void * regs
Registers.
Definition: intelxl.h:912
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:644
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:642
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
#define INTELXL_QXX_ENA_REQ
Enable request.
Definition: intelxl.h:643
unsigned int reg
Register block.
Definition: intelxl.h:774
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_QUEUE_ENABLE_DELAY_US
Time to wait for a queue to become enabled.
Definition: intelxl.h:607
#define EIO
Input/output error.
Definition: errno.h:434
unsigned int tail
Tail register.
Definition: intelxl.h:776

References DBGC, EIO, INTELXL_QUEUE_ENABLE_DELAY_US, INTELXL_QXX_ENA, INTELXL_QXX_ENA_REQ, INTELXL_QXX_ENA_STAT, readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, udelay(), and writel().

Referenced by intelxl_create_ring().

◆ intelxl_disable_ring()

static int intelxl_disable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Disable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1233 of file intelxl.c.

1234  {
1235  void *ring_regs = ( intelxl->regs + ring->reg );
1236  uint32_t qxx_ena;
1237  unsigned int i;
1238 
1239  /* Disable ring */
1240  writel ( 0, ( ring_regs + INTELXL_QXX_ENA ) );
1241 
1242  /* Wait for ring to be disabled */
1243  for ( i = 0 ; i < INTELXL_QUEUE_DISABLE_MAX_WAIT_MS ; i++ ) {
1244 
1245  /* Check if ring is disabled */
1246  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1247  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) )
1248  return 0;
1249 
1250  /* Delay */
1251  mdelay ( 1 );
1252  }
1253 
1254  DBGC ( intelxl, "INTELXL %p ring %06x timed out waiting for disable: "
1255  "%#08x\n", intelxl, ring->tail, qxx_ena );
1256  return -ETIMEDOUT;
1257 }
void * regs
Registers.
Definition: intelxl.h:912
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:644
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:642
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
unsigned int reg
Register block.
Definition: intelxl.h:774
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS
Maximum time to wait for a queue to become disabled.
Definition: intelxl.h:613
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:79
unsigned int tail
Tail register.
Definition: intelxl.h:776
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:670

References DBGC, ETIMEDOUT, INTELXL_QUEUE_DISABLE_MAX_WAIT_MS, INTELXL_QXX_ENA, INTELXL_QXX_ENA_STAT, mdelay(), readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, and writel().

Referenced by intelxl_create_ring(), and intelxl_destroy_ring().

◆ intelxl_create_ring()

int intelxl_create_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Create descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1266 of file intelxl.c.

1267  {
1269  int rc;
1270 
1271  /* Allocate descriptor ring */
1272  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1273  goto err_alloc;
1274 
1275  /* Program queue context */
1276  address = dma ( &ring->map, ring->desc.raw );
1277  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1278  goto err_context;
1279 
1280  /* Enable ring */
1281  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1282  goto err_enable;
1283 
1284  return 0;
1285 
1286  intelxl_disable_ring ( intelxl, ring );
1287  err_enable:
1288  err_context:
1289  intelxl_free_ring ( intelxl, ring );
1290  err_alloc:
1291  return rc;
1292 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:784
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1208
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1233
void * raw
Raw data.
Definition: intelxl.h:764
union intelxl_ring::@79 desc
Descriptors.
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:996
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:767
unsigned long physaddr_t
Definition: stdint.h:20
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:957

References address, intelxl_ring::context, intelxl_ring::desc, dma(), intelxl_alloc_ring(), intelxl_disable_ring(), intelxl_enable_ring(), intelxl_free_ring(), intelxl_ring::map, intelxl_ring::raw, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_destroy_ring()

void intelxl_destroy_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Destroy descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 1300 of file intelxl.c.

1301  {
1302  int rc;
1303 
1304  /* Disable ring */
1305  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1306  /* Leak memory; there's nothing else we can do */
1307  return;
1308  }
1309 
1310  /* Free descriptor ring */
1311  intelxl_free_ring ( intelxl, ring );
1312 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1233
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:996

References intelxl_disable_ring(), intelxl_free_ring(), and rc.

Referenced by ice_close(), ice_open(), intelxl_close(), and intelxl_open().

◆ intelxl_refill_rx()

static void intelxl_refill_rx ( struct intelxl_nic intelxl)
static

Refill receive descriptor ring.

Parameters
intelxlIntel device

Definition at line 1319 of file intelxl.c.

1319  {
1321  struct io_buffer *iobuf;
1322  unsigned int rx_idx;
1323  unsigned int rx_tail;
1324  unsigned int refilled = 0;
1325 
1326  /* Refill ring */
1327  while ( ( intelxl->rx.prod - intelxl->rx.cons ) < INTELXL_RX_FILL ) {
1328 
1329  /* Allocate I/O buffer */
1330  iobuf = alloc_rx_iob ( intelxl->mfs, intelxl->dma );
1331  if ( ! iobuf ) {
1332  /* Wait for next refill */
1333  break;
1334  }
1335 
1336  /* Get next receive descriptor */
1337  rx_idx = ( intelxl->rx.prod++ % INTELXL_RX_NUM_DESC );
1338  rx = &intelxl->rx.desc.rx[rx_idx].data;
1339 
1340  /* Populate receive descriptor */
1341  rx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1342  rx->flags = 0;
1343 
1344  /* Record I/O buffer */
1345  assert ( intelxl->rx_iobuf[rx_idx] == NULL );
1346  intelxl->rx_iobuf[rx_idx] = iobuf;
1347 
1348  DBGC2 ( intelxl, "INTELXL %p RX %d is [%08lx,%08lx)\n",
1349  intelxl, rx_idx, virt_to_phys ( iobuf->data ),
1350  ( virt_to_phys ( iobuf->data ) + intelxl->mfs ) );
1351  refilled++;
1352  }
1353 
1354  /* Push descriptors to card, if applicable */
1355  if ( refilled ) {
1356  wmb();
1357  rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1358  writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1359  }
1360 }
void * regs
Registers.
Definition: intelxl.h:912
struct dma_device * dma
DMA device.
Definition: intelxl.h:914
wmb()
unsigned int prod
Producer index.
Definition: intelxl.h:769
#define cpu_to_le64(value)
Definition: byteswap.h:109
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
unsigned int cons
Consumer index.
Definition: intelxl.h:771
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:954
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:268
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
union intelxl_ring::@79 desc
Descriptors.
Receive data descriptor.
Definition: intelxl.h:710
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:188
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:762
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:53
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
unsigned int tail
Tail register.
Definition: intelxl.h:776
#define INTELXL_RX_FILL
Receive descriptor ring fill level.
Definition: intelxl.h:824
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:750
A persistent I/O buffer.
Definition: iobuf.h:38

References alloc_rx_iob(), assert(), intelxl_ring::cons, cpu_to_le64, io_buffer::data, intelxl_rx_descriptor::data, DBGC2, intelxl_ring::desc, intelxl_nic::dma, INTELXL_RX_FILL, INTELXL_RX_NUM_DESC, iob_dma(), intelxl_nic::mfs, NULL, intelxl_ring::prod, intelxl_nic::regs, rx, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, intelxl_ring::tail, wmb(), and writel().

Referenced by intelxl_open(), and intelxl_poll().

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters
intelxlIntel device

Definition at line 1367 of file intelxl.c.

1367  {
1368  unsigned int i;
1369 
1370  /* Discard any unused receive buffers */
1371  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1372  if ( intelxl->rx_iobuf[i] )
1373  free_rx_iob ( intelxl->rx_iobuf[i] );
1374  intelxl->rx_iobuf[i] = NULL;
1375  }
1376 }
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:954
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:215
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322

References free_rx_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by ice_close(), intelxl_close(), and intelxlvf_close().

◆ intelxl_open()

static int intelxl_open ( struct net_device netdev)
static

Open network device.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 1391 of file intelxl.c.

1391  {
1392  struct intelxl_nic *intelxl = netdev->priv;
1393  unsigned int queue;
1394  int rc;
1395 
1396  /* Calculate maximum frame size */
1397  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
1398  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
1399 
1400  /* Set MAC address */
1401  if ( ( rc = intelxl_admin_mac_write ( netdev ) ) != 0 )
1402  goto err_mac_write;
1403 
1404  /* Set maximum frame size */
1405  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
1406  goto err_mac_config;
1407 
1408  /* Associate transmit queue to PF */
1410  INTELXL_QXX_CTL_PFVF_PF_INDX ( intelxl->pf ) ),
1411  ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_CTL ) );
1412 
1413  /* Clear transmit pre queue disable */
1414  queue = ( intelxl->base + intelxl->queue );
1417  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1418 
1419  /* Reset transmit queue head */
1420  writel ( 0, ( intelxl->regs + INTELXL_QTX_HEAD ( intelxl->queue ) ) );
1421 
1422  /* Create receive descriptor ring */
1423  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
1424  goto err_create_rx;
1425 
1426  /* Create transmit descriptor ring */
1427  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->tx ) ) != 0 )
1428  goto err_create_tx;
1429 
1430  /* Fill receive ring */
1431  intelxl_refill_rx ( intelxl );
1432 
1433  /* Restart autonegotiation */
1434  intelxl_admin_autoneg ( intelxl );
1435 
1436  /* Update link state */
1438 
1439  return 0;
1440 
1443  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1445  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1446  err_create_tx:
1447  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1448  err_create_rx:
1449  err_mac_config:
1450  err_mac_write:
1451  return rc;
1452 }
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:626
void * regs
Registers.
Definition: intelxl.h:912
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1300
#define INTELXL_QXX_CTL_PFVF_Q_PF
PF queue.
Definition: intelxl.h:649
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:627
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:416
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:27
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
unsigned int queue
Queue number.
Definition: intelxl.h:925
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1319
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
#define ETH_HLEN
Definition: if_ether.h:10
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)
PF index.
Definition: intelxl.h:651
void * priv
Driver private data.
Definition: netdevice.h:432
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
static struct net_device * netdev
Definition: gdbudp.c:52
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1266
unsigned int reg
Register block.
Definition: intelxl.h:774
static int intelxl_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: intelxl.c:737
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:610
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
unsigned int pf
Physical function number.
Definition: intelxl.h:919
static int intelxl_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: intelxl.c:527
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:630
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS
Clear disable.
Definition: intelxl.h:632
unsigned int base
Absolute queue number base.
Definition: intelxl.h:921
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:762
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_QXX_CTL
Queue Control Register (offset)
Definition: intelxl.h:647
#define INTELXL_QTX_HEAD(x)
Global Transmit Queue Head register.
Definition: intelxl.h:623
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:712

References intelxl_nic::base, ETH_HLEN, intelxl_admin_autoneg(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_write(), INTELXL_ALIGN, intelxl_create_ring(), intelxl_destroy_ring(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_QTX_HEAD, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, INTELXL_QXX_CTL, INTELXL_QXX_CTL_PFVF_PF_INDX, INTELXL_QXX_CTL_PFVF_Q_PF, intelxl_refill_rx(), intelxl_nic::mfs, net_device::mtu, netdev, intelxl_nic::pf, net_device::priv, queue, intelxl_nic::queue, rc, intelxl_ring::reg, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_close()

static void intelxl_close ( struct net_device netdev)
static

Close network device.

Parameters
netdevNetwork device

Definition at line 1459 of file intelxl.c.

1459  {
1460  struct intelxl_nic *intelxl = netdev->priv;
1461  unsigned int queue;
1462 
1463  /* Dump contexts (for debugging) */
1465  sizeof ( struct intelxl_context_tx ) );
1467  sizeof ( struct intelxl_context_rx ) );
1468 
1469  /* Pre-disable transmit queue */
1470  queue = ( intelxl->base + intelxl->queue );
1473  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1475 
1476  /* Destroy transmit descriptor ring */
1477  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1478 
1479  /* Destroy receive descriptor ring */
1480  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1481 
1482  /* Discard any unused receive buffers */
1483  intelxl_empty_rx ( intelxl );
1484 }
Receive queue context.
Definition: intelxl.h:568
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:626
void * regs
Registers.
Definition: intelxl.h:912
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1300
static void intelxl_context_dump(struct intelxl_nic *intelxl, uint32_t op, size_t len)
Dump queue context (for debugging)
Definition: intelxl.c:1012
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:627
unsigned int queue
Queue number.
Definition: intelxl.h:925
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:513
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:515
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
void * priv
Driver private data.
Definition: netdevice.h:432
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:610
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:630
unsigned int base
Absolute queue number base.
Definition: intelxl.h:921
uint16_t queue
Queue ID.
Definition: ena.h:22
Transmit queue context.
Definition: intelxl.h:536
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1367

References intelxl_nic::base, intelxl_context_dump(), intelxl_destroy_ring(), intelxl_empty_rx(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, netdev, net_device::priv, queue, intelxl_nic::queue, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_transmit()

int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 1493 of file intelxl.c.

1493  {
1494  struct intelxl_nic *intelxl = netdev->priv;
1496  unsigned int tx_idx;
1497  unsigned int tx_tail;
1498  size_t len;
1499 
1500  /* Get next transmit descriptor */
1501  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1502  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1503  intelxl );
1504  return -ENOBUFS;
1505  }
1506  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1507  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1508  tx = &intelxl->tx.desc.tx[tx_idx].data;
1509 
1510  /* Populate transmit descriptor */
1511  len = iob_len ( iobuf );
1512  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1513  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1516  wmb();
1517 
1518  /* Notify card that there are packets ready to transmit */
1519  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1520 
1521  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1522  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1523  ( virt_to_phys ( iobuf->data ) + len ) );
1524  return 0;
1525 }
void * regs
Registers.
Definition: intelxl.h:912
wmb()
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:670
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:667
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:769
#define cpu_to_le64(value)
Definition: byteswap.h:109
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:760
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:686
unsigned int cons
Consumer index.
Definition: intelxl.h:771
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:704
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
void * priv
Driver private data.
Definition: netdevice.h:432
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:268
union intelxl_ring::@79 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:673
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:160
Transmit data descriptor.
Definition: intelxl.h:657
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:683
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
#define ENOBUFS
No buffer space available.
Definition: errno.h:499
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:53
unsigned int tail
Tail register.
Definition: intelxl.h:776
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:812
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_dma(), iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, wmb(), and writel().

◆ intelxl_poll_tx()

static void intelxl_poll_tx ( struct net_device netdev)
static

Poll for completed packets.

Parameters
netdevNetwork device

Definition at line 1532 of file intelxl.c.

1532  {
1533  struct intelxl_nic *intelxl = netdev->priv;
1534  struct intelxl_tx_writeback_descriptor *tx_wb;
1535  unsigned int tx_idx;
1536 
1537  /* Check for completed packets */
1538  while ( intelxl->tx.cons != intelxl->tx.prod ) {
1539 
1540  /* Get next transmit descriptor */
1541  tx_idx = ( intelxl->tx.cons % INTELXL_TX_NUM_DESC );
1542  tx_wb = &intelxl->tx.desc.tx[tx_idx].wb;
1543 
1544  /* Stop if descriptor is still in use */
1545  if ( ! ( tx_wb->flags & INTELXL_TX_WB_FL_DD ) )
1546  return;
1547  DBGC2 ( intelxl, "INTELXL %p TX %d complete\n",
1548  intelxl, tx_idx );
1549 
1550  /* Complete TX descriptor */
1552  intelxl->tx.cons++;
1553  }
1554 }
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:779
unsigned int prod
Producer index.
Definition: intelxl.h:769
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:760
unsigned int cons
Consumer index.
Definition: intelxl.h:771
Transmit writeback descriptor.
Definition: intelxl.h:689
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
union intelxl_ring::@79 desc
Descriptors.
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
#define INTELXL_TX_WB_FL_DD
Transmit writeback descriptor complete.
Definition: intelxl.h:699
#define DBGC2(...)
Definition: compiler.h:522
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:706

References intelxl_ring::cons, DBGC2, intelxl_ring::desc, intelxl_tx_writeback_descriptor::flags, INTELXL_TX_NUM_DESC, INTELXL_TX_WB_FL_DD, netdev, netdev_tx_complete_next(), net_device::priv, intelxl_ring::prod, intelxl_ring::tx, intelxl_nic::tx, and intelxl_tx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll_rx()

static void intelxl_poll_rx ( struct net_device netdev)
static

Poll for received packets.

Parameters
netdevNetwork device

Definition at line 1561 of file intelxl.c.

1561  {
1562  struct intelxl_nic *intelxl = netdev->priv;
1563  struct intelxl_rx_writeback_descriptor *rx_wb;
1564  struct io_buffer *iobuf;
1565  unsigned int rx_idx;
1566  unsigned int tag;
1567  size_t len;
1568 
1569  /* Check for received packets */
1570  while ( intelxl->rx.cons != intelxl->rx.prod ) {
1571 
1572  /* Get next receive descriptor */
1573  rx_idx = ( intelxl->rx.cons % INTELXL_RX_NUM_DESC );
1574  rx_wb = &intelxl->rx.desc.rx[rx_idx].wb;
1575 
1576  /* Stop if descriptor is still in use */
1577  if ( ! ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_DD ) ) )
1578  return;
1579 
1580  /* Populate I/O buffer */
1581  iobuf = intelxl->rx_iobuf[rx_idx];
1582  intelxl->rx_iobuf[rx_idx] = NULL;
1583  len = INTELXL_RX_WB_LEN ( le32_to_cpu ( rx_wb->len ) );
1584  iob_put ( iobuf, len );
1585 
1586  /* Find VLAN device, if applicable */
1587  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_VLAN ) ) {
1588  tag = VLAN_TAG ( le16_to_cpu ( rx_wb->vlan ) );
1589  } else {
1590  tag = 0;
1591  }
1592 
1593  /* Hand off to network stack */
1594  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_RXE ) ) {
1595  DBGC ( intelxl, "INTELXL %p RX %d error (length %zd, "
1596  "flags %08x)\n", intelxl, rx_idx, len,
1597  le32_to_cpu ( rx_wb->flags ) );
1598  vlan_netdev_rx_err ( netdev, tag, iobuf, -EIO );
1599  } else {
1600  DBGC2 ( intelxl, "INTELXL %p RX %d complete (length "
1601  "%zd)\n", intelxl, rx_idx, len );
1602  vlan_netdev_rx ( netdev, tag, iobuf );
1603  }
1604  intelxl->rx.cons++;
1605  }
1606 }
#define VLAN_TAG(tci)
Extract VLAN tag from tag control information.
Definition: vlan.h:30
#define iob_put(iobuf, len)
Definition: iobuf.h:125
#define le32_to_cpu(value)
Definition: byteswap.h:114
uint16_t vlan
VLAN tag.
Definition: intelxl.h:724
#define INTELXL_RX_WB_FL_DD
Receive writeback descriptor complete.
Definition: intelxl.h:736
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:769
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:752
unsigned int cons
Consumer index.
Definition: intelxl.h:771
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:954
void * priv
Driver private data.
Definition: netdevice.h:432
ring len
Length.
Definition: dwmac.h:231
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
union intelxl_ring::@79 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:108
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:762
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define le16_to_cpu(value)
Definition: byteswap.h:113
#define INTELXL_RX_WB_LEN(len)
Receive writeback descriptor length.
Definition: intelxl.h:745
__weak void vlan_netdev_rx(struct net_device *netdev, unsigned int tag, struct io_buffer *iobuf)
Add VLAN tag-stripped packet to queue (when VLAN support is not present)
Definition: netdevice.c:1210
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:434
__weak void vlan_netdev_rx_err(struct net_device *netdev, unsigned int tag __unused, struct io_buffer *iobuf, int rc)
Discard received VLAN tag-stripped packet (when VLAN support is not present)
Definition: netdevice.c:1228
Receive writeback descriptor.
Definition: intelxl.h:720
uint64_t tag
Identity tag.
Definition: edd.h:31
#define INTELXL_RX_WB_FL_RXE
Receive writeback descriptor error.
Definition: intelxl.h:742
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
#define INTELXL_RX_WB_FL_VLAN
Receive writeback descriptor VLAN tag present.
Definition: intelxl.h:739
A persistent I/O buffer.
Definition: iobuf.h:38

References intelxl_ring::cons, cpu_to_le32, DBGC, DBGC2, intelxl_ring::desc, EIO, intelxl_rx_writeback_descriptor::flags, INTELXL_RX_NUM_DESC, INTELXL_RX_WB_FL_DD, INTELXL_RX_WB_FL_RXE, INTELXL_RX_WB_FL_VLAN, INTELXL_RX_WB_LEN, iob_put, le16_to_cpu, le32_to_cpu, len, intelxl_rx_writeback_descriptor::len, netdev, NULL, net_device::priv, intelxl_ring::prod, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, tag, intelxl_rx_writeback_descriptor::vlan, vlan_netdev_rx(), vlan_netdev_rx_err(), VLAN_TAG, and intelxl_rx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll()

void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters
netdevNetwork device

Definition at line 1613 of file intelxl.c.

1613  {
1614  struct intelxl_nic *intelxl = netdev->priv;
1615 
1616  /* Poll for completed packets */
1617  intelxl_poll_tx ( netdev );
1618 
1619  /* Poll for received packets */
1620  intelxl_poll_rx ( netdev );
1621 
1622  /* Poll for admin events */
1624 
1625  /* Refill RX ring */
1626  intelxl_refill_rx ( intelxl );
1627 
1628  /* Rearm interrupt, since otherwise receive descriptors will
1629  * be written back only after a complete cacheline (four
1630  * packets) have been received.
1631  *
1632  * There is unfortunately no efficient way to determine
1633  * whether or not rearming the interrupt is necessary. If we
1634  * are running inside a hypervisor (e.g. using a VF or PF as a
1635  * passed-through PCI device), then the MSI-X write is
1636  * redirected by the hypervisor to the real host APIC and the
1637  * host ISR then raises an interrupt within the guest. We
1638  * therefore cannot poll the nominal MSI-X target location to
1639  * watch for the value being written. We could read from the
1640  * INT_DYN_CTL register, but this is even less efficient than
1641  * just unconditionally rearming the interrupt.
1642  */
1643  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1644 }
void * regs
Registers.
Definition: intelxl.h:912
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:838
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1532
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1319
void * priv
Driver private data.
Definition: netdevice.h:432
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:836
unsigned int intr
Interrupt control register.
Definition: intelxl.h:935
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1561

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

◆ intelxl_probe()

static int intelxl_probe ( struct pci_device pci)
static

Probe PCI device.

Parameters
pciPCI device
Return values
rcReturn status code

Definition at line 1667 of file intelxl.c.

1667  {
1668  struct net_device *netdev;
1669  struct intelxl_nic *intelxl;
1670  uint32_t pffunc_rid;
1671  uint32_t pfgen_portnum;
1672  uint32_t pflan_qalloc;
1673  int rc;
1674 
1675  /* Allocate and initialise net device */
1676  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
1677  if ( ! netdev ) {
1678  rc = -ENOMEM;
1679  goto err_alloc;
1680  }
1683  intelxl = netdev->priv;
1684  pci_set_drvdata ( pci, netdev );
1685  netdev->dev = &pci->dev;
1686  memset ( intelxl, 0, sizeof ( *intelxl ) );
1687  intelxl->intr = INTELXL_PFINT_DYN_CTL0;
1688  intelxl->handle = intelxl_admin_event;
1694  sizeof ( intelxl->tx.desc.tx[0] ),
1697  sizeof ( intelxl->rx.desc.rx[0] ),
1699 
1700  /* Fix up PCI device */
1701  adjust_pci_device ( pci );
1702 
1703  /* Map registers */
1704  intelxl->regs = pci_ioremap ( pci, pci->membase, INTELXL_BAR_SIZE );
1705  if ( ! intelxl->regs ) {
1706  rc = -ENODEV;
1707  goto err_ioremap;
1708  }
1709 
1710  /* Configure DMA */
1711  intelxl->dma = &pci->dma;
1712  dma_set_mask_64bit ( intelxl->dma );
1713  netdev->dma = intelxl->dma;
1714 
1715  /* Locate PCI Express capability */
1716  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
1717  if ( ! intelxl->exp ) {
1718  DBGC ( intelxl, "INTELXL %p missing PCIe capability\n",
1719  intelxl );
1720  rc = -ENXIO;
1721  goto err_exp;
1722  }
1723 
1724  /* Reset the function via PCIe FLR */
1725  pci_reset ( pci, intelxl->exp );
1726 
1727  /* Get function number, port number and base queue number */
1728  pffunc_rid = readl ( intelxl->regs + INTELXL_PFFUNC_RID );
1729  intelxl->pf = INTELXL_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
1730  pfgen_portnum = readl ( intelxl->regs + INTELXL_PFGEN_PORTNUM );
1731  intelxl->port = INTELXL_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
1732  pflan_qalloc = readl ( intelxl->regs + INTELXL_PFLAN_QALLOC );
1733  intelxl->base = INTELXL_PFLAN_QALLOC_FIRSTQ ( pflan_qalloc );
1734  DBGC ( intelxl, "INTELXL %p PF %d using port %d queues [%#04x-%#04x]\n",
1735  intelxl, intelxl->pf, intelxl->port, intelxl->base,
1736  INTELXL_PFLAN_QALLOC_LASTQ ( pflan_qalloc ) );
1737 
1738  /* Enable MSI-X dummy interrupt */
1739  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
1740  INTELXL_MSIX_VECTOR ) ) != 0 )
1741  goto err_msix;
1742 
1743  /* Open admin queues */
1744  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
1745  goto err_open_admin;
1746 
1747  /* Get firmware version */
1748  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
1749  goto err_admin_version;
1750 
1751  /* Report driver version */
1752  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
1753  goto err_admin_driver;
1754 
1755  /* Clear PXE mode */
1756  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
1757  goto err_admin_clear_pxe;
1758 
1759  /* Get switch configuration */
1760  if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
1761  goto err_admin_switch;
1762 
1763  /* Get VSI configuration */
1764  if ( ( rc = intelxl_admin_vsi ( intelxl ) ) != 0 )
1765  goto err_admin_vsi;
1766 
1767  /* Configure switch for promiscuous mode */
1768  if ( ( rc = intelxl_admin_promisc ( intelxl ) ) != 0 )
1769  goto err_admin_promisc;
1770 
1771  /* Get MAC address */
1772  if ( ( rc = intelxl_admin_mac_read ( netdev ) ) != 0 )
1773  goto err_admin_mac_read;
1774 
1775  /* Configure queue register addresses */
1776  intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1777  intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1778  intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1779  intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1780 
1781  /* Configure interrupt causes */
1784  intelxl->regs + INTELXL_QINT_TQCTL ( intelxl->queue ) );
1785  writel ( ( INTELXL_QINT_RQCTL_NEXTQ_INDX ( intelxl->queue ) |
1788  intelxl->regs + INTELXL_QINT_RQCTL ( intelxl->queue ) );
1791  intelxl->regs + INTELXL_PFINT_LNKLST0 );
1793  intelxl->regs + INTELXL_PFINT_ICR0_ENA );
1794 
1795  /* Register network device */
1796  if ( ( rc = register_netdev ( netdev ) ) != 0 )
1797  goto err_register_netdev;
1798 
1799  /* Set initial link state */
1801 
1802  return 0;
1803 
1805  err_register_netdev:
1806  err_admin_mac_read:
1807  err_admin_promisc:
1808  err_admin_vsi:
1809  err_admin_switch:
1810  err_admin_clear_pxe:
1811  err_admin_driver:
1812  err_admin_version:
1813  intelxl_close_admin ( intelxl );
1814  err_open_admin:
1815  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1816  err_msix:
1817  pci_reset ( pci, intelxl->exp );
1818  err_exp:
1819  iounmap ( intelxl->regs );
1820  err_ioremap:
1821  netdev_nullify ( netdev );
1822  netdev_put ( netdev );
1823  err_alloc:
1824  return rc;
1825 }
static int intelxl_admin_promisc(struct intelxl_nic *intelxl)
Set VSI promiscuous modes.
Definition: intelxl.c:681
Receive queue context.
Definition: intelxl.h:568
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)
First queue.
Definition: intelxl.h:893
void * regs
Registers.
Definition: intelxl.h:912
#define INTELXL_QRX(x)
Global Receive Queue register block.
Definition: intelxl.h:639
unsigned long membase
Memory base.
Definition: pci.h:220
struct dma_device * dma
DMA device.
Definition: intelxl.h:914
#define INTELXL_PFLAN_QALLOC_LASTQ(x)
Last queue.
Definition: intelxl.h:896
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct dma_device dma
DMA device.
Definition: pci.h:215
#define INTELXL_PFFUNC_RID
Function Requester ID Information Register.
Definition: intelxl.h:886
static int intelxl_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: intelxl.c:593
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:40
#define INTELXL_PFLAN_QALLOC
PF Queue Allocation Register.
Definition: intelxl.h:892
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:39
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)
Queue index.
Definition: intelxl.h:863
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:963
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE
End of list.
Definition: intelxl.h:876
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:37
Admin queue register offsets.
Definition: intelxl.h:64
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:561
#define INTELXL_PFINT_ICR0_ENA
PF Interrupt Zero Cause Enablement Register.
Definition: intelxl.h:858
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:467
struct dma_device * dma
DMA device.
Definition: netdevice.h:367
static int intelxl_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: intelxl.c:479
#define INTELXL_PFINT_ICR0_ENA_ADMINQ
Admin event.
Definition: intelxl.h:859
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: intelxl.h:902
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:877
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:89
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:760
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:241
struct device dev
Generic device.
Definition: pci.h:213
unsigned int queue
Queue number.
Definition: intelxl.h:925
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:937
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:519
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:366
#define ENOMEM
Not enough space.
Definition: errno.h:535
#define INTELXL_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: intelxl.h:901
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:476
#define INTELXL_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:883
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX
Receive queue.
Definition: intelxl.h:852
#define INTELXL_PFINT_DYN_CTL0
PF Interrupt Zero Dynamic Control Register.
Definition: intelxl.h:837
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:827
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:576
static void intelxl_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
Handle admin event.
Definition: intelxl.c:797
#define INTELXL_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:871
Admin queue version number.
Definition: intelxl.h:91
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX
Transmit queue.
Definition: intelxl.h:869
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
void * priv
Driver private data.
Definition: netdevice.h:432
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
union intelxl_ring::@79 desc
Descriptors.
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:942
unsigned int reg
Register block.
Definition: intelxl.h:774
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:762
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:760
unsigned int intr
Interrupt control register.
Definition: intelxl.h:935
A network device.
Definition: netdevice.h:353
#define INTELXL_QTX(x)
Global Transmit Queue register block.
Definition: intelxl.h:636
#define ENODEV
No such device.
Definition: errno.h:510
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:532
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:91
unsigned int port
Port number.
Definition: intelxl.h:923
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define INTELXL_PFINT_LNKLST0
PF Interrupt Zero Linked List Register.
Definition: intelxl.h:843
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:796
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:98
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:907
struct device * dev
Underlying hardware device.
Definition: netdevice.h:365
#define INTELXL_QINT_TQCTL(x)
Transmit Queue Interrupt Cause Control Register.
Definition: intelxl.h:874
unsigned int pf
Physical function number.
Definition: intelxl.h:919
#define ENXIO
No such device or address.
Definition: errno.h:600
#define INTELXL_QXX_TAIL
Queue Tail Pointer Register (offset)
Definition: intelxl.h:654
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)
Queue index.
Definition: intelxl.h:844
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:265
unsigned int base
Absolute queue number base.
Definition: intelxl.h:921
void iounmap(volatile const void *io_addr)
Unmap I/O address.
unsigned int tail
Tail register.
Definition: intelxl.h:776
#define INTELXL_QINT_RQCTL(x)
Receive Queue Interrupt Cause Control Register.
Definition: intelxl.h:862
#define INTELXL_BAR_SIZE
BAR size.
Definition: intelxl.h:21
static int intelxl_admin_vsi(struct intelxl_nic *intelxl)
Get VSI parameters.
Definition: intelxl.c:647
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:410
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:929
static struct net_device_operations intelxl_operations
Network device operations.
Definition: intelxl.c:1647
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: intelxl.h:887
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:762
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:424
Transmit queue context.
Definition: intelxl.h:536
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:63

References adjust_pci_device(), alloc_etherdev(), intelxl_nic::base, intelxl_nic::command, DBGC, intelxl_ring::desc, pci_device::dev, net_device::dev, pci_device::dma, net_device::dma, intelxl_nic::dma, dma_set_mask_64bit(), ENODEV, ENOMEM, ENXIO, intelxl_nic::event, intelxl_nic::exp, intelxl_nic::handle, intelxl_admin_clear_pxe(), INTELXL_ADMIN_CMD, intelxl_admin_driver(), intelxl_admin_event(), INTELXL_ADMIN_EVT, intelxl_admin_link(), intelxl_admin_mac_read(), intelxl_admin_promisc(), intelxl_admin_switch(), intelxl_admin_vsi(), INTELXL_BAR_SIZE, intelxl_close_admin(), intelxl_init_admin(), intelxl_init_ring(), INTELXL_MAX_PKT_LEN, intelxl_msix_disable(), intelxl_msix_enable(), INTELXL_MSIX_VECTOR, intelxl_open_admin(), intelxl_operations, INTELXL_PFFUNC_RID, INTELXL_PFFUNC_RID_FUNC_NUM, INTELXL_PFGEN_PORTNUM, INTELXL_PFGEN_PORTNUM_PORT_NUM, INTELXL_PFINT_DYN_CTL0, INTELXL_PFINT_ICR0_ENA, INTELXL_PFINT_ICR0_ENA_ADMINQ, INTELXL_PFINT_LNKLST0, INTELXL_PFINT_LNKLST0_FIRSTQ_INDX, INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX, INTELXL_PFLAN_QALLOC, INTELXL_PFLAN_QALLOC_FIRSTQ, INTELXL_PFLAN_QALLOC_LASTQ, INTELXL_QINT_RQCTL, INTELXL_QINT_RQCTL_CAUSE_ENA, INTELXL_QINT_RQCTL_NEXTQ_INDX, INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX, INTELXL_QINT_TQCTL, INTELXL_QINT_TQCTL_CAUSE_ENA, INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE, INTELXL_QRX, INTELXL_QTX, INTELXL_QXX_TAIL, INTELXL_RX_NUM_DESC, INTELXL_TX_NUM_DESC, intelxl_nic::intr, iounmap(), net_device::max_pkt_len, pci_device::membase, memset(), netdev, netdev_init(), netdev_nullify(), netdev_put(), PCI_CAP_ID_EXP, pci_find_capability(), pci_ioremap(), pci_reset(), pci_set_drvdata(), intelxl_nic::pf, intelxl_nic::port, net_device::priv, intelxl_nic::queue, rc, readl(), intelxl_ring::reg, register_netdev(), intelxl_nic::regs, intelxl_ring::rx, intelxl_nic::rx, intelxl_ring::tail, intelxl_ring::tx, intelxl_nic::tx, unregister_netdev(), and writel().

◆ intelxl_remove()

static void intelxl_remove ( struct pci_device pci)
static

Remove PCI device.

Parameters
pciPCI device

Definition at line 1832 of file intelxl.c.

1832  {
1833  struct net_device *netdev = pci_get_drvdata ( pci );
1834  struct intelxl_nic *intelxl = netdev->priv;
1835 
1836  /* Unregister network device */
1838 
1839  /* Close admin queues */
1840  intelxl_close_admin ( intelxl );
1841 
1842  /* Disable MSI-X dummy interrupt */
1843  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1844 
1845  /* Reset the NIC */
1846  pci_reset ( pci, intelxl->exp );
1847 
1848  /* Free network device */
1849  iounmap ( intelxl->regs );
1850  netdev_nullify ( netdev );
1851  netdev_put ( netdev );
1852 }
void * regs
Registers.
Definition: intelxl.h:912
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:89
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:937
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:576
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:942
A network device.
Definition: netdevice.h:353
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:532
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:91
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:907
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:376
void iounmap(volatile const void *io_addr)
Unmap I/O address.
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:929

References intelxl_nic::exp, intelxl_close_admin(), intelxl_msix_disable(), INTELXL_MSIX_VECTOR, iounmap(), netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), pci_reset(), net_device::priv, intelxl_nic::regs, and unregister_netdev().

Variable Documentation

◆ intelxl_admin_offsets

Initial value:
= {
}
#define INTELXL_ADMIN_BAH
Admin Queue Base Address High Register (offset)
Definition: intelxl.h:46
#define INTELXL_ADMIN_BAL
Admin Queue Base Address Low Register (offset)
Definition: intelxl.h:43
#define INTELXL_ADMIN_TAIL
Admin Queue Tail Register (offset)
Definition: intelxl.h:57
#define INTELXL_ADMIN_LEN
Admin Queue Length Register (offset)
Definition: intelxl.h:49
#define INTELXL_ADMIN_HEAD
Admin Queue Head Register (offset)
Definition: intelxl.h:54

Admin queue register offsets.

Definition at line 109 of file intelxl.c.

◆ intelxl_operations

struct net_device_operations intelxl_operations
static
Initial value:
= {
.open = intelxl_open,
.close = intelxl_close,
.transmit = intelxl_transmit,
.poll = intelxl_poll,
}
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1493
static int intelxl_open(struct net_device *netdev)
Open network device.
Definition: intelxl.c:1391
static void intelxl_close(struct net_device *netdev)
Close network device.
Definition: intelxl.c:1459
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1613

Network device operations.

Definition at line 1647 of file intelxl.c.

Referenced by intelxl_probe().

◆ intelxl_nics

struct pci_device_id intelxl_nics[]
static
Initial value:
= {
PCI_ROM ( 0x8086, 0x0cf8, "x710-n3000", "X710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x0d58, "xxv710-n3000", "XXV710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x104e, "x710-sfp-b", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x104f, "x710-kx-b", "X710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1572, "x710-sfp", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x1574, "xl710-qemu", "Virtual XL710", 0 ),
PCI_ROM ( 0x8086, 0x1580, "xl710-kx-b", "XL710 40GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1581, "xl710-kx-c", "XL710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1583, "xl710-qda2", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1584, "xl710-qda1", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1585, "x710-qsfp", "X710 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1586, "x710-10gt", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x1587, "x710-kr2", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1588, "x710-kr2-a", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1589, "x710-10gt4", "X710 10GBASE-T4", 0 ),
PCI_ROM ( 0x8086, 0x158a, "xxv710", "XXV710 25GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x158b, "xxv710-sfp28", "XXV710 25GbE SFP28", 0 ),
PCI_ROM ( 0x8086, 0x15ff, "x710-10gt-b", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37ce, "x722-kx", "X722 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x37cf, "x722-qsfp", "X722 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d0, "x722-sfp", "X722 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d1, "x722-1gt", "X722 1GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d2, "x722-10gt", "X722 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d3, "x722-sfp-i", "X722 10GbE SFP+", 0 ),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:308

PCI device IDs.

Definition at line 1855 of file intelxl.c.

◆ __pci_driver

struct pci_driver intelxl_driver __pci_driver
Initial value:
= {
.ids = intelxl_nics,
.id_count = ( sizeof ( intelxl_nics ) / sizeof ( intelxl_nics[0] ) ),
.probe = intelxl_probe,
}
static struct pci_device_id intelxl_nics[]
PCI device IDs.
Definition: intelxl.c:1855
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static int intelxl_probe(struct pci_device *pci)
Probe PCI device.
Definition: intelxl.c:1667
static void intelxl_remove(struct pci_device *pci)
Remove PCI device.
Definition: intelxl.c:1832

PCI driver.

Definition at line 1883 of file intelxl.c.