iPXE
Functions | Variables
intelxl.c File Reference

Intel 40 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/vlan.h>
#include <ipxe/iobuf.h>
#include <ipxe/pci.h>
#include <ipxe/version.h>
#include "intelxl.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
int intelxl_msix_enable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Enable MSI-X dummy interrupt. More...
 
void intelxl_msix_disable (struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
 Disable MSI-X dummy interrupt. More...
 
static int intelxl_alloc_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Allocate admin queue. More...
 
static void intelxl_enable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Enable admin queue. More...
 
static void intelxl_disable_admin (struct intelxl_nic *intelxl, struct intelxl_admin *admin)
 Disable admin queue. More...
 
static void intelxl_free_admin (struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
 Free admin queue. More...
 
struct intelxl_admin_descriptorintelxl_admin_command_descriptor (struct intelxl_nic *intelxl)
 Get next admin command queue descriptor. More...
 
union intelxl_admin_bufferintelxl_admin_command_buffer (struct intelxl_nic *intelxl)
 Get next admin command queue data buffer. More...
 
static void intelxl_admin_event_init (struct intelxl_nic *intelxl, unsigned int index)
 Initialise admin event queue descriptor. More...
 
int intelxl_admin_command (struct intelxl_nic *intelxl)
 Issue admin queue command. More...
 
static int intelxl_admin_version (struct intelxl_nic *intelxl)
 Get firmware version. More...
 
static int intelxl_admin_driver (struct intelxl_nic *intelxl)
 Report driver version. More...
 
static int intelxl_admin_shutdown (struct intelxl_nic *intelxl)
 Shutdown admin queues. More...
 
static int intelxl_admin_mac_read (struct net_device *netdev)
 Get MAC address. More...
 
static int intelxl_admin_mac_write (struct net_device *netdev)
 Set MAC address. More...
 
int intelxl_admin_clear_pxe (struct intelxl_nic *intelxl)
 Clear PXE mode. More...
 
static int intelxl_admin_switch (struct intelxl_nic *intelxl)
 Get switch configuration. More...
 
static int intelxl_admin_vsi (struct intelxl_nic *intelxl)
 Get VSI parameters. More...
 
static int intelxl_admin_promisc (struct intelxl_nic *intelxl)
 Set VSI promiscuous modes. More...
 
int intelxl_admin_mac_config (struct intelxl_nic *intelxl)
 Set MAC configuration. More...
 
static int intelxl_admin_autoneg (struct intelxl_nic *intelxl)
 Restart autonegotiation. More...
 
static int intelxl_admin_link (struct net_device *netdev)
 Get link status. More...
 
static void intelxl_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
 Handle admin event. More...
 
static void intelxl_refill_admin (struct intelxl_nic *intelxl)
 Refill admin event queue. More...
 
void intelxl_poll_admin (struct net_device *netdev)
 Poll admin event queue. More...
 
int intelxl_open_admin (struct intelxl_nic *intelxl)
 Open admin queues. More...
 
void intelxl_reopen_admin (struct intelxl_nic *intelxl)
 Reopen admin queues (after virtual function reset) More...
 
void intelxl_close_admin (struct intelxl_nic *intelxl)
 Close admin queues. More...
 
int intelxl_alloc_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Allocate descriptor ring. More...
 
void intelxl_free_ring (struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
 Free descriptor ring. More...
 
static void intelxl_context_dump (struct intelxl_nic *intelxl, uint32_t op, size_t len)
 Dump queue context (for debugging) More...
 
static int intelxl_context_line (struct intelxl_nic *intelxl, struct intelxl_context_line *line, unsigned int index, uint32_t op)
 Program queue context line. More...
 
static int intelxl_context (struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
 Program queue context. More...
 
static int intelxl_context_tx (struct intelxl_nic *intelxl, physaddr_t address)
 Program transmit queue context. More...
 
static int intelxl_context_rx (struct intelxl_nic *intelxl, physaddr_t address)
 Program receive queue context. More...
 
static int intelxl_enable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Enable descriptor ring. More...
 
static int intelxl_disable_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Disable descriptor ring. More...
 
int intelxl_create_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Create descriptor ring. More...
 
void intelxl_destroy_ring (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Destroy descriptor ring. More...
 
static void intelxl_refill_rx (struct intelxl_nic *intelxl)
 Refill receive descriptor ring. More...
 
void intelxl_empty_rx (struct intelxl_nic *intelxl)
 Discard unused receive I/O buffers. More...
 
static int intelxl_open (struct net_device *netdev)
 Open network device. More...
 
static void intelxl_close (struct net_device *netdev)
 Close network device. More...
 
int intelxl_transmit (struct net_device *netdev, struct io_buffer *iobuf)
 Transmit packet. More...
 
static void intelxl_poll_tx (struct net_device *netdev)
 Poll for completed packets. More...
 
static void intelxl_poll_rx (struct net_device *netdev)
 Poll for received packets. More...
 
void intelxl_poll (struct net_device *netdev)
 Poll for completed and received packets. More...
 
static int intelxl_probe (struct pci_device *pci)
 Probe PCI device. More...
 
static void intelxl_remove (struct pci_device *pci)
 Remove PCI device. More...
 

Variables

const struct intelxl_admin_offsets intelxl_admin_offsets
 Admin queue register offsets. More...
 
static struct net_device_operations intelxl_operations
 Network device operations. More...
 
static struct pci_device_id intelxl_nics []
 PCI device IDs. More...
 
struct pci_driver intelxl_driver __pci_driver
 PCI driver. More...
 

Detailed Description

Intel 40 Gigabit Ethernet network card driver.

Definition in file intelxl.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ intelxl_msix_enable()

int intelxl_msix_enable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Enable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector
Return values
rcReturn status code

Definition at line 62 of file intelxl.c.

63  {
64  int rc;
65 
66  /* Enable MSI-X capability */
67  if ( ( rc = pci_msix_enable ( pci, &intelxl->msix ) ) != 0 ) {
68  DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
69  intelxl, strerror ( rc ) );
70  goto err_enable;
71  }
72 
73  /* Enable dummy interrupt */
74  pci_msix_unmask ( &intelxl->msix, vector );
75 
76  return 0;
77 
78  pci_msix_disable ( pci, &intelxl->msix );
79  err_enable:
80  return rc;
81 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:207
uint32_t vector
MSI-X vector.
Definition: ena.h:20
#define DBGC(...)
Definition: compiler.h:505
static void pci_msix_unmask(struct pci_msix *msix, unsigned int vector)
Unmask MSI-X interrupt vector.
Definition: pcimsix.h:76
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
struct pci_msix msix
MSI-X interrupt.
Definition: intelxl.h:938
int pci_msix_enable(struct pci_device *pci, struct pci_msix *msix)
Enable MSI-X interrupts.
Definition: pcimsix.c:136

References DBGC, intelxl_nic::msix, pci_msix_disable(), pci_msix_enable(), pci_msix_unmask(), rc, strerror(), and vector.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_msix_disable()

void intelxl_msix_disable ( struct intelxl_nic intelxl,
struct pci_device pci,
unsigned int  vector 
)

Disable MSI-X dummy interrupt.

Parameters
intelxlIntel device
pciPCI device
vectorMSI-X vector

Definition at line 90 of file intelxl.c.

91  {
92 
93  /* Disable dummy interrupts */
94  pci_msix_mask ( &intelxl->msix, vector );
95 
96  /* Disable MSI-X capability */
97  pci_msix_disable ( pci, &intelxl->msix );
98 }
void pci_msix_disable(struct pci_device *pci, struct pci_msix *msix)
Disable MSI-X interrupts.
Definition: pcimsix.c:207
uint32_t vector
MSI-X vector.
Definition: ena.h:20
static void pci_msix_mask(struct pci_msix *msix, unsigned int vector)
Mask MSI-X interrupt vector.
Definition: pcimsix.h:64
struct pci_msix msix
MSI-X interrupt.
Definition: intelxl.h:938

References intelxl_nic::msix, pci_msix_disable(), pci_msix_mask(), and vector.

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_admin()

static int intelxl_alloc_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Allocate admin queue.

Parameters
intelxlIntel device
adminAdmin queue
Return values
rcReturn status code

Definition at line 123 of file intelxl.c.

124  {
125  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
126  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
127 
128  /* Allocate admin queue */
129  admin->buf = dma_alloc ( intelxl->dma, &admin->map, ( buf_len + len ),
130  INTELXL_ALIGN );
131  if ( ! admin->buf )
132  return -ENOMEM;
133  admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
134 
135  DBGC ( intelxl, "INTELXL %p A%cQ is at [%08lx,%08lx) buf "
136  "[%08lx,%08lx)\n", intelxl,
137  ( ( admin == &intelxl->command ) ? 'T' : 'R' ),
138  virt_to_phys ( admin->desc ),
139  ( virt_to_phys ( admin->desc ) + len ),
140  virt_to_phys ( admin->buf ),
141  ( virt_to_phys ( admin->buf ) + buf_len ) );
142  return 0;
143 }
struct dma_device * dma
DMA device.
Definition: intelxl.h:913
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define ENOMEM
Not enough space.
Definition: errno.h:534
ring len
Length.
Definition: dwmac.h:231
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.

References intelxl_admin::buf, intelxl_nic::command, DBGC, intelxl_admin::desc, intelxl_nic::dma, dma_alloc(), ENOMEM, INTELXL_ADMIN_NUM_DESC, INTELXL_ALIGN, len, and intelxl_admin::map.

Referenced by intelxl_open_admin().

◆ intelxl_enable_admin()

static void intelxl_enable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Enable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 151 of file intelxl.c.

152  {
153  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
154  const struct intelxl_admin_offsets *regs = admin->regs;
155  void *admin_regs = ( intelxl->regs + admin->base );
157 
158  /* Initialise admin queue */
159  memset ( admin->desc, 0, len );
160 
161  /* Reset head and tail registers */
162  writel ( 0, admin_regs + regs->head );
163  writel ( 0, admin_regs + regs->tail );
164 
165  /* Reset queue index */
166  admin->index = 0;
167 
168  /* Program queue address */
169  address = dma ( &admin->map, admin->desc );
170  writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
171  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
172  writel ( ( ( ( uint64_t ) address ) >> 32 ),
173  admin_regs + regs->bah );
174  } else {
175  writel ( 0, admin_regs + regs->bah );
176  }
177 
178  /* Program queue length and enable queue */
181  admin_regs + regs->len );
182 }
void * regs
Registers.
Definition: intelxl.h:911
#define INTELXL_ADMIN_LEN_ENABLE
Queue enable.
Definition: intelxl.h:50
Admin queue register offsets.
Definition: intelxl.h:63
uint64_t address
Base address.
Definition: ena.h:24
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:462
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_ADMIN_LEN_LEN(x)
Queue length.
Definition: intelxl.h:49
struct i386_regs regs
Definition: registers.h:15
unsigned long physaddr_t
Definition: stdint.h:20
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
void * memset(void *dest, int character, size_t len) __nonnull

References address, intelxl_admin::base, intelxl_admin::desc, dma(), intelxl_admin::index, INTELXL_ADMIN_LEN_ENABLE, INTELXL_ADMIN_LEN_LEN, INTELXL_ADMIN_NUM_DESC, len, intelxl_admin::map, memset(), regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_reopen_admin().

◆ intelxl_disable_admin()

static void intelxl_disable_admin ( struct intelxl_nic intelxl,
struct intelxl_admin admin 
)
static

Disable admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 190 of file intelxl.c.

191  {
192  const struct intelxl_admin_offsets *regs = admin->regs;
193  void *admin_regs = ( intelxl->regs + admin->base );
194 
195  /* Disable queue */
196  writel ( 0, admin_regs + regs->len );
197 }
void * regs
Registers.
Definition: intelxl.h:911
Admin queue register offsets.
Definition: intelxl.h:63
unsigned int base
Register block base.
Definition: intelxl.h:462
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464

References intelxl_admin::base, regs, intelxl_admin::regs, intelxl_nic::regs, and writel().

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_free_admin()

static void intelxl_free_admin ( struct intelxl_nic *intelxl  __unused,
struct intelxl_admin admin 
)
static

Free admin queue.

Parameters
intelxlIntel device
adminAdmin queue

Definition at line 205 of file intelxl.c.

206  {
207  size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
208  size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
209 
210  /* Free queue */
211  dma_free ( &admin->map, admin->buf, ( buf_len + len ) );
212 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
ring len
Length.
Definition: dwmac.h:231
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453

References intelxl_admin::buf, intelxl_admin::desc, dma_free(), INTELXL_ADMIN_NUM_DESC, len, and intelxl_admin::map.

Referenced by intelxl_close_admin(), and intelxl_open_admin().

◆ intelxl_admin_command_descriptor()

struct intelxl_admin_descriptor* intelxl_admin_command_descriptor ( struct intelxl_nic intelxl)

Get next admin command queue descriptor.

Parameters
intelxlIntel device
Return values
cmdCommand descriptor

Definition at line 221 of file intelxl.c.

221  {
222  struct intelxl_admin *admin = &intelxl->command;
224 
225  /* Get and initialise next descriptor */
226  cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
227  memset ( cmd, 0, sizeof ( *cmd ) );
228  return cmd;
229 }
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
Admin queue descriptor.
Definition: intelxl.h:415
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
void * memset(void *dest, int character, size_t len) __nonnull

References cmd, intelxl_nic::command, intelxl_admin::desc, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_descriptor(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), and intelxlvf_admin_command_descriptor().

◆ intelxl_admin_command_buffer()

union intelxl_admin_buffer* intelxl_admin_command_buffer ( struct intelxl_nic intelxl)

Get next admin command queue data buffer.

Parameters
intelxlIntel device
Return values
bufData buffer

Definition at line 238 of file intelxl.c.

238  {
239  struct intelxl_admin *admin = &intelxl->command;
240  union intelxl_admin_buffer *buf;
241 
242  /* Get next data buffer */
243  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
244  memset ( buf, 0, sizeof ( *buf ) );
245  return buf;
246 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
Admin queue data buffer.
Definition: intelxl.h:401
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_admin::buf, intelxl_nic::command, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, and memset().

Referenced by ice_admin_command_buffer(), intelxl_admin_driver(), intelxl_admin_mac_read(), intelxl_admin_switch(), intelxl_admin_vsi(), and intelxlvf_admin_command_buffer().

◆ intelxl_admin_event_init()

static void intelxl_admin_event_init ( struct intelxl_nic intelxl,
unsigned int  index 
)
static

Initialise admin event queue descriptor.

Parameters
intelxlIntel device
indexEvent queue index

Definition at line 254 of file intelxl.c.

255  {
256  struct intelxl_admin *admin = &intelxl->event;
257  struct intelxl_admin_descriptor *evt;
258  union intelxl_admin_buffer *buf;
260 
261  /* Initialise descriptor */
262  evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
263  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
264  address = dma ( &admin->map, buf );
266  evt->len = cpu_to_le16 ( sizeof ( *buf ) );
267  evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
268  evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
269 }
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:451
long index
Definition: bigint.h:62
uint16_t flags
Flags.
Definition: intelxl.h:417
unsigned long long uint64_t
Definition: stdint.h:13
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
uint16_t len
Data length.
Definition: intelxl.h:421
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define cpu_to_le32(value)
Definition: byteswap.h:107
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
union intelxl_admin_params params
Parameters.
Definition: intelxl.h:429
uint32_t high
Buffer address high.
Definition: intelxl.h:81
Admin queue descriptor.
Definition: intelxl.h:415
uint32_t low
Buffer address low.
Definition: intelxl.h:83
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin_buffer_params buffer
Additional data buffer command parameters.
Definition: intelxl.h:370
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Admin queue data buffer.
Definition: intelxl.h:401

References address, intelxl_admin::buf, intelxl_admin_params::buffer, cpu_to_le16, cpu_to_le32, intelxl_admin::desc, dma(), intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_admin_buffer_params::high, index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_NUM_DESC, intelxl_admin_descriptor::len, intelxl_admin_buffer_params::low, intelxl_admin::map, and intelxl_admin_descriptor::params.

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_admin_command()

int intelxl_admin_command ( struct intelxl_nic intelxl)

Issue admin queue command.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 277 of file intelxl.c.

277  {
278  struct intelxl_admin *admin = &intelxl->command;
279  const struct intelxl_admin_offsets *regs = admin->regs;
280  void *admin_regs = ( intelxl->regs + admin->base );
282  union intelxl_admin_buffer *buf;
284  uint32_t cookie;
285  uint16_t silence;
286  unsigned int index;
287  unsigned int tail;
288  unsigned int i;
289  int rc;
290 
291  /* Get next queue entry */
292  index = admin->index++;
293  tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
294  cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
295  buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
296  DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
297  intelxl, index, le16_to_cpu ( cmd->opcode ) );
298  if ( cmd->cookie )
299  DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->cookie ) );
300  DBGC2 ( intelxl, ":\n" );
301 
302  /* Allow expected errors to be silenced */
303  silence = cmd->ret;
304  cmd->ret = 0;
305 
306  /* Sanity checks */
307  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
308  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
309  assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
310 
311  /* Populate data buffer address if applicable */
312  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
313  address = dma ( &admin->map, buf );
314  cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
315  cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
316  }
317 
318  /* Populate cookie, if not being (ab)used for VF opcode */
319  if ( ! cmd->cookie )
320  cmd->cookie = cpu_to_le32 ( index );
321 
322  /* Record cookie */
323  cookie = cmd->cookie;
324 
325  /* Post command descriptor */
326  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
327  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_RD ) ) {
328  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
329  le16_to_cpu ( cmd->len ) );
330  }
331  wmb();
332  writel ( tail, admin_regs + regs->tail );
333 
334  /* Wait for completion */
335  for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
336 
337  /* If response is not complete, delay 1ms and retry */
338  if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
339  mdelay ( 1 );
340  continue;
341  }
342  DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
343  intelxl, index );
344  DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
345  sizeof ( *cmd ) );
346  if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
347  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
348  le16_to_cpu ( cmd->len ) );
349  }
350 
351  /* Check for cookie mismatch */
352  if ( cmd->cookie != cookie ) {
353  DBGC ( intelxl, "INTELXL %p admin command %#x bad "
354  "cookie %#x\n", intelxl, index,
355  le32_to_cpu ( cmd->cookie ) );
356  rc = -EPROTO;
357  goto err;
358  }
359 
360  /* Check for unexpected errors */
361  if ( ( cmd->ret != 0 ) && ( cmd->ret != silence ) ) {
362  DBGC ( intelxl, "INTELXL %p admin command %#x error "
363  "%d\n", intelxl, index,
364  le16_to_cpu ( cmd->ret ) );
365  rc = -EIO;
366  goto err;
367  }
368 
369  /* Success */
370  return 0;
371  }
372 
373  rc = -ETIMEDOUT;
374  DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
375  intelxl, index );
376  err:
377  DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
378  return rc;
379 }
void * regs
Registers.
Definition: intelxl.h:911
#define INTELXL_ADMIN_FL_ERR
Admin descriptor completed in error.
Definition: intelxl.h:439
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define le32_to_cpu(value)
Definition: byteswap.h:113
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue register offsets.
Definition: intelxl.h:63
uint64_t address
Base address.
Definition: ena.h:24
Admin queue.
Definition: intelxl.h:451
#define DBGC(...)
Definition: compiler.h:505
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
long index
Definition: bigint.h:62
unsigned long long uint64_t
Definition: stdint.h:13
unsigned int base
Register block base.
Definition: intelxl.h:462
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
#define INTELXL_ADMIN_FL_CMP
Admin descriptor contains a completion.
Definition: intelxl.h:436
unsigned int index
Queue index.
Definition: intelxl.h:459
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define DBGC_HDA(...)
Definition: compiler.h:506
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct dma_mapping map
DMA mapping.
Definition: intelxl.h:457
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define EPROTO
Protocol error.
Definition: errno.h:624
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
struct i386_regs regs
Definition: registers.h:15
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
#define cpu_to_le16(value)
Definition: byteswap.h:106
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_MAX_WAIT_MS
Maximum time to wait for an admin request to complete.
Definition: intelxl.h:486
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Admin queue data buffer.
Definition: intelxl.h:401

References address, assert(), intelxl_admin::base, intelxl_admin::buf, cmd, intelxl_nic::command, cpu_to_le16, cpu_to_le32, DBGC, DBGC2, DBGC2_HDA, DBGC_HDA, intelxl_admin::desc, dma(), EIO, EPROTO, ETIMEDOUT, index, intelxl_admin::index, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_CMP, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_FL_ERR, INTELXL_ADMIN_FL_RD, INTELXL_ADMIN_MAX_WAIT_MS, INTELXL_ADMIN_NUM_DESC, le16_to_cpu, le32_to_cpu, intelxl_admin::map, mdelay(), rc, regs, intelxl_admin::regs, intelxl_nic::regs, wmb(), and writel().

Referenced by ice_admin_add_txq(), ice_admin_autoneg(), ice_admin_disable_txq(), ice_admin_link(), ice_admin_mac_read(), ice_admin_mac_write(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ice_admin_version(), intelxl_admin_autoneg(), intelxl_admin_clear_pxe(), intelxl_admin_driver(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_read(), intelxl_admin_mac_write(), intelxl_admin_promisc(), intelxl_admin_shutdown(), intelxl_admin_switch(), intelxl_admin_version(), intelxl_admin_vsi(), intelxlvf_admin_command(), intelxlvf_admin_request_qps(), and intelxlvf_reset_admin().

◆ intelxl_admin_version()

static int intelxl_admin_version ( struct intelxl_nic intelxl)
static

Get firmware version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 387 of file intelxl.c.

387  {
390  unsigned int api;
391  int rc;
392 
393  /* Populate descriptor */
395  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
396  version = &cmd->params.version;
397 
398  /* Issue command */
399  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
400  return rc;
401  api = le16_to_cpu ( version->api.major );
402  DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
403  intelxl, le16_to_cpu ( version->firmware.major ),
404  le16_to_cpu ( version->firmware.minor ),
405  api, le16_to_cpu ( version->api.minor ) );
406 
407  /* Check for API compatibility */
408  if ( api > INTELXL_ADMIN_API_MAJOR ) {
409  DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
410  intelxl, api );
411  return -ENOTSUP;
412  }
413 
414  return 0;
415 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct pci_api * api
API for this bus:dev.fn address.
Definition: pcicloud.c:42
#define DBGC(...)
Definition: compiler.h:505
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
u32 version
Driver version.
Definition: ath9k_hw.c:1983
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:87
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:489
Admin queue Get Version command parameters.
Definition: intelxl.h:98
#define le16_to_cpu(value)
Definition: byteswap.h:112
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References api, cmd, cpu_to_le16, DBGC, ENOTSUP, INTELXL_ADMIN_API_MAJOR, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_VERSION, le16_to_cpu, rc, and version.

◆ intelxl_admin_driver()

static int intelxl_admin_driver ( struct intelxl_nic intelxl)
static

Report driver version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 423 of file intelxl.c.

423  {
425  struct intelxl_admin_driver_params *driver;
426  union intelxl_admin_buffer *buf;
427  int rc;
428 
429  /* Populate descriptor */
431  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
433  cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
434  driver = &cmd->params.driver;
435  driver->major = product_major_version;
436  driver->minor = product_minor_version;
437  buf = intelxl_admin_command_buffer ( intelxl );
438  snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
440 
441  /* Issue command */
442  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
443  return rc;
444 
445  return 0;
446 }
const char product_short_name[]
Product short name string.
Definition: version.c:76
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
char name[32]
Driver name.
Definition: intelxl.h:131
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:238
struct intelxl_admin_driver_buffer driver
Driver Version data buffer.
Definition: intelxl.h:403
Admin queue Driver Version command parameters.
Definition: intelxl.h:113
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
const int product_major_version
Product major version.
Definition: version.c:64
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
const char product_name[]
Product name string.
Definition: version.c:73
#define INTELXL_ADMIN_DRIVER
Admin queue Driver Version command.
Definition: intelxl.h:110
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
const int product_minor_version
Product minor version.
Definition: version.c:67
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, intelxl_admin_buffer::driver, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_DRIVER, INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, intelxl_admin_driver_buffer::name, product_major_version, product_minor_version, product_name, product_short_name, rc, and snprintf().

Referenced by intelxl_probe().

◆ intelxl_admin_shutdown()

static int intelxl_admin_shutdown ( struct intelxl_nic intelxl)
static

Shutdown admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 454 of file intelxl.c.

454  {
457  int rc;
458 
459  /* Populate descriptor */
461  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
462  shutdown = &cmd->params.shutdown;
464 
465  /* Issue command */
466  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
467  return rc;
468 
469  return 0;
470 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
#define INTELXL_ADMIN_SHUTDOWN
Admin queue Shutdown command.
Definition: intelxl.h:135
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Admin queue Shutdown command parameters.
Definition: intelxl.h:138
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_SHUTDOWN_UNLOADING
Driver is unloading.
Definition: intelxl.h:146
void shutdown(int flags)
Shut down iPXE.
Definition: init.c:100
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_SHUTDOWN, INTELXL_ADMIN_SHUTDOWN_UNLOADING, rc, and shutdown().

Referenced by intelxl_close_admin().

◆ intelxl_admin_mac_read()

static int intelxl_admin_mac_read ( struct net_device netdev)
static

Get MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 478 of file intelxl.c.

478  {
479  struct intelxl_nic *intelxl = netdev->priv;
482  union intelxl_admin_buffer *buf;
483  uint8_t *mac;
484  int rc;
485 
486  /* Populate descriptor */
488  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
489  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
490  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
491  read = &cmd->params.mac_read;
492  buf = intelxl_admin_command_buffer ( intelxl );
493  mac = buf->mac_read.pf;
494 
495  /* Issue command */
496  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
497  return rc;
498 
499  /* Check that MAC address is present in response */
500  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
501  DBGC ( intelxl, "INTELXL %p has no MAC address\n", intelxl );
502  return -ENOENT;
503  }
504 
505  /* Check that address is valid */
506  if ( ! is_valid_ether_addr ( mac ) ) {
507  DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
508  intelxl, eth_ntoa ( mac ) );
509  return -ENOENT;
510  }
511 
512  /* Copy MAC address */
513  DBGC ( intelxl, "INTELXL %p has MAC address %s\n",
514  intelxl, eth_ntoa ( mac ) );
516 
517  return 0;
518 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct option_descriptor read[1]
Definition: nvo_cmd.c:115
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:514
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:238
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:160
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint8_t pf[ETH_ALEN]
Physical function MAC address.
Definition: intelxl.h:165
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
struct intelxl_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: intelxl.h:405
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:149
Admin queue Manage MAC Address Read command parameters.
Definition: intelxl.h:152
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
unsigned char uint8_t
Definition: stdint.h:10
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define ETH_ALEN
Definition: if_ether.h:8
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:381
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, DBGC, ENOENT, ETH_ALEN, eth_ntoa(), net_device::hw_addr, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_MAC_READ, INTELXL_ADMIN_MAC_READ_VALID_LAN, is_valid_ether_addr(), mac, intelxl_admin_buffer::mac_read, memcpy(), netdev, intelxl_admin_mac_read_buffer::pf, net_device::priv, rc, and read.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_write()

static int intelxl_admin_mac_write ( struct net_device netdev)
static

Set MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 526 of file intelxl.c.

526  {
527  struct intelxl_nic *intelxl = netdev->priv;
530  union {
532  struct {
533  uint16_t high;
534  uint32_t low;
535  } __attribute__ (( packed ));
536  } mac;
537  int rc;
538 
539  /* Populate descriptor */
542  write = &cmd->params.mac_write;
543  memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
544  write->high = bswap_16 ( mac.high );
545  write->low = bswap_32 ( mac.low );
546 
547  /* Issue command */
548  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
549  return rc;
550 
551  return 0;
552 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
#define __attribute__(x)
Definition: compiler.h:10
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
void * memcpy(void *dest, const void *src, size_t len) __nonnull
void * priv
Driver private data.
Definition: netdevice.h:431
#define bswap_16(value)
Definition: byteswap.h:58
uint16_t high
MAC address first 16 bits, byte-swapped.
Definition: intelxl.h:184
static struct net_device * netdev
Definition: gdbudp.c:52
uint32_t low
MAC address last 32 bits, byte-swapped.
Definition: intelxl.h:186
#define bswap_32(value)
Definition: byteswap.h:70
device nvs write
Definition: threewire.h:61
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:175
unsigned char uint8_t
Definition: stdint.h:10
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define ETH_ALEN
Definition: if_ether.h:8
unsigned int uint32_t
Definition: stdint.h:12
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
Admin queue Manage MAC Address Write command parameters.
Definition: intelxl.h:178
#define cpu_to_le16(value)
Definition: byteswap.h:106
__be32 raw[7]
Definition: CIB_PRM.h:28
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:387
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References __attribute__, bswap_16, bswap_32, cmd, cpu_to_le16, ETH_ALEN, intelxl_admin_mac_write_params::high, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_WRITE, net_device::ll_addr, intelxl_admin_mac_write_params::low, mac, memcpy(), netdev, net_device::priv, raw, rc, and write.

Referenced by intelxl_open().

◆ intelxl_admin_clear_pxe()

int intelxl_admin_clear_pxe ( struct intelxl_nic intelxl)

Clear PXE mode.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 560 of file intelxl.c.

560  {
562  struct intelxl_admin_clear_pxe_params *pxe;
563  int rc;
564 
565  /* Populate descriptor */
569  pxe = &cmd->params.pxe;
571 
572  /* Issue command */
573  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
574  return rc;
575 
576  /* Check for expected errors */
577  if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
578  DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
579  intelxl );
580  return 0;
581  }
582 
583  return 0;
584 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
Admin queue Clear PXE Mode command parameters.
Definition: intelxl.h:195
#define INTELXL_ADMIN_CLEAR_PXE_MAGIC
Clear PXE Mode magic value.
Definition: intelxl.h:203
uint8_t magic
Magic value.
Definition: intelxl.h:197
#define INTELXL_ADMIN_EEXIST
Error: attempt to create something that already exists.
Definition: intelxl.h:448
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_CLEAR_PXE
Admin queue Clear PXE Mode command.
Definition: intelxl.h:192
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, INTELXL_ADMIN_CLEAR_PXE, INTELXL_ADMIN_CLEAR_PXE_MAGIC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_EEXIST, intelxl_admin_clear_pxe_params::magic, and rc.

Referenced by ice_probe(), and intelxl_probe().

◆ intelxl_admin_switch()

static int intelxl_admin_switch ( struct intelxl_nic intelxl)
static

Get switch configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 592 of file intelxl.c.

592  {
594  struct intelxl_admin_switch_params *sw;
595  union intelxl_admin_buffer *buf;
596  uint16_t next = 0;
597  int rc;
598 
599  /* Get each configuration in turn */
600  do {
601  /* Populate descriptor */
603  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
604  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
605  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
606  sw = &cmd->params.sw;
607  sw->next = next;
608  buf = intelxl_admin_command_buffer ( intelxl );
609 
610  /* Issue command */
611  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
612  return rc;
613 
614  /* Dump raw configuration */
615  DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
616  intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
617  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
618 
619  /* Parse response */
620  if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
621  intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
622  DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
623  "downlink %#04x conn %#02x\n", intelxl,
624  intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
625  le16_to_cpu ( buf->sw.cfg.downlink ),
626  buf->sw.cfg.connection );
627  }
628 
629  } while ( ( next = sw->next ) );
630 
631  /* Check that we found a VSI */
632  if ( ! intelxl->vsi ) {
633  DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
634  return -ENOENT;
635  }
636 
637  return 0;
638 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:206
uint8_t type
Switching element type.
Definition: intelxl.h:211
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:514
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:238
struct intelxl_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: intelxl.h:407
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:926
uint16_t downlink
Downlink switching element ID.
Definition: intelxl.h:219
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
uint8_t connection
Connection type.
Definition: intelxl.h:223
#define le16_to_cpu(value)
Definition: byteswap.h:112
uint32_t next
Next descriptor address.
Definition: dwmac.h:22
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
uint16_t uplink
Uplink switching element ID.
Definition: intelxl.h:217
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin_switch_config cfg
Switch configuration.
Definition: intelxl.h:252
Admin queue Get Switch Configuration command parameters.
Definition: intelxl.h:234
#define INTELXL_ADMIN_SWITCH_TYPE_VSI
Virtual Station Inferface element type.
Definition: intelxl.h:231
uint16_t seid
Switching element ID.
Definition: intelxl.h:215
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References intelxl_admin_switch_buffer::cfg, cmd, intelxl_admin_switch_config::connection, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, intelxl_admin_switch_config::downlink, ENOENT, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_SWITCH, INTELXL_ADMIN_SWITCH_TYPE_VSI, le16_to_cpu, next, rc, intelxl_admin_switch_config::seid, intelxl_admin_buffer::sw, intelxl_admin_switch_config::type, intelxl_admin_switch_config::uplink, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_vsi()

static int intelxl_admin_vsi ( struct intelxl_nic intelxl)
static

Get VSI parameters.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 646 of file intelxl.c.

646  {
649  union intelxl_admin_buffer *buf;
650  int rc;
651 
652  /* Populate descriptor */
654  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
655  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
656  cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
657  vsi = &cmd->params.vsi;
658  vsi->vsi = cpu_to_le16 ( intelxl->vsi );
659  buf = intelxl_admin_command_buffer ( intelxl );
660 
661  /* Issue command */
662  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
663  return rc;
664 
665  /* Parse response */
666  intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
667  intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
668  DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
669  intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
670 
671  return 0;
672 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint16_t queue[16]
Queue numbers.
Definition: intelxl.h:273
uint16_t qset[8]
Queue set handles for each traffic class.
Definition: intelxl.h:277
struct intelxl_admin_vsi_buffer vsi
Get VSI Parameters data buffer.
Definition: intelxl.h:409
Admin queue Get VSI Parameters command parameters.
Definition: intelxl.h:259
unsigned int qset
Queue set handle.
Definition: intelxl.h:928
#define DBGC(...)
Definition: compiler.h:505
union intelxl_admin_buffer * intelxl_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: intelxl.c:238
#define INTELXL_ADMIN_VSI
Admin queue Get VSI Parameters command.
Definition: intelxl.h:256
unsigned int queue
Queue number.
Definition: intelxl.h:924
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:926
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:261
#define le16_to_cpu(value)
Definition: byteswap.h:112
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue data buffer.
Definition: intelxl.h:401

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_buffer(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_VSI, le16_to_cpu, intelxl_admin_vsi_buffer::qset, intelxl_nic::qset, intelxl_admin_vsi_buffer::queue, intelxl_nic::queue, rc, intelxl_admin_vsi_params::vsi, intelxl_admin_buffer::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_promisc()

static int intelxl_admin_promisc ( struct intelxl_nic intelxl)
static

Set VSI promiscuous modes.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 680 of file intelxl.c.

680  {
682  struct intelxl_admin_promisc_params *promisc;
683  uint16_t flags;
684  int rc;
685 
686  /* Populate descriptor */
688  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
693  promisc = &cmd->params.promisc;
694  promisc->flags = cpu_to_le16 ( flags );
695  promisc->valid = cpu_to_le16 ( flags );
696  promisc->vsi = cpu_to_le16 ( intelxl->vsi );
697 
698  /* Issue command */
699  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
700  return rc;
701 
702  return 0;
703 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
#define INTELXL_ADMIN_PROMISC_FL_VLAN
Promiscuous VLAN mode.
Definition: intelxl.h:307
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_PROMISC
Admin queue Set VSI Promiscuous Modes command.
Definition: intelxl.h:283
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:926
uint16_t flags
Flags.
Definition: intelxl.h:288
uint8_t flags
Flags.
Definition: ena.h:18
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
uint16_t vsi
VSI switching element ID.
Definition: intelxl.h:292
Admin queue Set VSI Promiscuous Modes command parameters.
Definition: intelxl.h:286
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_PROMISC_FL_BROADCAST
Promiscuous broadcast mode.
Definition: intelxl.h:304
uint16_t valid
Valid flags.
Definition: intelxl.h:290
#define INTELXL_ADMIN_PROMISC_FL_UNICAST
Promiscuous unicast mode.
Definition: intelxl.h:298
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define INTELXL_ADMIN_PROMISC_FL_MULTICAST
Promiscuous multicast mode.
Definition: intelxl.h:301

References cmd, cpu_to_le16, flags, intelxl_admin_promisc_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_PROMISC, INTELXL_ADMIN_PROMISC_FL_BROADCAST, INTELXL_ADMIN_PROMISC_FL_MULTICAST, INTELXL_ADMIN_PROMISC_FL_UNICAST, INTELXL_ADMIN_PROMISC_FL_VLAN, rc, intelxl_admin_promisc_params::valid, intelxl_admin_promisc_params::vsi, and intelxl_nic::vsi.

Referenced by intelxl_probe().

◆ intelxl_admin_mac_config()

int intelxl_admin_mac_config ( struct intelxl_nic intelxl)

Set MAC configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 711 of file intelxl.c.

711  {
713  struct intelxl_admin_mac_config_params *config;
714  int rc;
715 
716  /* Populate descriptor */
719  config = &cmd->params.mac_config;
720  config->mfs = cpu_to_le16 ( intelxl->mfs );
722 
723  /* Issue command */
724  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
725  return rc;
726 
727  return 0;
728 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
size_t mfs
Maximum frame size.
Definition: intelxl.h:915
Admin queue Set MAC Configuration command parameters.
Definition: intelxl.h:313
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
#define INTELXL_ADMIN_MAC_CONFIG
Admin queue Set MAC Configuration command.
Definition: intelxl.h:310
Admin queue descriptor.
Definition: intelxl.h:415
uint16_t mfs
Maximum frame size.
Definition: intelxl.h:315
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_MAC_CONFIG_FL_CRC
Append CRC on transmit.
Definition: intelxl.h:323
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_mac_config_params::flags, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_MAC_CONFIG, INTELXL_ADMIN_MAC_CONFIG_FL_CRC, intelxl_admin_mac_config_params::mfs, intelxl_nic::mfs, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_admin_autoneg()

static int intelxl_admin_autoneg ( struct intelxl_nic intelxl)
static

Restart autonegotiation.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 736 of file intelxl.c.

736  {
738  struct intelxl_admin_autoneg_params *autoneg;
739  int rc;
740 
741  /* Populate descriptor */
743  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
744  autoneg = &cmd->params.autoneg;
747 
748  /* Issue command */
749  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
750  return rc;
751 
752  return 0;
753 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:337
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:326
Admin queue Restart Autonegotiation command parameters.
Definition: intelxl.h:329
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:340
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, intelxl_admin_autoneg_params::flags, INTELXL_ADMIN_AUTONEG, INTELXL_ADMIN_AUTONEG_FL_ENABLE, INTELXL_ADMIN_AUTONEG_FL_RESTART, intelxl_admin_command(), intelxl_admin_command_descriptor(), and rc.

Referenced by intelxl_open().

◆ intelxl_admin_link()

static int intelxl_admin_link ( struct net_device netdev)
static

Get link status.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 761 of file intelxl.c.

761  {
762  struct intelxl_nic *intelxl = netdev->priv;
765  int rc;
766 
767  /* Populate descriptor */
769  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
770  link = &cmd->params.link;
772 
773  /* Issue command */
774  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
775  return rc;
776  DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
777  intelxl, link->phy, link->speed, link->status );
778 
779  /* Update network device */
780  if ( link->status & INTELXL_ADMIN_LINK_UP ) {
782  } else {
784  }
785 
786  return 0;
787 }
struct intelxl_admin_descriptor * intelxl_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: intelxl.c:221
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
#define DBGC(...)
Definition: compiler.h:505
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:230
void * priv
Driver private data.
Definition: netdevice.h:431
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:788
static struct net_device * netdev
Definition: gdbudp.c:52
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:277
Admin queue descriptor.
Definition: intelxl.h:415
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:365
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:362
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, intelxl_admin_command(), intelxl_admin_command_descriptor(), INTELXL_ADMIN_LINK, INTELXL_ADMIN_LINK_NOTIFY, INTELXL_ADMIN_LINK_UP, link, netdev, netdev_link_down(), netdev_link_up(), net_device::priv, and rc.

Referenced by intelxl_admin_event(), intelxl_open(), and intelxl_probe().

◆ intelxl_admin_event()

static void intelxl_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor evt,
union intelxl_admin_buffer *buf  __unused 
)
static

Handle admin event.

Parameters
netdevNetwork device
evtEvent descriptor
bufData buffer

Definition at line 796 of file intelxl.c.

798  {
799  struct intelxl_nic *intelxl = netdev->priv;
800 
801  /* Ignore unrecognised events */
802  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
803  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
804  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
805  return;
806  }
807 
808  /* Update link status */
810 }
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
uint16_t opcode
Opcode.
Definition: intelxl.h:419
#define DBGC(...)
Definition: compiler.h:505
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define cpu_to_le16(value)
Definition: byteswap.h:106
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:761

References cpu_to_le16, DBGC, INTELXL_ADMIN_LINK, intelxl_admin_link(), le16_to_cpu, netdev, intelxl_admin_descriptor::opcode, and net_device::priv.

Referenced by intelxl_probe().

◆ intelxl_refill_admin()

static void intelxl_refill_admin ( struct intelxl_nic intelxl)
static

Refill admin event queue.

Parameters
intelxlIntel device

Definition at line 817 of file intelxl.c.

817  {
818  struct intelxl_admin *admin = &intelxl->event;
819  const struct intelxl_admin_offsets *regs = admin->regs;
820  void *admin_regs = ( intelxl->regs + admin->base );
821  unsigned int tail;
822 
823  /* Update tail pointer */
824  tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
826  wmb();
827  writel ( tail, admin_regs + regs->tail );
828 }
void * regs
Registers.
Definition: intelxl.h:911
wmb()
Admin queue register offsets.
Definition: intelxl.h:63
Admin queue.
Definition: intelxl.h:451
unsigned int base
Register block base.
Definition: intelxl.h:462
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
unsigned int index
Queue index.
Definition: intelxl.h:459
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct i386_regs regs
Definition: registers.h:15
unsigned int tail
Tail Register offset.
Definition: intelxl.h:73
const struct intelxl_admin_offsets * regs
Register offsets.
Definition: intelxl.h:464
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943

References intelxl_admin::base, intelxl_nic::event, intelxl_admin::index, INTELXL_ADMIN_NUM_DESC, regs, intelxl_admin::regs, intelxl_nic::regs, intelxl_admin_offsets::tail, wmb(), and writel().

Referenced by intelxl_poll_admin(), and intelxl_reopen_admin().

◆ intelxl_poll_admin()

void intelxl_poll_admin ( struct net_device netdev)

Poll admin event queue.

Parameters
netdevNetwork device

Definition at line 835 of file intelxl.c.

835  {
836  struct intelxl_nic *intelxl = netdev->priv;
837  struct intelxl_admin *admin = &intelxl->event;
838  struct intelxl_admin_descriptor *evt;
839  union intelxl_admin_buffer *buf;
840 
841  /* Check for events */
842  while ( 1 ) {
843 
844  /* Get next event descriptor and data buffer */
845  evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
846  buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
847 
848  /* Stop if descriptor is not yet completed */
849  if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
850  return;
851  DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
852  intelxl, admin->index );
853  DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
854  sizeof ( *evt ) );
855  if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
856  DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
857  le16_to_cpu ( evt->len ) );
858  }
859 
860  /* Handle event */
861  intelxl->handle ( netdev, evt, buf );
862 
863  /* Reset descriptor and refill queue */
864  intelxl_admin_event_init ( intelxl, admin->index );
865  admin->index++;
866  intelxl_refill_admin ( intelxl );
867  }
868 }
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:962
union intelxl_admin_buffer * buf
Data buffers.
Definition: intelxl.h:455
Admin queue.
Definition: intelxl.h:451
uint16_t flags
Flags.
Definition: intelxl.h:417
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
uint16_t len
Data length.
Definition: intelxl.h:421
unsigned int index
Queue index.
Definition: intelxl.h:459
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:254
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:817
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct intelxl_admin_descriptor * desc
Descriptors.
Definition: intelxl.h:453
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define le16_to_cpu(value)
Definition: byteswap.h:112
Admin queue descriptor.
Definition: intelxl.h:415
#define DBGC2(...)
Definition: compiler.h:522
#define cpu_to_le16(value)
Definition: byteswap.h:106
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943
#define INTELXL_ADMIN_FL_DD
Admin descriptor done.
Definition: intelxl.h:433
Admin queue data buffer.
Definition: intelxl.h:401

References intelxl_admin::buf, cpu_to_le16, DBGC2, DBGC2_HDA, intelxl_admin::desc, intelxl_nic::event, intelxl_admin_descriptor::flags, intelxl_nic::handle, intelxl_admin::index, intelxl_admin_event_init(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_DD, INTELXL_ADMIN_NUM_DESC, intelxl_refill_admin(), le16_to_cpu, intelxl_admin_descriptor::len, netdev, and net_device::priv.

Referenced by intelxl_poll(), and intelxlvf_admin_command().

◆ intelxl_open_admin()

int intelxl_open_admin ( struct intelxl_nic intelxl)

Open admin queues.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 876 of file intelxl.c.

876  {
877  int rc;
878 
879  /* Allocate admin event queue */
880  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
881  goto err_alloc_event;
882 
883  /* Allocate admin command queue */
884  if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
885  goto err_alloc_command;
886 
887  /* (Re)open admin queues */
888  intelxl_reopen_admin ( intelxl );
889 
890  return 0;
891 
892  intelxl_disable_admin ( intelxl, &intelxl->command );
893  intelxl_disable_admin ( intelxl, &intelxl->event );
894  intelxl_free_admin ( intelxl, &intelxl->command );
895  err_alloc_command:
896  intelxl_free_admin ( intelxl, &intelxl->event );
897  err_alloc_event:
898  return rc;
899 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
static int intelxl_alloc_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Allocate admin queue.
Definition: intelxl.c:123
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:205
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:190
void intelxl_reopen_admin(struct intelxl_nic *intelxl)
Reopen admin queues (after virtual function reset)
Definition: intelxl.c:906
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943

References intelxl_nic::command, intelxl_nic::event, intelxl_alloc_admin(), intelxl_disable_admin(), intelxl_free_admin(), intelxl_reopen_admin(), and rc.

Referenced by ice_probe(), intelxl_probe(), and intelxlvf_probe().

◆ intelxl_reopen_admin()

void intelxl_reopen_admin ( struct intelxl_nic intelxl)

Reopen admin queues (after virtual function reset)

Parameters
intelxlIntel device

Definition at line 906 of file intelxl.c.

906  {
907  unsigned int i;
908 
909  /* Enable admin event queue */
910  intelxl_enable_admin ( intelxl, &intelxl->event );
911 
912  /* Enable admin command queue */
913  intelxl_enable_admin ( intelxl, &intelxl->command );
914 
915  /* Initialise all admin event queue descriptors */
916  for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
917  intelxl_admin_event_init ( intelxl, i );
918 
919  /* Post all descriptors to event queue */
920  intelxl_refill_admin ( intelxl );
921 }
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
static void intelxl_enable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Enable admin queue.
Definition: intelxl.c:151
#define INTELXL_ADMIN_NUM_DESC
Number of admin queue descriptors.
Definition: intelxl.h:483
static void intelxl_admin_event_init(struct intelxl_nic *intelxl, unsigned int index)
Initialise admin event queue descriptor.
Definition: intelxl.c:254
static void intelxl_refill_admin(struct intelxl_nic *intelxl)
Refill admin event queue.
Definition: intelxl.c:817
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_event_init(), INTELXL_ADMIN_NUM_DESC, intelxl_enable_admin(), and intelxl_refill_admin().

Referenced by intelxl_open_admin(), and intelxlvf_reset_wait().

◆ intelxl_close_admin()

void intelxl_close_admin ( struct intelxl_nic intelxl)

Close admin queues.

Parameters
intelxlIntel device

Definition at line 928 of file intelxl.c.

928  {
929 
930  /* Shut down admin queues */
931  intelxl_admin_shutdown ( intelxl );
932 
933  /* Disable admin queues */
934  intelxl_disable_admin ( intelxl, &intelxl->command );
935  intelxl_disable_admin ( intelxl, &intelxl->event );
936 
937  /* Free admin queues */
938  intelxl_free_admin ( intelxl, &intelxl->command );
939  intelxl_free_admin ( intelxl, &intelxl->event );
940 }
static int intelxl_admin_shutdown(struct intelxl_nic *intelxl)
Shutdown admin queues.
Definition: intelxl.c:454
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
static void intelxl_free_admin(struct intelxl_nic *intelxl __unused, struct intelxl_admin *admin)
Free admin queue.
Definition: intelxl.c:205
static void intelxl_disable_admin(struct intelxl_nic *intelxl, struct intelxl_admin *admin)
Disable admin queue.
Definition: intelxl.c:190
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943

References intelxl_nic::command, intelxl_nic::event, intelxl_admin_shutdown(), intelxl_disable_admin(), and intelxl_free_admin().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ intelxl_alloc_ring()

int intelxl_alloc_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Allocate descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 956 of file intelxl.c.

957  {
958  int rc;
959 
960  /* Allocate descriptor ring */
961  ring->desc.raw = dma_alloc ( intelxl->dma, &ring->map, ring->len,
962  INTELXL_ALIGN );
963  if ( ! ring->desc.raw ) {
964  rc = -ENOMEM;
965  goto err_alloc;
966  }
967 
968  /* Initialise descriptor ring */
969  memset ( ring->desc.raw, 0, ring->len );
970 
971  /* Reset tail pointer */
972  writel ( 0, ( intelxl->regs + ring->tail ) );
973 
974  /* Reset counters */
975  ring->prod = 0;
976  ring->cons = 0;
977 
978  DBGC ( intelxl, "INTELXL %p ring %06x is at [%08lx,%08lx)\n",
979  intelxl, ring->tail, virt_to_phys ( ring->desc.raw ),
980  ( virt_to_phys ( ring->desc.raw ) + ring->len ) );
981 
982  return 0;
983 
984  dma_free ( &ring->map, ring->desc.raw, ring->len );
985  err_alloc:
986  return rc;
987 }
void * regs
Registers.
Definition: intelxl.h:911
size_t len
Length (in bytes)
Definition: intelxl.h:777
struct dma_device * dma
DMA device.
Definition: intelxl.h:913
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
#define ENOMEM
Not enough space.
Definition: errno.h:534
unsigned int cons
Consumer index.
Definition: intelxl.h:770
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@79 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
unsigned int tail
Tail register.
Definition: intelxl.h:775
void * memset(void *dest, int character, size_t len) __nonnull

References intelxl_ring::cons, DBGC, intelxl_ring::desc, intelxl_nic::dma, dma_alloc(), dma_free(), ENOMEM, INTELXL_ALIGN, intelxl_ring::len, intelxl_ring::map, memset(), intelxl_ring::prod, intelxl_ring::raw, rc, intelxl_nic::regs, intelxl_ring::tail, and writel().

Referenced by ice_create_tx(), intelxl_create_ring(), and intelxlvf_open().

◆ intelxl_free_ring()

void intelxl_free_ring ( struct intelxl_nic *intelxl  __unused,
struct intelxl_ring ring 
)

Free descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 995 of file intelxl.c.

996  {
997 
998  /* Free descriptor ring */
999  dma_free ( &ring->map, ring->desc.raw, ring->len );
1000  ring->desc.raw = NULL;
1001 }
size_t len
Length (in bytes)
Definition: intelxl.h:777
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@79 desc
Descriptors.
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321

References intelxl_ring::desc, dma_free(), intelxl_ring::len, intelxl_ring::map, NULL, and intelxl_ring::raw.

Referenced by ice_create_tx(), ice_destroy_tx(), intelxl_create_ring(), intelxl_destroy_ring(), intelxlvf_close(), and intelxlvf_open().

◆ intelxl_context_dump()

static void intelxl_context_dump ( struct intelxl_nic intelxl,
uint32_t  op,
size_t  len 
)
static

Dump queue context (for debugging)

Parameters
intelxlIntel device
opContext operation
lenSize of context

Definition at line 1011 of file intelxl.c.

1011  {
1012  struct intelxl_context_line line;
1013  uint32_t pfcm_lanctxctl;
1014  uint32_t pfcm_lanctxstat;
1015  unsigned int queue;
1016  unsigned int index;
1017  unsigned int i;
1018 
1019  /* Do nothing unless debug output is enabled */
1020  if ( ! DBG_EXTRA )
1021  return;
1022 
1023  /* Dump context */
1024  DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
1025  for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
1026 
1027  /* Start context operation */
1028  queue = ( intelxl->base + intelxl->queue );
1029  pfcm_lanctxctl =
1033  writel ( pfcm_lanctxctl,
1034  intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1035 
1036  /* Wait for operation to complete */
1037  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1038 
1039  /* Check if operation is complete */
1040  pfcm_lanctxstat = readl ( intelxl->regs +
1042  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1043  break;
1044 
1045  /* Delay */
1046  mdelay ( 1 );
1047  }
1048 
1049  /* Read context data */
1050  for ( i = 0 ; i < ( sizeof ( line ) /
1051  sizeof ( line.raw[0] ) ) ; i++ ) {
1052  line.raw[i] = readl ( intelxl->regs +
1053  INTELXL_PFCM_LANCTXDATA ( i ) );
1054  }
1055  DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
1056  &line, sizeof ( line ) );
1057  }
1058 }
void * regs
Registers.
Definition: intelxl.h:911
Queue context line.
Definition: intelxl.h:529
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
long index
Definition: bigint.h:62
unsigned int queue
Queue number.
Definition: intelxl.h:924
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:503
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:525
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:506
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define DBGC2(...)
Definition: compiler.h:522
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:526
unsigned int base
Absolute queue number base.
Definition: intelxl.h:920
#define DBG_EXTRA
Definition: compiler.h:319
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:502
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:499
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ
Read context.
Definition: intelxl.h:519

References intelxl_nic::base, DBG_EXTRA, DBGC2, DBGC2_HDA, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_READ, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, len, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

Referenced by intelxl_close().

◆ intelxl_context_line()

static int intelxl_context_line ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
unsigned int  index,
uint32_t  op 
)
static

Program queue context line.

Parameters
intelxlIntel device
lineQueue context line
indexLine number
opContext operation
Return values
rcReturn status code

Definition at line 1069 of file intelxl.c.

1071  {
1072  uint32_t pfcm_lanctxctl;
1073  uint32_t pfcm_lanctxstat;
1074  unsigned int queue;
1075  unsigned int i;
1076 
1077  /* Write context data */
1078  for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
1079  writel ( le32_to_cpu ( line->raw[i] ),
1080  intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
1081  }
1082 
1083  /* Start context operation */
1084  queue = ( intelxl->base + intelxl->queue );
1085  pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
1088  writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
1089 
1090  /* Wait for operation to complete */
1091  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
1092 
1093  /* Check if operation is complete */
1094  pfcm_lanctxstat = readl ( intelxl->regs +
1096  if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
1097  return 0;
1098 
1099  /* Delay */
1100  mdelay ( 1 );
1101  }
1102 
1103  DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
1104  intelxl, pfcm_lanctxctl );
1105  return -ETIMEDOUT;
1106 }
void * regs
Registers.
Definition: intelxl.h:911
uint32_t raw[4]
Raw data.
Definition: intelxl.h:531
#define le32_to_cpu(value)
Definition: byteswap.h:113
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE
Write context.
Definition: intelxl.h:521
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
long index
Definition: bigint.h:62
unsigned int queue
Queue number.
Definition: intelxl.h:924
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x)
Queue number.
Definition: intelxl.h:503
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_PFCM_LANCTXSTAT
CMLAN Context Status Register.
Definition: intelxl.h:525
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x)
Sub-line.
Definition: intelxl.h:506
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define INTELXL_PFCM_LANCTXSTAT_DONE
Complete.
Definition: intelxl.h:526
unsigned int base
Absolute queue number base.
Definition: intelxl.h:920
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define INTELXL_PFCM_LANCTXCTL
CMLAN Context Control Register.
Definition: intelxl.h:502
#define INTELXL_PFCM_LANCTXDATA(x)
CMLAN Context Data Register.
Definition: intelxl.h:499

References intelxl_nic::base, DBGC, ETIMEDOUT, index, INTELXL_CTX_MAX_WAIT_MS, INTELXL_PFCM_LANCTXCTL, INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE, INTELXL_PFCM_LANCTXCTL_QUEUE_NUM, INTELXL_PFCM_LANCTXCTL_SUB_LINE, INTELXL_PFCM_LANCTXDATA, INTELXL_PFCM_LANCTXSTAT, INTELXL_PFCM_LANCTXSTAT_DONE, le32_to_cpu, mdelay(), op, queue, intelxl_nic::queue, intelxl_context_line::raw, readl(), intelxl_nic::regs, and writel().

◆ intelxl_context()

static int intelxl_context ( struct intelxl_nic intelxl,
struct intelxl_context_line line,
size_t  len,
uint32_t  op 
)
static

Program queue context.

Parameters
intelxlIntel device
lineQueue context lines
lenSize of context
opContext operation
Return values
rcReturn status code

Definition at line 1117 of file intelxl.c.

1119  {
1120  unsigned int index;
1121  int rc;
1122 
1123  DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
1124  intelxl, op, len );
1125  DBGC2_HDA ( intelxl, 0, line, len );
1126 
1127  /* Program one line at a time */
1128  for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
1129  if ( ( rc = intelxl_context_line ( intelxl, line++, index,
1130  op ) ) != 0 )
1131  return rc;
1132  }
1133 
1134  return 0;
1135 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
Queue context line.
Definition: intelxl.h:529
long index
Definition: bigint.h:62
ring len
Length.
Definition: dwmac.h:231
#define DBGC2_HDA(...)
Definition: compiler.h:523
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define DBGC2(...)
Definition: compiler.h:522

References DBGC2, DBGC2_HDA, index, len, op, and rc.

Referenced by intelxl_context_rx(), and intelxl_context_tx().

◆ intelxl_context_tx()

static int intelxl_context_tx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program transmit queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1144 of file intelxl.c.

1145  {
1146  union {
1147  struct intelxl_context_tx tx;
1148  struct intelxl_context_line line;
1149  } ctx;
1150  int rc;
1151 
1152  /* Initialise context */
1153  memset ( &ctx, 0, sizeof ( ctx ) );
1154  ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
1155  ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
1156  ctx.tx.count =
1158  ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
1159 
1160  /* Program context */
1161  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1163  return rc;
1164 
1165  return 0;
1166 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:529
unsigned int qset
Queue set handle.
Definition: intelxl.h:928
#define cpu_to_le64(value)
Definition: byteswap.h:108
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:514
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1117
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
#define INTELXL_CTX_TX_FL_NEW
New transmit queue context.
Definition: intelxl.h:555
#define INTELXL_CTX_TX_QSET(qset)
Transmit queue set.
Definition: intelxl.h:564
#define INTELXL_CTX_TX_BASE(base)
Transmit queue base address.
Definition: intelxl.h:558
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_CTX_TX_COUNT(count)
Transmit queue count.
Definition: intelxl.h:561
Transmit queue context.
Definition: intelxl.h:535
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_TX_BASE, INTELXL_CTX_TX_COUNT, INTELXL_CTX_TX_FL_NEW, INTELXL_CTX_TX_QSET, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_TX_NUM_DESC, memset(), intelxl_nic::qset, rc, and tx.

◆ intelxl_context_rx()

static int intelxl_context_rx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program receive queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 1175 of file intelxl.c.

1176  {
1177  union {
1178  struct intelxl_context_rx rx;
1179  struct intelxl_context_line line;
1180  } ctx;
1181  uint64_t base_count;
1182  int rc;
1183 
1184  /* Initialise context */
1185  memset ( &ctx, 0, sizeof ( ctx ) );
1187  ctx.rx.base_count = cpu_to_le64 ( base_count );
1188  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
1190  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
1191 
1192  /* Program context */
1193  if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
1195  return rc;
1196 
1197  return 0;
1198 }
Receive queue context.
Definition: intelxl.h:567
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:591
uint64_t address
Base address.
Definition: ena.h:24
Queue context line.
Definition: intelxl.h:529
unsigned long long uint64_t
Definition: stdint.h:13
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:600
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
size_t mfs
Maximum frame size.
Definition: intelxl.h:915
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:594
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:512
static int intelxl_context(struct intelxl_nic *intelxl, struct intelxl_context_line *line, size_t len, uint32_t op)
Program queue context.
Definition: intelxl.c:1117
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:597
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:587
void * memset(void *dest, int character, size_t len) __nonnull

References address, cpu_to_le16, cpu_to_le64, ctx, intelxl_context(), INTELXL_CTX_RX_BASE_COUNT, INTELXL_CTX_RX_FL_CRCSTRIP, INTELXL_CTX_RX_FL_DSIZE, INTELXL_CTX_RX_LEN, INTELXL_CTX_RX_MFS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_RX_NUM_DESC, memset(), intelxl_nic::mfs, rc, and rx.

◆ intelxl_enable_ring()

static int intelxl_enable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Enable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1207 of file intelxl.c.

1208  {
1209  void *ring_regs = ( intelxl->regs + ring->reg );
1210  uint32_t qxx_ena;
1211 
1212  /* Enable ring */
1213  writel ( INTELXL_QXX_ENA_REQ, ( ring_regs + INTELXL_QXX_ENA ) );
1215  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1216  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) ) {
1217  DBGC ( intelxl, "INTELXL %p ring %06x failed to enable: "
1218  "%#08x\n", intelxl, ring->tail, qxx_ena );
1219  return -EIO;
1220  }
1221 
1222  return 0;
1223 }
void * regs
Registers.
Definition: intelxl.h:911
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:643
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:641
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define INTELXL_QXX_ENA_REQ
Enable request.
Definition: intelxl.h:642
unsigned int reg
Register block.
Definition: intelxl.h:773
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_QUEUE_ENABLE_DELAY_US
Time to wait for a queue to become enabled.
Definition: intelxl.h:606
#define EIO
Input/output error.
Definition: errno.h:433
unsigned int tail
Tail register.
Definition: intelxl.h:775

References DBGC, EIO, INTELXL_QUEUE_ENABLE_DELAY_US, INTELXL_QXX_ENA, INTELXL_QXX_ENA_REQ, INTELXL_QXX_ENA_STAT, readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, udelay(), and writel().

Referenced by intelxl_create_ring().

◆ intelxl_disable_ring()

static int intelxl_disable_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Disable descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1232 of file intelxl.c.

1233  {
1234  void *ring_regs = ( intelxl->regs + ring->reg );
1235  uint32_t qxx_ena;
1236  unsigned int i;
1237 
1238  /* Disable ring */
1239  writel ( 0, ( ring_regs + INTELXL_QXX_ENA ) );
1240 
1241  /* Wait for ring to be disabled */
1242  for ( i = 0 ; i < INTELXL_QUEUE_DISABLE_MAX_WAIT_MS ; i++ ) {
1243 
1244  /* Check if ring is disabled */
1245  qxx_ena = readl ( ring_regs + INTELXL_QXX_ENA );
1246  if ( ! ( qxx_ena & INTELXL_QXX_ENA_STAT ) )
1247  return 0;
1248 
1249  /* Delay */
1250  mdelay ( 1 );
1251  }
1252 
1253  DBGC ( intelxl, "INTELXL %p ring %06x timed out waiting for disable: "
1254  "%#08x\n", intelxl, ring->tail, qxx_ena );
1255  return -ETIMEDOUT;
1256 }
void * regs
Registers.
Definition: intelxl.h:911
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define INTELXL_QXX_ENA_STAT
Enabled status.
Definition: intelxl.h:643
#define INTELXL_QXX_ENA
Queue Enable Register (offset)
Definition: intelxl.h:641
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
unsigned int reg
Register block.
Definition: intelxl.h:773
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS
Maximum time to wait for a queue to become disabled.
Definition: intelxl.h:612
unsigned int uint32_t
Definition: stdint.h:12
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669

References DBGC, ETIMEDOUT, INTELXL_QUEUE_DISABLE_MAX_WAIT_MS, INTELXL_QXX_ENA, INTELXL_QXX_ENA_STAT, mdelay(), readl(), intelxl_ring::reg, intelxl_nic::regs, intelxl_ring::tail, and writel().

Referenced by intelxl_create_ring(), and intelxl_destroy_ring().

◆ intelxl_create_ring()

int intelxl_create_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Create descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 1265 of file intelxl.c.

1266  {
1268  int rc;
1269 
1270  /* Allocate descriptor ring */
1271  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
1272  goto err_alloc;
1273 
1274  /* Program queue context */
1275  address = dma ( &ring->map, ring->desc.raw );
1276  if ( ( rc = ring->context ( intelxl, address ) ) != 0 )
1277  goto err_context;
1278 
1279  /* Enable ring */
1280  if ( ( rc = intelxl_enable_ring ( intelxl, ring ) ) != 0 )
1281  goto err_enable;
1282 
1283  return 0;
1284 
1285  intelxl_disable_ring ( intelxl, ring );
1286  err_enable:
1287  err_context:
1288  intelxl_free_ring ( intelxl, ring );
1289  err_alloc:
1290  return rc;
1291 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
int(* context)(struct intelxl_nic *intelxl, physaddr_t address)
Program queue context.
Definition: intelxl.h:783
static int intelxl_enable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Enable descriptor ring.
Definition: intelxl.c:1207
uint64_t address
Base address.
Definition: ena.h:24
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1232
void * raw
Raw data.
Definition: intelxl.h:763
union intelxl_ring::@79 desc
Descriptors.
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:995
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
unsigned long physaddr_t
Definition: stdint.h:20
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:956

References address, intelxl_ring::context, intelxl_ring::desc, dma(), intelxl_alloc_ring(), intelxl_disable_ring(), intelxl_enable_ring(), intelxl_free_ring(), intelxl_ring::map, intelxl_ring::raw, and rc.

Referenced by ice_open(), and intelxl_open().

◆ intelxl_destroy_ring()

void intelxl_destroy_ring ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)

Destroy descriptor ring.

Parameters
intelxlIntel device
ringDescriptor ring

Definition at line 1299 of file intelxl.c.

1300  {
1301  int rc;
1302 
1303  /* Disable ring */
1304  if ( ( rc = intelxl_disable_ring ( intelxl, ring ) ) != 0 ) {
1305  /* Leak memory; there's nothing else we can do */
1306  return;
1307  }
1308 
1309  /* Free descriptor ring */
1310  intelxl_free_ring ( intelxl, ring );
1311 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static int intelxl_disable_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Disable descriptor ring.
Definition: intelxl.c:1232
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:995

References intelxl_disable_ring(), intelxl_free_ring(), and rc.

Referenced by ice_close(), ice_open(), intelxl_close(), and intelxl_open().

◆ intelxl_refill_rx()

static void intelxl_refill_rx ( struct intelxl_nic intelxl)
static

Refill receive descriptor ring.

Parameters
intelxlIntel device

Definition at line 1318 of file intelxl.c.

1318  {
1320  struct io_buffer *iobuf;
1321  unsigned int rx_idx;
1322  unsigned int rx_tail;
1323  unsigned int refilled = 0;
1324 
1325  /* Refill ring */
1326  while ( ( intelxl->rx.prod - intelxl->rx.cons ) < INTELXL_RX_FILL ) {
1327 
1328  /* Allocate I/O buffer */
1329  iobuf = alloc_rx_iob ( intelxl->mfs, intelxl->dma );
1330  if ( ! iobuf ) {
1331  /* Wait for next refill */
1332  break;
1333  }
1334 
1335  /* Get next receive descriptor */
1336  rx_idx = ( intelxl->rx.prod++ % INTELXL_RX_NUM_DESC );
1337  rx = &intelxl->rx.desc.rx[rx_idx].data;
1338 
1339  /* Populate receive descriptor */
1340  rx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1341  rx->flags = 0;
1342 
1343  /* Record I/O buffer */
1344  assert ( intelxl->rx_iobuf[rx_idx] == NULL );
1345  intelxl->rx_iobuf[rx_idx] = iobuf;
1346 
1347  DBGC2 ( intelxl, "INTELXL %p RX %d is [%08lx,%08lx)\n",
1348  intelxl, rx_idx, virt_to_phys ( iobuf->data ),
1349  ( virt_to_phys ( iobuf->data ) + intelxl->mfs ) );
1350  refilled++;
1351  }
1352 
1353  /* Push descriptors to card, if applicable */
1354  if ( refilled ) {
1355  wmb();
1356  rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1357  writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1358  }
1359 }
void * regs
Registers.
Definition: intelxl.h:911
struct dma_device * dma
DMA device.
Definition: intelxl.h:913
wmb()
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define cpu_to_le64(value)
Definition: byteswap.h:108
size_t mfs
Maximum frame size.
Definition: intelxl.h:915
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:951
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:953
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:267
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
union intelxl_ring::@79 desc
Descriptors.
Receive data descriptor.
Definition: intelxl.h:709
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition: iobuf.c:187
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:52
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_RX_FILL
Receive descriptor ring fill level.
Definition: intelxl.h:823
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
struct intelxl_rx_data_descriptor data
Receive data descriptor.
Definition: intelxl.h:749
A persistent I/O buffer.
Definition: iobuf.h:37

References alloc_rx_iob(), assert(), intelxl_ring::cons, cpu_to_le64, io_buffer::data, intelxl_rx_descriptor::data, DBGC2, intelxl_ring::desc, intelxl_nic::dma, INTELXL_RX_FILL, INTELXL_RX_NUM_DESC, iob_dma(), intelxl_nic::mfs, NULL, intelxl_ring::prod, intelxl_nic::regs, rx, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, intelxl_ring::tail, wmb(), and writel().

Referenced by intelxl_open(), and intelxl_poll().

◆ intelxl_empty_rx()

void intelxl_empty_rx ( struct intelxl_nic intelxl)

Discard unused receive I/O buffers.

Parameters
intelxlIntel device

Definition at line 1366 of file intelxl.c.

1366  {
1367  unsigned int i;
1368 
1369  /* Discard any unused receive buffers */
1370  for ( i = 0 ; i < INTELXL_RX_NUM_DESC ; i++ ) {
1371  if ( intelxl->rx_iobuf[i] )
1372  free_rx_iob ( intelxl->rx_iobuf[i] );
1373  intelxl->rx_iobuf[i] = NULL;
1374  }
1375 }
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:953
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition: iobuf.c:214
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321

References free_rx_iob(), INTELXL_RX_NUM_DESC, NULL, and intelxl_nic::rx_iobuf.

Referenced by ice_close(), intelxl_close(), and intelxlvf_close().

◆ intelxl_open()

static int intelxl_open ( struct net_device netdev)
static

Open network device.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 1390 of file intelxl.c.

1390  {
1391  struct intelxl_nic *intelxl = netdev->priv;
1392  unsigned int queue;
1393  int rc;
1394 
1395  /* Calculate maximum frame size */
1396  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
1397  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
1398 
1399  /* Set MAC address */
1400  if ( ( rc = intelxl_admin_mac_write ( netdev ) ) != 0 )
1401  goto err_mac_write;
1402 
1403  /* Set maximum frame size */
1404  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
1405  goto err_mac_config;
1406 
1407  /* Associate transmit queue to PF */
1409  INTELXL_QXX_CTL_PFVF_PF_INDX ( intelxl->pf ) ),
1410  ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_CTL ) );
1411 
1412  /* Clear transmit pre queue disable */
1413  queue = ( intelxl->base + intelxl->queue );
1416  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1417 
1418  /* Reset transmit queue head */
1419  writel ( 0, ( intelxl->regs + INTELXL_QTX_HEAD ( intelxl->queue ) ) );
1420 
1421  /* Create receive descriptor ring */
1422  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
1423  goto err_create_rx;
1424 
1425  /* Create transmit descriptor ring */
1426  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->tx ) ) != 0 )
1427  goto err_create_tx;
1428 
1429  /* Fill receive ring */
1430  intelxl_refill_rx ( intelxl );
1431 
1432  /* Restart autonegotiation */
1433  intelxl_admin_autoneg ( intelxl );
1434 
1435  /* Update link state */
1437 
1438  return 0;
1439 
1442  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1444  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1445  err_create_tx:
1446  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1447  err_create_rx:
1448  err_mac_config:
1449  err_mac_write:
1450  return rc;
1451 }
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:625
void * regs
Registers.
Definition: intelxl.h:911
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1299
#define INTELXL_QXX_CTL_PFVF_Q_PF
PF queue.
Definition: intelxl.h:648
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:626
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:415
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
size_t mfs
Maximum frame size.
Definition: intelxl.h:915
unsigned int queue
Queue number.
Definition: intelxl.h:924
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1318
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:951
#define ETH_HLEN
Definition: if_ether.h:9
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x)
PF index.
Definition: intelxl.h:650
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static struct net_device * netdev
Definition: gdbudp.c:52
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1265
unsigned int reg
Register block.
Definition: intelxl.h:773
static int intelxl_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: intelxl.c:736
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:609
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:949
unsigned int pf
Physical function number.
Definition: intelxl.h:918
static int intelxl_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: intelxl.c:526
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:629
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS
Clear disable.
Definition: intelxl.h:631
unsigned int base
Absolute queue number base.
Definition: intelxl.h:920
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:761
uint16_t queue
Queue ID.
Definition: ena.h:22
#define INTELXL_QXX_CTL
Queue Control Register (offset)
Definition: intelxl.h:646
#define INTELXL_QTX_HEAD(x)
Global Transmit Queue Head register.
Definition: intelxl.h:622
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:711

References intelxl_nic::base, ETH_HLEN, intelxl_admin_autoneg(), intelxl_admin_link(), intelxl_admin_mac_config(), intelxl_admin_mac_write(), INTELXL_ALIGN, intelxl_create_ring(), intelxl_destroy_ring(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_QTX_HEAD, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, INTELXL_QXX_CTL, INTELXL_QXX_CTL_PFVF_PF_INDX, INTELXL_QXX_CTL_PFVF_Q_PF, intelxl_refill_rx(), intelxl_nic::mfs, net_device::mtu, netdev, intelxl_nic::pf, net_device::priv, queue, intelxl_nic::queue, rc, intelxl_ring::reg, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_close()

static void intelxl_close ( struct net_device netdev)
static

Close network device.

Parameters
netdevNetwork device

Definition at line 1458 of file intelxl.c.

1458  {
1459  struct intelxl_nic *intelxl = netdev->priv;
1460  unsigned int queue;
1461 
1462  /* Dump contexts (for debugging) */
1464  sizeof ( struct intelxl_context_tx ) );
1466  sizeof ( struct intelxl_context_rx ) );
1467 
1468  /* Pre-disable transmit queue */
1469  queue = ( intelxl->base + intelxl->queue );
1472  ( intelxl->regs + INTELXL_GLLAN_TXPRE_QDIS ( queue ) ) );
1474 
1475  /* Destroy transmit descriptor ring */
1476  intelxl_destroy_ring ( intelxl, &intelxl->tx );
1477 
1478  /* Destroy receive descriptor ring */
1479  intelxl_destroy_ring ( intelxl, &intelxl->rx );
1480 
1481  /* Discard any unused receive buffers */
1482  intelxl_empty_rx ( intelxl );
1483 }
Receive queue context.
Definition: intelxl.h:567
#define INTELXL_GLLAN_TXPRE_QDIS(x)
Global Transmit Pre Queue Disable register.
Definition: intelxl.h:625
void * regs
Registers.
Definition: intelxl.h:911
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1299
static void intelxl_context_dump(struct intelxl_nic *intelxl, uint32_t op, size_t len)
Dump queue context (for debugging)
Definition: intelxl.c:1011
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x)
Queue index.
Definition: intelxl.h:626
unsigned int queue
Queue number.
Definition: intelxl.h:924
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX
RX queue type.
Definition: intelxl.h:512
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX
TX queue type.
Definition: intelxl.h:514
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:951
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US
Time to wait for a transmit queue to become pre-disabled.
Definition: intelxl.h:609
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:949
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS
Set disable.
Definition: intelxl.h:629
unsigned int base
Absolute queue number base.
Definition: intelxl.h:920
uint16_t queue
Queue ID.
Definition: ena.h:22
Transmit queue context.
Definition: intelxl.h:535
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1366

References intelxl_nic::base, intelxl_context_dump(), intelxl_destroy_ring(), intelxl_empty_rx(), INTELXL_GLLAN_TXPRE_QDIS, INTELXL_GLLAN_TXPRE_QDIS_QINDX, INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS, INTELXL_PFCM_LANCTXCTL_TYPE_RX, INTELXL_PFCM_LANCTXCTL_TYPE_TX, INTELXL_QUEUE_PRE_DISABLE_DELAY_US, netdev, net_device::priv, queue, intelxl_nic::queue, intelxl_nic::regs, intelxl_nic::rx, intelxl_nic::tx, udelay(), and writel().

◆ intelxl_transmit()

int intelxl_transmit ( struct net_device netdev,
struct io_buffer iobuf 
)

Transmit packet.

Parameters
netdevNetwork device
iobufI/O buffer
Return values
rcReturn status code

Definition at line 1492 of file intelxl.c.

1492  {
1493  struct intelxl_nic *intelxl = netdev->priv;
1495  unsigned int tx_idx;
1496  unsigned int tx_tail;
1497  size_t len;
1498 
1499  /* Get next transmit descriptor */
1500  if ( ( intelxl->tx.prod - intelxl->tx.cons ) >= INTELXL_TX_FILL ) {
1501  DBGC ( intelxl, "INTELXL %p out of transmit descriptors\n",
1502  intelxl );
1503  return -ENOBUFS;
1504  }
1505  tx_idx = ( intelxl->tx.prod++ % INTELXL_TX_NUM_DESC );
1506  tx_tail = ( intelxl->tx.prod % INTELXL_TX_NUM_DESC );
1507  tx = &intelxl->tx.desc.tx[tx_idx].data;
1508 
1509  /* Populate transmit descriptor */
1510  len = iob_len ( iobuf );
1511  tx->address = cpu_to_le64 ( iob_dma ( iobuf ) );
1512  tx->len = cpu_to_le32 ( INTELXL_TX_DATA_LEN ( len ) );
1515  wmb();
1516 
1517  /* Notify card that there are packets ready to transmit */
1518  writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1519 
1520  DBGC2 ( intelxl, "INTELXL %p TX %d is [%08lx,%08lx)\n",
1521  intelxl, tx_idx, virt_to_phys ( iobuf->data ),
1522  ( virt_to_phys ( iobuf->data ) + len ) );
1523  return 0;
1524 }
void * regs
Registers.
Definition: intelxl.h:911
wmb()
#define INTELXL_TX_DATA_EOP
Transmit data descriptor end of packet.
Definition: intelxl.h:669
#define INTELXL_TX_DATA_DTYP
Transmit data descriptor type.
Definition: intelxl.h:666
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
#define cpu_to_le64(value)
Definition: byteswap.h:108
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
#define INTELXL_TX_DATA_LEN(len)
Transmit data descriptor length.
Definition: intelxl.h:685
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_tx_data_descriptor data
Transmit data descriptor.
Definition: intelxl.h:703
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
ring len
Length.
Definition: dwmac.h:231
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition: iobuf.h:267
union intelxl_ring::@79 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define INTELXL_TX_DATA_RS
Transmit data descriptor report status.
Definition: intelxl.h:672
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:159
Transmit data descriptor.
Definition: intelxl.h:656
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define INTELXL_TX_DATA_JFDI
Transmit data descriptor pretty please.
Definition: intelxl.h:682
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:949
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
void * data
Start of data.
Definition: iobuf.h:52
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_TX_FILL
Transmit descriptor ring maximum fill level.
Definition: intelxl.h:811
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References intelxl_ring::cons, cpu_to_le32, cpu_to_le64, io_buffer::data, intelxl_tx_descriptor::data, DBGC, DBGC2, intelxl_ring::desc, ENOBUFS, INTELXL_TX_DATA_DTYP, INTELXL_TX_DATA_EOP, INTELXL_TX_DATA_JFDI, INTELXL_TX_DATA_LEN, INTELXL_TX_DATA_RS, INTELXL_TX_FILL, INTELXL_TX_NUM_DESC, iob_dma(), iob_len(), len, netdev, net_device::priv, intelxl_ring::prod, intelxl_nic::regs, intelxl_ring::tail, tx, intelxl_ring::tx, intelxl_nic::tx, wmb(), and writel().

◆ intelxl_poll_tx()

static void intelxl_poll_tx ( struct net_device netdev)
static

Poll for completed packets.

Parameters
netdevNetwork device

Definition at line 1531 of file intelxl.c.

1531  {
1532  struct intelxl_nic *intelxl = netdev->priv;
1533  struct intelxl_tx_writeback_descriptor *tx_wb;
1534  unsigned int tx_idx;
1535 
1536  /* Check for completed packets */
1537  while ( intelxl->tx.cons != intelxl->tx.prod ) {
1538 
1539  /* Get next transmit descriptor */
1540  tx_idx = ( intelxl->tx.cons % INTELXL_TX_NUM_DESC );
1541  tx_wb = &intelxl->tx.desc.tx[tx_idx].wb;
1542 
1543  /* Stop if descriptor is still in use */
1544  if ( ! ( tx_wb->flags & INTELXL_TX_WB_FL_DD ) )
1545  return;
1546  DBGC2 ( intelxl, "INTELXL %p TX %d complete\n",
1547  intelxl, tx_idx );
1548 
1549  /* Complete TX descriptor */
1551  intelxl->tx.cons++;
1552  }
1553 }
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:778
unsigned int prod
Producer index.
Definition: intelxl.h:768
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
unsigned int cons
Consumer index.
Definition: intelxl.h:770
Transmit writeback descriptor.
Definition: intelxl.h:688
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
union intelxl_ring::@79 desc
Descriptors.
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:949
#define INTELXL_TX_WB_FL_DD
Transmit writeback descriptor complete.
Definition: intelxl.h:698
#define DBGC2(...)
Definition: compiler.h:522
struct intelxl_tx_writeback_descriptor wb
Transmit writeback descriptor.
Definition: intelxl.h:705

References intelxl_ring::cons, DBGC2, intelxl_ring::desc, intelxl_tx_writeback_descriptor::flags, INTELXL_TX_NUM_DESC, INTELXL_TX_WB_FL_DD, netdev, netdev_tx_complete_next(), net_device::priv, intelxl_ring::prod, intelxl_ring::tx, intelxl_nic::tx, and intelxl_tx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll_rx()

static void intelxl_poll_rx ( struct net_device netdev)
static

Poll for received packets.

Parameters
netdevNetwork device

Definition at line 1560 of file intelxl.c.

1560  {
1561  struct intelxl_nic *intelxl = netdev->priv;
1562  struct intelxl_rx_writeback_descriptor *rx_wb;
1563  struct io_buffer *iobuf;
1564  unsigned int rx_idx;
1565  unsigned int tag;
1566  size_t len;
1567 
1568  /* Check for received packets */
1569  while ( intelxl->rx.cons != intelxl->rx.prod ) {
1570 
1571  /* Get next receive descriptor */
1572  rx_idx = ( intelxl->rx.cons % INTELXL_RX_NUM_DESC );
1573  rx_wb = &intelxl->rx.desc.rx[rx_idx].wb;
1574 
1575  /* Stop if descriptor is still in use */
1576  if ( ! ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_DD ) ) )
1577  return;
1578 
1579  /* Populate I/O buffer */
1580  iobuf = intelxl->rx_iobuf[rx_idx];
1581  intelxl->rx_iobuf[rx_idx] = NULL;
1582  len = INTELXL_RX_WB_LEN ( le32_to_cpu ( rx_wb->len ) );
1583  iob_put ( iobuf, len );
1584 
1585  /* Find VLAN device, if applicable */
1586  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_VLAN ) ) {
1587  tag = VLAN_TAG ( le16_to_cpu ( rx_wb->vlan ) );
1588  } else {
1589  tag = 0;
1590  }
1591 
1592  /* Hand off to network stack */
1593  if ( rx_wb->flags & cpu_to_le32 ( INTELXL_RX_WB_FL_RXE ) ) {
1594  DBGC ( intelxl, "INTELXL %p RX %d error (length %zd, "
1595  "flags %08x)\n", intelxl, rx_idx, len,
1596  le32_to_cpu ( rx_wb->flags ) );
1597  vlan_netdev_rx_err ( netdev, tag, iobuf, -EIO );
1598  } else {
1599  DBGC2 ( intelxl, "INTELXL %p RX %d complete (length "
1600  "%zd)\n", intelxl, rx_idx, len );
1601  vlan_netdev_rx ( netdev, tag, iobuf );
1602  }
1603  intelxl->rx.cons++;
1604  }
1605 }
#define VLAN_TAG(tci)
Extract VLAN tag from tag control information.
Definition: vlan.h:29
#define iob_put(iobuf, len)
Definition: iobuf.h:124
#define le32_to_cpu(value)
Definition: byteswap.h:113
uint16_t vlan
VLAN tag.
Definition: intelxl.h:723
#define INTELXL_RX_WB_FL_DD
Receive writeback descriptor complete.
Definition: intelxl.h:735
#define DBGC(...)
Definition: compiler.h:505
unsigned int prod
Producer index.
Definition: intelxl.h:768
struct intelxl_rx_writeback_descriptor wb
Receive writeback descriptor.
Definition: intelxl.h:751
unsigned int cons
Consumer index.
Definition: intelxl.h:770
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:951
struct io_buffer * rx_iobuf[INTELXL_RX_NUM_DESC]
Receive I/O buffers.
Definition: intelxl.h:953
void * priv
Driver private data.
Definition: netdevice.h:431
ring len
Length.
Definition: dwmac.h:231
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
union intelxl_ring::@79 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:107
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define INTELXL_RX_WB_LEN(len)
Receive writeback descriptor length.
Definition: intelxl.h:744
__weak void vlan_netdev_rx(struct net_device *netdev, unsigned int tag, struct io_buffer *iobuf)
Add VLAN tag-stripped packet to queue (when VLAN support is not present)
Definition: netdevice.c:1209
#define DBGC2(...)
Definition: compiler.h:522
#define EIO
Input/output error.
Definition: errno.h:433
__weak void vlan_netdev_rx_err(struct net_device *netdev, unsigned int tag __unused, struct io_buffer *iobuf, int rc)
Discard received VLAN tag-stripped packet (when VLAN support is not present)
Definition: netdevice.c:1227
Receive writeback descriptor.
Definition: intelxl.h:719
uint64_t tag
Identity tag.
Definition: edd.h:30
#define INTELXL_RX_WB_FL_RXE
Receive writeback descriptor error.
Definition: intelxl.h:741
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
#define INTELXL_RX_WB_FL_VLAN
Receive writeback descriptor VLAN tag present.
Definition: intelxl.h:738
A persistent I/O buffer.
Definition: iobuf.h:37

References intelxl_ring::cons, cpu_to_le32, DBGC, DBGC2, intelxl_ring::desc, EIO, intelxl_rx_writeback_descriptor::flags, INTELXL_RX_NUM_DESC, INTELXL_RX_WB_FL_DD, INTELXL_RX_WB_FL_RXE, INTELXL_RX_WB_FL_VLAN, INTELXL_RX_WB_LEN, iob_put, le16_to_cpu, le32_to_cpu, len, intelxl_rx_writeback_descriptor::len, netdev, NULL, net_device::priv, intelxl_ring::prod, intelxl_ring::rx, intelxl_nic::rx, intelxl_nic::rx_iobuf, tag, intelxl_rx_writeback_descriptor::vlan, vlan_netdev_rx(), vlan_netdev_rx_err(), VLAN_TAG, and intelxl_rx_descriptor::wb.

Referenced by intelxl_poll().

◆ intelxl_poll()

void intelxl_poll ( struct net_device netdev)

Poll for completed and received packets.

Parameters
netdevNetwork device

Definition at line 1612 of file intelxl.c.

1612  {
1613  struct intelxl_nic *intelxl = netdev->priv;
1614 
1615  /* Poll for completed packets */
1616  intelxl_poll_tx ( netdev );
1617 
1618  /* Poll for received packets */
1619  intelxl_poll_rx ( netdev );
1620 
1621  /* Poll for admin events */
1623 
1624  /* Refill RX ring */
1625  intelxl_refill_rx ( intelxl );
1626 
1627  /* Rearm interrupt, since otherwise receive descriptors will
1628  * be written back only after a complete cacheline (four
1629  * packets) have been received.
1630  *
1631  * There is unfortunately no efficient way to determine
1632  * whether or not rearming the interrupt is necessary. If we
1633  * are running inside a hypervisor (e.g. using a VF or PF as a
1634  * passed-through PCI device), then the MSI-X write is
1635  * redirected by the hypervisor to the real host APIC and the
1636  * host ISR then raises an interrupt within the guest. We
1637  * therefore cannot poll the nominal MSI-X target location to
1638  * watch for the value being written. We could read from the
1639  * INT_DYN_CTL register, but this is even less efficient than
1640  * just unconditionally rearming the interrupt.
1641  */
1642  writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
1643 }
void * regs
Registers.
Definition: intelxl.h:911
#define INTELXL_INT_DYN_CTL_INTENA
Enable.
Definition: intelxl.h:837
static void intelxl_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intelxl.c:1531
static void intelxl_refill_rx(struct intelxl_nic *intelxl)
Refill receive descriptor ring.
Definition: intelxl.c:1318
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
void intelxl_poll_admin(struct net_device *netdev)
Poll admin event queue.
Definition: intelxl.c:835
unsigned int intr
Interrupt control register.
Definition: intelxl.h:934
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
static void intelxl_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intelxl.c:1560

References INTELXL_INT_DYN_CTL_INTENA, intelxl_poll_admin(), intelxl_poll_rx(), intelxl_poll_tx(), intelxl_refill_rx(), intelxl_nic::intr, netdev, net_device::priv, intelxl_nic::regs, and writel().

◆ intelxl_probe()

static int intelxl_probe ( struct pci_device pci)
static

Probe PCI device.

Parameters
pciPCI device
Return values
rcReturn status code

Definition at line 1666 of file intelxl.c.

1666  {
1667  struct net_device *netdev;
1668  struct intelxl_nic *intelxl;
1669  uint32_t pffunc_rid;
1670  uint32_t pfgen_portnum;
1671  uint32_t pflan_qalloc;
1672  int rc;
1673 
1674  /* Allocate and initialise net device */
1675  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
1676  if ( ! netdev ) {
1677  rc = -ENOMEM;
1678  goto err_alloc;
1679  }
1682  intelxl = netdev->priv;
1683  pci_set_drvdata ( pci, netdev );
1684  netdev->dev = &pci->dev;
1685  memset ( intelxl, 0, sizeof ( *intelxl ) );
1686  intelxl->intr = INTELXL_PFINT_DYN_CTL0;
1687  intelxl->handle = intelxl_admin_event;
1693  sizeof ( intelxl->tx.desc.tx[0] ),
1696  sizeof ( intelxl->rx.desc.rx[0] ),
1698 
1699  /* Fix up PCI device */
1700  adjust_pci_device ( pci );
1701 
1702  /* Map registers */
1703  intelxl->regs = pci_ioremap ( pci, pci->membase, INTELXL_BAR_SIZE );
1704  if ( ! intelxl->regs ) {
1705  rc = -ENODEV;
1706  goto err_ioremap;
1707  }
1708 
1709  /* Configure DMA */
1710  intelxl->dma = &pci->dma;
1711  dma_set_mask_64bit ( intelxl->dma );
1712  netdev->dma = intelxl->dma;
1713 
1714  /* Locate PCI Express capability */
1715  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
1716  if ( ! intelxl->exp ) {
1717  DBGC ( intelxl, "INTELXL %p missing PCIe capability\n",
1718  intelxl );
1719  rc = -ENXIO;
1720  goto err_exp;
1721  }
1722 
1723  /* Reset the function via PCIe FLR */
1724  pci_reset ( pci, intelxl->exp );
1725 
1726  /* Get function number, port number and base queue number */
1727  pffunc_rid = readl ( intelxl->regs + INTELXL_PFFUNC_RID );
1728  intelxl->pf = INTELXL_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
1729  pfgen_portnum = readl ( intelxl->regs + INTELXL_PFGEN_PORTNUM );
1730  intelxl->port = INTELXL_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
1731  pflan_qalloc = readl ( intelxl->regs + INTELXL_PFLAN_QALLOC );
1732  intelxl->base = INTELXL_PFLAN_QALLOC_FIRSTQ ( pflan_qalloc );
1733  DBGC ( intelxl, "INTELXL %p PF %d using port %d queues [%#04x-%#04x]\n",
1734  intelxl, intelxl->pf, intelxl->port, intelxl->base,
1735  INTELXL_PFLAN_QALLOC_LASTQ ( pflan_qalloc ) );
1736 
1737  /* Enable MSI-X dummy interrupt */
1738  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
1739  INTELXL_MSIX_VECTOR ) ) != 0 )
1740  goto err_msix;
1741 
1742  /* Open admin queues */
1743  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
1744  goto err_open_admin;
1745 
1746  /* Get firmware version */
1747  if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
1748  goto err_admin_version;
1749 
1750  /* Report driver version */
1751  if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
1752  goto err_admin_driver;
1753 
1754  /* Clear PXE mode */
1755  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
1756  goto err_admin_clear_pxe;
1757 
1758  /* Get switch configuration */
1759  if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
1760  goto err_admin_switch;
1761 
1762  /* Get VSI configuration */
1763  if ( ( rc = intelxl_admin_vsi ( intelxl ) ) != 0 )
1764  goto err_admin_vsi;
1765 
1766  /* Configure switch for promiscuous mode */
1767  if ( ( rc = intelxl_admin_promisc ( intelxl ) ) != 0 )
1768  goto err_admin_promisc;
1769 
1770  /* Get MAC address */
1771  if ( ( rc = intelxl_admin_mac_read ( netdev ) ) != 0 )
1772  goto err_admin_mac_read;
1773 
1774  /* Configure queue register addresses */
1775  intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1776  intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1777  intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1778  intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1779 
1780  /* Configure interrupt causes */
1783  intelxl->regs + INTELXL_QINT_TQCTL ( intelxl->queue ) );
1784  writel ( ( INTELXL_QINT_RQCTL_NEXTQ_INDX ( intelxl->queue ) |
1787  intelxl->regs + INTELXL_QINT_RQCTL ( intelxl->queue ) );
1790  intelxl->regs + INTELXL_PFINT_LNKLST0 );
1792  intelxl->regs + INTELXL_PFINT_ICR0_ENA );
1793 
1794  /* Register network device */
1795  if ( ( rc = register_netdev ( netdev ) ) != 0 )
1796  goto err_register_netdev;
1797 
1798  /* Set initial link state */
1800 
1801  return 0;
1802 
1804  err_register_netdev:
1805  err_admin_mac_read:
1806  err_admin_promisc:
1807  err_admin_vsi:
1808  err_admin_switch:
1809  err_admin_clear_pxe:
1810  err_admin_driver:
1811  err_admin_version:
1812  intelxl_close_admin ( intelxl );
1813  err_open_admin:
1814  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1815  err_msix:
1816  pci_reset ( pci, intelxl->exp );
1817  err_exp:
1818  iounmap ( intelxl->regs );
1819  err_ioremap:
1820  netdev_nullify ( netdev );
1821  netdev_put ( netdev );
1822  err_alloc:
1823  return rc;
1824 }
static int intelxl_admin_promisc(struct intelxl_nic *intelxl)
Set VSI promiscuous modes.
Definition: intelxl.c:680
Receive queue context.
Definition: intelxl.h:567
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x)
First queue.
Definition: intelxl.h:892
void * regs
Registers.
Definition: intelxl.h:911
#define INTELXL_QRX(x)
Global Receive Queue register block.
Definition: intelxl.h:638
unsigned long membase
Memory base.
Definition: pci.h:219
struct dma_device * dma
DMA device.
Definition: intelxl.h:913
#define INTELXL_PFLAN_QALLOC_LASTQ(x)
Last queue.
Definition: intelxl.h:895
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct dma_device dma
DMA device.
Definition: pci.h:214
#define INTELXL_PFFUNC_RID
Function Requester ID Information Register.
Definition: intelxl.h:885
static int intelxl_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: intelxl.c:592
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:39
#define INTELXL_PFLAN_QALLOC
PF Queue Allocation Register.
Definition: intelxl.h:891
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x)
Queue index.
Definition: intelxl.h:862
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:962
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE
End of list.
Definition: intelxl.h:875
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:36
Admin queue register offsets.
Definition: intelxl.h:63
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:560
#define INTELXL_PFINT_ICR0_ENA
PF Interrupt Zero Cause Enablement Register.
Definition: intelxl.h:857
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:941
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:466
struct dma_device * dma
DMA device.
Definition: netdevice.h:366
static int intelxl_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: intelxl.c:478
#define INTELXL_PFINT_ICR0_ENA_ADMINQ
Admin event.
Definition: intelxl.h:858
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: intelxl.h:901
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:876
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:88
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:240
struct device dev
Generic device.
Definition: pci.h:212
unsigned int queue
Queue number.
Definition: intelxl.h:924
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:936
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:518
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:365
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define INTELXL_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: intelxl.h:900
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:951
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:475
#define INTELXL_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:882
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX
Receive queue.
Definition: intelxl.h:851
#define INTELXL_PFINT_DYN_CTL0
PF Interrupt Zero Dynamic Control Register.
Definition: intelxl.h:836
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:826
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:575
static void intelxl_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf __unused)
Handle admin event.
Definition: intelxl.c:796
#define INTELXL_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: intelxl.h:870
Admin queue version number.
Definition: intelxl.h:90
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX
Transmit queue.
Definition: intelxl.h:868
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
union intelxl_ring::@79 desc
Descriptors.
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:941
unsigned int reg
Register block.
Definition: intelxl.h:773
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:759
unsigned int intr
Interrupt control register.
Definition: intelxl.h:934
A network device.
Definition: netdevice.h:352
#define INTELXL_QTX(x)
Global Transmit Queue register block.
Definition: intelxl.h:635
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:531
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:90
unsigned int port
Port number.
Definition: intelxl.h:922
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define INTELXL_PFINT_LNKLST0
PF Interrupt Zero Linked List Register.
Definition: intelxl.h:842
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:795
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:949
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:97
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:906
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
#define INTELXL_QINT_TQCTL(x)
Transmit Queue Interrupt Cause Control Register.
Definition: intelxl.h:873
unsigned int pf
Physical function number.
Definition: intelxl.h:918
#define ENXIO
No such device or address.
Definition: errno.h:599
#define INTELXL_QXX_TAIL
Queue Tail Pointer Register (offset)
Definition: intelxl.h:653
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x)
Queue index.
Definition: intelxl.h:843
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
unsigned int base
Absolute queue number base.
Definition: intelxl.h:920
void iounmap(volatile const void *io_addr)
Unmap I/O address.
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define INTELXL_QINT_RQCTL(x)
Receive Queue Interrupt Cause Control Register.
Definition: intelxl.h:861
#define INTELXL_BAR_SIZE
BAR size.
Definition: intelxl.h:20
static int intelxl_admin_vsi(struct intelxl_nic *intelxl)
Get VSI parameters.
Definition: intelxl.c:646
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:409
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:928
static struct net_device_operations intelxl_operations
Network device operations.
Definition: intelxl.c:1646
#define INTELXL_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: intelxl.h:886
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static int intelxl_admin_link(struct net_device *netdev)
Get link status.
Definition: intelxl.c:761
static int intelxl_admin_driver(struct intelxl_nic *intelxl)
Report driver version.
Definition: intelxl.c:423
Transmit queue context.
Definition: intelxl.h:535
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:943
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:62

References adjust_pci_device(), alloc_etherdev(), intelxl_nic::base, intelxl_nic::command, DBGC, intelxl_ring::desc, pci_device::dev, net_device::dev, pci_device::dma, net_device::dma, intelxl_nic::dma, dma_set_mask_64bit(), ENODEV, ENOMEM, ENXIO, intelxl_nic::event, intelxl_nic::exp, intelxl_nic::handle, intelxl_admin_clear_pxe(), INTELXL_ADMIN_CMD, intelxl_admin_driver(), intelxl_admin_event(), INTELXL_ADMIN_EVT, intelxl_admin_link(), intelxl_admin_mac_read(), intelxl_admin_promisc(), intelxl_admin_switch(), intelxl_admin_vsi(), INTELXL_BAR_SIZE, intelxl_close_admin(), intelxl_init_admin(), intelxl_init_ring(), INTELXL_MAX_PKT_LEN, intelxl_msix_disable(), intelxl_msix_enable(), INTELXL_MSIX_VECTOR, intelxl_open_admin(), intelxl_operations, INTELXL_PFFUNC_RID, INTELXL_PFFUNC_RID_FUNC_NUM, INTELXL_PFGEN_PORTNUM, INTELXL_PFGEN_PORTNUM_PORT_NUM, INTELXL_PFINT_DYN_CTL0, INTELXL_PFINT_ICR0_ENA, INTELXL_PFINT_ICR0_ENA_ADMINQ, INTELXL_PFINT_LNKLST0, INTELXL_PFINT_LNKLST0_FIRSTQ_INDX, INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX, INTELXL_PFLAN_QALLOC, INTELXL_PFLAN_QALLOC_FIRSTQ, INTELXL_PFLAN_QALLOC_LASTQ, INTELXL_QINT_RQCTL, INTELXL_QINT_RQCTL_CAUSE_ENA, INTELXL_QINT_RQCTL_NEXTQ_INDX, INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX, INTELXL_QINT_TQCTL, INTELXL_QINT_TQCTL_CAUSE_ENA, INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE, INTELXL_QRX, INTELXL_QTX, INTELXL_QXX_TAIL, INTELXL_RX_NUM_DESC, INTELXL_TX_NUM_DESC, intelxl_nic::intr, iounmap(), net_device::max_pkt_len, pci_device::membase, memset(), netdev, netdev_init(), netdev_nullify(), netdev_put(), PCI_CAP_ID_EXP, pci_find_capability(), pci_ioremap(), pci_reset(), pci_set_drvdata(), intelxl_nic::pf, intelxl_nic::port, net_device::priv, intelxl_nic::queue, rc, readl(), intelxl_ring::reg, register_netdev(), intelxl_nic::regs, intelxl_ring::rx, intelxl_nic::rx, intelxl_ring::tail, intelxl_ring::tx, intelxl_nic::tx, unregister_netdev(), and writel().

◆ intelxl_remove()

static void intelxl_remove ( struct pci_device pci)
static

Remove PCI device.

Parameters
pciPCI device

Definition at line 1831 of file intelxl.c.

1831  {
1832  struct net_device *netdev = pci_get_drvdata ( pci );
1833  struct intelxl_nic *intelxl = netdev->priv;
1834 
1835  /* Unregister network device */
1837 
1838  /* Close admin queues */
1839  intelxl_close_admin ( intelxl );
1840 
1841  /* Disable MSI-X dummy interrupt */
1842  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
1843 
1844  /* Reset the NIC */
1845  pci_reset ( pci, intelxl->exp );
1846 
1847  /* Free network device */
1848  iounmap ( intelxl->regs );
1849  netdev_nullify ( netdev );
1850  netdev_put ( netdev );
1851 }
void * regs
Registers.
Definition: intelxl.h:911
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:88
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:936
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:575
void * priv
Driver private data.
Definition: netdevice.h:431
static struct net_device * netdev
Definition: gdbudp.c:52
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:941
A network device.
Definition: netdevice.h:352
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:531
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:90
An Intel 40 Gigabit network card.
Definition: intelxl.h:909
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:906
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:375
void iounmap(volatile const void *io_addr)
Unmap I/O address.
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:928

References intelxl_nic::exp, intelxl_close_admin(), intelxl_msix_disable(), INTELXL_MSIX_VECTOR, iounmap(), netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), pci_reset(), net_device::priv, intelxl_nic::regs, and unregister_netdev().

Variable Documentation

◆ intelxl_admin_offsets

Initial value:
= {
}
#define INTELXL_ADMIN_BAH
Admin Queue Base Address High Register (offset)
Definition: intelxl.h:45
#define INTELXL_ADMIN_BAL
Admin Queue Base Address Low Register (offset)
Definition: intelxl.h:42
#define INTELXL_ADMIN_TAIL
Admin Queue Tail Register (offset)
Definition: intelxl.h:56
#define INTELXL_ADMIN_LEN
Admin Queue Length Register (offset)
Definition: intelxl.h:48
#define INTELXL_ADMIN_HEAD
Admin Queue Head Register (offset)
Definition: intelxl.h:53

Admin queue register offsets.

Definition at line 108 of file intelxl.c.

◆ intelxl_operations

struct net_device_operations intelxl_operations
static
Initial value:
= {
.open = intelxl_open,
.close = intelxl_close,
.transmit = intelxl_transmit,
.poll = intelxl_poll,
}
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1492
static int intelxl_open(struct net_device *netdev)
Open network device.
Definition: intelxl.c:1390
static void intelxl_close(struct net_device *netdev)
Close network device.
Definition: intelxl.c:1458
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1612

Network device operations.

Definition at line 1646 of file intelxl.c.

Referenced by intelxl_probe().

◆ intelxl_nics

struct pci_device_id intelxl_nics[]
static
Initial value:
= {
PCI_ROM ( 0x8086, 0x0cf8, "x710-n3000", "X710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x0d58, "xxv710-n3000", "XXV710 FPGA N3000", 0 ),
PCI_ROM ( 0x8086, 0x104e, "x710-sfp-b", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x104f, "x710-kx-b", "X710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1572, "x710-sfp", "X710 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x1574, "xl710-qemu", "Virtual XL710", 0 ),
PCI_ROM ( 0x8086, 0x1580, "xl710-kx-b", "XL710 40GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1581, "xl710-kx-c", "XL710 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1583, "xl710-qda2", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1584, "xl710-qda1", "XL710 40GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1585, "x710-qsfp", "X710 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x1586, "x710-10gt", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x1587, "x710-kr2", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1588, "x710-kr2-a", "XL710 20GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x1589, "x710-10gt4", "X710 10GBASE-T4", 0 ),
PCI_ROM ( 0x8086, 0x158a, "xxv710", "XXV710 25GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x158b, "xxv710-sfp28", "XXV710 25GbE SFP28", 0 ),
PCI_ROM ( 0x8086, 0x15ff, "x710-10gt-b", "X710 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37ce, "x722-kx", "X722 10GbE backplane", 0 ),
PCI_ROM ( 0x8086, 0x37cf, "x722-qsfp", "X722 10GbE QSFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d0, "x722-sfp", "X722 10GbE SFP+", 0 ),
PCI_ROM ( 0x8086, 0x37d1, "x722-1gt", "X722 1GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d2, "x722-10gt", "X722 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x37d3, "x722-sfp-i", "X722 10GbE SFP+", 0 ),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:307

PCI device IDs.

Definition at line 1854 of file intelxl.c.

◆ __pci_driver

struct pci_driver intelxl_driver __pci_driver
Initial value:
= {
.ids = intelxl_nics,
.id_count = ( sizeof ( intelxl_nics ) / sizeof ( intelxl_nics[0] ) ),
.probe = intelxl_probe,
}
static struct pci_device_id intelxl_nics[]
PCI device IDs.
Definition: intelxl.c:1854
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static int intelxl_probe(struct pci_device *pci)
Probe PCI device.
Definition: intelxl.c:1666
static void intelxl_remove(struct pci_device *pci)
Remove PCI device.
Definition: intelxl.c:1831

PCI driver.

Definition at line 1882 of file intelxl.c.